Nanowire device with mask layer

Abstract

A composition of matter comprising: a doped substrate; a mask layer having a thickness of 2 nm or less on top of the substrate, with a plurality of openings being present through the mask layer; and wherein a plurality of nanowires or nanocones are grown from the substrate in the openings, the nanowires or nanocones comprising at least one semiconductor group III-V compound.

Description

Technical Field

[0001] The present invention relates to a composition comprising nanowires or nanocones grown on a doped substrate through a mask layer. The composition of the formed material can be used in electronic devices such as LEDs, solar cells, transistors, lasers, or photodetectors. The present invention also relates to a composition / device comprising nanowires or nanocones on a metal substrate through a mask layer. Background Art

[0002] In recent years, as nanotechnology has become an important engineering discipline, the interest in semiconductor nanowires has been increasing. Nanowires, also referred to by some authors as nanocrystalline whiskers, nanorods, nanocolumns, nanorods, etc., have important applications in various electrical devices such as sensors, solar cells, transistors, and LEDs.

[0003] Conventionally, semiconductor nanowires are grown on the same substrate as the nanowires themselves (homoepitaxial growth). Thus, GaAs nanowires are grown on GaAs substrates, GaN nanowires are grown on GaN substrates, and so on. Of course, this ensures a lattice match between the crystal structure of the substrate and the crystal structure of the grown nanowires. In the case of heteroepitaxial growth, GaN nanowires are grown on sapphire or silicon substrates, etc. Both the substrate and the nanowires can have the same crystal structure.

[0004] To localize nanowires, it is known to use a mask having a pattern of an array of holes, where only / mainly nanowires are allowed to grow in the hole-patterned regions. The mask can also promote NW growth in a direction perpendicular to the substrate. Typically, a silica layer is applied to the substrate and etched to form holes in a desired pattern. Then, nanowires are grown only / mainly at the positions of the holes.

[0005] The growth of nanowires (NWs) on graphene is known, where graphene is used as an electrode. In WO2012 / 080252, the growth of semiconductor nanowires on graphene substrates is discussed. WO2013 / 104723 relates to an improvement over the disclosure of WO2012 / 080252, where a graphene top contact is employed on the NWs grown on graphene. However, in these cases, nanowire growth occurs on the graphene layer rather than on the underlying substrate.

[0006] Graphene has been proposed as a possible mask layer and electrode (WO2021 / 009325). However, it is difficult to achieve good electrical contact with graphene.

[0007] The present inventors propose to use a thin mask layer on a doped substrate. Nanowires / nanocones grow through openings (such as patterned holes or defects) in the mask layer. The doped substrate is an active substrate that can participate in the functionalization of the device. The mask layer can be used as a tunneling barrier to improve vertical conduction in the device, thereby increasing efficiency. Similar benefits can be seen when using a metal (conductive) substrate. SUMMARY OF THE INVENTION

[0008] Accordingly, in one aspect, there is provided a composition of matter comprising:

[0009] a doped substrate;

[0010] a mask layer having a thickness of less than 2 nm on top of the substrate,

[0011] wherein there are a plurality of openings through the mask layer; and wherein

[0012] a plurality of nanowires or nanocones grow from the substrate in the openings, the nanowires or nanocones comprising at least one semiconductor group III-V compound.

[0013] In another aspect, there is provided a composition of matter comprising:

[0014] a doped substrate;

[0015] a mask layer having a thickness of less than 2 nm on top of the substrate, wherein there are a plurality of openings through the mask layer; and

[0016] a corrugated continuous group III-V film that is present on top of the mask layer and extends from the holes, for example formed by a plurality of merged nanowires or nanocones growing in the holes, the nanowires or nanocones comprising at least one semiconductor group III-V compound.

[0017] In another aspect, there is provided a device, such as an optoelectronic device, comprising a composition as defined herein, such as a solar cell, a photodetector, a transistor, a laser, or an LED, preferably an LED, more preferably a UV LED, even more preferably a UV-C LED.

[0018] In another aspect, there is provided a method for preparing a composition as defined herein, comprising:

[0019] (I) providing a mask layer having a thickness of less than 2 nm on a doped substrate;

[0020] (II) growing a plurality of nanowires or nanocones from the substrate in a plurality of openings in the mask layer, the nanowires or nanocones comprising at least one semiconductor group III-V compound.

[0021] In another aspect, a method for preparing a composition as defined herein is provided, comprising:

[0022] (I) providing a mask layer having a thickness of less than 2 nm carried on a doped substrate;

[0023] (II) growing a plurality of nanowires or nanocones from the substrate in a plurality of openings in the mask layer until the nanowires or nanocones merge, the nanowires or nanocones comprising at least one semiconductor group III-V compound.

[0024] In another aspect, a composition of matter is provided, comprising:

[0025] a metal substrate;

[0026] a mask layer having a thickness of less than 2 nm on top of the substrate, wherein a plurality of openings extend through the mask layer; and wherein

[0027] a plurality of nanowires or nanocones are located on the substrate in the openings, the nanowires or nanocones comprising at least one semiconductor group III-V compound.

[0028] In another aspect, a composition of matter is provided, comprising:

[0029] a metal substrate;

[0030] a mask layer having a thickness of less than 2 nm on top of the substrate, wherein a plurality of openings extend through the mask layer; and

[0031] a corrugated continuous group III-V film, the corrugated continuous group III-V film being present on top of the mask layer and extending from the openings, for example formed by a plurality of merged nanowires or nanocones grown in the openings, the nanowires or nanocones comprising at least one semiconductor group III-V compound.

[0032] In another aspect, a method for preparing a device (such as an optoelectronic device) is provided, which comprises the following steps:

[0033] (I) removing the nanowires or nanocones from the substrate in the composition as defined herein; and

[0034] (II) transferring the removed nanowires or nanocones to a different substrate, wherein the second substrate is doped / conductive or undoped / insulating.

[0035] In another aspect, a method for preparing a device (such as an optoelectronic device) is provided, which comprises the following steps:

[0036] (I) Removing a continuous III-V film from a substrate in a composition as defined herein; and

[0037] (II) Transferring the removed III-V film to a different substrate, wherein the second substrate is doped / conductive or undoped / insulating.

[0038] Unless otherwise indicated, where technically feasible, the features of the aspects and / or embodiments indicated herein can be used alone or in combination in all aspects and embodiments of the present invention. Detailed Description

[0039] Definitions

[0040] Group III-V compound semiconductors mean compound semiconductors containing at least one element from Group III and at least one element from Group V. There can be more than one element from each group, such as InGaAs, AlGaN (i.e., ternary compounds), AlInGaN (i.e., quaternary compounds), and the like. The term semiconductor nanowire or nanocone means a nanowire or nanocone made of a semiconductor material from Group III-V elements.

[0041] The term nanowire is used herein to describe a solid wire-like structure of nanoscale dimensions. The nanowire preferably has a uniform diameter over most of the nanowire (e.g., at least 75% of its length). The term nanowire is intended to encompass the use of nanorods, nanocolumns, nanopyramids, or nanowhiskers, some of which may have a tapered end structure. Nanowires can be said to be substantially in one-dimensional form, where their width or diameter is on the nanoscale, and their length is typically in the range of a few hundred nanometers to a few micrometers. Ideally, the nanowire diameter (width) is not greater than 500 nm. Ideally, the diameter (width) of the nanowire is from 50 to 500 nanometers; however, the diameter can exceed a few micrometers (referred to as a microwire).

[0042] Ideally, the diameter of the nanowire base and the nanowire top should remain approximately the same (e.g., within 20% of each other).

[0043] The term nanocone refers to a solid conical structure. The term cone is used herein to define a structure having a base, the sides of which taper to a single point, typically located above the center of the base. It should be understood that the single vertex may appear chamfered, e.g., such that the cone has a flat top. Generally, the chamfered portion is less than 50%, e.g., less than 40%, e.g., less than 30%, e.g., less than 20%, e.g., less than 10%, e.g., less than 5% of the total length of the nanocone side. The nanocone can have multiple faces, such as 3 to 8 faces, or 4 to 7 faces. Thus, the base of the nanocone can be square, pentagonal, hexagonal, heptagonal, octagonal, etc. The cone forms a face that tapers from the base to a central point (thus forming a triangular face). The triangular face typically terminates in a (1-101) or (1-102) plane. The triangular side surface having a (1-101) facet can converge to a point at the tip, or can form a new facet ((1-102) plane) before converging at the tip. In some cases, the nanocone is truncated at the top, where its top terminates in the {0001} plane. Before beginning to taper to form the conical structure, the base itself can include a portion of uniform cross-section. Thus, the thickness of the base can be up to 500 nm, e.g., up to 200 nm, such as 50 nm.

[0044] The diameter (width) of the base of the nanocone at its widest point can be 50 and 500 nm. In another embodiment, the diameter (width) of the base of the nanocone at its widest point can be 200 nm to 1 (one) micron. The height of the nanocone can be 200 nm to several microns, such as 400 nm to 1 micron in length.

[0045] It should be understood that the substrate includes a plurality of nanowires or nanocones. This can be referred to as an array of nanowires or nanocones.

[0046] The graphene layer is a film composed of a single layer or multiple layers of graphene or its derivatives. The term graphene refers to a planar sheet of sp 2 -bonded carbon atoms in a honeycomb crystal structure. Although graphene is preferably used, derivatives of graphene can also be used, such as those that have been surface-modified. For example, hydrogen atoms can be attached to the graphene surface to form graphane. Graphene with oxygen atoms as well as carbon and hydrogen atoms attached to the surface is called graphene oxide. Surface modification can also be carried out by chemical doping or oxygen / hydrogen or nitrogen plasma treatment.

[0047] The term epitaxy comes from the Greek roots epi, meaning "above," and taxis, meaning "in an ordered manner." The atomic arrangement of a nanowire or nanocone is based on the crystalline structure of the substrate. Typically, there is no epitaxial relationship between the nanowire / nanocone and the mask layer. It is a commonly used term in the art. Epitaxial growth herein means the growth of nanowires or nanocones on a substrate that mimics the orientation of the substrate.

[0048] Selective area growth (SAG) is the most promising method for growing site-specific nanowires or nanocones. This method is different from the self-assembled metal-catalyst-assisted vapor-liquid-solid (VLS) method, in which metal catalysts are used as nucleation sites for the growth of nanowires or nanocones at random positions. Another self-assembly method for growing nanowires or nanocones is the catalyst-free method, in which nanowires or nanocones nucleate at random positions. These methods result in large fluctuations in the length and diameter of nanowires and the height and width of nanocones. Site-specific nanowires or nanocones can also be grown by catalyst-assisted methods.

[0049] The SAG method or the catalyst-assisted site-specific growth method generally requires a mask with a nanopore pattern on the substrate. Nanowires or nanocones mainly nucleate in the holes of the patterned mask on the substrate. This results in a uniform size and predefined positions of the nanowires or nanocones. Nanowires / nanocones can also nucleate on the substrate in any defect in the mask layer that exposes the underlying substrate.

[0050] Molecular beam epitaxy (MBE) is a method for forming depositions on a crystalline substrate. The MBE process is carried out by heating the crystalline substrate in a vacuum, thereby supplying energy to the lattice structure of the substrate. Then, a beam (or beams) of atomic or molecular mass is directed onto the surface of the substrate. The term element used above is intended to cover the application of atoms, molecules, or ions of the element. When the directed atoms or molecules reach the surface of the substrate, the directed atoms or atom molecules encounter the energized lattice structure or catalyst droplets of the substrate, as described in detail below. Over time, the incoming atoms form nanowires.

[0051] Metalorganic vapor phase epitaxy (MOVPE) (also known as metalorganic chemical vapor deposition (MOCVD)) is an alternative to MBE for forming depositions on a crystalline substrate. In the case of MOVPE, the deposition material is supplied in the form of metalorganic precursors, which decompose when they reach the high-temperature substrate, thereby leaving atoms on the surface of the substrate. In addition, this method requires carrier gases (usually H2 and / or N2) to transport the deposition material (atoms / molecules) over the surface of the substrate. These atoms react with other atoms to form an epitaxial layer on the surface of the substrate. Careful selection of deposition parameters results in the formation of nanowires.

[0052] The term directly-bearing means that the layer in question is adjacent.

[0053] Mask layer

[0054] The mask layer can be used for various purposes. The openings in the mask allow the NW / NP material to be epitaxial with the substrate (NW = nanowire, NP = nanopyramid). Surprisingly, the mask layer also serves as a tunnel junction for conduction from the substrate to the NW / NP (or from the NW / NP to the substrate) for the portion that laterally extends on the mask layer from the NW / NP (i.e., outside the opening). The intentional patterning of the openings in the mask layer enables the positioning of the nanowires / nanopyramids (i.e., SAG).

[0055] The mask layer can comprise or consist of a two-dimensional (2D) material. A two-dimensional material herein means a material having a layered structure, such as a two-dimensional material having a structure formed by sheets stacked on top of each other, preferably where the sheets are held together by van der Waals forces. The two-dimensional material can be graphene, hexagonal-BN (h-BN), MoS2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3, or NiTe2. While graphene is preferred, other "graphene-like" materials having a two-dimensional structure are thus also applicable herein, such as layers of hexagonal-BN, MoS2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3, or NiTe2. Thus, the mask layer can be a graphene, hexagonal-BN, MoS2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3, or NiTe2 mask layer. Preferably, the mask layer is a graphene mask layer or an h-BN mask layer, and most preferably a graphene mask layer.

[0056] As used herein, the term graphene refers to a planar sheet of sp 2 bonded carbon atoms densely packed in a honeycomb (hexagonal) lattice. The term "graphene" also means a structure having a small number of graphene sheets. The interplanar spacing in graphene is 0.335 nm.

[0057] Ideally, the mask layer should contain less than 10 sheets of two-dimensional material (i.e., graphene or graphene-like material), preferably less than 5 sheets, preferably less than 4 sheets, preferably less than 3 sheets, preferably less than 2 sheets of two-dimensional material. Preferably, the mask layer should contain 1-5 sheets, preferably 1-4 sheets, preferably 1-3 sheets, preferably 1-2 sheets of two-dimensional material, and most preferably 1 sheet of two-dimensional material (i.e., monolayer graphene or graphene-like material). Particularly preferably, it is an atomically thick planar graphene sheet.

[0058] In terms of measuring the thickness, preferably, if the thickness of the mask layer is generally 2 nm or less. The mask layer preferably contains only a few sheets of two-dimensional material (i.e., graphene or graphene-like material) and ideally has a thickness of less than 1.5 nm. Even more preferably, the thickness of the mask layer can be 1 nm or less, more preferably the thickness is 0.9 nm or less, more preferably the thickness is 0.8 nm or less, more preferably the thickness is 0.7 nm or less, more preferably the thickness is 0.6 nm or less, more preferably the thickness is 0.5 nm or less. The preferred thickness range includes 0.3 - 2 nm, preferably 0.3 - 1.5 nm, such as 0.3 - 1 nm, 0.3 - 0.9 nm, 0.3 - 0.8 nm, 0.3 - 0.7 nm, such as 0.3 - 0.5 nm.

[0059] The mask layer can be used as (or is) a tunnel barrier, for example, for carrier tunneling injection from a doped substrate to a III-V nanowire or nanocone. Carrier tunneling injection typically occurs where the nanowire / nanocone extends laterally over the mask layer. Having a thin mask layer is important for electronic performance. The thinner the mask layer, the better the tunneling between the substrate and the nanowire / nanocone. Particularly efficient tunneling through the mask is obtained when the mask layer is one or two atomic layers thick, preferably when the mask is a single-atom-thick graphene sheet. Mask layers much thicker than the above thickness generally do not exhibit the desired beneficial tunneling and thus will have poor tunneling efficiency.

[0060] The portion of the nanowire or nanocone that extends over the mask layer is in contact with the mask layer. Generally, the conductive path exists as follows: starting from the substrate, through the mask layer, and into the nanowire or nanocone. The conductive path passes through the region of the nanowire / nanocone that extends over the mask layer. Thus, the mask layer can be used as a tunnel barrier between the substrate and the portion of the NW / NP that extends over the mask layer (i.e., outside the opening).

[0061] The area of the mask layer is generally not limited. This can be up to 0.5 mm 2 or more, such as up to 5 mm 2 or more, such as up to 10 cm 2 . Thus, the area of the mask layer is only limited by practicality. For example, the size of a graphene wafer can be 1.0 to 100 square inches, such as 2 square inches, or even 50 square inches.

[0062] In a highly preferred embodiment, the mask layer is a single or multiple layer of graphene (preferably a single layer) grown on a metal catalyst by using a chemical vapor deposition (CVD) method. The metal catalyst can be a metal film or foil made of, for example, Cu, Ni, or Pt. The transfer of the graphene layer grown on these metal catalysts to another substrate may be affected by the techniques discussed in detail below. The graphene layer can also be directly grown on a doped substrate (such as doped Si, Ge, or III-V substrate). In this case, no transfer process is required. The graphene layer can also be grown on a SiC substrate using a thermal sublimation process and, if necessary, transferred to the target substrate.

[0063] Preferably, the graphene layer is used without any surface modification.

[0064] The mask layer (such as graphene) can be doped to improve its conductivity. This can be beneficial if the mask layer is used as an electrode (such as the gate of a vertical transistor). The mask layer can be washed with isopropyl alcohol, acetone, or n-methyl-2-pyrrolidone to remove surface impurities. The cleaned graphene surface can be further modified by doping. Solutions of FeCl3, AuCl3, or GaCl3 can be used in the doping step.

[0065] Graphene layers are well-known for their excellent optical, electrical, thermal, and mechanical properties. They are very thin but very strong, lightweight, flexible, and impermeable. In the present invention, most importantly, they are thin tunneling barriers and hole masks for SAG of nanowires / nanocones.

[0066] When the nanowire or nanocone extends laterally on the mask outside the opening, there is a good electrical contact between the nanowire / nanocone and the substrate vertically passing through the tunneling barrier layer below. The nanowire or nanocone usually nucleates in the opening (whether a patterned hole or a defect) of the mask on the substrate and then grows laterally (i.e., radially) on the top surface of the mask layer (i.e., they "mushroom out" from the opening). Usually, the nanowire or nanocone nuclei extend laterally (i.e., radially) on the mask layer outside the mask opening. The portion extending on the mask layer is in direct contact and / or electrical contact with the mask layer. "Laterally" or "laterally" in this article means in the same plane as the substrate and / or the mask layer.

[0067] In this article, it is preferred that the mask layer is not an electrode or is not used as an electrode. Preferably, there is no electrical contact on the graphene layer. For some applications, such as transistors, it can be beneficial for the mask layer to be used as an electrode. Therefore, in a specific embodiment, the mask layer is used as (or is) an electrode. Thus, the composition can have electrical contact (direct contact, i.e., physical contact and electrical contact) with the mask layer. This can reduce the tunneling barrier and thus enhance the vertical tunneling current.

[0068] The mask layer is typically located directly on the substrate (or, if a silicon substrate is used, on the native intermediate silicon oxide film that typically covers the silicon substrate). The mask layer is planar.

[0069] The openings in the mask layer can be any kind of opening. They can be patterned holes (i.e., "intentionally" located holes) in the mask layer or pre-existing defects. They can also be defects formed during the growth of the nanowires / nanocones. The openings can be alignment holes or defect openings in the mask layer. The openings can have any size and can range from atomic vacancy defects in the mask layer to, for example, patterned holes with a diameter of up to, for example, 500 nm. The openings can have any shape, for example, they can be circular holes or elongated openings such as grain boundaries or cracks. The openings herein mean the openings in the mask layer that expose the surface of the substrate. The openings in the mask layer are the openings that enable the nanowires / nanocones to nucleate (usually epitaxially) from the substrate. Preferably, one nanowire or nanocone grows from each opening.

[0070] Patterning

[0071] The nanowires or nanocones initially grow or nucleate from the substrate. This occurs from / through the openings present in the mask layer. These openings can be in the form of (intentionally) patterned holes in the mask layer. Fabricating these holes is a well-known process and can be carried out using electron beam lithography and etching or any other known technique. Using conventional lithography techniques, such as photo / electron beam lithography, nanoimprinting, etc., the hole patterns in the mask can be easily fabricated. Focused ion beam techniques can also be used to generate a regular array of nucleation sites on the substrate surface for the growth of nanowires or nanocones. The holes generated in the mask layer and the seed layer can be arranged in any desired pattern.

[0072] The diameter of the holes is preferably up to 500 nm, such as up to 100 nm, ideally up to 20 to 200 nm. The diameter of the holes sets the maximum diameter of the nanowires or nanocones during the initial growth. However, by changing the growth parameters or by adopting a core-shell nanowire or nanocone geometry, nanowire or nanocone diameters larger than the hole size can be achieved. Preferably, the nanowires or nanocones extend laterally (i.e., radially) on the mask outside the holes.

[0073] The number of holes is a function of the area of the desired nanowires or nanocones and the desired nanowire or nanocone density.

[0074] The shape of the holes is not restricted. Although these holes can be circular, they can also be other shapes, such as triangular, rectangular, elliptical, etc. A "hole" is generally defined herein as having a minimum lateral dimension within 75% of its longest lateral dimension. The mask layer can be in electrical contact with the base of the nanowire or nanocone, which is useful when the mask layer serves as an electrode.

[0075] When the nanowire or nanocone begins to grow within the hole, this tends to ensure that the initial growth of the nanowire or nanocone is epitaxial and substantially perpendicular to the substrate. This is another preferred feature of the present invention.

[0076] Defect opening

[0077] The openings in the mask layer can also be defects in the mask layer. The defects can be formed during mask growth / fabrication or during nanowire / nanocone growth. The openings can be any type of defect, such as a point, grain boundary, region, or crack defect in the mask layer (see Qin et al., Journal of Applied Mechanics 2020, vol 87, 030802-1 to 030802-11). Defect openings are typically randomly located and are generally smaller than the positioned / patterned holes. In this case, the defect openings can have any size and any shape. The defect openings expose the surface of the substrate and enable the nanowire / nanocone to nucleate from the substrate, typically epitaxially.

[0078] As described above, the defects can be pre-existing defects in the mask layer. They can also be defects formed during nanowire / nanocone growth, for example, by annealing or external or in-situ plasma.

[0079] Point defects can be vacancies, dislocations, or S-W defects (Stone-Wales defects). A vacancy is the absence of one or more atoms in the crystal structure of the mask layer. A single vacancy is the absence of a single atom, while a double vacancy is the absence of a pair of atoms. Dislocations in graphene are typically pentagon-heptagon (5|7) pairs. S-W defects are topological defects formed without adding atoms to eliminate. In graphene, an S-W defect converts four adjacent hexagons into two pentagons and two heptagons (5|7|7|5). The heptagon can serve as an opening for the nanowire / nanocone to nucleate.

[0080] Grain boundary defects are the interfaces between two adjacent grains in the mask layer and are typically an array of dislocations arranged in a linear manner.

[0081] In this article, a region defect means a hole typically formed by the coalescence of multiple vacancies.

[0082] Crack defects are cracks in the mask layer. Therefore, it is usually elongated.

[0083] Substrate

[0084] Nanowires and nanocones typically grow initially from a substrate, and thus preferably, the substrate is a crystalline substrate.

[0085] The substrate can have a crystal orientation of

[111] ,

[110] ,

[100] , or

[0001] perpendicular to the surface.

[100] and

[111] are preferred, for example, for cubic semiconductors such as Si and GaAs. Commercially,

[100] is preferred, but for NW / NP growth,

[111] is preferred.

[0001] is also preferred, typically for SiC or III-N substrates. Thus, the substrate can be

[100] silicon or

[111] silicon.

[0086] The substrate can be selected from silicon, Ge, SiC, Ga2O3, or III-V substrates. The III-V materials described for nanowires / nanocones are also applicable to III-V substrates, and thus the definition of III-V materials for nanowires / nanocones also applies to V-V substrates. As the substrate, silicon is preferred. Silicon is an inexpensive and versatile substrate that can be easily manipulated. It also provides good protection for the mask and prevents oxidation (e.g., graphene oxidation if graphene is used). In particular, for example, it is more readily available than III-V semiconductor substrates. The combination of a silicon substrate and a graphene mask layer is advantageous because excellent SAG can be achieved for III-V materials, especially Ga-V materials such as GaAs, GaN, GaSb, and GaP. The silicon substrate is also non-polar, which is beneficial for suppressing nucleation on the graphene mask during SAG of nanowires / nanocones. The substrate in the present invention is doped, i.e., n-doped or p-doped, typically p-type doped. Preferably, it is highly doped (thus labeled "n++" or "p++"). The doped substrate is generally used as a current injector. The doped substrate can be an electron injector (if n-doped, such as an "n++" Si substrate) or a hole injector (if p-doped, such as a "p++" Si substrate). A high doping level is beneficial because it will reduce the barrier height and facilitate (increase) the vertical tunneling current between the substrate and the nanowires / nanocones. In addition, substrates such as silicon can accommodate high doping levels, thereby increasing current injection and device efficiency. One advantage of the present invention is that when a highly doped substrate (e.g., p++ Si) is used, since the doping density of the substrate is much higher than the doping density in the NW / NP core, hole injection can be much larger than expected (as long as effective tunneling occurs through the mask layer). For example, compared with p-GaN NW / NP, the p++ silicon substrate can be doped to a much higher level.

[0087] Doping of the substrate generally involves introducing impurity ions. The doping level can be controlled at about 1015 / cm 3 to 10 22 / cm 3 , for example 10 18 / cm 3 to 10 21 / cm 3 (These numbers refer to the number of dopants / impurity ions per cm 3 .) In a particular embodiment, the substrate is highly doped, for example having at least 10 15 / cm 3 , preferably at least 10 16 / cm 3 , preferably at least 10 17 / cm 3 , preferably at least 10 18 / cm 3 , preferably or at least 10 19 / cm 3 doping level. The substrate can be p-type doped or n-type doped. For applications such as UVC LEDs, the substrate is preferably p-type doped, but for other applications such as UVA / visible LEDs or photodetectors, the substrate is preferably n-type doped.

[0088] When the substrate is p-type doped, suitable acceptors for the substrate can be boron, aluminum, gallium, indium. Thus, the substrate can be doped with at least one of boron, aluminum, gallium or indium, preferably doped with boron. For an n-type substrate, suitable donors can be phosphorus, arsenic or antimony, preferably phosphorus. Thus, the substrate can be doped with at least one of phosphorus, arsenic or antimony. The dopant can be introduced during growth or can be introduced by ion implantation after the substrate is formed.

[0089] In the case of a silicon substrate, there is usually a natural SiO2 layer on the silicon substrate. Thus, in the present invention, the term "silicon substrate" does not exclude the presence of a very thin SiO2 layer on top of the substrate (i.e., at the interface with the graphene mask in the compositions / devices of the present invention). Thus, in a particular embodiment, the silicon substrate comprises this natural SiO2 layer. The thickness of the top natural SiO2 layer is typically less than 20 nm, preferably less than 10 nm, preferably less than 5 nm, preferably less than 3 nm, preferably less than 2 nm, preferably less than 1.9 nm, preferably less than 1 nm, for example 1-5 nm, 1-2 nm or 2-3 nm. Since the SiO2 layer is insulating, the vertical current from the Si substrate can only occur by tunneling, and the vertical tunneling current increases as the thickness of the natural SiO2 layer decreases. Thus, the inventors surprisingly found that this insulating layer together with the mask layer can form a conduction path. In addition, the inventors surprisingly found that compared to nanowires grown on a Si substrate without a graphene mask layer (i.e., 2.0-2.5 mm), when nanowires (such as GaN nanowires) are grown on a Si substrate in the presence of a graphene mask, the oxide at the nanowire / silicon interface is much thinner (i.e., 1.0-1.5 mm) (the structures depicted in FIGS. 6c and 6d). In addition, compared to the absence of a graphene mask, in the presence of a graphene mask layer, the conduction path between the n-doped nanowire and the n++-doped Si substrate is more efficient ( Figure 6e ).

[0090] The substrate can be used as a current injector. For example, it is much easier to fabricate electrical contacts on the substrate than on graphene. Some of the substrate can simply be etched away and a metal attached as the electrical contact. It may be difficult to fabricate electrical contacts on graphene or other graphene-like materials. In a particular embodiment, the substrate has electrical contacts (usually metallic), preferably contacts on the top side of the substrate (i.e., the same side as the NW / NP). For example, a portion of the top surface of the substrate can be etched away to connect the electrical contacts. The electrical contacts enable vertical hole tunneling injection or vertical electron tunneling injection. Thus, the substrate can be / used as an electrode.

[0091] In another embodiment, nanowires or nanocones can be grown on a substrate and then removed (e.g., exfoliated) from the substrate and transferred to a different substrate. The removal can be carried out via etching, lift-off, delamination, or electrochemical removal / exfoliation. The mask layer can be removed from the substrate in combination with the nanowires or nanocones, or the nanowires or nanocones can be removed from the substrate and the mask layer. The nanowires or nanocones removed from the original substrate can be transferred to a new substrate (optionally together with the removed mask layer). The new substrate can include any of the features of the substrates described herein. Alternatively, the new substrate can include a doped or conductive substrate, such as a metal (such as Co, Ti, Mo, stainless steel) that can be used as an electrical contact. The new substrate can be rigid or a thin film to allow for flexible devices. The electrical contact can enable vertical charge carrier tunneling injection to / from the doped / conductive substrate. Thus, the doped / conductive substrate can be used as an electrode.

[0092] For example, in the case of a metal substrate, the high conductivity of the substrate is also beneficial in terms of applying tunneling through the mask layer.

[0093] Accordingly, the present invention provides a composition of matter that comprises

[0094] a metal substrate;

[0095] a mask layer having a thickness of less than 2 nm on top of the substrate,

[0096] wherein there are a plurality of openings through the mask layer; and wherein

[0097] there are a plurality of nanowires or nanocones on the substrate in the openings, the nanowires or nanocones comprising at least one semiconductor group III-V compound

[0098] In this case, the metal substrate is a conductive metal and is different from the semiconductor. The nanowires or nanocones are located on the substrate and are generally in direct electrical contact with the substrate. The same considerations regarding their positioning on the metal substrate (e.g., perpendicular to the substrate) are the same as for the doped substrate.

[0099] In this embodiment, the same characteristics of the mask layer, nanowires / nanocones, devices, etc. apply to the embodiment in the case of a doped substrate, but for the sake of brevity, they are not repeated here.

[0100] The same considerations also apply to any merged structure, i.e., a non-planar film formed by the continuous merging of nanostructures or group III-Vs.

[0101] nanowires / nanocones

[0102] Where technically feasible, any discussion of nanowires (NWs) in this document equally applies to nanopyramids (NPs). The discussion of NWs / NPs can refer to the NW / NP core, or a combination of the core and additional layers located thereon.

[0103] To prepare nanowires or nanopyramids of commercial importance, preferably, these are epitaxially grown on a substrate. It is also desirable if the growth occurs perpendicular to the substrate and ideally along the

[111] (for cubic crystal structures) or

[0001] (for hexagonal crystal structures) directions. The phrase "growing from the substrate in the opening" means that the NW / NP is located above the opening and a portion of the nanowire / nanopyramid extends (downward) into the opening to the substrate, preferably with the NW / NP forming an epitaxial relationship with the substrate. Alternatively, the NW / NP is present in the opening of a mask layer. Alternatively, the nanowire / nanopyramid nucleates from or extends from the opening in the mask layer.

[0104] In grown nanopyramids, the triangular faces typically terminate in the (1-101) or (1-102) planes. The triangular side faces with (1-101) facets can converge to a single point at the tip, or can form new facets (1-102) before converging at the tip. In some cases, the nanopyramid is truncated at the top, where its top terminates in the {0001} plane.

[0105] Preferably, the nanowire and / or nanopyramid has a tapered tip.

[0106] Although it is desirable to have no lattice mismatch between the grown nanowire or nanopyramid and the substrate layer, the nanowire or nanopyramid can accommodate more lattice mismatch than, for example, a thin film.

[0107] The growth of the NW / NP can be controlled by the flux ratio. For example, if a high group V flux is employed, nanopyramids are promoted.

[0108] The grown nanowires can be said to be essentially in a one-dimensional form, where their width or diameter is on the nanoscale and their length is typically in the range of a few hundred nanometers to a few micrometers. Ideally, the nanowire diameter is no greater than 500 nm. Ideally, the nanowire diameter is 50 to 500 nm; however, the diameter can exceed a few micrometers (referred to as microfilaments).

[0109] Thus, the length of the grown nanowires in the present invention can be from 250 nm to a few micrometers, for example up to 5 micrometers. Preferably, the length of the nanowire is at least 1 micrometer. In the case of growing multiple nanowires, it is preferred if they all meet these size requirements. Ideally, at least 90% of the length of the nanowires grown on the substrate will be at least 1 micrometer. Preferably, substantially all of the nanowires will have a length of at least 1 micrometer.

[0110] The height of the nanocones can be from 250 nm to 1 micrometer, such as from 400 to 800 nm in height, for example, about 500 nm.

[0111] In addition, it will be preferred if the grown nanowires or nanocones have the same dimensions, such as within 10% of each other. Thus, at least 90% (preferably substantially all) of the nanowires or nanocones on the substrate will preferably have the same diameter and / or the same length (i.e., the diameter / length within 10% of each other). Thus, in essence, those skilled in the art are looking for uniformity and nanowires or nanocones that are substantially the same in terms of size.

[0112] The length of the nanowires or nanocones is generally controlled by the length of time the growth process runs. A longer process generally results in longer (much longer) nanowires.

[0113] The nanowires or nanocones generally have a hexagonal cross-sectional shape. The cross-sectional diameter of the nanowires can be from 25 nm to several micrometers (i.e., their thickness). As noted above, ideally, the diameter is constant in most of the nanowires. The nanowire diameter can be controlled by manipulating growth parameters, such as the substrate temperature and / or the atomic ratio used to fabricate the nanowires, as described further below.

[0114] In addition, the length and diameter of the nanowires or nanocones are affected by the temperature at which they are formed. Higher temperatures promote high aspect ratios (i.e., longer and / or thinner nanowires). Those skilled in the art can manipulate the growth process to design nanowires or nanocones of the desired size.

[0115] The nanowires or nanocones of the present invention are formed from at least one III-V compound, preferably a III-N compound. Group III options are B, Al, Ga, In, and Tl. The preferred options here are Ga, Al, and In.

[0116] Group V options are N, P, As, Sb. All are preferred. N is particularly preferred.

[0117] Of course, more than one group III element and / or more than one group V element can be used. The compound can be binary, ternary, quaternary, quinary, etc. Preferred compounds for nanowire or nanocone fabrication include AlAs, GaSb, GaP, GaN, AlN, AlGaN, AlGaInN, GaAs, InP, InN, InGaN, InGaAs, InSb, InAs, or AlGaAs. Compounds based on Al, Ga, and In combined with N are an option. Use of GaN, AlGaN, AlInGaN, or AlN is highly preferred. The above and below apply to both the nanowire / nanocone core and any intrinsic or doped layer on / around the top of the core. Generally, at least one of the intrinsic or doped layers on / around the top of the core is a ternary or quaternary compound layer, such as AlGaN.

[0118] Any additional layer on / around the top of the nanowire / nanocone core has an individual thickness in the range of 10 - 1000 nm.

[0119] It is most preferred if the nanowire or nanocone consists of Ga, Al, In, and N (along with any doping atoms discussed below).

[0120] The ternary compound can be of the formula XYZ, where X is a group III element, Y is a group III element different from X, and Z is a group V element. The molar ratio of X to Y in XYZ is preferably from 0.1 to 0.9, i.e., the formula is preferably X x Y 1-x Z, where the subscript X is from 0.1 to 0.9.

[0121] A quaternary system can also be used and can be represented, for example, by the formula A x B 1-x C y D 1-y (where A and B are group III elements, C and D are group V elements), or represented by the formula A x B y C 1-x-y D (where A, B, and C are group III elements and D is a group V element). Again, the subscripts x and y are generally from 0.1 to 0.9. Other options will be clear to the person skilled in the art.

[0122] While ternary / quaternary nanowires or nanocones can be used, binary materials such as GaN are preferably used for the nanowire core. Thus, the nanowire / nanocone can comprise GaN, such as n-GaN or p-GaN, preferably p-GaN. This is particularly preferred for UVC / UVB devices. The nanowire or nanocone core can comprise GaN, such as n-GaN or p-GaN, preferably p-GaN, or consist thereof. GaN has been shown to grow particularly well by SAG on graphene hole masks and form a good interface with graphene (outside the graphene openings). When Al is present in the core, the results are usually less good due to lower growth selectivity. Thus, it is preferred if the nanowire / nanocone core does not contain Al. Nanocones of Al-containing materials can be used to promote NW / NP nucleation (e.g., Al(Ga)N nanocones).

[0123] When GaN (such as n-GaN or p-GaN) is used for the nanowire / nanocone, good conduction is observed from the substrate, through the graphene mask, and through the nanowire.

[0124] As previously discussed, the nanowires / nanocones of the present invention generally extend on the surface of the mask layer. They grow / extend laterally (i.e., in the same plane as the substrate / mask) such that only the interior of the NW / NP core is formed over the openings masked by the mask layer. The NW / NP can grow out of the openings of the mask and then grow laterally (i.e., radially) to cover at least a portion of the top surface of the mask layer.

[0125] Doping

[0126] The nanowires or nanocones of the present invention can comprise p-n, n-p, n-i-p, or p-i-n junctions, such as to enable their use in LEDs. The nanowire or nanocone core generally has the same doping type as the substrate (e.g., if the substrate is n-type doped, then the nanowire or nanocone core will be n-type, and vice versa). These can be in the form of additional layers on or around the NW / NP core. Thus, the NW or nanocone of the present invention optionally has an undoped intrinsic semiconductor region disposed between a p-type semiconductor and an n-type semiconductor region. The intrinsic region can consist of a single layer of material or a heterostructure consisting of multiple quantum wells and barriers.

[0127] Thus, preferably, the nanowire or nanocone is doped. Preferably, the core and at least one additional layer on / around the core are doped. For example, during MBE or MOVPE growth, doping generally involves introducing impurity ions into the nanowire. The doping level can be controlled at about 10 15 / cm 3 to 10 20 / cm 3As needed, the nanowires or nanocones can be p-type doped or n-type doped. As described above, the nanowire / nanocone core can be, for example, p-doped, such as p-GaN. This is particularly preferred for UVC / UVB devices.

[0128] By doping an intrinsic semiconductor with donor (acceptor) impurities, the electron (hole) concentration in the n(p)-type semiconductor is greater than the hole (electron) concentration. Suitable donors (acceptors) for III-V compounds can be Te, Sn, Si (Be, Mg, and Zn). Silicon can be amphoteric (donor or acceptor), depending on the site where silicon goes, depending on the orientation of the growth surface, and the growth conditions. Dopants can be introduced by ion implantation during the growth process or after the formation of the nanowires or nanocones.

[0129] Higher carrier injection efficiency is required to obtain a higher external quantum efficiency (EQE) of the LED.

[0130] The nanowires / nanocones can include, for example, additional n, i-n, p-, i-p, n-i-p, or p-i-n layers located on or around the top of the NW / NP, preferably additional p-i-n or additional n-i-p layers. The nanowires / nanocones can also include, for example, p-AlGaN, i-AlGaN, and n-AlGaN layers (e.g., in this order, where p-AlGaN is adjacent to the core, such as a p-GaN core). Thus, in a particular embodiment, the nanowire or nanocone includes a p-GaN core or consists of a p-GaN core, and also has p-AlGaN, i-AlGaN, and n-AlGaN layers thereon. At least one of these layers, such as the top n-AlGaN layer, can continuously extend over multiple underlying layers and the NW / NP core.

[0131] The top layer (e.g., an n-type layer, preferably n-AlGaN) can be used as a top-emitting transparent electrode. Transparent here means transparent to the light emitted by the nanowires / nanocones. For example, in the case of a UV-C LED, this layer is at least transparent to UV-C light. In the case of a photodetector, transparent means transparent to any incident light. For example, if the composition / device is a solar cell, then transparent means at least transparent to sunlight.

[0132] The nanowires / nanocones generally have Al-containing layers. As the Al content in the AlGaN alloy increases, the ionization energy of the Mg acceptor increases, which makes it difficult to obtain a high hole concentration in the AlGaN alloy with a high Al content. To obtain a high hole injection efficiency (especially in the cladding / barrier layer composed of a high Al content), the inventors have designed many strategies that can be used alone or together.

[0133] Therefore, there are problems to be overcome during the doping process. It is preferred if the nanowires or nanocones of the present invention contain Al, for example, in at least one layer. Using Al is advantageous because a high Al content results in a high bandgap, enabling UV-C LED emission from the active layer(s) of the nanowires or nanocones and / or avoiding absorption of the emitted light in the doped cladding / barrier layer. In the case of a high bandgap, UV light is less likely to be absorbed by this part of the nanowires or nanocones. Therefore, it is preferred to use AlN or AlGaN in the nanowires or nanocones.

[0134] However, p-type doping of AlGaN or AlN for achieving high conductivity (high hole concentration) is challenging because the ionization energy of Mg or Be acceptors increases as the Al content in the AlGaN alloy increases. The present inventors have proposed various solutions to maximize the conductivity (i.e., maximize the hole concentration) in AlGaN alloys with a higher average Al content.

[0135] When one of the layers / regions of the nanowires or nanocones contains AlN or AlGaN, it is a challenge to achieve high conductivity by introducing p-type dopants.

[0136] One solution relies on short-period superlattices (SPSLs). In this approach, we grow a superlattice structure consisting of alternating layers with different Al contents (instead of a uniform AlGaN layer with a higher Al composition). For example, a cladding layer with a 35% Al content can be replaced by an SPSL that is 1.8 to 2.0 nm thick and consists of, for example, alternating Al x Ga 1-x N:Mg / Al y Ga 1-y N:Mg (where x = 0.30 / y = 0.40). The low ionization energy of acceptors in the layer with a lower Al composition leads to improved hole injection efficiency without sacrificing the barrier height in the cladding layer. The polarization field at the interface further enhances this effect. For better hole injection, the SPSL can be followed by a highly p-doped GaN:Mg layer.

[0137] More generally, the inventors propose using p-type doped Al x Ga 1-x N / Al y Ga 1-y N short-period superlattices (i.e., alternating thin layers of Al x Ga 1-x N and Al y Ga 1-y N) (instead of p-type doped Al z Ga 1-zAn alloy of AlxGay - zNz (where x < z < y) is introduced into (or onto) the nanowire or nanocone structure, where the molar fraction x of Al is less than y. It should be understood that x can be as low as 0 (i.e., GaN) and y can be as high as 1 (i.e., AlN). The superlattice period should preferably be less than 5 nm, such as 2 nm, in which case the superlattice will act as a single Al z Ga 1- z Gay - zNz alloy (where z is the layer - thickness - weighted average of x and y), but due to the higher p - type doping efficiency of the AlxGay - zNz layers with lower Al content, the superlattice has a higher conductivity than the Al x Ga 1-x Gay - zNz alloy. z Ga 1-z In nanowires or nanocones containing a p - type - doped superlattice, it is preferred if the p - type dopant is an alkaline earth metal (such as Mg or Be).

[0138] Another option for solving the doping problem of Al - containing nanowires / nanocones follows a similar principle. Instead of a superlattice containing thin AlGaN layers with low or no Al content, a nanostructure can be designed that contains a gradient of Al content (molar fraction) in the growth direction of AlGaN within the nanowire or nanocone. Thus, as the nanowire or nanocone grows, the Al content decreases / increases and then increases / decreases again to create an Al - content gradient within the nanowire or nanocone.

[0139] This can be referred to as polarization doping. In one method, these layers are graded from GaN to AlN or from AlN to GaN. The graded regions from GaN to AlN and from AlN to GaN may result in n - type and p - type conduction, respectively. This may be due to the presence of dipoles with different magnitudes compared to their adjacent dipoles. The graded regions from GaN to AlN and from AlN to GaN can be additionally doped with an n - type dopant and a p - type dopant, respectively.

[0140] In a preferred embodiment, Be is used as a dopant for p - type doping in AlGaN nanowires.

[0141]

[0142] ​Thus, one option would be to start with GaN nanowires / nanopyramids, gradually increasing the Al content and decreasing the Ga content to form AlN, perhaps with a growth thickness of more than 100 nm. This graded region can be used as a p-type or n-type region, depending respectively on the crystal plane, polarity, and whether the Al content in the graded region decreases or increases. Then, the reverse process is carried out to produce GaN again to create an n-type or p-type region (opposite to the previously prepared region). These graded regions can be additionally doped with n-type dopants (such as Si) and p-type dopants (such as Mg or Be) to obtain n-type or p-type regions with high carrier densities respectively. The crystal plane and polarity are determined by the type of nanowires / nanopyramids known in the art.

[0143] Thus, from another aspect, the nanowires or nanopyramids of the present invention contain Al, Ga, and N atoms, wherein during the growth of the nanowires or nanopyramids, the concentration of Al changes to create an Al concentration gradient within the nanowires or nanopyramids.

[0144] In a third embodiment, the problem of doping in Al-containing nanowires or nanopyramids is solved using a tunnel junction. A tunnel junction is a barrier between two conductive materials, such as a thin layer. In the context of the present invention, the barrier acts as an ohmic electrical contact in the middle of a semiconductor device.

[0145] In one method, a thin electron blocking layer is inserted immediately after the active region, followed by a p-type doped AlGaN cladding layer having an Al content higher than that used in the active layer. After the p-type doped cladding layer is a highly p-type doped cladding layer and a very thin tunnel junction layer, followed by an n-type doped AlGaN layer. The tunnel junction layer is selected such that electrons tunnel from the valence band in p-AlGaN to the conduction band in n-AlGaN, thereby generating holes injected into the p-AlGaN layer.

[0146] In a specific embodiment, the nanowires or nanopyramids contain two doped GaN regions (one p-doped region and one n-doped region) separated by an Al layer (such as a very thin Al layer). The thickness of the Al layer can be a few nanometers, for example, 1 to 10 nm. It should be understood that there are other alternative materials that can be used as a tunnel junction including a highly doped InGaN layer.

[0147] Surprisingly, the doped GaN layer can be grown on the Al layer.

[0148] Thus, in one embodiment, the present invention provides a nanowire or nanopyramid having a p-type doped (Al)GaN region and an n-type doped (Al)GaN region separated by an Al layer.

[0149] The nanowires or nanocones of the present invention can grow radially or axially into a heterostructure form. For example, for axially heterostructured nanowires or nanocones, a p-n junction can be axially formed by first growing a p-type doped core and then continuing to grow an n-type doped core (or vice versa). For radially heterostructured nanowires or nanocones, a p-n junction - core-shell nanowire can be radially formed by first growing a p-type doped nanowire or nanocone core and then growing an n-type doped semiconductor shell (or vice versa). The core can also be axially heterostructured and the shell can be radially heterostructured. An intrinsic shell can be placed between the doped regions of the p-i-n nanowire. The NW or nanocone grows axially or radially and thus consists of a first part and a second part. These two parts are doped differently to produce a p-n junction or a p-i-n junction. The first part or the second part of the NW or nanocone is a p-type doped part or an n-type doped part. The nanowire or nanocone can also have a combined axial and radial heterostructure and have additional doped cores or shell layers, thus forming, for example, a p-p-i-n junction (see Figure 3 and Figure 4 ).

[0150] However, it is particularly preferred if the NW / NP core has a conical tip and any additional p / i / n layers reflect the morphology (i.e., shape) of the underlying core. The additional layers (which can be considered as part of forming the nanowire / nanocone) can be restricted to the width of the NW / NP, or they can be in the form of a layer that continuously covers at least a part of a plurality of nanowires / nanocones. In a particular embodiment, at least one of the layers continuously covers at least a part of the nanowire / nanocone (i.e., the NW / NP core, where there may be a potential intermediate layer between the NW / NP core and the top continuous layer). The layer (s) that continuously cover at least a part of the NW / NP can be continuous in its upper region but can have voids in its lower region. The top layer (e.g., the top n layer) can be continuous, for example, it can cover at least 50% of the nanowire or nanocone, such as at least 75%, at least 90% or at least 99% of the nanowire. This is beneficial because the doped top layer (e.g., the n layer) can be used as a transparent current spreader, which has an acceptable sheet resistance when the continuous layer is not too thick. Preferably, the top layer has a thickness of 100 - 2000 nm, such as 500 nm. The layers below the top layer (e.g., the i layer and below) can be continuous, or they can be discontinuous (i.e., restricted to the width of the NW / NP).

[0151] epitaxy

[0152] The nanowires or nanocones of the present invention are preferably epitaxially grown on a substrate through openings in a mask layer. They are attached to the underlying substrate by covalent bonding. Thus, at the junction of the substrate and the base of the nanowire, crystal planes are formed epitaxially with the nanowire. These are stacked one after another in the same crystallographic direction, thus allowing the epitaxial growth of the nanowire. Preferably, the nanowires or nanocones grow vertically. The term "vertically" here is used to mean that the nanowires or nanocones grow perpendicular to the support. It should be understood that in experimental science, the growth angle may not be exactly 90°, but the term "vertically" means that the nanowires or nanocones are within about 10° of vertical / vertical, for example within 5°. Due to epitaxial growth via covalent bonding, close contact between the nanowire or nanocone and the substrate is expected.

[0153] As previously discussed, the nanowires / nanocones of the present invention generally extend on the surface of the mask. Even in the presence of an intermediate mask layer, the epitaxial relationship between the NW / NP core and the substrate is maintained. Thus, in a particular embodiment, the crystal structure of the NW / NP core matches the crystal structure of the substrate (i.e., there is an epitaxial relationship between the two). In a particular embodiment, there is no epitaxial relationship between the NW / NP core and the mask layer. The nucleated NW / NPs maintain their crystal orientation (epitaxial with the substrate) when laterally diffusing on the mask layer. The interaction between the NW / NP and the mask layer is typically through van der Waals forces (very weak bonding).

[0154] Thus, the nanowires / nanocones can be grown such that the crystal orientation and facet orientation of the nanowires or nanocones are guided by the crystalline substrate. Thus, the crystal orientation and facet orientation of all nanowires / nanocones are the same.

[0155] Surprisingly, it has been found that the conduction from the substrate through the mask is better than through the openings in the mask. Graphene and other graphene-like materials (when appropriately thin) are used as efficient tunneling barriers. Thus, the radial extension of the nanowires / nanocones on the top surface of the mask layer improves the electrical efficiency of the device.

[0156] It should be understood that the substrate contains a plurality of nanowires or nanocones. Preferably, the nanowires or nanocones grow substantially parallel to each other. Thus, preferably at least 90%, for example at least 95%, preferably substantially all of the nanowires or nanocones grow in the same direction from the same plane of the substrate.

[0157] It should be understood that there are many planes within the substrate from which epitaxial growth can occur. Preferably, substantially all of the nanowires or nanocones grow from the same plane. If this plane is parallel to the substrate surface, it is preferred. Ideally, the grown nanowires or nanocones are substantially parallel. Preferably, the nanowires or nanocones grow substantially perpendicular to the substrate.

[0158] For nanowires or nanocones with a cubic crystal structure, the nanowires of the present invention should preferably grow along the

[111] direction, and for nanowires or nanocones with a hexagonal crystal structure, they should preferably grow along the

[0001] direction. If the crystal structure of the grown nanowires or nanocones is cubic, the (111) interface between the nanowires or nanocones and the substrate represents the plane for axial growth. If the nanowires or nanocones have a hexagonal crystal structure, the (0001) interface between the nanowires or nanocones and the substrate represents the plane for axial growth. Planes (111) and (0001) both represent the same (hexagonal) plane of the nanowire, but the naming of the plane varies depending on the crystal structure of the grown nanowire.

[0159] The nanowires or nanocones are preferably grown by MBE or MOVPE. In the MBE method, molecular beams of each reactant are provided to the substrate, such as group III elements and group V elements preferably supplied simultaneously. Higher degrees of control over the nucleation and growth of the nanowires or nanocones on the substrate can be achieved by MBE techniques using migration enhanced epitaxy (MEE) or atomic layer MBE (ALMBE), where group III and group V elements can be supplied alternately, for example.

[0160] A preferred technique is solid source MBE, where very pure elements such as gallium and arsenic are heated in separate effusion cells until they start to slowly evaporate (e.g., gallium) or sublime (e.g., arsenic). Then, the gaseous elements condense on the substrate, where they can react with each other. In the example of gallium and arsenic, single crystal GaAs is formed. The use of the term "beam" means that the evaporated atoms (e.g., gallium) or molecules (e.g., As4 or As2) do not interact with each other or with the vacuum chamber gas before they reach the substrate.

[0161] MBE is carried out in ultra-high vacuum, where the background pressure is typically around 10 -10 to 10 -9 torr. The nanostructures typically grow slowly, for example at a rate of at most a few nanometers per hour, such as about 10 μm per hour. This allows for epitaxial growth of the nanowires or nanocones and maximizes the structural properties.

[0162] In the MOVPE method, the substrate is held in a reactor where carrier gases and metalorganic gases of each reactant are provided to the substrate, such as metalorganic precursors containing group III elements and organic precursors containing group V elements preferably supplied simultaneously. Typical carrier gases are hydrogen, nitrogen, or a mixture of both. Higher degrees of control over the nucleation and growth of the nanowires or nanocones on the substrate can be achieved by MOVPE techniques using pulsed layer growth techniques, where group III and group V elements can be supplied alternately, for example.

[0163] The epitaxial growth of nanowires or nanopyramids provides homogeneity to the resulting material, which can enhance various end properties, such as structural, mechanical, optical, or electrical properties.

[0164] Epitaxial nanowires or nanopyramids can be grown from gaseous, liquid, or solid precursors. Since the substrate serves as a seed crystal, the deposited nanowires or nanopyramids can exhibit a lattice structure and orientation similar to that of the substrate. Epitaxy is different from other thin-film deposition methods for depositing polycrystalline or amorphous films, even on single-crystalline substrates.

[0165] Selective area growth of nanowires or nanopyramids

[0166] For example, in the case of III-nitride nanowires, the nanowires or nanopyramids of the present invention can be grown by a selective area growth (SAG) method. In the case of MBE in the growth chamber or in the case of MOVPE in the reactor, the substrate temperature can be set to a temperature suitable for the growth of the nanowires or nanopyramids under discussion. In the case of MBE, the growth temperature can be in the range of 300 to 1000 °C. However, the temperature employed is specific to the nature of the material in the nanowire. For GaN, the preferred temperature is 700 to 950 °C, such as 800 to 900 °C, such as 810 °C. For AlGaN, the range is slightly higher, for example, 800 to 980 °C, such as 830 to 950 °C, such as 850 °C.

[0167] Therefore, it should be understood that the nanowires or nanopyramids can contain different III-V semiconductors within the nanowire, for example, starting from a GaN backbone and then an AlGaN composition or an AlGaInN component, etc.

[0168] The growth of doped GaN nanowires or nanopyramids can be initiated by simultaneously opening the shutters of the Ga effusion cell, the nitrogen plasma cell, and the dopant cell to initiate nanowire growth, herein referred to as the backbone. The length of the GaN backbone can be maintained between 10 nm and several hundred nanometers. Subsequently, if desired, the substrate temperature can be increased, and the aluminum shutter can be opened to initiate the growth of AlGaN nanowires or nanopyramids. The growth of AlGaN nanowires or nanopyramids can be initiated on the substrate without growing the GaN backbone, but the GaN backbone is preferred. During the growth of the nanowires or nanopyramids, n- and p-doped nanowires or nanopyramids can be obtained by opening the shutters of the n-dopant cell and the p-dopant cell, respectively. For example: an n-doped Si dopant cell for the nanowires or nanopyramids, and a p-doped Mg dopant cell for the nanowires and nanopyramids.

[0169] The temperature of the effusion cell can be used to control the growth rate. A convenient growth rate, as measured during conventional planar (layer-by-layer) growth, is from 0.05 to 2 μm per hour, for example 0.1 μm per hour. The Al / Ga ratio can be varied by changing the temperature of the effusion cell.

[0170] The pressure of the molecular beam can also be adjusted depending on the nature of the nanowires or nanocones being grown. A suitable level of the beam equivalent pressure is between 1×10 -7 and 1×10 -4 Torr.

[0171] The beam flux ratio between the reactants (e.g., group III atoms and group V molecules) can be varied, and the preferred flux ratio depends on other growth parameters and the nature of the nanowires or nanocones being grown. In the case of nitrides, the nanowires or nanocones are always grown under nitrogen-rich conditions.

[0172] One embodiment of the present invention is to employ a multi-step (e.g., two-step) growth procedure, for example to separately optimize nanowire or nanocone nucleation and nanowire or nanocone growth.

[0173] In the case of MOVPE, a significant benefit is that the nanowires or nanocones can be grown at a much faster growth rate. This method is advantageous for the growth of radial heterostructure nanowires or nanocones and microfilaments, such as: an n-doped GaN core with a shell composed of an intrinsic AlN / Al(In)GaN multiple quantum well (MQW), an AlGaN electron blocking layer (EBL), and a p-doped (Al)GaN shell. This method also allows the growth of axial heterostructure nanowires or nanocones using techniques such as pulsed growth techniques or a continuous growth mode (which has modified growth parameters, such as a lower V / III molar ratio and a higher substrate temperature).

[0174] More specifically, after placing the sample, the reactor must be evacuated and purged with N2 to remove oxygen and water in the reactor. This is to avoid any damage to the mask layer (e.g., graphene) at the growth temperature and to avoid unnecessary reactions of oxygen and water with the precursors. The total pressure is set to 50 to 400 Torr. After purging the reactor with N2, the substrate is thermally cleaned at a substrate temperature of about 1200 °C in an H2 atmosphere. Then, the substrate temperature can be set to a temperature suitable for the growth of the nanowires or nanocones under discussion. The growth temperature can be in the range of 700 to 1200 °C. However, the temperature employed is specific to the nature of the material in the nanowires. For GaN, the preferred temperature is 800 to 1150 °C, for example 900 to 1100 °C, such as 1100 °C or 1000 °C. For AlGaN, the range is slightly higher, for example 900 to 1250 °C, such as 1050 to 1250 °C, for example 1250 °C or 1150 °C.

[0175] Metal-organic precursors for the growth of nanowires or nanocones can be trimethylgallium (TMGa) or triethylgallium (TEGa) (for Ga), trimethylaluminum (TMAl) or triethylaluminum (TEAl) (for Al), trimethylindium (TMIn) or triethylindium (TEIn) (for In). Precursors for dopants can be SiH4 (for silicon) and bis(cyclopentadienyl)magnesium (Cp2Mg) or bis(methylcyclopentadienyl)magnesium ((MeCp)2Mg) (for Mg). The flow rates of TMGa, TMAl, and TMIn can be maintained at 5 to 100 sccm. The NH3 flow rate can vary between 5 and 150 sccm.

[0176] In particular, the growth of nanowires or nanocones can be achieved simply by using vapor-solid growth. Thus, in the context of MBE, simply applying reactants (such as In and N) to the substrate without any catalyst can result in the formation of nanowires. This forms another aspect of the present invention, which thus provides for the direct growth of semiconductor nanowires or nanocones formed from the above elements on the substrate. Thus, the term direct means that there is no catalyst film to facilitate the growth.

[0177] Catalyst-assisted growth of nanowires or nanocones

[0178] The nanowires or nanocones of the present invention can also be grown in the presence of a catalyst. The catalyst can be introduced into these openings to provide nucleation sites for the growth of nanowires or nanocones. The catalyst can be one of the so-called self-catalytic elements that make up the nanowires or nanocones, or any element different from those that make up the nanowires.

[0179] For catalyst-assisted growth, the catalyst can be Au or Ag, or the catalyst can be a metal from the group used in the growth of nanowires or nanocones (such as group III metals), particularly one of the metal elements that make up the actual nanowires or nanocones (self-catalytic). Thus, another element from group III can be used as a catalyst for the growth of III-V nanowires or nanocones, for example, using Ga as a catalyst for Ga group V nanowires or nanocones, and so on. Preferably, the catalyst is Au or the growth is self-catalytic (i.e., Ga is used for Ga group V nanowires or nanocones, etc.). The catalyst can be deposited on a substrate patterned with holes through a mask and an optional mask layer to serve as nucleation sites for the growth of nanowires or nanocones. Ideally, this can be achieved by forming a thin film of catalytic material on the mask layer after etching holes in the layer. When the temperature is raised to the NW or nanocone growth temperature, the catalyst film melts and the catalyst forms nano-sized granular droplets on the substrate, and these droplets form the points where nanowires or nanocones can grow.

[0180] This is called vapor - liquid - solid growth (VLS) because the catalyst is liquid, the molecular beam is vapor, and the nanowire or nanocone provides the solid component. In some cases, the catalyst particles can also be solid during the growth of the nanowire or nanocone (by the so - called vapor - solid - solid growth (VSS) mechanism). As the nanowire or nanocone grows (by the VLS method), a liquid (e.g., gold) droplet remains at the top of the nanowire. After growth, it still remains at the top of the nanowire or nanocone and thus may play an important role in contacting the top electrode.

[0181] As described above, self - catalytic nanowires or nanocones can also be prepared. Self - catalytic means that one of the components in the nanowire or nanocone acts as a catalyst for its growth.

[0182] For example, a Ga layer can be coated onto a mask layer and melted to form droplets as nucleation sites for the growth of Ga - containing nanowires or nanocones. Similarly, the Ga metal portion can eventually be located at the top of the nanowire.

[0183] More specifically, in the case of NWs grown by MBE, a Ga / In flux can be supplied to the substrate surface for a period of time to start forming Ga / In droplets on the surface when the substrate is heated. Then, the substrate temperature can be set to a temperature suitable for the growth of the nanowire or nanocone under discussion. The growth temperature can be in the range of 300 to 700 °C. However, the temperature employed is specific to the nature of the materials in the nanowire, the catalyst material, and the substrate material. For GaAs, the preferred temperature is 540 to 630 °C, such as 590 to 630 °C, such as 610 °C. For InAs, the range is lower, e.g., 420 to 540 °C, such as 430 to 540 °C, such as 450 °C.

[0184] Once the catalyst film is deposited and melted, the growth of the nanowire can be initiated by simultaneously opening the shutters of the Ga / In effusion cell and the anti - ion effusion cell.

[0185] The temperature of the effusion cell can be used to control the growth rate. As measured during conventional planar (layer - by - layer) growth, a convenient growth rate is 0.05 to 2 μm per hour, such as 0.1 μm per hour.

[0186] The pressure of the molecular beam can also be adjusted depending on the nature of the nanowire or nanocone being grown. A suitable level of the beam equivalent pressure is 1×10 -7 to 1×10 -5 Torr.

[0187] The beam flux ratio between the reactants (e.g., group - III atoms and group - V molecules) can vary, and the preferred flux ratio depends on other growth parameters and the nature of the nanowire or nanocone being grown.

[0188] It has been found that the beam flux ratio between reactants affects the crystal structure of the nanowires. For example, using Au as a catalyst, at a growth temperature of 540 °C, a planar (layer-by-layer) growth rate of Ga flux equivalent to 0.6 μm per hour, and a beam equivalent pressure (BEP) of 9×10 -6 Torr (for As4), the growth of GaAs nanowires or nanocones produces a wurtzite crystal structure. In contrast, at the same growth temperature, but a planar growth rate of Ga flux equivalent to 0.9 μm per hour and a BEP of 4×10 -6 Torr (for As4), the growth of GaAs nanowires or nanocones produces a zinc blende crystal structure.

[0189] In some cases, the nanowire diameter can be changed by varying the growth parameters. For example, when growing self-catalytic GaAs nanowires or nanocones under conditions where the growth rate of the axial nanowires or nanocones is determined by the As4 flux, the diameter of the nanowires or nanocones can be increased / decreased by increasing / decreasing the Ga:As4 flux ratio. Thus, those skilled in the art can manipulate the nanowires or nanocones in various ways. Additionally, the diameter can also be changed by growing a shell around the nanowire or nanocone core, thereby creating a core-shell geometry.

[0190] Thus, one embodiment of the present invention is to employ a multi-step (such as a two-step) growth procedure, for example, to separately optimize nanowire or nanocone nucleation and nanowire or nanocone growth.

[0191] Furthermore, the pore size can be controlled to ensure that only one nanowire or nanocone can grow in each pore. Thus, it is preferred if only one nanowire or nanocone grows in each pore of the mask. Finally, the pore size can be made large enough to allow the growth of nanowires or nanocones in the case of droplets of the catalyst formed within the pores. In this way, even when using Au catalysis, a regular array of nanowires or nanocones can be grown.

[0192] Coalescence

[0193] It may be that due to the growth of many nanowires or nanocones from the substrate, the nanowires / nanocones merge at a certain distance from the substrate or directly on top of the mask layer. Forming a large-area structure by the merging of the positioned nanowires / nanocones or by the merging of one of the top layers (such as n-AlGaN) can be beneficial. The merging of the nanowires may look almost like a film (for example, if the NW / NP has a conical tip, like a corrugated film, as described below). However, in a particular embodiment, the nanowire / nanocone nuclei are separate. In a particular embodiment, there is at least one layer (such as the top n-layer, such as n-AlGaN) covering at least a portion of the plurality of nanowires / nanocones (for example, by the merging of the layer). In such a case, the layer can be regarded as a layer continuously covering the plurality of nanowires / nanocones or at least a portion / most of them.

[0194] Merging refers to the lateral joining of two or more nanostructures during growth. For the case of merged nanowires / nanocones, it is typically through the inevitable merging of "island" nanostructures grown between them. This produces 2D or 3D structures. For merging, the nanostructures must preferably have their lattices oriented in the same direction so that the formation of gaps and dislocations can be largely eliminated, that is, the merged nanowires / nanocones or their doped layers must preferably have almost the same epitaxial relationship with respect to the substrate.

[0195] In a particular embodiment, the nanowire or nanocone nuclei do not merge. Preferably, any joining of the nanowires / nanocones is caused at least by a top doping layer (such as n-AlGaN) that continuously covers at least a portion, preferably all (or at least 50%, at least 75%, at least 90% or at least 99%) of the plurality of nanowires / nanocones.

[0196] Corrugated / non-planar structure

[0197] It is preferred if the nanowires and / or nanocones have conical tips. If there is a layer (such as the n-AlGaN top layer) continuously covering at least a portion of the NW / NP, the top surface of the structure is preferably non-planar and / or corrugated, with conical tips at the surface. Thus, the non-planar / corrugated layer / film is preferably a non-planar layer / film containing a plurality of protrusions, where the protrusions (such as conical protrusions) are located on top of the nanocone / nanowire tips. The non-planar / corrugated structure is also at the nanoscale, for example, having a thickness of 10 - 1000 nm. The top layer mimics the topography of the underlying nanostructures. In a particular embodiment, the plurality of NW / NP (optionally coated in a layer that continuously covers at least a portion of them) have a corrugated structure and / or are not planar. Thus, the structure is generally ridged. Thus, it is generally different from a planar thin film (i.e., a flat film) grown on the substrate.

[0198] The corrugated structure is beneficial as it enables good light extraction for both transverse electric (TE) and transverse magnetic (TM) polarizations (see Figure 5 ). Typically, manufacturers of nanostructured devices etch corrugated / ridged designs to improve light extraction. In this case, if NW / NPs with tapered tips are used, the corrugations are obtained without having to perform any subsequent etching steps. Thus, by using the NW / NP shape with tapered tips, benefits are obtained in terms of ease of fabrication and light extraction.

[0199] The NW / NP cores can be at least separate (i.e., non - merged), but alternatively, the entire NW / NP structure can be merged such that multiple nanowires / nanopyramids are similar to (or are) a corrugated film, i.e., ridged. In this case, the corrugated layer / membrane is preferably a non - planar layer comprising multiple protrusions, where the protrusions (e.g., tapered tips) are the tips of the nanopyramids / nanowires. Merging can be beneficial as the top continuous layer can act as a transparent electrode and top finger electrodes can be positioned thereon.

[0200] Thus, the material composition can include a corrugated continuous III - V film present on top of the mask layer and extending from the openings of the mask layer. The film typically extends above the mask layer. As for the NW / NP, the film typically has an epitaxial relationship with the substrate. The non - planar continuous III - V structure is typically formed by multiple merged nanowires or nanopyramids grown in the openings, which contain at least one semiconductor III - V compound. The film can have different layers corresponding to the different layers of the above - mentioned nanowires / nanopyramids.

[0201] The present invention thus provides a composition of matter, wherein the composition of matter comprises:

[0202] A doped substrate;

[0203] A mask layer located on top of the substrate;

[0204] wherein there are multiple openings through the mask layer; and

[0205] A corrugated continuous III - V film present on top of the layer and extending from the openings, e.g., formed by multiple merged nanowires or nanopyramids grown in the openings, which contain at least one semiconductor III - V compound.

[0206] The NW / NP cores can be merged, and additional intrinsic and / or doped layers (e.g., p, i, and / or n layers) can continuously cover at least a portion, preferably all, of the merged nanowires / nanopyramids. A corrugated film (typically grown by the merging of multiple nanowires or nanopyramids) generally grows from the substrate in the opening. Thus, the corrugated film can be regarded as multiple merged nanowires or nanopyramids growing from the substrate in the opening.

[0207] It should be understood that any discussion of the individual NW / NP nanowires / nanopyramids or additional intrinsic or doped layers also applies to structures in which the NW / NP or additional layers are merged. For example, the nanowire lengths discussed above will apply to the lengths of the merged nanowires. Any definition of a composition containing nanowires or nanopyramids (e.g., regarding the nature of the materials including the substrate, mask layer, NW / NP, etc.) applies herein where technically feasible. The materials used for the nanowires / nanopyramids can be applied to the corrugated film. The corrugated film can include the same layers as those contained in the nanowires / nanopyramids.

[0208] Device / Application

[0209] Semiconductor nanowires or nanopyramids have a wide range of utilities. They are semiconductors and can thus be expected to provide applications in any area where semiconductor technology is useful. They are mainly used in integrated nanoelectronic devices and nano-optoelectronic applications.

[0210] Ideal devices for their deployment can be solar cells, transistors, laser LEDs, or photodetectors.

[0211] Semiconductor nanowires or nanopyramids are useful in LEDs, particularly UV LEDs and especially UV-A, UV-B, or UV-C LEDs, more preferably UV-C LEDs. The present invention thus provides a device, such as an optoelectronic device, that contains a composition as defined herein, such as a solar cell, a photodetector, or an LED, preferably an LED, more preferably a UV LED, and more preferably a UV-C LED. Preferably, this device (whether an LED or otherwise) emits or absorbs light in the UV region, preferably the UV-C region. In the context of this disclosure, any discussion of light emission in the context of a light emitter (such as a UV LED) also applies to light absorption in the case of a light absorber.

[0212] In the compositions / devices of the present invention, each individual NW / NP can be regarded as an individual LED nanostructure (or an individual photodetector / solar cell). The nanowires or nanopyramids include a light generation (or light absorption) region.

[0213] It will be appreciated that the device of the present invention has electrodes such that charge can be transferred into the device. To produce an optoelectronic device, the top of the nanowire or nanocone preferably includes a top contact. In one embodiment, a conventional top contact portion is located on the top layer of the nanowire / nanocone, e.g., on a top n-type layer (e.g., n-AlGaN) located above the nanowire / nanocone core (this top layer can extend continuously above the underlying layer and the NW / NP core). This top contact should have a finger design to reduce the amount of contact blocking light from leaving or entering the device. The top contact can be a strip of metal, one dimension of which is substantially larger than the other, e.g., strip-shaped. Thus, it is preferred that the metal contact layer or metal stack contact layer does not cover all of the nanowires / nanocones. Thus, the area covered by the n-contact is typically 50% or less, preferably 20% or less, of the top surface area of the nanowire or nanocone. A single finger contact can be used for an LED device and is made of a metal that provides a good ohmic contact to the top-doped NW / NP layer. Alternatively, multiple finger contacts can be used. The opening of the fingers (distance between adjacent fingers) is typically greater than the NW / NP width such that most of the NW / NPs do not have a metal finger on their top (where light can escape). The thick n-AlGaN top layer has a low enough sheet resistance to laterally diffuse the current from the fingers before injecting the current into the active (intrinsic) region.

[0214] In one embodiment, a conventional top contact metal layer stack can be used. The contacts described herein are typically metallic and are selected, for example, to have ohmic behavior with the top layer.

[0215] In a particular embodiment, it is preferred that light is emitted (or absorbed in the case of a photodetector) through the top of the device, i.e., in a direction substantially opposite to the substrate. Thus, it is preferred that the device is not a flip-chip device or is not in a flip-chip configuration. Preferably, there is no (continuous) reflective layer on top of the NW / NP structure to direct the light back to the substrate. In a particular embodiment, the NW / NP does not include a (continuous) reflective layer covering the top of the NW / NP structure.

[0216] These contacts / contact pads can be electrically connected to appropriate power leads of the device package.

[0217] As described above, the doped substrate can act as an active injector of current. In a particular embodiment, there is a conductive path from the substrate through the mask layer and into the nanowire or nanocone. In the case where the nanowire / nanocone extends laterally above the top surface of the mask, the conductive path is higher in the region where the nanowire / nanocone extends above the mask layer. The conductive path is vertical, i.e., in the same axial direction as the nanowire / nanocone (see Figures 1-4)。If the substrate is p-doped, the conductive path of the holes (which is in the same direction as the current) is from the bottom to the top. For an n-doped substrate, the conductive path of the electrons is from the bottom to the top (NB: the direction of the current is defined as opposite to the direction of the electrons). Surprisingly, it has been found that the conduction from the substrate through the mask is higher than the conduction through the openings in the mask. Due to the formation of an insulating layer or a defect layer at the NW / NP interface with the substrate, the conduction through the openings in the mask layer may be poor, and thus it is important for the NW / NP to overgrow laterally outside the openings of the mask layer. In this case, smaller openings may be beneficial for maximizing the vertical conduction through tunneling.

[0218] Unless otherwise stated, the term "bottom" refers to the substrate side of the nanowire / nanopyramid, and the term "top" refers to the side of the nanowire / nanopyramid opposite to the substrate.

[0219] The present invention will now be further discussed in connection with the following non-limiting examples and drawings. Description of the Drawings

[0220] Figure 1 Shown is a positioned flat-tip nanowire epitaxially grown on a doped crystalline substrate carrying a mask layer, in which holes have been etched. The nanowires first nucleate epitaxially through the holes in the mask layer on the substrate. As the nanowires continue to grow axially and radially, they also grow on top of the mask layer, maintaining the epitaxial relationship with the substrate. The nanowires grow as axial heterostructures to fabricate an axial p-i-n nanowire device structure on a p-doped substrate (as shown) or an n-i-p junction nanowire device structure on an n-doped substrate (not shown). The vertical dotted arrow in the p-i-n nanowire device indicates the hole current injected from the p-doped substrate into the p-doped nanowire through tunneling through the mask layer.

[0221] Figure 2 Similar to Figure 1 , the only difference being that the nanowire has a tapered tip. The nanowires grow as axial heterostructures to fabricate an axial p-i-n nanowire device structure on a p-doped substrate (as shown) or an n-i-p junction nanowire device structure on an n-doped substrate (not shown).

[0222] Figure 3 Similar to Figure 2 , the only difference being that the nanowires are either completely incorporated directly into the doped nanowire core or completely incorporated due to the growth of an additional doped nanowire shell layer. The nanowires grow as axial heterostructures to fabricate axial p-i-n and p-p-i-n nanowire device structures on a p-doped substrate (as shown) or n-i-p and n-n-i-p junction nanowire device structures on an n-doped substrate (not shown).

[0223] Figure 4 Similar to Figure 3 , but with merged nanocones instead of merged nanowires. The nanocones are grown as axial heterostructures to fabricate axial p-i-n and p-p-i-n nanocone device structures on a P-doped substrate (as shown) respectively, or n-i-p and n-n-i-p junction nanocone device structures on an n-doped substrate (not shown).

[0224] Figure 5 Shown is a top-emitting nanowire GaN / AlGaN UV LED device grown according to the present invention on a hole etch mask layer carried on a p-doped Si substrate. The dashed arrows show the idealized TM and TE polarized light generated from one exemplary nanowire in the active multiple quantum well region and how they are guided towards the conical top surfaces of some adjacent nanowires. The LED device has a metal bottom contact with the Si substrate and metal finger contacts covering the tops of some nanowires.

[0225] Figures 6(a) and (b) show respectively a top view and a 30° tilted view scanning electron microscope (SEM) image of n-GaN nanowires grown on the graphene-covered portion of a doped Si wafer.

[0226] Figures 6(c) and (d) show respectively a top view and a 30° tilted view scanning electron microscope (SEM) image of n-GaN nanowires grown on a doped Si wafer in a nearby region without any graphene.

[0227] Figure 6e Shown respectively are ++ - the current density-voltage characteristics of n-GaN nanowires grown on the graphene-covered portion (solid circles) of an n ++ -Si wafer and on the portion (solid squares) of the n

[0228] Examples

[0229] Figure 6 shows the experimental results of self-assembled n-GaN nanowires grown by plasma-assisted molecular beam epitaxy (MBE) on a 2-inch diameter n ++ -Si wafer (resistivity < 0.005 Ohm·cm) doped to a level of about 10 19 / cm 3 and with its central portion covered with about 1 cm 2A single-layer polycrystalline CVD graphene (i.e., a single atomic layer of carbon atoms in a hexagonal pattern). HF etching was performed immediately before graphene transfer to reduce the thickness of the native SiO2 present on the Si substrate. After graphene transfer, the sample was loaded into the MBE chamber. Then, in an MBE system equipped with a Knudsen Si cell, a SUMO Ga cell, and a Riber S63 RF nitrogen plasma source, the growth of silicon-doped n-GaN nanowires was carried out under nitrogen-rich conditions. A two-step process was used for n-GaN nanowire growth, where, at a growth temperature of 720 °C, a first step of 30 minutes was carried out with a Ga flux of 0.6×10 -7 Torr, followed by a 11-minute ramp before a second growth step of 60 minutes at a growth temperature of 750 °C with a Ga flux of 1.8×10 -7 Torr. The Si cell was maintained at 1200 °C during the first growth step and at 1255 °C during the second growth step, while the N plasma was always maintained at a nitrogen gas flow rate of 0.8 sccm at an RF power of 450 W.

[0230] Figures 6(a) and (b) show the top view and 30° tilted view scanning electron microscope (SEM) images of n-GaN nanowires grown on the graphene-covered portion of the Si wafer, respectively. From the top view image in (a), it can be seen that the GaN nanowire facets are aligned with each other in the same orientation and epitaxially merge in a larger area, indicating that the GaN nanowires are epitaxial with the Si(111) substrate, and thus the nucleation of GaN nanowires is initiated through the openings in the graphene.

[0231] To measure the conduction between the n ++ -Si wafer and the n-GaN nanowires, a device of 1 mm 2 was fabricated, having ohmic metal contacts on the bottom (negative potential) of the n ++ -Si wafer and on the top (positive potential) of the n-GaN nanowires, as schematically indicated in the inset of Figure 6(e). Figure 6(e) shows the resulting current density-voltage characteristics of n-GaN nanowires grown on the graphene-covered portion (solid circles) of the n ++ -Si wafer and on the portion (solid squares) of the n ++ -Si wafer not covered with graphene, respectively. It can be seen that on the device fabricated on the graphene-covered portion of the Si wafer with near-ohmic behavior, the conduction is much higher in both the positive bias direction and the negative bias direction, while on the portion without graphene, onset voltages of about 1 and -2 V are seen in the forward and reverse directions, respectively. When measured on the graphene-covered portion of the Si substrate, the high conduction and near-ohmic performance indicate tunneling.

Claims

1. A composition of a substance, comprising: A doped substrate; A mask layer having a thickness of less than 2 nm on top of the substrate, wherein there are a plurality of openings through the mask layer; And wherein A plurality of nanowires or nanocones are grown from the substrate in the openings, and the nanowires or nanocones comprise at least one semiconductor group III-V compound.

2. The composition according to any one of the preceding claims, wherein the substrate is p-doped or n-doped, preferably p-doped.

3. The composition according to any one of the preceding claims, wherein the substrate is doped to 10 15 / cm 3 to 10 22 / cm 3 , for example 10 18 / cm 3 to 10 21 / cm 3 level.

4. The composition according to any one of the preceding claims, wherein the substrate is silicon, Ge, SiC, Ga2O3 or a group III-V substrate, preferably a silicon substrate.

5. The composition according to any one of the preceding claims, wherein the doped substrate is used as a current injector.

6. The composition according to any one of the preceding claims, wherein the composition comprises electrical contacts on the doped substrate.

7. The composition according to any one of the preceding claims, wherein the mask layer is a two-dimensional material, such as a graphene, hexagonal BN, MoS2, WS2, MoSe2, NbSe2, TaSe2, Bi2Te3, Bi2Se3 or NiTe2 mask layer, preferably a graphene mask layer, preferably an atomic-thickness graphene mask layer.

8. The composition according to any one of the preceding claims, wherein the nanowires or nanocones comprise GaN, preferably comprise a GaN core, preferably a doped GaN core, more preferably a p-GaN core.

9. The composition according to any one of the preceding claims, wherein the nanowires or nanocones extend laterally (i.e., radially) above the mask layer outside the openings.

10. The composition according to any one of the preceding claims, wherein the mask layer is used as a tunneling barrier, for example, for conducting current from the substrate into the nanowires / nanocones, or from the nanowires / nanocones into the substrate, for example, as a tunneling barrier for vertical hole or electron tunneling injection from the doped substrate to the nanowires or nanocones.

11. The composition according to any one of the preceding claims, wherein the mask layer has a thickness of less than 1.5 nm, more preferably less than 1 nm, more preferably less than 0.9 nm, more preferably less than 0.8 nm, more preferably less than 0.7 nm, more preferably less than 0.6 nm, more preferably less than 0.5 nm.

12. The composition according to any one of the preceding claims, wherein the mask layer is a two-dimensional material, and the mask layer is 1-5 atomic sheets thick, preferably 1-4 atomic sheets thick, preferably 1-3 atomic sheets thick, preferably 1-2 atomic sheets thick, preferably 1 atomic sheet thick.

13. The composition according to any one of the preceding claims, wherein the substrate is a silicon substrate and comprises a native silicon dioxide layer at the interface with the mask layer, preferably, wherein the silicon dioxide layer has a thickness of less than 10 nm, preferably less than 5 nm, preferably less than 3 nm, preferably less than 2 nm, such as 1 - 5 nm, 1 - 2 nm or 2 - 3 nm.

14. The composition according to any one of the preceding claims, wherein the nanowire or nanocone comprises a p-n junction or a p-i-n junction, preferably, wherein the p-n junction or p-i-n junction comprises p-AlGaN and n-AlGaN, preferably wherein the nanowire or nanocone comprises a p-i-n junction containing p-AlGaN, i-AlGaN and n-AlGaN.

15. The composition according to claim 14, wherein the intrinsic layer (i-layer) is a multiple quantum well.

16. The composition according to any one of the preceding claims, wherein - if the nanowire / nanocone core is p-doped, there is an additional intrinsic layer and an n-type layer on the nanowire / nanocone core, preferably, there is an additional p-type layer, intrinsic layer and n-type layer on the nanowire / nanocone core; or - if the nanowire / nanocone core is n-doped, there is an additional intrinsic layer and a p-type layer on the nanowire / nanocone core, preferably, there is an additional n-type layer, intrinsic layer and p-type layer on the nanowire / nanocone core.

17. The composition according to any one of the preceding claims, wherein the composition of the material is an electronic or optoelectronic device, preferably a transistor, a solar cell, a laser, a photodetector or an LED, preferably an LED, preferably a UV LED, preferably a UVC LED.

18. The composition according to any one of the preceding claims, wherein the composition is not in a flip-chip die configuration, or wherein the composition does not comprise a light-reflecting layer covering (e.g., continuously covering) the top of the nanowire or nanocone.

19. The composition according to any one of the preceding claims, wherein the top layer of the p-n junction or p-i-n junction, preferably the top n-layer, serves as a transparent current spreader.

20. The composition according to any one of the preceding claims, wherein the tip of the nanowire / nanocone core is conical.

21. The composition according to any one of the preceding claims, comprising a layer continuously covering at least a portion of the plurality of nanowires / nanocones, such as at least 50%, at least 75%, at least 90%, or at least 99% of the nanowires / nanocones.

22. The composition according to claim 21, wherein the top layer of the nanowire / nanocone has a non-planar structure, such as a corrugated structure.

23. The composition according to claims 21 - 22, wherein the continuous layer is a top doped layer, preferably an n-type top doped layer, such as n-AlGaN.

24. The composition according to any one of the preceding claims, wherein the nanowire or nanocone is doped.

25. The composition according to any one of the preceding claims, wherein the nanowires or nanocones are of core - shell or radial heterostructure, preferably of axial heterostructure.

26. The composition according to any one of the preceding claims, wherein a metal contact layer or a metal stacked contact layer is present at the top of the nanowires or nanocones, preferably, wherein the metal contact layer or the metal stacked contact layer has a finger - like design, for example, is a strip.

27. The composition according to any one of the preceding claims, wherein the nanowires or nanocones are epitaxially grown from the substrate through openings in a mask, i.e., wherein the nanowires or nanocones are epitaxial with the substrate.

28. The composition according to any one of the preceding claims, wherein an electrical contact is in contact with the mask layer.

29. The composition according to any one of the preceding claims, wherein the openings in the mask layer are defects or patterned holes.

30. A composition of matter, comprising: a doped substrate; a mask layer having a thickness of less than 2 nm on top of the substrate, wherein there are a plurality of openings through the mask layer; and a corrugated continuous III - V film, the corrugated continuous III - V film being present on top of the mask layer and extending from the openings, for example, formed by a plurality of merged nanowires or nanocones grown in the openings, the nanowires or nanocones comprising at least one semiconductor compound of Group III - V.

31. A device, such as an optoelectronic device, comprising the composition according to any one of claims 1 - 30, such as a solar cell, a photodetector, a transistor, a laser or an LED, preferably an LED, more preferably a UV LED, even more preferably a UV - C LED.

32. A method for preparing the composition according to any one of claims 1 - 29, comprising: (I) providing a mask layer having a thickness of less than 2 nm on a doped substrate; (II) growing a plurality of nanowires or nanocones from the substrate in a plurality of openings in the mask layer, the nanowires or nanocones comprising at least one semiconductor compound of Group III - V.

33. A method for preparing the composition according to claim 30, comprising: (I) providing a mask layer having a thickness of less than 2 nm carried on a doped substrate; (II) growing a plurality of nanowires or nanocones from the substrate in a plurality of openings in the mask layer until the nanowires or nanocones merge, the nanowires or nanocones comprising at least one semiconductor compound of Group III - V.

34. The method according to claims 32 - 33, further comprising the step of: (III) growing an additional layer such that a p - n junction or a p - i - n junction is provided in the nanowires or nanocones.

35. The method according to claim 32, comprising: (I) providing a mask layer having a thickness of less than 2 nm carried on a doped substrate; (I’) etching a plurality of holes through the mask layer; and (II) Growing a plurality of nanowires or nanocones in the holes from the substrate, the nanowires or nanocones comprising at least one semiconductor Group III-V compound.

36. A method for preparing the composition according to claim 33, comprising: (I) Providing a mask layer having a thickness of less than 2 nm carried on a doped substrate; (I’) Etching a plurality of holes through the mask layer; And (II) Growing a plurality of nanowires or nanocones in the holes from the substrate until the nanowires or nanocones merge, the nanowires or nanocones comprising at least one semiconductor Group III-V compound.

37. A composition of matter, comprising A metal substrate; A mask layer having a thickness of less than 2 nm on the substrate, Wherein there are a plurality of openings through the mask layer; and wherein A plurality of nanowires or nanocones are located on the substrate in the openings, the nanowires or nanocones comprising at least one semiconductor Group III-V compound.

38. A composition of matter, comprising: A metal substrate; A mask layer having a thickness of less than 2 nm on top of the substrate, wherein there are a plurality of openings through the mask layer; And A corrugated continuous III-V film, the corrugated continuous III-V film being present on top of the mask layer and extending from the openings, for example formed by a plurality of merged nanowires or nanocones grown in the openings, the nanowires or nanocones comprising at least one semiconductor Group III-V compound.

39. A method for preparing a device, such as an optoelectronic device, comprising the steps of: (I) Removing the nanowires or nanocones from the substrate in the composition according to any one of claims 1-29; And (II) Transferring the removed nanowires or nanocones to a different substrate, wherein the second substrate is doped or undoped.

40. The method according to claim 39, wherein the mask layer is removed from the substrate together with the nanowires or nanocones, or wherein the nanowires or nanocones are removed from both the substrate and the mask layer.

41. The method according to claim 39 or 40, wherein the different substrate is - a metal substrate (such as Cu, Ti, Mo, stainless steel), preferably, wherein the different substrate provides electrical contact (such as bottom contact); or - An insulating substrate.

42. A method for preparing a device, such as an optoelectronic device, comprising the steps of: (I) Removing the continuous III-V film from the substrate in the composition according to claim 30; And (II) Transferring the removed III-V film to a different substrate, wherein the second substrate is doped / conductive or undoped / insulating.

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