Voltage stabilizing circuit, chip system and electronic equipment

Abstract

The embodiment of the invention provides a voltage stabilizing circuit, a chip system and electronic equipment, relates to the technical field of integrated circuits, and is used for improving the power-on and power-off speed of the voltage stabilizing circuit and avoiding overshoot at the same time. The voltage stabilizing circuit comprises an input end, an output end, an LDO circuit, a slow start module and a switching circuit. The input end of the voltage stabilizing circuit is coupled to the input end of the slow start module and the voltage input end of the LDO circuit, the output end of the slow start module is coupled to the control end of the LDO circuit, the voltage output end of the LDO circuit is coupled to the voltage input end of the switching circuit, and the voltage output end of the switching circuit is coupled to the output end of the voltage stabilizing circuit; the slow start module is used for slowing down the rise of the output voltage of the voltage output end of the LDO circuit; when the output voltage of the voltage output end of the LDO circuit does not rise any more, the output end of the voltage stabilizing circuit supplies power to the load when the switching circuit is switched on, and stops supplying power to the load when the switching circuit is switched off.

Description

[0001] This application is a divisional application. The application number of the original application is 202311292273.3, the original application date is September 28, 2023, and the entire content of the original application is incorporated herein by reference. Technical Field

[0002] This application relates to the field of integrated circuit technology, and particularly to a voltage stabilizing circuit, a chip system, and an electronic device. Background Art

[0003] Currently, many electronic devices use a low dropout regulator (LDO) circuit to supply power to a load. One performance requirement for the LDO circuit is to be able to power on and off quickly to achieve a fast response for powering the load. However, the fast power on and off of the LDO circuit can cause overshoot problems in the output voltage and current of the LDO circuit, which has a negative impact on the power supply to the load. Summary of the Invention

[0004] Embodiments of this application provide a voltage stabilizing circuit, a chip system, and an electronic device, which are used to improve the power on and off speed of the voltage stabilizing circuit while avoiding overshoot.

[0005] To achieve the above object, the embodiments of this application adopt the following technical solutions:

[0006] In a first aspect, a voltage stabilizing circuit is provided, including: an input terminal, an output terminal, an LDO circuit, a soft start module, and a switching circuit; the input terminal of the voltage stabilizing circuit is coupled to the input terminal of the soft start module and the voltage input terminal of the LDO circuit, and the input terminal of the voltage stabilizing circuit is used to input a supply voltage; the output terminal of the soft start module is coupled to the control terminal of the LDO circuit, the voltage output terminal of the LDO circuit is coupled to the voltage input terminal of the switching circuit, and the voltage output terminal of the switching circuit is coupled to the output terminal of the voltage stabilizing circuit; the soft start module is used to slow down the rise of the output voltage of the output terminal of the soft start module when the supply voltage is input to the input terminal of the voltage stabilizing circuit, so as to slow down the rise of the output voltage of the voltage output terminal of the LDO circuit; when the output voltage of the voltage output terminal of the LDO circuit no longer rises, the output terminal of the voltage stabilizing circuit supplies power to the load when the switching circuit is turned on, and stops supplying power to the load when the switching circuit is turned off.

[0007] In the voltage stabilizing circuit provided by the embodiments of this application, the soft start module causes the slow power on speed of the LDO circuit while solving the overshoot problem. In the continuous power supply state of the LDO circuit, the output voltage of the voltage stabilizing circuit is controlled by the switching circuit. When the switching circuit is turned on, the voltage stabilizing circuit supplies power to the load, and when the switching circuit is turned off, the voltage stabilizing circuit stops supplying power to the load. Since the voltage difference between the input terminal and the output terminal of the switching circuit is smaller, the overshoot is smaller when quickly turning on and off, thereby achieving fast power on and off of the voltage stabilizing circuit while solving the overshoot problem.

[0008] In a possible implementation, the switching circuit includes a first switching transistor; the control terminal of the first switching transistor is used to input a first enabling signal, the first controlled terminal of the first switching transistor is the voltage input terminal of the switching circuit, and the second controlled terminal of the first switching transistor is the voltage output terminal of the switching circuit. The first enabling signal is generated by the controller, independent of the LDO circuit and the soft-start module, and can flexibly control the conduction or cutoff of the first switching transistor, thereby controlling the output voltage of the voltage regulation circuit.

[0009] In a possible implementation, the first switching transistor is a P-channel metal oxide semiconductor field effect transistor (PMOS transistor). The gate of the PMOS transistor is the control terminal of the first switching transistor, the source of the PMOS transistor is the first controlled terminal of the first switching transistor, and the drain of the PMOS transistor is the first controlled terminal of the first switching transistor.

[0010] In a possible implementation, the soft-start module includes a capacitor. The capacitor can slow down the rise of the output voltage of the soft-start module, thereby making the output voltage of the LDO circuit rise smoothly and avoiding the occurrence of spike pulses.

[0011] In a possible implementation, the LDO circuit includes a bandgap reference module, a differential amplifier, a second switching transistor, and a voltage dividing circuit; the differential amplifier includes a first input terminal, a second input terminal, an output terminal, and a control terminal; the voltage dividing circuit includes a voltage dividing node; the voltage input terminal of the bandgap reference module is coupled to the input terminal of the voltage regulation circuit, and the enabling terminal of the bandgap reference module is used to input a second enabling signal; the first input terminal of the differential amplifier is coupled to the voltage output terminal of the bandgap reference module, the second input terminal of the differential amplifier is coupled to the voltage dividing node of the voltage dividing circuit, the output terminal of the differential amplifier is coupled to the control terminal of the second switching transistor, the first controlled terminal of the second switching transistor is coupled to the voltage input terminal of the LDO circuit, and the second controlled terminal of the second switching transistor is coupled to the voltage output terminal of the LDO circuit; the control terminal of the differential amplifier is coupled to the output terminal of the soft-start module; the voltage dividing circuit is coupled to the voltage output terminal of the LDO circuit.

[0012] The differential amplifier is used to improve the stability of the output voltage of the LDO circuit while deepening the feedback effect. The differential amplifier amplifies the small error signal between the feedback voltage and the reference voltage, and then outputs it to the output terminal of the LDO circuit through the second switching transistor. A negative feedback is formed through the voltage dividing circuit, ensuring that the output voltage of the LDO circuit is stabilized at a specified value.

[0013] In a possible implementation, the second switching transistor is a PMOS transistor. The gate of the PMOS transistor is the control end of the second switching transistor, the source of the PMOS transistor is the first controlled end of the second switching transistor, and the drain of the PMOS transistor is the second controlled end of the second switching transistor. The PMOS transistor conducts when the gate voltage is lower than the source voltage, and the PMOS transistor turns off when the gate voltage is higher than the source voltage.

[0014] In a possible implementation, the voltage dividing circuit includes a first resistor and a second resistor; the first end of the first resistor is coupled to the voltage output end of the LDO circuit, the second end of the second resistor is grounded, and the second end of the first resistor and the first end of the second resistor are coupled to a voltage dividing node. The voltage dividing circuit is used to divide the output voltage of the LDO circuit to obtain a feedback voltage.

[0015] In a possible implementation, the voltage stabilizing circuit further includes an AND gate; the control signal output end of the soft start module is coupled to the first input end of the AND gate, the second input end of the AND gate is used to input a second enable signal, and the output end of the AND gate is coupled to the enable end of the differential amplifier.

[0016] In a second aspect, a chip system is provided, and the chip system includes the voltage stabilizing circuit of the first aspect and any of its implementations.

[0017] In a third aspect, a chip system is provided, and the chip system includes the LDO circuit and the soft start module in the voltage stabilizing circuit of the first aspect and any of its implementations, and the chip system is coupled to the switching circuit in the voltage stabilizing circuit.

[0018] In a fourth aspect, an electronic device is provided, and the electronic device includes the voltage stabilizing circuit of the first aspect and any of its implementations and a load, and the voltage stabilizing circuit is used to supply power to the load.

[0019] The technical effects of the second aspect to the fourth aspect refer to the technical effects of the first aspect and any of its implementations, and will not be repeated here. Description of the Drawings

[0020] Figure 1 It is a schematic structural diagram of an electronic device provided by an embodiment of the present application;

[0021] Figure 2 It is a schematic structural diagram of the first voltage stabilizing circuit provided by an embodiment of the present application;

[0022] Figure 3 It is a schematic diagram of the power-on and power-off waveforms of the first voltage stabilizing circuit provided by an embodiment of the present application;

[0023] Figure 4 It is a schematic structural diagram of the second voltage stabilizing circuit provided by an embodiment of the present application;

[0024] Figure 5Schematic diagram of the power-on and power-off waveforms of the second voltage stabilization circuit provided by the embodiment of the present application;

[0025] Figure 6 Schematic diagram of the structure of the third voltage stabilization circuit provided by the embodiment of the present application;

[0026] Figure 7 Schematic diagram of the power-on and power-off waveforms of the third voltage stabilization circuit provided by the embodiment of the present application;

[0027] Figure 8 Schematic diagram of the structure of the first chip system provided by the embodiment of the present application;

[0028] Figure 9 Schematic diagram of the structure of the second chip system provided by the embodiment of the present application. Detailed implementation manners

[0029] First, some concepts related to the present application are described.

[0030] The terms "first", "second", etc. involved in the embodiments of the present application are only used for the purpose of distinguishing the same type of features, and should not be understood as indicating relative importance, quantity, order, etc.

[0031] The terms "exemplary" or "for example" and the like involved in the embodiments of the present application are used to represent examples, illustrations or explanations. Any embodiment or design solution described as "exemplary" or "for example" in the present application should not be construed as being more preferred or more advantageous than other embodiments or design solutions. Exactly speaking, the use of the terms "exemplary" or "for example" and the like is intended to present the relevant concepts in a specific manner.

[0032] The terms "coupled" and "connected" involved in the embodiments of the present application should be understood in a broad sense. For example, it may refer to a direct physical connection, or an indirect connection implemented through electronic devices, such as a connection implemented through resistors, inductors, capacitors or other electronic devices.

[0033] The electronic device provided by the embodiment of the present application may be an electronic device including a voltage stabilizing circuit. The electronic device may be mobile or fixed. The electronic device may be deployed on land (such as indoors or outdoors, handheld or vehicle-mounted, etc.), may also be deployed on water (such as a ship, etc.), and may also be deployed in the air (such as an airplane, a balloon, a satellite, etc.). The electronic device may be referred to as a user equipment (UE), an access terminal, a terminal unit, a subscriber unit, a terminal station, a mobile station (MS), a mobile phone, a terminal agent, or a terminal device, etc. For example, the electronic device may be a mobile phone, a tablet computer, a laptop computer, a smart bracelet, a smart watch, a power bank, a new energy vehicle, or other electronic devices. The embodiment of the present application does not limit the specific type and structure of the electronic device, and a possible structure of the electronic device will be described below.

[0034] Taking the electronic device as a mobile phone as an example, Figure 1 A possible structure of the electronic device 1 is shown. Exemplarily, the electronic device 1 may include a voltage stabilizing circuit 10, a power management chip 11, a controller 12, and a load 13. The voltage output terminal of the power management chip 11 is coupled to the input terminal of the voltage stabilizing circuit 10. When the power adapter 2 is connected to the power management chip 11 (by wire or wirelessly), the power management chip 11 converts the output voltage of the power adapter 2 into the input voltage of the voltage stabilizing circuit 10, and the voltage stabilizing circuit 10 converts it into the supply voltage of the load. The enable signal output terminal of the controller 12 is coupled to the enable terminal of the voltage stabilizing circuit 10, and is used to output an enable signal to control the power on and off of the voltage stabilizing circuit 10.

[0035] Figure 2 A schematic structural diagram of a voltage stabilizing circuit 10 provided by the embodiment of the present application is shown. The voltage stabilizing circuit 10 includes an LDO circuit 101. It should be noted that the voltage input terminal of the LDO circuit 101 is the input terminal of the voltage stabilizing circuit 10; the voltage output terminal of the LDO circuit 101 is the output terminal of the voltage stabilizing circuit 10. The LDO circuit 101 can realize the conversion of the power supply voltage, and has the advantages of low cost, low noise, and small static current, and is usually used in the step-down field.

[0036] The LDO circuit 101 includes a bandgap reference module BR, a differential amplifier AMP, a switching transistor Q1 (such as a PMOS transistor), and a voltage dividing circuit F.

[0037] The enable terminal CON1 of the voltage stabilizing circuit 10 is coupled to the enable terminal of the bandgap reference module BR and the enable terminal of the differential amplifier AMP; the voltage input terminal of the bandgap reference module BR is coupled to the input terminal of the voltage stabilizing circuit 10, the first input terminal (e.g., the inverting input terminal) of the differential amplifier AMP is coupled to the voltage output terminal of the bandgap reference module BR, the second input terminal (e.g., the non-inverting input terminal) of the differential amplifier AMP is coupled to the voltage dividing node of the voltage dividing circuit F, the output terminal of the differential amplifier AMP is coupled to the control terminal of the switching transistor Q1, the first controlled terminal of the switching transistor Q1 is coupled to the voltage input terminal of the LDO circuit 101, and the second controlled terminal of the switching transistor Q1 is coupled to the voltage output terminal of the LDO circuit 101; the voltage dividing circuit F is coupled to the voltage output terminal of the LDO circuit 101.

[0038] The voltage input terminal of the bandgap reference module BR is used to input the supply voltage Vin, the enable terminal of the bandgap reference module BR is used to input the enable signal EN1 from a controller (e.g., Figure 1 the controller 12 in it), and the voltage output terminal of the bandgap reference module BR is used to output the reference voltage Vref. The first input terminal (e.g., the inverting input terminal) of the differential amplifier AMP is used to input the reference voltage Vref, the enable terminal of the differential amplifier AMP is used to input the enable signal EN1, and the output terminal of the differential amplifier AMP is coupled to the control terminal of the switching transistor Q1. The first controlled terminal of the switching transistor Q1 is the voltage input terminal of the LDO circuit 101 (which is also the input terminal IN of the voltage stabilizing circuit 10), and the second controlled terminal of the switching transistor Q1 is the voltage output terminal of the LDO circuit 101 (which is also the output terminal OUT of the voltage stabilizing circuit 10). The first end of the voltage dividing circuit F is coupled to the voltage output terminal of the LDO circuit 101, and the second end of the voltage dividing circuit F is grounded to GND.

[0039] The voltage dividing circuit F includes a first resistor R1 and a second resistor R2. The first resistor R1 and the second resistor R2 are serially coupled between the voltage output terminal of the LDO circuit 101 and the ground GND. The second end of the first resistor R1 and the first end of the second resistor R2 are coupled to the voltage dividing node. That is, the first end of the first resistor R1 is coupled to the second controlled terminal of the switching transistor Q1, the second end of the first resistor R1 is coupled to the first end of the second resistor R2, and the second end of the second resistor R2 is grounded. The first resistor R1 and the second resistor R2 are used to divide the output voltage Vout1 of the LDO circuit 101 to obtain the feedback voltage Vf:

[0040] Vf = Vout1 * R2 / (R1 + R2)

[0041] The differential amplifier AMP amplifies the small error signal between the feedback voltage Vf and the reference voltage Vref. Taking the first input terminal as the inverting input terminal and the second input terminal as the non-inverting input terminal as an example, when the reference voltage Vref is greater than the feedback voltage Vf, the differential amplifier AMP outputs a low level; when the reference voltage Vref is less than the feedback voltage Vf, the differential amplifier AMP outputs a high level.

[0042] Taking the switching transistor Q1 as a PMOS transistor as an example, the gate of the PMOS transistor is the control terminal of the switching transistor Q1, the source of the PMOS transistor is the first controlled terminal of the switching transistor Q1, and the drain of the PMOS transistor is the second controlled terminal of the switching transistor Q1. When the gate voltage is lower than the source voltage, the PMOS transistor is turned on; when the gate voltage is higher than the source voltage, the PMOS transistor is turned off.

[0043] The above differential amplifier AMP, voltage dividing circuit F, and switching transistor Q1 form a negative feedback circuit, making the output voltage Vout1 of the LDO circuit 101 stable at a specified value. Specifically, Figure 2 The working process of the voltage stabilizing circuit 10 shown is as follows:

[0044] In the initial state, although the LDO circuit 101 is supplied with the input power supply voltage Vin, and the first input terminal of the differential amplifier AMP inputs the reference voltage Vref. However, the enable signal EN1 is at a low level, and the differential amplifier AMP is in a high impedance state because it is disabled and does not output a voltage. The switching transistor Q1 is turned off, and the output voltage Vout1 of the LDO circuit 101 is 0, making the feedback voltage Vf 0.

[0045] When the enable signal EN1 is at a high level, since the reference voltage Vref is greater than the feedback voltage Vf, the differential amplifier AMP outputs a low level, the switching transistor Q1 is turned on, and the output voltage Vout1 of the LDO circuit 101 rises rapidly, making the feedback voltage Vf also rise rapidly. When the feedback voltage Vf rises to be greater than the reference voltage Vref, the differential amplifier AMP outputs a high level, the switching transistor Q1 is turned off, and the output voltage Vout1 of the LDO circuit 101 starts to drop, and the feedback voltage Vf on the second resistor R2 also drops accordingly until the reference voltage Vref is greater than the feedback voltage Vf, and the above process will be repeated. Therefore, the output voltage Vout1 is stabilized at a preset value, and this preset value is equal to K times the reference voltage Vref.

[0046] Table 1 shows the above Figure 2 truth table of the output voltage Vout1 of the voltage stabilizing circuit 10 in (i.e., the output voltage Vout1 of the LDO circuit 101). It can be seen from Table 1 that only when the power supply voltage Vin is at a high level and the enable signal EN1 is at a high level, the output voltage Vout1 of the voltage stabilizing circuit 10 can be at a high level.

[0047] Table 1

[0048]

[0049] Figure 3 shows the power-on and power-off waveforms of the voltage stabilization circuit 10 above. After inputting the supply voltage Vin, when the enable signal EN1 steps up from zero, as can be seen from 31 and 32, Figure 2 when the output current I of the voltage stabilization circuit 10 (i.e., the output current I of the LDO circuit 101) in [it] rapidly rises, an inrush current is generated; as can be seen from 33 and 34, when the output voltage Vout1 of the voltage stabilization circuit 10 rapidly rises, a spike voltage is generated. Figure 2 In an electronic device, the inrush current generated at the moment of power-on may cause breakdown damage to the load; in a chip system, the uncertain value of the spike voltage sometimes affects the function judgment at the moment of chip power-on, and sometimes may even cause the chip to fail.

[0050] To solve the overshoot problem, it is necessary to improve the voltage stabilization circuit 10 shown in

[0051] For example, on the basis of the voltage stabilization circuit 10 shown in Figure 2 the voltage stabilization circuit 10 shown in Figure 2 further includes a soft-start module 102 and an AND gate AND. Figure 4 The signal output end of the soft-start module 102 is coupled to the first input end of the AND gate AND, the enable end CON1 of the voltage stabilization circuit 10 is coupled to the second input end of the AND gate AND, and the output end of the AND gate AND is coupled to the enable end of the differential amplifier AMP.

[0052] The voltage input end of the soft-start module 102 is used to input the supply voltage Vin, the first input end of the AND gate AND is used to input the output voltage of the soft-start module 102, the second input end of the AND gate AND is used to input the enable signal EN1 from a controller (such as

[0053] the controller 12 in [it]), and the output signal of the soft-start module 102 and the enable signal EN1 jointly enable the differential amplifier AMP through the AND gate AND. Figure 1 For example, the soft-start module 102 includes a capacitor C. The first end of the capacitor C is coupled to the input end IN of the voltage stabilization circuit 10, and the second end of the capacitor C is coupled to the first input end of the AND gate AND. After the soft-start module 102 inputs the supply voltage Vin, since the charges on the electrodes of the capacitor C accumulate gradually, the output voltage of the soft-start module 102 rises slowly.

[0054]

[0055] Figure 4 In addition to the soft-start module 102 and the AND gate AND, Figure 4The structure of the voltage stabilizing circuit 10 shown is the same as that of Figure 2 the voltage stabilizing circuit 10 shown, and the functions of each device are also the same as those of Figure 2 the voltage stabilizing circuit 10 shown. Therefore, its connection relationship, structure, and function can be referred to Figure 2 the voltage stabilizing circuit 10 shown, and no further elaboration will be made here.

[0056] Figure 4 The working process of the voltage stabilizing circuit 10 shown is similar to that of Figure 2 the voltage stabilizing circuit 10 shown. The difference is that the output voltage of the soft-start module 102 rises slowly. Therefore, when the enable signal EN1 is at a high level, when the voltage at the first input terminal of the AND gate AND rises slowly to a high level and is ANDed with the enable signal EN1, the AND gate AND will output a high level, and only then can the differential amplifier AMP be enabled together, causing the differential amplifier AMP to start outputting a voltage. When the reference voltage Vref is greater than the feedback voltage Vf, the differential amplifier AMP slowly outputs a low level, and the switching transistor Q1 gradually conducts, and the output voltage Vout1 of the LDO circuit 101 can slowly rise.

[0057] Table 2 shows Figure 4 the truth table of the output voltage Vout1 of the voltage stabilizing circuit 10 shown (i.e., the output voltage Vout1 of the LDO circuit 101). Figure 4 The voltage stabilizing circuit 10 shown is different from Figure 2 the voltage stabilizing circuit 10 shown in that Figure 4 the voltage stabilizing circuit 10 shown slows down the power-on speed of the output voltage Vout1 of the LDO circuit 101. Its truth table is the same as that of Figure 2 the voltage stabilizing circuit 10 shown. Only when the supply voltage Vin is at a high level and the enable signal EN1 is at a high level, can the output voltage Vout1 of the voltage stabilizing circuit 10 be at a high level.

[0058] Table 2

[0059]

[0060] Figure 5 shows Figure 4 the power-on and power-off waveform diagram of the voltage stabilizing circuit 10 shown. After adding the soft-start module 102, when the enable signal EN1 rises stepwise, as can be seen from 51 and 52, Figure 4 the output current I of the voltage stabilizing circuit 10 in (i.e., the output current I of the LDO circuit 101) has no inrush current; as can be seen from 53 and 54, the output voltage Vout1 of the voltage stabilizing circuit 10 has no spike voltage generated, but the power-on speed is slow.

[0061] After adding the soft start module 102, although the overshoot problem is solved, it also causes the output voltage Vout1 of the voltage regulator circuit 10 to rise slowly during power-on. In practical applications, it is difficult to meet the response speed requirements of some loads, and sometimes it even causes timing errors in the hardware circuit.

[0062] To solve the problem of slow power-on, it is necessary to Figure 4 improve the voltage regulator circuit 10 shown in Figure 4 Based on the voltage regulator circuit 10 shown in Figure 6 The voltage regulator circuit 10 shown in Figure 1 also includes a switch circuit 103. The switch circuit 103 is coupled to the output terminal of the LDO circuit 101. In the state where the LDO circuit 101 is continuously powered, by controlling the conduction or cutoff of the switch circuit 103, it is possible to control whether the voltage regulator circuit 10 supplies energy to the load (such as Figure 1 the load 13 in). Since the voltage difference between the input terminal and the output terminal of the switch circuit 103 is smaller in the state where the LDO circuit 101 is continuously powered, when quickly conducting and cutoff, the overshoot is smaller, thereby realizing the fast power-on and power-off of the voltage regulator circuit 10 while solving the overshoot problem.

[0063] Specifically, the output terminal of the LDO circuit 101 is coupled to the voltage input terminal of the switch circuit 103, and the voltage output terminal of the switch circuit 103 is used to supply power to the load 13. In the state where the LDO circuit 101 is continuously powered, the controller (such as Figure 1 the controller 12 in) outputs an enable signal EN2 to the control terminal of the switch circuit 103 (which is also the enable terminal CON2 of the voltage regulator circuit 10) to control the switch circuit 103 to conduct. At this time, the switch circuit 103 supplies power to the load, and the controller 12 stops outputting the enable signal EN2 to the control terminal of the switch circuit 103 to control the switch circuit 103 to cutoff. At this time, the switch circuit 103 stops supplying power to the load. The switch circuit 103 can be implemented by a triode, a switch tube, etc.

[0064] In a possible implementation manner, the switch circuit 103 includes a switch tube Q2. The control terminal of the switch tube Q2 is used to input the enable signal EN2. The first controlled terminal of the switch tube Q2 is the voltage input terminal of the switch circuit 103, and the second controlled terminal of the switch tube Q2 is the voltage output terminal of the switch circuit 103 (which is also the output terminal OUT of the voltage regulator circuit 10).

[0065] Exemplarily, when the switching transistor Q2 is a PMOS transistor, the gate of the PMOS transistor is the control end of the switching transistor Q2, the source of the PMOS transistor is the first controlled end of the switching transistor Q2, and the drain of the PMOS transistor is the second controlled end of the switching transistor Q2. When the gate voltage is lower than the source voltage, the PMOS transistor conducts; when the gate voltage is higher than the source voltage, the PMOS transistor turns off. Therefore, when the enable signal EN2 is at a low level, the PMOS transistor conducts; when the enable signal EN2 is at a high level, the PMOS transistor turns off.

[0066] In the embodiments of the present application, the connection relationship, structure, and function of the LDO circuit 101 and the soft-start module 102 can be referred to Figure 4 the relevant descriptions in the voltage regulation circuit 10 shown, and will not be elaborated here.

[0067] In the embodiments of the present application, the working process of the voltage regulation circuit 10 is as follows:

[0068] After the input supply voltage Vin is applied, when the enable signal EN1 is at a high level, since the output voltage of the soft-start module 102 rises slowly, the switching transistor Q1 gradually conducts, and the output voltage Vout1 of the LDO circuit 101 rises slowly. At this time, when the enable signal EN2 is at a low level, the switching transistor Q2 conducts, and the output voltage Vout2 of the voltage regulation circuit 10 rises slowly; when the enable signal EN2 is at a high level, the switching transistor Q2 turns off, and the output voltage Vout2 of the voltage regulation circuit 10 is at a low level.

[0069] The enable signal EN1 remains at a high level, and the output voltage Vout1 of the LDO circuit 101 remains at a high level. At this time, when the enable signal EN2 is at a low level, the switching transistor Q2 conducts, and the output voltage Vout2 of the voltage regulation circuit 10 powers on quickly; when the enable signal EN2 is at a high level, the switching transistor Q2 turns off, and the output voltage Vout2 of the voltage regulation circuit 10 powers off quickly.

[0070] Table 3 shows the above Figure 6 truth table of the output voltage Vout2 of the voltage regulation circuit 10. Since the switching circuit 103 is serially coupled to the voltage output end of the LDO circuit 101, it is a logical AND relationship in the circuit. When the enable signal EN1 is at a high level, the switching transistor Q1 conducts; when the enable signal EN2 is at a low level, the switching transistor Q2 conducts. Therefore, only when the supply voltage Vin is at a high level, the enable signal EN1 is at a high level, and the enable signal EN2 is at a low level, the output voltage Vout2 of the voltage regulation circuit 10 can be at a high level.

[0071] Table 3

[0072]

[0073] Figure 7 shows the aboveFigure 6 The waveforms of the power-on and power-off of the voltage stabilizing circuit 10. As can be seen from 71, when the enable signal EN1 is at a high level and the enable signal EN2 is at a low level for the first time, the output voltage Vout2 of the voltage stabilizing circuit 10 powers on slowly; as can be seen from 72 and 73, in the subsequent process, when the enable signal EN1 is at a high level and the enable signal EN2 is at a low level, the output voltage Vout2 of the voltage stabilizing circuit 10 can power on quickly.

[0074] In summary, the voltage stabilizing circuit, chip system, and electronic device provided by the embodiments of the present application can flexibly control the output voltage of the voltage stabilizing circuit by adding a switching circuit, and can achieve a fast power-on while solving the overshoot problem, so as to meet the requirements of the hardware circuit for the power-on timing in practical applications.

[0075] As Figure 8 shown, the embodiments of the present application provide a first chip system 80, and the chip system 80 includes a voltage stabilizing circuit 10.

[0076] As Figure 9 shown, the embodiments of the present application provide a second chip system 80. The chip system 80 includes the LDO circuit 101 and the soft start module 102 in the voltage stabilizing circuit 10, and the chip system is coupled to the switching circuit 103 in the voltage stabilizing circuit 10.

[0077] In several embodiments provided by the present application, it should be understood that the disclosed systems, devices, and apparatuses can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For example, the division of the modules is only a logical function division, and there may be other division methods in actual implementation. For example, multiple modules or components can be combined or integrated into another device, or some features can be ignored or not executed. Another point is that the displayed or discussed coupling or direct coupling or communication connection between each other can be through some interfaces, and the indirect coupling or communication connection of the devices or modules can be in an electrical, mechanical, or other form.

[0078] The modules described as separate components may or may not be physically separated, and the components displayed as modules may or may not be physical modules, that is, they may be located in one device, or may be distributed to multiple devices. Some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0079] In addition, the functional modules in each embodiment of the present application can be integrated in one device, or each module can exist physically alone, or two or more modules can be integrated in one device.

[0080] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present application are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions may be transmitted from a website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or data center that includes one or more media integrated therein. The available medium may be a magnetic medium (such as a floppy disk, hard disk, magnetic tape), an optical medium (such as a DVD), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0081] As described above, the above are only specific embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed in the present application can easily think of changes or substitutions, which should all be covered by the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A voltage stabilizing circuit, characterized in that, Comprising: A low dropout linear regulator (LDO) circuit, a soft start module, and a switching circuit; The input terminal of the voltage regulator circuit is used for inputting a supply voltage; The enable terminal of the voltage regulator circuit is used for inputting a first enable signal; the control terminal of the switching circuit is used for inputting a second enable signal; The input terminal of the voltage regulator circuit is coupled to the voltage input terminal of the soft start module and the voltage input terminal of the LDO circuit; the output terminal of the soft start module is coupled to the control terminal of the LDO circuit; the enable terminal of the voltage regulator circuit is coupled to the enable terminal of the LDO circuit; the voltage input terminal of the switching circuit is coupled to the voltage output terminal of the LDO circuit; the output terminal of the voltage regulator circuit is coupled to the voltage output terminal of the switching circuit and the voltage output terminal of the LDO circuit; After the supply voltage is input, when the first enable signal is at a high level, the voltage regulator circuit is configured to slowly power up the output voltage of the voltage regulator circuit when the second enable signal is at a low level for the first time; the voltage regulator circuit is further configured to quickly power up the output voltage of the voltage regulator circuit when the second enable signal transitions from a high level to a low level, and / or, quickly power down the output voltage of the voltage regulator circuit when the second enable signal transitions from a low level to a high level.

2. The voltage stabilizing circuit according to claim 1, wherein After the supply voltage is input, when the first enable signal is at a high level, the voltage regulator circuit is configured to slowly power up the output voltage of the voltage regulator circuit when the second enable signal is at a low level for the first time, including: After the supply voltage is input, when the first enable signal is at a high level, the output voltage of the soft start module slowly rises, and the output voltage of the LDO circuit slowly rises; When the second enable signal is at a low level for the first time, the switching circuit conducts, and the output voltage of the voltage regulator circuit slowly powers up.

3. The voltage stabilizing circuit according to claim 1 or 2, characterized in that The voltage regulator circuit is further configured to quickly power up the output voltage of the voltage regulator circuit when the second enable signal transitions from a high level to a low level, including: When the first enable signal remains at a high level, the output voltage of the LDO circuit remains at a high level. When the second enable signal transitions from a high level to a low level, the switching circuit conducts, and the output voltage of the voltage regulator circuit quickly powers up.

4. The voltage stabilizing circuit according to any one of claims 1 to 3, characterized in that, The voltage regulator circuit is further configured to quickly power down the output voltage of the voltage regulator circuit when the second enable signal transitions from a low level to a high level, including: When the first enable signal remains at a high level, the output voltage of the LDO circuit remains at a high level. When the second enable signal transitions from a low level to a high level, the switching circuit turns off, and the output voltage of the voltage regulator circuit quickly powers down.

5. The voltage stabilizing circuit according to any one of claims 1-4, characterized in that, The soft start module is configured to slow down the rise of the output voltage of the LDO circuit by slowing down the rise of the output voltage of the soft start module when the supply voltage is input to the input terminal of the voltage regulator circuit.

6. The voltage stabilizing circuit according to any one of claims 1-5, characterized in that The LDO circuit includes a bandgap reference module BR, an AND gate, a differential amplifier AMP, a first switching transistor, and a voltage dividing circuit; the voltage dividing circuit includes a voltage dividing node; the input end of the voltage regulating circuit is coupled to the voltage input end of the BR and the first controlled end of the first switching transistor; the first controlled end of the first switching transistor is coupled to the voltage input end of the LDO circuit; the output end of the soft start module is coupled to the first input end of the AND gate; the enable end of the voltage regulating circuit is coupled to the second input end of the AND gate and the enable end of the BR; the voltage output end of the BR is coupled to the first input end of the AMP; the second input end of the AMP is coupled to the voltage dividing node of the voltage dividing circuit; the output end of the AMP is coupled to the control end of the first switching transistor; the control end of the AMP is coupled to the output end of the AND gate; the voltage input end of the switching circuit is coupled to the second controlled end of the first switching transistor and the first end of the voltage dividing circuit; the second end of the voltage dividing circuit is grounded.

7. The voltage stabilizing circuit according to any one of claims 1-6, characterized in that, The output end of the voltage regulating circuit supplies power to the load when the output voltage of the voltage regulating circuit powers on rapidly, and stops supplying power to the load when the output voltage of the voltage regulating circuit powers off rapidly.

8. The voltage stabilizing circuit according to any one of claims 1-7, characterized in that, The switching circuit includes a second switching transistor. The control end of the second switching transistor is used to input a second enable signal, the first controlled end of the second switching transistor is the voltage input end of the switching circuit, and the second controlled end of the second switching transistor is the voltage output end of the switching circuit.

9. The voltage stabilizing circuit according to claim 8, characterized in that, The second switching transistor is a P-type metal oxide semiconductor field effect transistor PMOS transistor.

10. The voltage stabilizing circuit according to any one of claims 1-9, characterized in that, The soft start module includes a capacitor.

11. The voltage stabilizing circuit according to claim 6, characterized in that, The first switching transistor is a PMOS transistor.

12. The voltage stabilizing circuit according to claim 6, characterized in that, The voltage dividing circuit includes a first resistor and a second resistor; the first end of the first resistor is coupled to the voltage output end of the LDO circuit, the second end of the second resistor is grounded, and the second end of the first resistor and the first end of the second resistor are coupled at the voltage dividing node.

13. A voltage stabilizing method, characterized in that, Applied to an electronic device, the electronic device includes: a low dropout linear regulator LDO circuit, a soft start module, a switching circuit, and a controller; the controller is used to execute the voltage regulating method; the input end of the LDO circuit is used to input a supply voltage; the enable end of the LDO circuit is used to input a first enable signal; the control end of the switching circuit is used to input a second enable signal; the input end of the LDO circuit is coupled to the voltage input end of the soft start module; the output end of the soft start module is coupled to the control end of the LDO circuit; the voltage input end of the switching circuit is coupled to the voltage output end of the LDO circuit; the method includes: After inputting the supply voltage, when controlling the first enable signal to be at a high level, control the second enable signal to be at a low level for the first time, and the output voltage of the voltage output terminal of the switching circuit powers on slowly; also control the second enable signal to transition from a high level to a low level, and the output voltage of the voltage output terminal of the switching circuit powers on quickly, and / or, also control the second enable signal to transition from a low level to a high level, and the output voltage of the voltage output terminal of the switching circuit powers off quickly.

14. The voltage stabilization method according to claim 13, characterized in that, After inputting the supply voltage, when controlling the first enable signal to be at a high level, controlling the second enable signal to be at a low level for the first time, and the output voltage of the voltage output terminal of the switching circuit powers on slowly, includes: After inputting the supply voltage, when controlling the first enable signal to be at a high level, the output voltage of the soft-start module rises slowly, and the output voltage of the output voltage of the LDO circuit rises slowly; When controlling the second enable signal to be at a low level for the first time, the switching circuit conducts, and the output voltage of the voltage output terminal of the switching circuit powers on slowly.

15. The voltage stabilization method according to claim 13 or 14, characterized in that, The further control that the second enable signal transitions from a high level to a low level, and the output voltage of the voltage output terminal of the switching circuit powers on quickly, includes: When the first enable signal remains at a high level, the output voltage of the LDO circuit remains at a high level. When further controlling the second enable signal to transition from a high level to a low level, the switching circuit conducts, and the output voltage of the voltage output terminal of the switching circuit powers on quickly.

16. The voltage stabilizing method according to any one of claims 13-15, characterized in that The further control that the second enable signal transitions from a low level to a high level, and the output voltage of the voltage output terminal of the switching circuit powers off quickly, includes: When the first enable signal remains at a high level, the output voltage of the LDO circuit remains at a high level. When further controlling the second enable signal to transition from a low level to a high level, the switching circuit turns off, and the output voltage of the voltage output terminal of the switching circuit powers off quickly.

17. The voltage stabilizing method according to any one of claims 13-16, characterized in that, When the supply voltage is input to the input terminal of the LDO circuit, control the soft-start module to slow down the rise of the output voltage of the soft-start module to slow down the rise of the output voltage of the voltage output terminal of the LDO circuit.

18. The voltage stabilizing method according to any one of claims 13-17, characterized in that The LDO circuit includes a bandgap reference module BR, an AND gate, a differential amplifier AMP, a first switching transistor, and a voltage dividing circuit; the voltage dividing circuit includes a voltage dividing node; the input end of the LDO circuit is coupled to the voltage input end of the BR and the first controlled end of the first switching transistor; the first controlled end of the first switching transistor is coupled to the voltage input end of the LDO circuit; the output end of the soft start module is coupled to the first input end of the AND gate; the enable end of the LDO circuit is coupled to the second input end of the AND gate and the enable end of the BR; the voltage output end of the BR is coupled to the first input end of the AMP; the second input end of the AMP is coupled to the voltage dividing node of the voltage dividing circuit; the output end of the AMP is coupled to the control end of the first switching transistor; the control end of the AMP is coupled to the output end of the AND gate; the voltage input end of the switching circuit is coupled to the second controlled end of the first switching transistor and the first end of the voltage dividing circuit; the second end of the voltage dividing circuit is grounded.

19. The voltage stabilization method according to any one of claims 13-18, characterized in that, The voltage output end of the switching circuit supplies power to the load when the output voltage of the switching circuit powers on rapidly, and stops supplying power to the load when the output voltage of the switching circuit powers off rapidly.

20. The voltage stabilization method according to any one of claims 13-19, characterized in that, The switching circuit includes a second switching transistor. The control end of the second switching transistor is used to input a second enable signal, the first controlled end of the second switching transistor is the voltage input end of the switching circuit, and the second controlled end of the second switching transistor is the voltage output end of the switching circuit.

21. The voltage stabilization method according to claim 20, characterized in that, The second switching transistor is a P-type metal oxide semiconductor field effect transistor (PMOS transistor).

22. The voltage stabilization method according to any one of claims 13-21, characterized in that, The soft start module includes a capacitor.

23. The voltage stabilization method according to claim 18, characterized in that, The first switching transistor is a PMOS transistor.

24. The voltage stabilization method according to claim 18, characterized in that, The voltage dividing circuit includes a first resistor and a second resistor; the first end of the first resistor is coupled to the voltage output end of the LDO circuit, the second end of the second resistor is grounded, and the second end of the first resistor and the first end of the second resistor are coupled at the voltage dividing node.

25. An electronic device, characterized in that, It includes a voltage stabilizing circuit, a power management chip, a controller, and a load as described in any one of claims 1-12. The voltage output end of the power management chip is coupled to the input end of the voltage stabilizing circuit; the enable end of the voltage stabilizing circuit is coupled to the controller, and the output end of the voltage stabilizing circuit is coupled to the load; the controller is used to control the voltage stabilizing circuit to supply power to the load.

26. An electronic device, characterized in that, It includes a memory and one or more controllers, and the memory is coupled to the controller; wherein, computer program code is stored in the memory, and the computer program code includes computer instructions. When the computer instructions are executed by the controller, the electronic device executes the voltage stabilizing method as described in any one of claims 13-24.

27. A computer-readable storage medium, characterized in that, It includes computer instructions. When the computer instructions run on the electronic device, the electronic device executes the voltage stabilizing method as described in any one of claims 13-24.

28. A computer program product, characterized in that, When the computer program product runs on a computer, the computer executes the voltage stabilizing method as described in any one of claims 13-24.

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