Computing storage system, operating method thereof, and electronic device

Abstract

A computing storage system, an operating method thereof, and an electronic device are provided. The computing storage system includes: a storage device configured to store data; and a computing device comprising a non-volatile memory fast flow controller (NFC), an accelerator, and a memory, the computing device configured to perform data processing on input data provided from the storage device or a host device external to the computing storage system, the NFC comprising a power management (PM) module, the PM module is configured to identify whether a target command related to power control of the accelerator is received from among a plurality of commands received from the host device, and when the target command is received, perform the power control of the accelerator based on the target command.

Description

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0010401, filed with the Korean Intellectual Property Office on January 23, 2024, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The inventive concept relates to a compute-storage system for performing power management of a computing device. Background Art

[0003] In an electronic device including a storage device and a host device, instructions (or programs) and data may be stored in the storage device, and the instructions and data need to be sent from the storage device to the host device to perform data processing based on the instructions. Therefore, even when the processing speed of the host device increases, the data transfer speed between the host device and the storage device may become an obstacle to performance improvement, and thus may limit the throughput of the entire system. To solve the above problems, a compute-storage system including both components of an existing storage device and a computing device capable of processing data has been studied.

[0004] Recently, the Non-Volatile Memory Express (NVMe) Compute-Storage (CS) specification has been proposed to control a storage device and a computing device of a compute-storage system as one NVMe device. Here, the NVMe CS specification may be a specification added to perform data processing / computation and data storage in a storage system, and may include content for storing / executing a program in a compute slot or accessing a dynamic random access memory (DRAM) for computation. Thus, a host device may manage a storage device and a computing device through one NVMe interface (e.g., a single NVMe CS interface). However, although the storage device and the computing device can be managed through one NVMe interface (e.g., a single NVMe CS interface) in a compute-storage system, independent power management of the computing device may not be performed separately from the storage device. Specifically, when a storage server uses a field programmable gate array (FPGA) including a compute-storage system, the computing device may consume a large amount of power even in a standby state where it does not perform data processing / computation. Thus, there is a need to separately manage the power of the computing device. Accordingly, there is a need to develop a method for solving the above problems. Summary of the Invention

[0005] Some example embodiments of the inventive concept provide a method and apparatus capable of performing independent power management of a computing device separately from power management of a storage device in a compute-storage system capable of managing a storage device and a computing device through one interface (e.g., a single Non-Volatile Memory Express (NVMe) Compute-Storage (CS) interface).

[0006] The technical problems of the inventive concept are not limited to the above-mentioned technical problems, and other technical problems not mentioned can be clearly understood by those of ordinary skill in the art from the following description.

[0007] According to an exemplary embodiment of the inventive concept, a compute-storage system may include: a storage device configured to store data; and a computing device including a non-volatile memory express controller (NFC), an accelerator, and a memory, the computing device being configured to perform data processing on input data provided from the storage device or a host device external to the compute-storage system, the NFC including a power management (PM) module, wherein the PM module is configured to: identify whether a target command related to power control of the accelerator is received among a plurality of commands received from the host device, and when the target command is received, perform power control of the accelerator based on the target command.

[0008] According to an exemplary embodiment of the inventive concept, a method of operating a compute-storage system including a computing device and a storage device may include: identifying whether a target command related to power control of an accelerator of the computing device is received among a plurality of commands received from a host device external to the compute-storage system; and when the target command is received, performing power control of the accelerator based on the target command.

[0009] According to an exemplary embodiment of the inventive concept, an electronic device may include: a host device; and a compute-storage system including a storage device and a computing device, the compute-storage system being configured to be operatively connected to the host device, wherein the compute-storage system is configured to: when a first target command or a second target command related to power control of the computing device is received from the host device, control a change in the power state of the computing device based on the first target command and the second target command, and when a command related to power control of the storage device is received from the host device, bypass the command related to power control of the storage device to the storage device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Exemplary embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0011] Figure 1A 、 Figure 1B and Figure 1C illustrate an example of a compute-storage system according to some exemplary embodiments.

[0012] Figure 2 illustrate a compute-storage system according to an exemplary embodiment.

[0013] Figure 3A illustrate an example of a field included in a signal according to an exemplary embodiment.

[0014] Figure 3BShows an example of a field included in a signal according to an example embodiment.

[0015] Figure 4A Is a view showing the operation of a compute storage system according to an example embodiment.

[0016] Figure 4B Is a view showing the operation of a compute storage system according to an example embodiment.

[0017] Figure 4C Is a view showing the operation of a compute storage system according to an example embodiment.

[0018] Figure 5 Shows a flowchart of a method for operating a compute storage system according to an example embodiment.

[0019] Figure 6 Is a block diagram schematically showing a compute storage system and a data processing system according to an example embodiment.

[0020] Figure 7 Is a block diagram showing an electronic device according to an example embodiment. Detailed Description

[0021] Hereinafter, some example embodiments will be described in detail with reference to the drawings. The example embodiments are shown in the drawings and their related detailed descriptions are given, but the illustrations and descriptions are not intended to limit the various example embodiments to a specific form. For example, it will be apparent to those of ordinary skill in the art that the example embodiments can be changed in various forms.

[0022] In the description, a compute storage system may be a compute storage system that includes a storage device and a computing device and is capable of managing the storage device and the computing device through a non-volatile memory express (NVMe) interface (e.g., a single NVMe compute storage (CS) interface).

[0023] Figure 1A 、 Figure 1B and Figure 1C Show examples of a compute storage system according to some example embodiments.

[0024] For example, Figure 1A 、 Figure 1B and Figure 1C Show examples of cases where no computation is performed in a computing device (e.g., an accelerator) of a compute storage system. In Figure 1A 、 Figure 1B and Figure 1C The tenth accelerator 10, the eleventh accelerator 11, the twelfth accelerator 12, the twentieth accelerator 20, the twenty-first accelerator 21, and the twenty-second accelerator 22 may correspond to the computing engines of multiple computing devices included in the compute storage system.

[0025] Referring to Figure 1A Figure 1A , the tenth accelerator 10 of the compute storage system is operably connected to the zero-th disk DISK0, and the twentieth accelerator 20 is operably connected to the third disk DISK3. Figure 1A It can be shown a case of configuring a RAID (Redundant Array of Independent Disks) 1 by using the compute storage system, but the example embodiments are not limited thereto.

[0026] The compute storage system can receive commands and input data for data processing from a host (or host device) 100. The compute storage system can store output data obtained by processing the input data based on the tenth accelerator 10 according to the command in the zero-th disk DISK0. The compute storage system can mirror the output data and send the mirrored output data to the third disk DISK3. Here, the third disk DISK3 can simply receive the output data from the zero-th disk DISK0 and store the received output data, and can not perform data calculation through the twentieth accelerator 20. Therefore, the twentieth accelerator 20 can continue to consume power without performing data calculation or data processing, and thus, the compute storage system needs to control the power state of the twentieth accelerator 20 to an idle state.

[0027] Referring to Figure 1B Figure 1B , the tenth accelerator 10 of the compute storage system is operably connected to the zero-th disk DISK0, the eleventh accelerator 11 is operably connected to the first disk DISK1, the twelfth accelerator 12 is operably connected to the second disk DISK2, and the twentieth accelerator 20 is operably connected to the third disk DISK3. Figure 1B It can be shown a case of configuring a RAID 5 by using the compute storage system, but the example embodiments are not limited thereto.

[0028] A compute storage system can receive commands and input data for data processing from a host 100. The compute storage system can store output data obtained by processing the input data based on a tenth accelerator 10, an eleventh accelerator 11, and a twelfth accelerator 12 in a zero-th disk DISK0, a first disk DISK1, and a second disk DISK2 respectively connected to the tenth accelerator 10, the eleventh accelerator 11, and the twelfth accelerator 12. The compute storage system can reconstruct the output data stored in the zero-th disk DISK0, the first disk DISK1, and the second disk DISK2 based on the tenth accelerator 10, the eleventh accelerator 11, and the twelfth accelerator 12, and send the reconstructed output data to a third disk DISK3. Here, the third disk DISK3 can simply receive and store the reconstructed data, and can not perform data calculation through a twentieth accelerator 20. Therefore, the twentieth accelerator 20 can consume power without performing data calculation or data processing, and thus, the compute storage system needs to control the power state of the twentieth accelerator 20 to an idle state.

[0029] Referring to Figure 1C , a first server 1 (or Server 1) of the compute storage system can include a tenth accelerator 10, an eleventh accelerator 11, and a twelfth accelerator 12, and a second server 2 (or Server 2) can include a twentieth accelerator 20, a twenty-first accelerator 21, and a twenty-second accelerator 22. Here, the tenth accelerator 10 can be operably connected to the zero-th disk DISK0, the eleventh accelerator 11 can be operably connected to the first disk DISK1, and the twelfth accelerator 12 can be operably connected to the second disk DISK2. The twentieth accelerator 20 can be operably connected to the third disk DISK3, the twenty-first accelerator 21 can be operably connected to the fourth disk DISK4, and the twenty-second accelerator 22 can be operably connected to the fifth disk DISK5. Figure 1C A case where a 2-node high availability (HA) is configured based on the first server 1 and the second server 2 can be shown, but the example embodiments are not limited thereto. Here, each of the first server 1 and the second server 2 can be a storage server, and can be a device including a host device 100 and a compute storage system 200 described below referring to Figure 2 .

[0030] The compute storage system can receive commands and input data for data processing from the host 100. The compute storage system can store the output data obtained by processing the input data based on the tenth accelerator 10, the eleventh accelerator 11, and the twelfth accelerator 12 in the zero-th disk DISK0, the first disk DISK1, and the second disk DISK2 respectively connected to the tenth accelerator 10, the eleventh accelerator 11, and the twelfth accelerator 12. The compute storage system can mirror the output data stored in the zero-th disk DISK0, the first disk DISK1, and the second disk DISK2, and send the mirrored output data to the third disk DISK3, the fourth disk DISK4, and the fifth disk DISK5 of the second server 2. Here, the third disk DISK3, the fourth disk DISK4, and the fifth disk DISK5 can simply receive and store the mirrored data, and do not perform data calculations through the twentieth accelerator 20, the twenty-first accelerator 21, and the twenty-second accelerator 22. Therefore, the twentieth accelerator 20, the twenty-first accelerator 21, and the twenty-second accelerator 22 can consume power without performing data calculations or data processing. The compute storage system needs to change the power states of the twentieth accelerator 20, the twenty-first accelerator 21, and the twenty-second accelerator 22 to reduce or prevent undesired power consumption.

[0031] Accordingly, some example embodiments can provide a compute storage system and an operation method thereof that can independently control the power state of a computing device (e.g., an accelerator).

[0032] For example, when a computing device (e.g., an accelerator) does not perform data calculations / processing, some example embodiments can provide a compute storage system and an operation method thereof that can reduce or prevent undesired power consumption by changing the power state of the computing device (e.g., an accelerator) through independent power management of the computing device (e.g., an accelerator). The following will refer to the Figures 2 to 5 detailed description given below.

[0033] Although for ease of description, some example embodiments of the compute storage system have been described based on Figure 1A , Figure 1B and Figure 1C , the compute storage system according to the example embodiments is not limited thereto, and can be various compute storage systems that require independent power management for computing devices.

[0034] According to some example embodiments of the compute storage system, its operation method, and an electronic device, independent power management of the computing device can be performed.

[0035] A computing storage system, an operating method thereof, and an electronic device according to some example embodiments may adaptively perform power management of a computing device according to an operating state of the computing device. For example, when the computing device does not perform a computing operation, the computing storage system may reduce or prevent an undesired power consumption in the computing device by changing a power state of the computing device.

[0036] In addition, when power consumed by the computing device is reduced, an overall energy efficiency of the computing storage system and the electronic device including the computing storage system may be increased or maximized.

[0037] Figure 2 A computing storage system 200 according to an example embodiment is shown.

[0038] Referring to Figure 2 , the computing storage system 200 according to the example embodiment may include a computing device 210, a memory (e.g., volatile memory (VM)) 240, and a storage device 250.

[0039] A host device 100 may manage an overall operation of the computing storage system 200. For example, the host device 100 may send a plurality of NVMe commands (including a target command described below) to the computing storage system 200 to manage the overall operation of the computing storage system 200.

[0040] The host device 100 may store data in the computing storage system 200 and read data from the computing storage system 200. For example, the host device 100 may store a write request and write data in the computing storage system 200, or may send a read request to the computing storage system 200. In addition, the host device 100 may assign tasks and data to the computing storage system 200 and control the computing storage system 200 such that the computing storage system 200 performs the tasks. For example, the host device 100 may send a data processing request for "performing a task together with data to be processed by the computing storage system 200" to the computing storage system 200, or may send a data processing request for data pre-stored in the computing storage system 200 to the computing storage system 200.

[0041] In an example embodiment, the host device 100 may send power management (PM) requests for the computing device 210 and the storage device 250 to the compute storage system 200. For example, the host device 100 may send commands related to the power management of the computing device 210 (e.g., target commands or target PM commands) to the compute storage system 200. Here, the target commands may include a first target command for requesting power state information supported by the computing device 210 (e.g., an adder) and a second target command for requesting the current power state information of the computing device 210 (e.g., an adder) or for requesting a change in the power state of the computing device 210 (e.g., an adder). Here, the content of the second target command may vary according to the value stored in a specific field (e.g., the first field). For example, when a is stored in a specific field (e.g., the first field), the second target command may be a command for requesting the current power state information of the computing device 210 (e.g., an adder). As another example, when b is stored in a specific field (e.g., the first field), the second target command may be a command for requesting a change in the power state of the computing device 210 (e.g., an adder).

[0042] The host device 100 may be implemented as a central processing unit (CPU), a processor, a microprocessor, an application processor (AP), a system on chip (SoC), etc.

[0043] The compute storage system 200 may include a computing device 210, a storage device 250, and a VM 240. The compute storage system 200 may be referred to as a compute storage device. The compute storage system 200 may store or process data in response to requests from the host device 100. In an example embodiment, the compute storage system 200 may be implemented as a storage acceleration platform that accelerates data processing by internally storing and processing data. For example, the compute storage system 200 may be an intelligent solid state drive (SSD). The compute storage system 200 may be a compute storage system capable of managing the computing device 210 and the storage device 250 through one interface (e.g., a single NVMe compute storage (CS) interface).

[0044] The storage device 250 may include a memory controller 251 and a non-volatile memory (NVM) 253, and may store data provided from the host device 100 in the NVM 253.

[0045] The memory controller 251 may manage the overall operation of the storage device 250 and may control the NVM 253 to perform operations according to requests received from the host device 100. For example, in response to a write request or a read request from the host device 100, the memory controller 251 may control the NVM 253 to write data to the NVM 253 or read data from the NVM 253, and may control the erase operation of the NVM 253. In addition, the memory controller 251 may manage the main operations of the NVM 253 (such as garbage collection, bad block management, read recycling, and read replacement), and may manage the power of the NVM 253. In one exemplary embodiment, the memory controller 251 of the storage device 250 may change the power state of the storage device 250 based on a command related to power management of the storage device 250 bypassed or sent from the NVM flow controller (NFC) 220 (or the PM module 221 of the NFC 220).

[0046] The NVM 253 may store data. The NVM 253 may store data provided from the host device 100 or data provided from the computing device 210. The NVM 253 may include a memory cell array (MCA), and the memory cell array (MCA) includes non-volatile memory cells capable of retaining stored data even when the power of the storage device 250 is cut off, and the MCA may be divided into a plurality of memory blocks. The plurality of memory blocks may have a two-dimensional horizontal structure in which memory cells are two-dimensionally arranged on the same plane (or layer) or a three-dimensional vertical structure in which non-volatile memory cells are three-dimensionally arranged. The memory cells may be single-level cells (SLCs) that store one bit of data or multi-level cells (MLCs) that store two or more bits of data. However, the inventive concept is not limited thereto, and each memory cell may be a three-level cell (TLC) that stores 3 bits of data or a quad-level cell (QLC) that stores 4 bits of data.

[0047] In one exemplary embodiment, the NVM 253 may include a plurality of dies or chips, and each of the plurality of dies or chips includes an MCA. For example, the NVM 253 may include a plurality of chips, and each of the plurality of chips may include a plurality of dies. In one exemplary embodiment, the NVM 253 may further include a plurality of channels, and each of the plurality of channels includes a plurality of chips.

[0048] In one exemplary embodiment, the NVM 253 may be a NAND flash device. However, the inventive concept is not limited thereto, and the NVM 253 may be implemented as a resistive memory device (such as a resistive random access memory (ReRAM)), a phase change RAM (random access memory) (PRAM), and a magnetic RAM (MRAM).

[0049] The computing device 210 can be a device that performs data processing on data received from the host device 100 and can perform data processing in response to a data processing request received from the host device 100. For example, the computing device 210 can perform data processing on input data by driving an application. The application can include multiple data operations related to tasks such as performing arithmetic operations, convolution operations, polling operations, etc. For example, when the computing device 210 performs a neural network-based task, the application can include a neural network model. The neural network model can include multiple data operations based on at least one of a convolutional neural network (CNN), region-based convolutional neural network (R-CNN), region proposal network (RPN), recurrent neural network (RNN), stacked deep neural network (S-DNN), state space dynamic neural network (S-SDNN), deconvolution network, deep belief network (DBN), restricted Boltzmann machine (RBM), fully convolutional network, long short-term memory (LSTM) network, classification network, and various types of neural networks, as well as the input, output size, weights, biases, etc. of the multiple data operations.

[0050] For example, the computing device 210 can be implemented as a graphics processing unit (GPU), a digital signal processor (DSP), a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a neural processing unit (NPU), etc. However, the computing device 210 is not limited thereto, and can include various types of accelerators (or accelerator circuits) 230 that perform data processing (e.g., data calculation) required to execute an assigned task in parallel.

[0051] The computing device 210 can include an NFC 220 and an accelerator 230, and the NFC 220 includes a PM module 221.

[0052] The NFC 220 can manage the transmission of requests, data, etc. between the host device 100 and the accelerator 230 within the computing device 210 in the computing storage system 200. In addition, the NFC 220 can manage the transmission of requests, data, etc. between the host device 100 and the storage device 250 in the computing storage system 200. For example, the NFC 220 can support the NVMe CS specification (e.g., a single NVMeCS interface specification, etc.), but the exemplary embodiments are not limited thereto.

[0053] NFC 220 can receive a plurality of commands for the storage device 250 and the computing device 210 (e.g., the accelerator 230). For example, NFC 220 can receive a data processing request from the host device 100. The data processing request can be a request for the computing device 210 to perform data processing on data pre-stored in the storage device 250 or on data received from the host device 100. When a data processing request is received from the host device 100, NFC 220 can send the data processing request to the accelerator 230. Accordingly, data processing corresponding to the data processing request can be performed by the accelerator 230 of the computing device 210.

[0054] In response to receiving a command related to power management of the storage device 250 among the plurality of commands, the NFC 220 (or the PM module 221) according to an example embodiment can bypass or send the command related to power management of the storage device 250 to the storage device 250.

[0055] In one example embodiment, NFC 220 can include a PM module 221. The PM module 221 of NFC 220 can be a module for controlling the power state of the accelerator 230. The PM module 221 can identify (or parse) a command related to power management of the computing device 210 (e.g., the accelerator 230) (e.g., a first target command and / or a second target command) among the plurality of commands. A command related to power management of the computing device 210 (e.g., the accelerator 230) can be referred to as a target command (e.g., a target PM command).

[0056] In one example embodiment, in response to receiving a first target command from the host device 100, the PM module 221 of NFC 220 can store information about whether the computing storage system 200 supports the NVMe CS specification (e.g., a single NVMe CS interface specification, etc.) in the zero-th field of the first target command, store information about the number of power states supported by the accelerator 230 in the first field of the first target command, and store information about the characteristics of the power states supported by the accelerator 230 in the second field of the first target command. The PM module 221 can send the first target command with the above information items stored in the zero-th field, the first field, and the second field respectively to the host device 100.

[0057] In an example embodiment, the host device 100 may store a request for the NFC 220 (e.g., a request for the current power state information of the accelerator 230) in a specific field (e.g., the first field) of a second target command, and send the stored request (e.g., the second target command storing the request in the specific field (e.g., the first field)) to the NFC 220. The PM module 221 of the NFC 220 of the computing device 210 may decode the second target command received from the host device 100. As a result of the decoding, when the second target command is a command for requesting the current power state information of the accelerator 230, the PM module 221 may send a signal for requesting the current power state information of the accelerator 230 to the accelerator 230 based on the second target command. The PM module 221 may receive the current power state information of the accelerator 230 from the accelerator 230. The PM module 221 may store the current power state information of the accelerator 230 in a specific field (e.g., the second field) of the second target command, and send the stored current power state information to the host device 100. The following refers to Figure 3B A detailed description of the second target command is given.

[0058] In an example embodiment, the host device 100 may store a request for the NFC 220 (e.g., a request for changing the power state of the accelerator 230) in a specific field (e.g., the first field) of a second target command, store the power state information of the accelerator 230 to be changed in a specific field (e.g., the second field) of the second target command, and send the second target command, the stored request, and the stored power state information to the NFC 220. The PM module 221 of the NFC 220 of the computing device 210 may decode the second target command received from the host device 100. As a result of the decoding, when the second target command is a command for requesting to change the power state of the accelerator 230, the PM module 221 may send a control signal for changing the power state of the accelerator 230 to the accelerator 230 based on the second target command. The accelerator 230 may change its power state to the power state included in the control signal (e.g., the power state requested by the host device 100 through the second field of the second target command). Refer to Figure 3B A detailed description of the second target command is given.

[0059] The accelerator 230 may perform data processing in response to a data processing request. In response to the data processing request, the accelerator 230 may perform data processing on data pre-stored in the storage device 250 or on data received from the host device 100. The accelerator 230 may store the values calculated during the data processing in internal registers. In addition, the accelerator 230 may store the data generated during the data processing and the data generated as a result of the data processing in the VM 240. The accelerator 230 may store the data generated as a result of the data processing in the storage device 250 via the NFC 220.

[0060] In one example embodiment, in response to receiving a control signal corresponding to a first target command from the NFC 220, the accelerator 230 may send power state information supported by the accelerator 230 (e.g., information about the number of power states supported by the accelerator 230 and information about the characteristics of the power states) to the NFC 220.

[0061] In one example embodiment, in response to receiving a control signal corresponding to a second target command from the NFC 220, the accelerator 230 may send the current power state information of the accelerator 230 to the NFC 220.

[0062] In one example embodiment, in response to receiving a control signal corresponding to a second target command from the NFC 220, the accelerator 230 may change the power state of the accelerator 230 according to the control signal. For example, the accelerator 230 may change the power state of the accelerator 230 to the power state included in the control signal (e.g., the power state requested by the host device 100).

[0063] The VM 240 may store data for data processing by the computing device 210. The VM 240 may store the data generated by the computing device 210 or the data generated as a result of the data processing. Here, when the computing device 210 performs data processing based on the data stored in the storage device 250, the data stored in the storage device 250 may be read and stored in the VM 240. The VM 240 may be implemented as a volatile memory (such as DRAM, static RAM (SRAM), etc.). Although the VM 240 is shown in the drawings as being provided outside the computing device 210, the example embodiment is not limited thereto. For example, the VM 240 may be provided inside the computing device 210 as a component of the computing device 210.

[0064] As described above, when using the compute storage system 200 according to the example embodiment, power control of the computing device 210 (e.g., the accelerator 230 of the computing device 210) can be performed separately from the storage device 250, and thus, unwanted power consumption can be reduced or prevented in the computing device 210 to improve the energy efficiency of the entire compute storage system 200.

[0065] Figure 3A An example showing fields included in a signal according to an example embodiment.

[0066] For example, Figure 3A An example showing fields for power management of the computing device 210 (e.g., the accelerator 230) of the compute storage system 200 included in a first target command according to an example embodiment (hereinafter referred to as the NVMe PM field). For example, the first target command may correspond to a command of the NVMe CS specification (e.g., an identify controller command). In Figure 3A , I / O may represent an "I / O command", Admin may represent an "administrator command", and Disc may represent an "NVMe over Fabrics Discovery command". And furthermore, in Figure 3A , M may represent "Mandatory", O may represent "Optional", and R may represent "Reserved". However, the example embodiment is not limited thereto.

[0067] Referring to Figure 3A , the NVMe PM field of the first target command according to the example embodiment ( Figure 3A 's table) may include a field (e.g., the shaded part of Figure 3A 's table) for storing data / information for power control of the computing device 210 (e.g., the accelerator 230) and a field (e.g., the non-shaded part of Figure 3A 's table) for storing data / information for power control of the storage device 250.

[0068] In one example embodiment, in the first target command, the field (e.g., the shaded part of Figure 3A 's table) for storing data / information for power control of the computing device 210 (e.g., the accelerator 230) may include a zero field (not shown) to a second field.

[0069] In an example embodiment, information about an interface supported by the compute storage system 200 (e.g., information about the NVMe CS specification related to the interface) may be stored (e.g., OACS

[13] =1) in the zero-th field (not shown) of the first target command (e.g., the optional administrative common support (OACS) bit field). For example, the host device 100 may identify whether the compute storage system 200 supports the NVMe CS specification (e.g., a single NVMe CS interface specification, etc.) by decoding the zero-th field (not shown) of the first target command received from the NFC 220. For example, when OACS

[13] =1, the host device 100 may identify that the compute storage system 200 supports the NVMe CS specification.

[0070] In an example embodiment, information about the number of power states supported by the computing device 210 (e.g., the accelerator 230) (e.g., 1806 bytes) may be stored in the first field of the first target command (e.g., Figure 3A the number of accelerator power state supports (NAPSS) field). For example, the host device 100 may identify the number of power states supported by the computing device 210 (e.g., the accelerator 230) (e.g., 32) by identifying the data in the first field of the first target command received from the NFC 220 (e.g., Figure 3A the NAPSS field).

[0071] In an example embodiment, information about the corresponding power states supported by the computing device 210 (e.g., the accelerator 230) and the characteristics of the corresponding power states (e.g., descriptors of the corresponding power states (e.g., the power state 0 descriptor (PSD0) corresponding to bytes 2079:2048 and the power state 0 descriptor (PSD31) corresponding to bytes 3071:3040)) may be stored in the second field of the first target command. The second field may include a plurality of sub-fields (e.g., Figure 3A the first accelerator power state descriptor (APSD) field APSD0 to the thirty-second APSD field APSD31) corresponding to the power states supported by the computing device 210 (e.g., the accelerator 230), respectively.

[0072] For example, the host device 100 may identify the sub-fields in the second field of the first target command received from the NFC 220 (e.g., Figure 3AData of the first APSD field APSD0 to the thirty - second APSD field APSD31) is used to identify the corresponding power states supported by the computing device 210 (e.g., the accelerator 230) and the characteristics of the corresponding power states. Here, the first APSD field APSD0 (e.g., byte 3103:3072) may include information about the characteristics of the first power state of the computing device 210 (e.g., the accelerator 230) (e.g., accelerator power state 0 descriptor (APSD0)), and the thirty - second APSD field APSD31 (e.g., byte 4095:4064) may include information about the characteristics of the thirty - second power state of the computing device 210 (e.g., the accelerator 230) (e.g., accelerator power state 0 descriptor (APSD31)). For example, the first power state of the computing device 210 (e.g., the accelerator 230) may represent a state that does not limit the maximum power consumption of the computing device 210 (e.g., the accelerator 230), the second power state of the computing device 210 (e.g., the accelerator 230) may represent a state that limits the maximum power consumption of the computing device 210 (e.g., the accelerator 230) by 10%, the third power state of the computing device 210 (e.g., the accelerator 230) may represent a state that limits the maximum power consumption of the computing device 210 (e.g., the accelerator 230) by 20%, and the thirty - second power state of the computing device 210 (e.g., the accelerator 230) may represent an idle state that maximally limits the maximum power consumption of the computing device 210 (e.g., the accelerator 230). However, the power states supported by the computing device 210 (e.g., the accelerator 230) according to this example embodiment are examples for ease of description. The example embodiment is not limited thereto and may include various different power states.

[0073] As described above, the PM module 221 of the NFC 220 can provide the power states supported by the computing device 210 (e.g., the accelerator 230) to the host device 100 through the sub - fields of the second field of the first target command (e.g., the first APSD field APSD0 to the thirty - second field APSD31), so that the host device 100 can change / set the power state of the computing device 210 (e.g., the accelerator 230).

[0074] Although for ease of description, Figure 3A it is shown that the number of power states supported by the computing device 210 (e.g., the accelerator 230) is 32, but the power states supported by the computing device 210 (e.g., the accelerator 230) according to the example embodiment are not limited thereto and may include fewer or more power states.

[0075] Figure 3B The figure illustrates an example of the fields included in the signal according to the example embodiment.

[0076] For example,Figure 3B Shows a field for power management of the computing device 210 (e.g., accelerator 230) of the storage system 200 included in the second target command according to an exemplary embodiment (hereinafter referred to as the NVMe PM field). For example, the second target command may correspond to the set / get feature command of the NVMe CS specification. However, the second target command according to the exemplary embodiment is not limited thereto.

[0077] Refer to Figure 3B , the NVMe PM field of the second target command according to the exemplary embodiment ( Figure 3B 's table) may include a field for storing data / information for power control of the computing device 210 (e.g., accelerator 230) (e.g., Figure 3B 's shaded part in the table) and a field for storing data / information for power control of the storage device 250 (e.g., Figure 3B 's unshaded part in the table).

[0078] In one exemplary embodiment, in the second target command, the field for storing data / information for power control of the computing device 210 (e.g., accelerator 230) (e.g., Figure 3B 's shaded part) may include a first field.

[0079] In one exemplary embodiment, information about the request content of the host device 100 may be stored in the header (not shown) of the second target command. The NFC 220 may identify the request content of the host device 100 by decoding the header of the second target command. For example, the PM module 221 of the NFC 220 may decode the header of the second target command to identify whether the host device 100 is requesting the current power state information of the computing device 210 (e.g., accelerator 230) or a change in the power state of the computing device 210 (e.g., accelerator 230).

[0080] In one exemplary embodiment, the first field of the second target command (e.g., Figure 3B 's accelerator power state (APS) field in) may store the current power state information of the computing device 210 (e.g., accelerator 230) or the power state information of the computing device 210 (e.g., accelerator 230) to be changed.

[0081] In one exemplary embodiment, as a result of decoding the header of the second target command, when the host device 100 requests the current power state information of the computing device 210 (e.g., accelerator 230), the PM module 221 of the NFC 220 may store the current power state information of the computing device 210 (e.g., accelerator 230) in the first field of the second target command (e.g., Figure 3Bin the APS field), and send the stored current power state information to the host device 100.

[0082] In one example embodiment, as a result of decoding the header of the second target command, when the host device 100 requests a change in the power state of the computing device 210 (e.g., accelerator 230), the host device 100 may store information about the power state of the computing device 210 (e.g., accelerator 230) to be changed in the first field of the second target command (e.g., Figure 3B the APS field), and send the stored information to the NFC 220. For example, the host device 100 may store any one of the power states supported by the computing device 210 (e.g., accelerator 230) (e.g., Figure 3A the first power state to the thirty-second power state) as the power state of the computing device 210 (e.g., accelerator 230) to be changed in the first field of the second target command (e.g., Figure 3B the APS field), and send the stored power state to the NFC 220. The PM module 221 may send a control signal for changing the power state of the accelerator 230 to the accelerator 230. The accelerator 230 may change the power state of the accelerator 230 to the power state included in the control signal. When information about a power state not supported by the accelerator 230 is stored in the first field of the second target command, the PM module 221 of the NFC 220 may stop operating according to the second command and return a field error to the host device 100. When the operating state of the computing device 210 changes (e.g., changes from an idle state to an active state, or from an active state to an idle state, etc.), the second target command for changing the power state of the computing device 210 (e.g., accelerator 230) may be sent from the host device 100 to the NFC 220.

[0083] Figure 4A is a view showing the operation of a compute storage system according to an example embodiment.

[0084] Figures 4A to 4C is a view showing the operation of the NFC 220 (e.g., PM module 221) of the compute storage system 200 controlling the power of the computing device 210 (e.g., accelerator 230) when 2-node HA is configured by using storage servers (e.g., Server 0510 of the zero server and Server 1530 of the first server). In Figures 4A to 4C each of the storage servers (e.g., Server 0510 of the zero server and Server 1530 of the first server) may include a compute storage system 200, and the compute storage system 200 includes a computing device 210 and a host device 100. Compared with FIGS. 1 toFigure 3B identical to the description of Figures 4A to 4C The description of is shown in FIGS. 1 to Figure 3B is replaced with the above description.

[0085] Referring to Figure 4A , the host device 100 may send a first target command to a storage server (e.g., the zero - th server Server 0 510 and the first server Server 1 530) to identify interface information (e.g., information regarding the NVMe CS specification related to the interface) supported by the storage server (e.g., the zero - th server Server0 510 and the first server Server 1 530) (or the compute - storage system 200 included in each of the storage servers). Each NFC 220 (e.g., the PM module 221) included in the storage server (e.g., the zero - th server Server 0 510 and the first server Server 1 530) may store in the first target command (referring to Figure 3A ): 1) information regarding the interface supported by each compute - storage system 200 (e.g., information regarding the NVMe CS specification related to the interface) and 2) information regarding the power states supported by the accelerators (e.g., the tenth accelerator 10 511 to the twenty - first accelerator 21 532) of each compute - storage system 200, and send the stored information to the host device 100. The host device 100 may identify / verify whether each of the storage servers (e.g., the zero - th server Server0 510 and the first server Server1 530) (or the compute - storage system 200 included in each of the storage servers) supports the NVMe CS specification, and the power states supported by the accelerators (e.g., the tenth accelerator 10 511 to the twenty - first accelerator 21 532) of the compute - storage system 200 of each of the storage servers (e.g., the zero - th server Server 0510 and the first server Server 1 530) through the first target command received from the NFC 220.

[0086] Figure 4B is a diagram showing the operation of a compute - storage system according to an example embodiment.

[0087] Referring to Figure 4B, the host device 100 can send data I / O and commands CMD (e.g., commands for indicating calculations and data synchronization (for configuring 2-node HA)) to the zeroth server Server 0 510. The zeroth server Server 0 510 can store the output data obtained by performing calculations on the data I / O based on the tenth accelerator 10 511 and the eleventh accelerator 11 512 according to the command CMD in the zeroth disk DISK0 and the first disk DISK1. The zeroth server Server 0 510 can synchronize the output data with the first server Server 1 530 to configure 2-node HA (synchronize data) according to the command CMD. For example, the zeroth server Server 0 510 can send the output data stored in the zeroth disk DISK0 and the first disk DISK1 to the second disk DISK2 and the third disk DISK3 of the first server Server 1 530. Here, the second disk DISK2 and the third disk DISK3 receive the output data from the zeroth disk DISK0 and the first disk DISK1 and store the received output data, simply for data synchronization, and may not perform data calculations through the twentieth accelerator 20 531 and the twenty-first accelerator 21 532. Therefore, the host device 100 can change / set the power states of the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 to the idle state. For example, the host device 100 can send a second target command (refer to Figure 3B ) for requesting a change in the power states of the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 to the NFC 220 of the first server Server 1 530. In response to receiving the second target command, the NFC 220 (e.g., the PM module 221) of the first server Server 1 530 can send a control signal for changing the power states of the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 to the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 according to the second target command. The twentieth accelerator 20 531 and the twenty-first accelerator 21 532 can change the power states of the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 to the idle state according to the received control signal.

[0088] Figure 4C is a diagram showing the operation of a compute storage system according to an exemplary embodiment.

[0089] Refer to Figure 4C , in the configuration Figure 4BAfter the 2-node HA, an error may occur in the zero-th server Server 0 510, and the zero-th server Server 0 510 can failover to the first server Server 1 530. The host device 100 can set the power states of the tenth accelerator 10 511 and the eleventh accelerator 11 512 of the zero-th server Server 0 510 where the error occurred to the idle state PS (idle). For example, the host device 100 can send a second target command for requesting a change in the power states of the tenth accelerator 10 511 and the eleventh accelerator 11 512 to the NFC 220 of the zero-th server Server 0 510. In response to receiving the second target command, the NFC 220 (e.g., the PM module 221) of the zero-th server Server 0 510 can send a control signal for changing the power states of the tenth accelerator 10 511 and the eleventh accelerator 11 512 to the tenth accelerator 10 511 and the eleventh accelerator 11 512 according to the second target command. The tenth accelerator 10 511 and the eleventh accelerator 11 512 can change the power states of the tenth accelerator 10 511 and the eleventh accelerator 11 512 to the idle state PS (idle) according to the received control signal.

[0090] The host device 100 can continue to execute services on behalf of the zero-th server Server 0 510 where the error occurred through the first server Server 1 530. The host device 100 can change / set the power states of the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 of the first server Server 1 530 to the active state PS (active) to continue to execute services (e.g., data calculation) through the first server Server 1 530. For example, the host device 100 can send a second target command (refer to Figure 3B ) for requesting a change in the power states of the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 to the NFC 220 of the first server Server 1 530. In response to receiving the second target command, the NFC 220 (e.g., the PM module 221) of the first server Server 1 530 can send a control signal for changing the power states of the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 to the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 according to the second target command. The twentieth accelerator 20 531 and the twenty-first accelerator 21 532 can change the power states of the twentieth accelerator 20 531 and the twenty-first accelerator 21 532 from the idle state PS (idle) to the active state PS (active) according to the received control signal.

[0091] The host device 100 can send data I / O and commands CMD (e.g., commands for instructing computations to be performed according to failover) to the first server Server 1 530. The first server Server 1 530 can store the output data obtained by performing computations on the data I / O according to the command CMD based on the activated twentieth accelerator 20 531 and twenty-first accelerator 21 532 in the second disk DISK2 and the third disk DISK3.

[0092] As referred to above Figures 4A to 4C As described, the devices and methods according to those example embodiments can improve the energy efficiency of the entire system by adaptively performing power control of the computing device 210 (e.g., accelerator 230) according to the operating state of the computing device 210 (e.g., accelerator 230) (e.g., separately from the storage device 250).

[0093] Figure 5 A flowchart showing a method of operating a compute storage system according to an example embodiment.

[0094] Referring to Figure 5 , the method of operating for power control of the computing device 210 (e.g., accelerator 230) by the NFC 220 (e.g., PM module 221) of the compute storage system 200 may include operation S100 and operation S110. The same as the description of FIGS. 1 to Figure 4C The description of Figure 5 is replaced with the description of FIGS. 1 to Figure 4C . Referring to Figure 5 The compute storage system 200, computing device 210, NFC 220, PM module 221, accelerator 230, and storage device 250 described may correspond to the compute storage system 200, computing device 210, NFC 220, PM module 221, accelerator 230, and storage device 250 of FIGS. 1 to Figure 4C respectively.

[0095] In the description, the compute storage system may be a compute storage system including a storage device and a computing device and capable of managing the storage device and the computing device through one NVMe interface (e.g., a single NVMe CS interface).

[0096] In operation S100, the PM module 221 of the NFC 220 can identify whether a target command is received among a plurality of commands received from a host device 100 external to the computing storage system. Here, the target command can represent at least one command related to the power control of the accelerator 230 among the plurality of commands. For example, the type of the target command can include a first target command for requesting power state information supported by the accelerator 230 and a second target command for requesting the current power state information of the accelerator 230 or changing the power state of the accelerator 230.

[0097] In one example embodiment, in response to receiving a command related to the power control of the storage device 250 among the plurality of commands received from the host device 100, the PM module 221 can bypass or send the command related to the power control of the storage device 250 to the storage device 250.

[0098] In operation S110, when the target command is received, the PM module 221 of the NFC 220 can perform power control of the accelerator 230 of the computing device 210 based on the target command.

[0099] In one example embodiment, in response to receiving the first target command from the host device 100, the PM module 221 can store information about the number of power states supported by the accelerator 230 in the first field of the first target command, store information about the characteristics of each of the power states supported by the accelerator 230 in a sub - field of the second field of the first target command, and send the first target command with "information stored in the first and second fields" to the host device 100.

[0100] In one example embodiment, when the second target command is received, the PM module 221 can identify the content of the request from the host device 100 by decoding the header of the second target command.

[0101] In one example embodiment, when the content of the request from the host device requests the current power state information of the accelerator 230, the PM module 221 can send a signal for requesting the current power state information of the accelerator 230 to the accelerator 230 based on the second target command. The PM module 221 can receive the current power state information of the accelerator 230 from the accelerator 230. The PM module 221 can store the current power state information of the accelerator 230 in the first field of the second target command and send the stored current power state information to the host device 100.

[0102] In an exemplary embodiment, when a request content of the host device 100 requests a change in the power state of the accelerator 230, the PM module 221 may send a control signal for changing the power state of the accelerator 230 to the accelerator 230 based on a second target command. In a first field of the second target command, information about the power state of the accelerator 230 to be changed may be stored by the host device 100. When the operation state of the computing device 210 (e.g., the accelerator 230) is changed (e.g., from an idle state to an active state, or from an active state to an idle state), the second target command for changing the power state of the accelerator 230 may be sent from the host device 100 to the NFC 220. For example, different from the previous state, when the computation is not performed by the computing device 210 (e.g., the accelerator 230), the second target command for changing the power state of the accelerator 230 may be sent from the host device 100 to the NFC 220 of the computing storage system 200. For example, the cases where the computation is not performed by the computing device 210 (e.g., the accelerator 230) may include: the case where the memory included in the computing device 210 stores mirrored data (e.g., configuring RAID1), the case where the memory included in the computing device 210 stores rebuilt data (e.g., configuring RAID5), and the case where the storage server to which the computing device 210 belongs stores mirrored data (e.g., based on a 2-node HA configuration of the storage server) (refer to Figure 4B ). For example, different from the previous state, when an error occurs in another storage server and thus the storage server fails over to the server to which the computing device 210 belongs (refer to Figure 4C ), the second target command for changing the power state of the accelerator 230 may be sent from the host device 100 to the NFC 220 of the computing storage system 200. However, the exemplary embodiments for sending the second target command according to the exemplary embodiment are not limited to the above cases.

[0103] As described above, based on the computing storage system 200 and the operation method according to the above exemplary embodiment, the independent power control of the computing device 210 (e.g., the accelerator 230) may be performed separately from the power control of the storage device 250. Therefore, the computing storage system 200 according to the exemplary embodiment may reduce or prevent undesired power consumption through adaptive power control according to the operation state of the computing device 210 (e.g., the accelerator 230).

[0104] Figure 6 is a block diagram schematically showing a computing storage system and a data processing system according to an exemplary embodiment.

[0105] Refer to Figure 6, the data processing system 1000a may include a host device 100 and a compute storage system 200a, and the compute storage system 200a may include a computing device 210a, an NFC 220a including a PM module 221a, and an NVM 250a. Figure 6 The structure and operation of the compute storage system 200a may be similar to the structure and operation of the compute storage system 200 of FIG. 1.

[0106] However, as Figure 6 shown, the computing device 210a may communicate directly with the host device 100. The computing device 210a may communicate with the NFC 220a via a first path P1 and communicate with the host device 100 via a second path P2. The computing device 210a may include a first interface IF1 for communication with the NFC 220a and a second interface IF2 for communication with the host device 100.

[0107] The computing device 210a may receive data DT or command CMD that is not stored in the NVM 250a via the second path P2. For example, the computing device 210a may receive real-time data (e.g., log data) from the host device 100 via the second path P2 and process the received data DT. In one example embodiment, the computing device 210a may also receive an application via the second path P2. In addition, the computing device 210a may directly send the data processing result to the host device 100 via the second path P2, or send the data processing result to the NFC 220a via the first path P1 and the NFC 220a may send the data processing result to the host device 100.

[0108] In addition, the communication and operation between the NFC 220a and the host device 100 and the communication and operation between the NFC 220a and the computing device 210a (e.g., an accelerator (not shown) included in the computing device 210a) may be the same as those described above with reference to FIGS. 1 to Figure 5 For example, the PM module 221a of the NFC 220a may identify at least one target command related to the power control of the computing device 210a (e.g., an accelerator (not shown) included in the computing device 210a) from among a plurality of commands received from the host device 100. The PM module 221a may independently control the power of the computing device 210a according to the at least one target command. For example, the PM module 221a may report the current power state information of the computing device 210a (e.g., an accelerator (not shown) included in the computing device 210a) to the host device 100 and may change the power state of the computing device 210a (e.g., the accelerator (not shown) of the computing device 210a) according to at least one target command received from the host device 100.

[0109] Figure 7is a block diagram showing an electronic device according to an exemplary embodiment.

[0110] Referring Figure 7 , the electronic device 2000 may include a processor 2100, a display 2200, a storage device 2300, a modem 2400, an input / output (I / O) device 2500, and a power supply 2600.

[0111] The electronic device 2000 may be a personal computer (PC), a data server, an ultra-mobile PC (UMPC), a workstation, a netbook, a network-attached storage (NAS), a smart TV, an Internet of Things (IoT) device, a portable electronic device, etc. The portable electronic device may be a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA), a digital still camera, a digital video camera, an audio device, a portable multimedia player (PMP), a personal navigation device (PND), an MP3 player, a handheld game console, an e-book, a wearable device, etc.

[0112] The storage device 2300 may include a plurality of storage devices, and each of the plurality of storage devices may be implemented in the computing storage system 200 described above with reference to FIGS. 1 to Figure 6 . In addition, the storage device 2300, the processor 2100, the display 2200, the modem 2400, the I / O device 2500, and the power supply 2600 may be connected to each other through a channel 2700.

[0113] The storage device 2300 (including the computing storage system 200 of FIGS. 1 to Figure 6 ) according to the exemplary embodiment described above may perform the power control of the computing device 210 separately from the power control of the storage device 250. In addition, the storage device 2300 (including the computing storage system 200 of FIGS. 1 to Figure 6 ) may perform the power control of the computing device 210 adaptively according to the operating state of the computing device 210. For example, the storage device 2300 (including the computing storage system 200 of FIGS. 1 to Figure 6 ) may reduce or prevent unwanted power waste by changing the power state of the computing device 210 to an idle state when the computing device 210 does not perform data calculations. In addition, the storage device 2300 (including the computing storage system 200 of FIGS. 1 to Figure 6 ) may improve the energy efficiency of the entire system by independently / adaptively performing the power control of the computing device 210.

[0114] Any functional block shown in the drawings and described above can be implemented in a processing circuit, such as hardware including logic circuits, a hardware / software combination (such as a processor executing software), or a combination thereof. For example, the processing circuit may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), etc.

[0115] Although the inventive concept has been specifically shown and described with reference to some exemplary embodiments thereof, it will be understood that various changes in form and detail may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. A computing storage system, comprising: A storage device configured to store data; And A computing device including a non-volatile memory express controller and an accelerator, the computing device being configured to perform data processing on input data provided from the storage device or a host device external to the computing storage system, the non-volatile memory express controller including a power management module, Wherein the power management module is configured to: Identify whether a target command related to the power control of the accelerator is received among a plurality of commands received from the host device, and When the target command is received, perform power control of the accelerator based on the target command.

2. The computing storage system according to claim 1, wherein, The target commands include: A first target command for requesting power state information supported by the accelerator; and A second target command for requesting the current power state information of the accelerator or changing the power state of the accelerator.

3. The computing storage system according to claim 2, wherein The power management module is further configured to, in response to receiving the first target command from the host device: Store information about the number of power states supported by the accelerator in a first field of the first target command, Store information about the characteristics of the power states supported by the accelerator in a sub-field of a second field of the first target command, and Send the first target command storing the information about the number of power states supported by the accelerator and the information about the characteristics of the power states supported by the accelerator to the host device.

4. The computational storage system according to claim 2, wherein, The power management module is further configured to: identify the request content of the host device by decoding the header of the second target command when the second target command is received.

5. The computational storage system according to claim 4, wherein, When the request content of the host device requests the current power state information of the accelerator, the power management module is further configured to: Send a signal requesting the current power state information of the accelerator to the accelerator based on the second target command, Receive the current power state information of the accelerator from the accelerator, and Store the current power state information of the accelerator in a first field of the second target command and send the stored current power state information to the host device.

6. The computing storage system according to claim 4, wherein When the request content of the host device requests a change in the power state of the accelerator, the power management module is further configured to: send a control signal for changing the power state of the accelerator to the accelerator based on the second target command, and Information about the power state of the accelerator to be changed is stored by the host device in a first field of the second target command.

7. The computational storage system according to claim 2, wherein, The power management module is further configured to: receive a second target command for changing the power state of the accelerator from the host device when the operating state of the computing device is changed.

8. The computing storage system according to any one of claims 1 to 7, wherein, The power management module is further configured to: bypass a command related to the power control of the storage device to the storage device when a command related to the power control of the storage device is received among the plurality of commands received from the host device.

9. A method of operating a computing storage system including a computing device and a storage device, the method comprising: Identify whether a target command related to the power control of the accelerator of the computing device is received among a plurality of commands received from a host device external to the computing storage system; And When a target command is received, perform power control of the accelerator based on the target command.

10. The method according to claim 9, wherein, The target command includes: A first target command for requesting power state information supported by the accelerator; and A second target command for requesting current power state information of the accelerator or changing the power state of the accelerator.

11. The method according to claim 10, further comprising, in response to receiving a first target command from a host device: Store information about the number of power states supported by the accelerator in a first field of the first target command; Store information about the characteristics of the power states supported by the accelerator in a sub-field of a second field of the first target command; And Send the first target command storing the information about the number of power states supported by the accelerator and the information about the characteristics of the power states supported by the accelerator to the host device.

12. The method according to claim 10, further comprising: When a second target command is received, identify the request content of the host device by decoding the header of the second target command.

13. The method according to claim 12, further comprising, when the request content of the host device requests current power state information of the accelerator: Based on the second target command, send a signal requesting current power state information of the accelerator to the accelerator, Receive the current power state information of the accelerator from the accelerator, Store the current power state information of the accelerator in a first field of the second target command, and Send the stored current power state information to the host device.

14. The method according to claim 12, further comprising: When the request content of the host device requests a change in the power state of the accelerator, send a control signal for changing the power state of the accelerator to the accelerator based on the second target command, Wherein, information about the power state of the accelerator to be changed is stored by the host device in a first field of the second target command.

15. The method according to claim 10, further comprising: When the operating state of the computing device is changed, send a second target command for changing the power state of the accelerator from the host device to the computing storage system.

16. The method according to any one of claims 9 to 15, further comprising: When a command related to power control of the storage device among the plurality of commands received from the host device is received, bypass the command related to power control of the storage device to the storage device.

17. An electronic device, comprising: A host device; And A computing storage system including a storage device and a computing device, the computing storage system being configured to be operatively connected to the host device, Wherein, the computing storage system is configured to: When a first target command or a second target command related to power control of the computing device is received from the host device, control a change in the power state of the computing device based on the first target command or the second target command, and When a command related to power control of the storage device is received from the host device, bypass the command related to power control of the storage device to the storage device.

18. The electronic device according to claim 17, wherein, The compute storage system is further configured to: in response to receiving a first target command from a host device, send information about the interfaces supported by the compute storage system and power state information supported by the storage device and the compute device to the host device.

19. The electronic device according to claim 17 or 18, wherein, The compute storage system is further configured to: in response to receiving a second target command from a host device, send the current power state information of the compute device to the host device.

20. The electronic device according to claim 17 or 18, wherein The compute storage system is further configured to: in response to receiving a second target command from a host device, change the power state of the compute device based on the second target command.

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