Data reading method, device, system and equipment of FIFO (First In First Out) and medium

Abstract

The invention provides an FIFO (First In First Out) data reading method, device, system, equipment and medium, the method comprises the following steps: when a data reading request is triggered, calculating a read address according to a data reading address carried in the data reading request; the read address is used for representing a value when the read address register is about to be updated in the previous clock period; selecting target data from the next beat of data of the register file or the beat-to-write data through the multiplexer according to the beat-to-read address; the next beat of data of the register file refers to data stored in the register file in the next clock period; the current data are data which are currently written into a first-in first-out (FIFO) queue; and performing a beating operation on the target data through a register, and performing a reading operation through a data reading interface of the FIFO queue. According to the scheme, the overall delay of data reading is reduced, the running speed and performance of the whole system are improved, and then the running speed of a chip is increased.

Description

Technical Field

[0001] This application relates to the field of processor technologies, and in particular, to a method, apparatus, system, device, and medium for reading data of a FIFO. Background Art

[0002] With the continuous development of computer technologies, the First-In First-Out (FIFO) queue, as a core component for coordinating data transmission between a sending end and a receiving end, has been increasingly applied in numerous digital systems, such as communications, computer architectures, signal processing, etc. Its main function is to store and output data in the order of entry, ensuring the orderliness and integrity of the data. In a FIFO queue, the data element that was added to the queue earliest will be the first to leave the queue, that is, it follows the principle of "first in, first out".

[0003] Currently, in related technologies, a classical FIFO circuit structure is adopted. However, when a complex combinational logic is connected downstream of the FIFO, in the process of reading data from the classical FIFO design circuit structure, because a large MUX selector is passed when reading data from the register bank, the process of outputting data by the read operation will form a timing bottleneck, which means a time delay in data transmission, thereby affecting the operating speed and performance of the entire system, and further resulting in a reduction in the chip operating rate. Summary of the Invention

[0004] Embodiments of this application provide a method, apparatus, system, device, and medium for reading data of a FIFO.

[0005] In a first aspect of embodiments of this application, a method for reading data of a FIFO is provided. The method includes: When a data reading request is triggered, calculate the current beat read address according to the data reading address carried in the data reading request; the current beat read address is used to represent the value when the read address register is about to be updated in the previous clock cycle; Through the current beat read address, select target data from the next beat data of the register bank or the current beat write data through a multiplexer; the next beat data of the register bank refers to the data stored in the register bank in the next clock cycle; the current beat write data refers to the data currently being written into the first-in-first-out FIFO queue; Perform a beat operation on the target data through a register and perform a reading operation through the data reading interface of the FIFO queue.

[0006] In an optional embodiment of this application, calculating the current beat read address according to the data reading address includes: Obtain the value of the read address register just before it is updated in the previous clock cycle of the current clock cycle according to the data read address; Use the value of the read address register just before it is updated in the previous clock cycle as the read address of the current beat.

[0007] In an optional embodiment of the present application, the method further includes: When the data read request and the data write request occur simultaneously, determine the state of whether the FIFO is empty; When the FIFO is in an empty state, select the write data of the current beat as the target data through the multiplexer based on the read address of the current beat.

[0008] In the second aspect of the embodiments of the present application, a data reading device for a FIFO is provided, including: A calculation module, configured to calculate the read address of the current beat according to the data read address carried in the data read request when a data read request is triggered; the read address of the current beat is used to represent the value of the read address register just before it is updated in the previous clock cycle; A determination module, configured to select target data from the data of the next beat of the register bank or from the write data of the current beat through the multiplexer by means of the read address of the current beat; the data of the next beat of the register bank refers to the data stored in the register bank in the next clock cycle; the write data of the current beat refers to the data currently being written into the first-in-first-out FIFO queue; A reading module, configured to perform a pipelining operation on the target data through a register and perform a reading operation through the data reading interface of the FIFO queue.

[0009] In the third aspect of the embodiments of the present application, a data reading system for a FIFO is provided, including: A register bank, a multiplexer, a register, a read pointer, and a data reading interface. The multiplexer is communicatively connected to the register, and the data reading interface is communicatively connected to the register and the read pointer respectively; The read pointer is configured to: when a data read request is triggered, calculate the read address of the current beat according to the data read address carried in the data read request and send it to the multiplexer; the read address of the current beat is used to represent the value of the read address register just before it is updated in the previous clock cycle; The multiplexer is configured to: select target data from the data of the next beat of the register bank or from the write data of the current beat based on the read address of the current beat and send it to the register; the data of the next beat of the register bank refers to the data stored in the register bank in the next clock cycle; the write data of the current beat refers to the data currently being written into the first-in-first-out FIFO queue; The register is used to: perform a pipelining operation on the target data and transfer the target data to the data reading interface; The data reading interface is used to: perform a reading operation on the target data.

[0010] In a fourth aspect of the embodiments of the present application, a computer device is provided, including: a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, the steps of any one of the above methods are implemented.

[0011] In a fifth aspect of the embodiments of the present application, a computer-readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the steps of any one of the above methods are implemented.

[0012] In the embodiments of the present application, a data reading method, device, system, device and medium for a FIFO are provided. The method includes: when a data reading request is triggered, calculate the current beat read address according to the data reading address carried in the data reading request; the current beat read address is used to represent the value when the read address register is about to be updated in the previous clock cycle; through the current beat read address, select the target data from the next beat data of the register file or from the current beat write data through a multiplexer; the next beat data of the register file refers to the data stored in the register file in the next clock cycle; the current beat write data refers to the data currently being written into the first-in-first-out FIFO queue; perform a pipelining operation on the target data through the register and perform a reading operation through the data reading interface of the FIFO queue. In the technical solution of the present application, the current beat read address is calculated according to the data reading address carried in the data reading request, so that according to the current beat read address, the target data is directly selected from the next beat data (Read Data Next) or the current beat write data (Write Data) of the register file, skipping the waiting time for selecting data after the traditional calculation of the read address, and performing pipelining synchronization according to the target data through the register to read through the data reading interface, thereby effectively reducing the overall delay of data reading, solving the problem of output data timing delay brought by the above-mentioned classic FIFO, avoiding becoming the timing bottleneck of the downstream complex combinational logic, improving the running speed and performance of the entire system, and further improving the chip running rate. Description of the Drawings

[0013] The drawings described herein are used to provide a further understanding of the present application, and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application, and do not constitute an improper limitation of the present application. In the drawings: Figure 1 It is a schematic diagram of the existing classic FIFO cache circuit structure provided by an embodiment of the present application; Figure 2Schematic diagram of the timing delay caused by read data in the FIFO cache circuit provided by an embodiment of the present application; Figure 3 Schematic structural diagram of a computer device provided by an embodiment of the present application; Figure 4 Schematic flow diagram of the data reading method of the FIFO provided by an embodiment of the present application; Figure 5 Schematic flow diagram of the data reading method of the FIFO provided by another embodiment of the present application; Figure 6 Schematic structural diagram of the data reading device of the FIFO provided by an embodiment of the present application; Figure 7 Schematic structural diagram of the data reading system of the FIFO provided by an embodiment of the present application. Detailed implementation manners

[0014] In the process of implementing the present application, the inventor found that in the traditional multi-stage pipelined configurable issue CPU pipeline structure, simultaneous update of the BHT by multiple branch jump instructions would cause BHT address conflict problems, thus affecting the performance of the processor.

[0015] In order to make the technical solutions and advantages in the embodiments of the present application clearer and more understandable, the following further describes the exemplary embodiments of the present application in detail with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than an exhaustive list of all embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0016] As mentioned in the background art, the combinational logic in the traditional classical synchronous FIFO circuit includes: write enable (WE) logic, read enable (RE) logic, status detection logic, and address update logic. Among them, for the write enable logic, in the synchronous FIFO circuit, the write enable signal is usually calculated by combinational logic from the externally input write request signal and other control signals (such as the not-full flag); when the FIFO is not full and a valid write request is received, the write enable signal is activated, allowing data to be written into the FIFO. For the read enable logic, similar to the write enable logic, the read enable signal is also generated by combinational logic, calculated from the externally input read request signal and other control signals (such as the not-empty flag) through combinational logic; when the FIFO is not empty and a valid read request is received, the read enable signal will be activated, allowing data to be read from the FIFO.

[0017] The status detection logic includes the logic for detecting the empty and full states. The empty state detection determines whether the FIFO is empty by checking if the read and write pointers are equal, which is the result of combinational logic operations. The full state detection is to judge whether the write pointer is about to catch up with the read pointer. For example, it checks if the write pointer is 1 different from the read pointer or a threshold preset according to a specific depth to determine whether the FIFO is full, which is also the function of combinational logic. For the address update logic, in the FIFO system, the actual update actions of the write address and read address are triggered at the clock edge, which belongs to sequential logic to ensure the synchronization of operations. And the judgment of whether the address needs to be incremented uses combinational logic, which immediately obtains the result based on the current conditions and does not rely on the clock signal. When a write operation occurs (i.e., there is external data to be written into the FIFO) and the FIFO is not full (there is space to accommodate new data), the combinational logic will judge that the increment condition is met, and then the write pointer will be incremented in the next clock cycle to point to the next writable position. When a read operation occurs (i.e., external data needs to be read from the FIFO) and the FIFO is not empty (there is data to be read), the combinational logic judges that it meets the requirements, and the read pointer will be incremented in the next clock cycle to point to the next readable position.

[0018] Please refer to Figure 1 as shown Figure 1 is a schematic diagram of an existing classic FIFO cache circuit structure, including core components and interface signals. The core components include: a register file, a multiplexer (MUX), a write pointer, a read pointer, and a compare logic module. The register file is used to store data and is the main storage body of the FIFO. The multiplexer selects one path of data from different data input sources as the write data to be written into the register file according to the control signal. The write pointer is used to indicate the position where data is written into the register file and is updated by the write enable signal (WE). The read pointer is used to indicate the position where data is read from the register file and is updated by the read enable signal (RE). The compare logic module outputs the status signals of the FIFO, namely "full" and "empty", by comparing the states of the read and write pointers.

[0019] The above interface signals include write interface signals and read interface signals. The write interface signals include i_wdata, i_valid, i_ready, and full. The read interface signals include: o_rdata, o_valid, o_ready, and empty. Among them, the i_wdata signal represents the input data to be written, i_valid represents whether the input data is valid, i_ready represents whether the FIFO is ready to receive new data, and full feedbacks the state that the FIFO is full, preventing new data from being written. o_rdata represents the data read from the FIFO for output, o_valid represents whether the output data is valid, o_ready represents whether the receiving end is ready to receive data, and empty is used to feedback the state that the FIFO is empty, preventing data from being read. The above circuit works together through these components and signals to achieve the orderly writing and reading of data, ensuring the correct operation of the FIFO in different states.

[0020] In the read operation of the classic FIFO design, there is a problem related to the FIFO depth. When the FIFO is connected to complex combinational logic downstream, the process of outputting data during the read operation will form a timing bottleneck. This means that the time delay of data transmission may affect the operating speed and performance of the entire system. Specifically, when reading data from the FIFO, it is necessary to select the corresponding correct read data (ReadData) from the register file according to the generated read address (Read Pointer). And this selection process goes through a large MUX (multiplexer) selector. Since the large MUX needs to select from multiple data paths, its internal logic will generate a delay, which is the first combinational logic delay (Delay1) mentioned in the text. When the FIFO depth increases, the number of selection paths that the MUX needs to process increases, and this delay may further increase, thus having a more serious impact on the timing of the entire system. Especially when the downstream combinational logic is also complex, the accumulated delay may cause the data to not be correctly transmitted within the expected time.

[0021] Please refer to Figure 2 As shown, the existing classic FIFO design will generate a logical timing delay between the read request and the read data. And the FIFO component is crucial in chip design, undertaking the functions of data caching and orderly transmission. However, the timing delay generated by the above classic FIFO design will cause a timing bottleneck in the downstream part of the FIFO on the chip data path. That is, when the data is transmitted to the downstream module, due to the existence of the delay, it is difficult to meet the high-speed and real-time data processing requirements, which may lead to problems such as a decrease in the operating efficiency of the entire chip or even data transmission errors.

[0022] Based on the above defects, the present application provides a method for reading data from a FIFO. Compared with the related art, in the technical solution of the present application, the read address of the current cycle is calculated based on the data read address carried in the data read request, and then the target data is directly selected from the next-cycle read data (Read Data Next) or the current-cycle write data (Write Data) of the register file according to the read address of the current cycle, skipping the waiting time for selecting data after calculating the traditional read address. Then, the register performs pipelining synchronization according to the target data and reads it through the data read interface, thus effectively reducing the overall latency of data reading, solving the problem of output data timing delay caused by the above-mentioned classic FIFO, avoiding becoming the timing bottleneck of the downstream complex combinational logic, improving the running speed and performance of the entire system, and further enhancing the chip running rate.

[0023] Please refer to Figure 3 , a schematic structural diagram of a computer device provided in an embodiment of the present application. As Figure 3 shown, the computer device includes a processor, a memory, a network interface, a display screen, and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium can be, for example, a disk. Files (which can be files to be processed or processed files), an operating system, and computer programs are stored in the non-volatile storage medium. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it implements a method for reading data from a FIFO. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer covered on the display screen, or a button, a trackball, or a touchpad provided on the housing of the computer device, or an external keyboard, touchpad, or mouse, etc.

[0024] Please refer to Figure 4 , in the following embodiments, taking the above computer device as the execution subject and applying the method for reading data from a FIFO provided in the embodiments of the present application to the above computer device for data reading as an example for specific description. The method for reading data from a FIFO provided in the embodiments of the present application includes the following steps 201-203: Step 201, when a data read request is triggered, calculate the read address of the current cycle according to the data read address carried in the data read request; the read address of the current cycle is used to represent the value when the read address register is about to be updated in the previous clock cycle.

[0025] It should be noted that the above-mentioned current read address generally refers to the value when the read address register is about to be updated in the previous clock cycle. It represents the read address to be used in the read operation in the next clock cycle. The current read address is the read address value at a special time point between the current clock cycle and the next clock cycle. When the current clock cycle is about to end, the read address register is ready to be updated, and the value about to be updated into the register at this time is the current read address. It is not the read address currently in use, but the read address to be adopted in the next read operation. Its function is to determine the address of the next read operation in advance, so as to read data more efficiently. Through the above-mentioned current read address, the final data to be read can be directly selected from the data in the next cycle of the register file or the current write data, thus avoiding the delay caused by first calculating the read address and then selecting data according to the read address in the traditional method, and greatly improving the efficiency and speed of data reading.

[0026] In this embodiment, from the perspective of circuit implementation, the current read address depends on the control logic of the read pointer and the state changes of related registers. Through a specific circuit structure and signal control, the specific current read address value can be obtained at the appropriate time point and used for subsequent data selection and read operations.

[0027] Specifically, when a data read request is triggered in the FIFO, the data read request carries a data read address. According to the data read address, calculate the value when the read address register is about to be updated in the previous clock cycle of the current clock cycle, and use this value as the current read address.

[0028] Step 202: Select the target data from the data in the next cycle of the register file or the current write data through the current read address by means of a multiplexer; the data in the next cycle of the register file refers to the data stored in the register file in the next clock cycle; the current write data refers to the data currently being written into the first-in-first-out (FIFO) queue.

[0029] It should be noted that the above-mentioned target data refers to the data to be read. The target data can be represented in different data forms. For example, it can be represented in the form of a table, a picture, text, audio / video, or other forms. The target data can be one, two, or more.

[0030] Specifically, after obtaining the current read address, according to the current read address, select the target data from the data in the next cycle of the register file or the current write data through a multiplexer. The multiplexer has a selection function and can select the target data from one of the two situations. For example, it can select the target data from the data in the next cycle of the register file, or it can select the target data from the current write data. The target data is the data corresponding to the current read address.

[0031] Step 203: Perform a pipelining operation on the target data through a register and perform a read operation through the data read interface of the FIFO queue.

[0032] It can be understood that the above register can be a D-type flip-flop (DFF). Due to the differences in signal transmission delays on different paths in the circuit, the arrival times of data may be inconsistent, resulting in data instability. Triggered by the clock signal, the DFF temporarily stores the input data for one clock cycle, synchronizes the data with the system clock, ensures that all relevant components process the data under the same time reference, and avoids errors caused by data asynchronization. Moreover, it can temporarily store the data selected by the multiplexer (MUX) from the register file or other data sources, making the data stable in the register. In this way, the data finally delivered to the FIFO data read interface is more reliable, ensuring the correctness of data output and preventing the subsequent circuit modules from being affected by unstable factors such as data jitter during data processing.

[0033] Specifically, after selecting the target data through the multiplexer, the target data is delivered into the register (DFF, D-type flip-flop) for pipelining operation. The main purpose of the pipelining operation is to synchronize the data. In digital circuits, due to the possible differences in signal transmission delays on different paths, the arrival times of data may be inconsistent, which may lead to data instability or errors. By temporarily storing the data for one clock cycle (i.e., one pipelining stage), the data is stabilized in the register, ensuring that the data can be correctly processed and transmitted in the next clock cycle.

[0034] In this embodiment, it helps to eliminate the delay impact caused by combinational logic such as multiplexing. Through the pipelining operation (temporarily storing for one stage), the timing of the data is readjusted, enabling the data to be transmitted to the downstream module at a more appropriate rhythm, which contributes to the efficient and stable operation of the entire FIFO system.

[0035] An FIFO data reading method is provided in an embodiment of the present application. The method includes: when a data reading request is triggered, calculate the current beat read address according to the data reading address carried in the data reading request; the current beat read address represents the value when the read address register is about to be updated in the previous clock cycle; select target data from the next beat data of the register file or the current beat write data through the current beat read address by means of a multiplexer; the next beat data of the register file refers to the data stored in the register file in the next clock cycle; the current beat write data refers to the data currently being written into the first-in-first-out (FIFO) queue; perform a beat operation on the target data through a register and perform a reading operation through the data reading interface of the FIFO queue. In the technical solution of the present application, the current beat read address is calculated according to the data reading address carried in the data reading request, and thus, according to the current beat read address, the target data is directly selected from the next beat data (Read Data Next) of the register file or the current beat write data (Write Data), skipping the waiting time for selecting data after the traditional calculation of the read address, and performing beat synchronization on the target data through the register to read through the data reading interface, thereby effectively reducing the overall delay of data reading, solving the problem of output data timing delay caused by the above-mentioned classical FIFO, avoiding becoming a timing bottleneck of the downstream complex combinational logic, improving the operation speed and performance of the entire system, and further enhancing the chip operation rate.

[0036] In an optional embodiment of the present application, a specific implementation manner for calculating the current beat read address according to the data reading address is provided in the embodiment of the present application. The method includes: Obtain the value when the read address register is about to be updated in the previous clock cycle before the current clock cycle according to the data reading address; use the value when the read address register is about to be updated in the previous clock cycle as the current beat read address.

[0037] Specifically, the above-mentioned current beat read address is essentially a read address to be used in one clock cycle, generally obtained by incrementing the current data reading address. The current beat read address is the next beat address calculated in the current clock cycle and takes effect in the next clock cycle after being synchronized by the register. According to the data reading address, use the value when the read address register is about to be updated in the previous clock cycle as the current beat read address.

[0038] In this embodiment, by obtaining the value of the read address register just before it was about to be updated in the previous clock cycle based on the data read address, and using the value of the read address register just before it was about to be updated in the previous clock cycle as the read address for the current cycle, it is possible to provide data guidance information for subsequent data reading, enabling the direct selection of data from the next-cycle data or the current-cycle write data in the register file when reading data, skipping the waiting time for address calculation, reducing the delay of the critical path, and shortening the data preparation time, thereby avoiding the combinational logic delay in the traditional design and further improving the data reading efficiency.

[0039] In an alternative embodiment of the present application, the present application also provides a specific implementation of another FIFO data reading method. Please refer to Figure 5 as shown, the method includes: Step 301, when a data read request and a data write request occur simultaneously, determine the state of whether the FIFO is empty.

[0040] Step 302, when the FIFO is in an empty state, select the current-cycle write data as the target data through a multiplexer based on the current-cycle read address.

[0041] Exemplarily, in the present application embodiment, there is a special scenario where read and write requests occur simultaneously, which means that at the same moment, a data read request and a data write request are triggered, that is, a request to both write data into the FIFO and read data from the FIFO is triggered. Then it is necessary to determine whether the FIFO is in an empty state. It can be to send a status acquisition request to the comparison logic module, so that the comparison logic module receives and responds to the status acquisition request and feedbacks the status information of the FIFO. When the status information of the FIFO is empty (empty = 1), it means that there is no stored data in the FIFO available for reading.

[0042] It can be understood that in the above special scenario where data read and write requests are triggered simultaneously, since the FIFO is empty and new write data has just arrived, the register file has not had time to update and store the next-cycle data (Read DataNext), so the desired read data cannot be directly obtained from the register file.

[0043] To address the above situation, when encountering the above special scenario, the target data is directly obtained from the current-cycle write data (Write Data) through a multiplexer (MUX) according to the current-cycle write address. Then the target data is subjected to a pipelining operation through a register (DFF) and a read operation is performed through the data reading interface of the FIFO queue, thus realizing the data reading process.

[0044] In the embodiment of the present application, compared with the classic FIFO, when reading data, a large MUX is passed because data is selected from the register file according to the read address, resulting in a combinational logic delay (Delay1) in the design. However, through the processing and overall design of the special scenario where read and write requests occur simultaneously in the present application solution, the overall delay of data reading is effectively reduced, this combinational logic delay can be eliminated, the speed and efficiency of data reading are improved, and the timing bottleneck problem existing in the classic FIFO design is solved.

[0045] On the other hand, the embodiment of the present application provides a data reading device for the FIFO. Please refer to Figure 6 As shown, the data reading device for the FIFO includes: A calculation module 410, configured to calculate the current beat read address according to the data read address carried in the data read request when a data read request is triggered; the current beat read address is used to represent the value when the read address register is about to be updated in the previous clock cycle; A determination module 420, configured to select target data from the next beat data of the register file or the current beat write data through a multiplexer by means of the current beat read address; the next beat data of the register file refers to the data stored in the register file in the next clock cycle; the current beat write data refers to the data currently being written into the first-in-first-out FIFO queue; A reading module 430, configured to perform a beat operation on the target data through a register and perform a reading operation through the data reading interface of the FIFO queue.

[0046] Optionally, the above calculation module 410 is specifically configured to: Obtain the value when the read address register is about to be updated in the previous clock cycle before the current clock cycle according to the data read address; Use the value when the read address register is about to be updated in the previous clock cycle as the current beat read address.

[0047] Optionally, the above device is further configured to: When a data read request and a data write request occur simultaneously, determine the state of whether the FIFO is empty; When the FIFO is in an empty state, select the current beat write data as the target data through a multiplexer based on the current beat read address.

[0048] The data reading device of the FIFO provided by the embodiment of the present application calculates the current beat reading address through the data reading address carried in the data reading request, and thus directly selects the target data from the next beat data (Read DataNext) or the current beat write data (Write Data) of the register file according to the current beat reading address, skipping the waiting time for selecting data after calculating the traditional reading address, and performing pipelining synchronization on the target data through the register to read through the data reading interface, thereby effectively reducing the overall latency of data reading, solving the problem of output data timing latency caused by the above classical FIFO, avoiding becoming the timing bottleneck of the downstream complex combinational logic, improving the operation speed and performance of the entire system, and further enhancing the chip operation rate. Each module in the above data reading device of the FIFO can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or be independent of it, or be stored in the memory in the computer device in software form, so as to facilitate the processor to call and execute the operations corresponding to the above respective modules.

[0049] On the other hand, the embodiment of the present application provides a data reading system of the FIFO. The data reading system of the FIFO includes: a register file, a multiplexer, a register, a read pointer, and a data reading interface. The multiplexer establishes a communication connection with the register, and the data reading interface respectively establishes communication connections with the register and the read pointer.

[0050] The read pointer is used for: when triggering a data reading request, calculating the current beat reading address according to the data reading address carried in the data reading request and sending it to the multiplexer; the current beat reading address is used to represent the value when the read address register is about to be updated in the previous clock cycle; the multiplexer is used for: selecting the target data from the next beat data of the register file or from the current beat write data based on the current beat reading address and sending it to the register; the next beat data of the register file refers to the data stored in the register file in the next clock cycle; the current beat write data refers to the data currently being written into the first-in-first-out FIFO queue; the register is used for: performing a pipelining operation on the target data and transmitting the target data to the data reading interface; the data reading interface is used for: performing a reading operation on the target data.

[0051] Specifically, please refer to Figure 7As shown, the above-mentioned register file is used to store data and is the core part of the FIFO for storing data. The above-mentioned read pointer is used to indicate the position of reading data from the register file, including calculating the value of the read address register that was about to be updated in the previous clock cycle as the read address for the current cycle based on the data read address carried in the data read request, and sending it to the multiplexer (MUX), so that the multiplexer (MUX) selects the target data from the data in the next cycle of the register file or the data written in the current cycle based on the read address for the current cycle and sends it to the register. This register is, for example, a DFF, and the register performs a pipelining operation on the target data and then sends it to the data read interface, so that a read operation is performed through the data read interface.

[0052] It should be noted that when a data read request is triggered, the read pointer calculates the read address for the current cycle (Read Pointer Next) according to the data read address carried in the data read request, and uses the read address for the current cycle to select the target data from the data in the next cycle of the register file (Read Data Next) or the data written in the current cycle (Write Data) and sends it to the multiplexer (MUX), so that the multiplexer (MUX) selects the target data from the data in the next cycle of the register file or the data written in the current cycle based on the read address for the current cycle and sends it to the DFF. The DFF performs a pipelining operation on the target data and then sends it to the data read interface, so that a read operation is performed through the data read interface.

[0053] It can be understood that taking the register as a D-type flip-flop DFF as an example, in the embodiment of the present application, the D-type flip-flop stores the input data under the trigger of the clock signal and outputs it after one clock cycle, so that after the pipelining operation, the timing of the data becomes more stable and controllable. Finally, the stable data is sent to the data read interface of the FIFO for use by subsequent circuit modules. This can ensure the correctness and stability of the data when it is output from the FIFO, and avoid errors or abnormal situations caused by unstable data.

[0054] In the data read system of the FIFO provided in the embodiment of the present application, the read address for the current cycle is calculated according to the data read address carried in the data read request, so that according to the read address for the current cycle, the target data is directly selected from the data in the next cycle of the register file (Read Data Next) or the data written in the current cycle (Write Data), skipping the waiting time for selecting data after the traditional calculation of the read address, and performing pipelining synchronization according to the target data through the register to read through the data read interface, thereby effectively reducing the overall delay of data reading, solving the problem of timing delay of the output data brought by the above-mentioned classic FIFO, avoiding becoming the timing bottleneck of the downstream complex combinational logic, improving the running speed and performance of the entire system, and further improving the chip running rate.

[0055] In an optional embodiment of the present application, the above-mentioned FIFO data reading system further includes: a write pointer and a comparison logic module, and the comparison logic module establishes a communication connection with the write pointer and the data reading interface.

[0056] The write pointer is used to: indicate the position where data is written into the register file; the comparison logic module is used to: compare the states of the read pointer and the write pointer, generate the status signal of the FIFO, and the status signal includes an empty state or a full state; the multiplexer is further used to: when a data reading request and a data writing request occur simultaneously and the FIFO is in an empty state, select the write data of the current cycle as the target data.

[0057] It can be understood that the above-mentioned write pointer (Write Pointer) indicates the position where data is written into the register file. The comparison logic module is used to: compare the states of the read pointer and the write pointer, generate the status signal of the FIFO, and the status signal includes an empty state or a full state. The empty state means, for example, empty = 1, and the full state means, for example, empty = 0.

[0058] When empty = 1, it indicates that the register file is in an empty state, that is, there is no valid data available for reading. At this time, if there is a data reading request, the FIFO cannot provide valid data, usually blocking the continuation of the read operation to avoid reading incorrect data. At the same time, it will also feedback the "empty" status signal to the read interface (Read Interface) to let the external module know that there is no data to read in the current FIFO.

[0059] When empty = 0, it means that there is valid data in the register file, that is, there is data available for the read operation. In this state, if the read enable signal (RE) is valid, the read pointer (Read Pointer) can select data from the register file according to the set logic and output the data to the external module through the subsequent data selection and processing process.

[0060] As an implementable manner, during the data writing process, the external data (i_wdata) is input to the data writing interface (Write Interface). When the i_valid signal is valid and triggered by the write enable signal (WE), it is written into the register file (Register File) through the multiplexer controller, and the write pointer is also updated accordingly. At the same time, the comparison logic module monitors the status of the write pointer in real time. If the FIFO is in a full state, it outputs a "full" signal to block the writing.

[0061] As another implementable manner, during the data reading process, when a data reading request is triggered, according to the calculated read address of the current cycle (Read Pointer Next), the target data to be finally read can be directly selected from the data of the next cycle (Read Data Next) or the write data of the current cycle (Write Data) in the register file through a multiplexer MUX, and then after performing a pipelining operation through a register DFF, the read data (o_rdata) is output through a data reading interface (Read Interface).

[0062] Among them, when both a data reading request and a data writing request are triggered simultaneously, in the special scenario where the FIFO is in an empty state (empty = 1) received by the comparison logic module, the target data is directly selected from the write data of the current cycle (Write Data) through the multiplexer MUX. After the selected target data performs a pipelining operation through the register DFF, the read data (o_rdata) is output through the data reading interface (Read Interface).

[0063] In the embodiment of the present application, the comparison logic module compares the states of the read pointer and the write pointer to generate the status signal of the FIFO, and when the data reading and writing requests occur simultaneously and the FIFO is empty, the write data of the current cycle is selected as the target data, avoiding the combinational logic delay caused by the large MUX when the read operation outputs data in the classic FIFO design and eliminating the timing bottleneck.

[0064] In an optional embodiment of the present application, the FIFO data reading system further includes: at least one multiplex controller, and the multiplex controller establishes a communication connection with the register file; Each multiplex controller is used to: receive a control signal, and according to the control signal, select one path of input data from multiple input data and output it to the next component; the next component includes at least one of the following: the next multiplex controller, the register file.

[0065] In this embodiment, please continue to refer to Figure 7 As shown, there can be multiple multiplex controllers. For example, taking the multiplex controller including two as an example, they are the first multiplex controller and the second multiplex controller respectively. The first multiplex controller establishes a communication connection with the register file (Register File), and the register file also establishes a communication connection with the second multiplex controller.

[0066] Among them, the write data output by the data write interface (Write Interface) and the data output by the write pointer (Write Pointer) are both output to the first multiplexer controller. Then, the first multiplexer controller receives a control signal and can select one of the two paths of data for output. Similarly, the second multiplexer controller can also select one of the two paths of data for output to the multiplexer according to the corresponding control signal.

[0067] In this embodiment, by setting at least one multiplexer controller, it is possible to select one of the multiple input data for output to the next multiplexer controller or register file according to the control signal, realizing the orderly flow of data and improving the data reading or writing efficiency.

[0068] In an alternative embodiment of the present application, the data reading system of the FIFO further includes: a data write interface, and the data write interface establishes a communication connection with the write pointer. The data write interface is used to output a write enable signal to control the update of the write pointer through the write enable signal; the data read interface is used to output a read enable signal to control the update of the read pointer through the read enable signal.

[0069] It should be noted that the above data write interface is the channel for external data to enter the FIFO register file, and the write enable signal is the switch that controls whether data can be written through this interface. Only when the write enable signal is valid (usually high level) and the data valid signal (i_valid) also meets the requirements, the external data (i_wdata) can pass through the data write interface, be stored in the register file through the multiplexer controller, and at the same time the write pointer is updated accordingly. If the write enable signal is invalid, even if there is external data input, it cannot be written into the FIFO register file.

[0070] The above data read interface is the channel for the FIFO to output data to the outside, and the read enable signal determines whether the read operation can be performed. When the read enable signal is valid, the FIFO selects the target data from the register file according to the read pointer or the current read address, and after latching through a register (such as through a D flip-flop), outputs it to the external module through the data read interface. If the read enable signal is invalid, even if there is data in the register file, the read and output operations will not be executed.

[0071] In this embodiment, by setting a data writing interface, the data can be written in an orderly manner, improving the data writing speed. And when the snapshot read address pre-selects the target data, skipping the waiting time for selecting data after the traditional read address calculation, combined with the D-type flip-flop for clocking synchronization, it effectively eliminates the combinational logic delay caused by the large MUX in the classic FIFO, improves the data reading speed, reduces the overall system latency, and in the special scenario where read and write requests occur simultaneously and the FIFO is empty, it can select and output data from the snapshot write data through a multiplexer, ensuring that the system can still work properly in extreme cases, avoiding errors, and improving the working stability.

[0072] It should be understood that although the steps in the flowchart are shown sequentially in the direction of the arrows, these steps do not necessarily have to be executed in the order indicated by the arrows. Unless otherwise clearly stated in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least some of the steps in the figure may include multiple sub-steps or multiple stages. These sub-steps or stages do not necessarily have to be executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages does not necessarily have to be sequential, but can be executed alternately or alternately with at least a part of other steps or sub-steps or stages of other steps.

[0073] In one embodiment, a computer device is provided. The internal structure diagram of the computer device can be as Figure 3 shown. The computer device includes a processor, a memory, a network interface, and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, it realizes a data reading method of a FIFO as described above. It includes: including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, it realizes any step in the data reading method of the FIFO as described above.

[0074] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by the processor, it can realize any step in the data reading method of the FIFO as described above.

[0075] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0076] The present application is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to the embodiments of the present application. It should be understood that each flow and / or block in the flowchart and / or block diagram, as well as the combination of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, such that the instructions executed by the processor of the computer or other programmable data processing devices generate means for implementing the functions specified in Figure 1 one or more of the processes or Figure 1 blocks.

[0077] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory generate a manufactured article including instruction means that implement the functions specified in Figure 1 one or more of the processes or Figure 1 blocks.

[0078] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operation steps are executed on the computer or other programmable device to generate a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in Figure 1 one or more of the processes or Figure 1 blocks.

[0079] Although the preferred embodiments of the present application have been described, those skilled in the art can make additional changes and modifications to these embodiments once they learn the basic creative concepts. Therefore, the appended claims are intended to be construed to include the preferred embodiments as well as all changes and modifications falling within the scope of the present application.

[0080] Obviously, those skilled in the art can make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalent technologies, this application is also intended to include these modifications and variations.

Claims

1. A data reading method for FIFO, characterized in that The data reading method of the FIFO includes: When a data reading request is triggered, calculate the current beat read address according to the data reading address carried in the data reading request; the current beat read address is used to represent the value when the read address register is about to be updated in the previous clock cycle; Select the target data from the next beat data of the register file or the current beat write data through the multiplexer by means of the current beat read address; the next beat data of the register file refers to the data stored in the register file in the next clock cycle; the current beat write data refers to the data currently being written into the first-in first-out FIFO queue; Perform a beat operation on the target data through the register and perform a reading operation through the data reading interface of the FIFO queue.

2. The method according to claim 1, characterized in that, Calculating the current beat read address according to the data reading address includes: According to the data reading address, obtain the value when the read address register is about to be updated in the previous clock cycle of the current clock cycle; Use the value when the read address register is about to be updated in the previous clock cycle as the current beat read address.

3. The method according to claim 1, wherein The method further includes: When the data reading request and the data writing request occur simultaneously, judge the state of whether the FIFO is empty; When the FIFO is in an empty state, select the current beat write data as the target data through the multiplexer based on the current beat read address.

4. A data reading device for FIFO, characterized in that, The data reading device of the FIFO includes: A calculation module, configured to calculate a current beat read address according to the data reading address carried in the data reading request when a data reading request is triggered; the current beat read address is used to represent the value when the read address register is about to be updated in the previous clock cycle; A determination module, configured to select the target data from the next beat data of the register file or the current beat write data through the multiplexer by means of the current beat read address; the next beat data of the register file refers to the data stored in the register file in the next clock cycle; the current beat write data refers to the data currently being written into the first-in first-out FIFO queue; A reading module, configured to perform a beat operation on the target data through the register and perform a reading operation through the data reading interface of the FIFO queue.

5. A data reading system for a FIFO, characterized in that, The data reading system of the FIFO includes: a register file, a multiplexer, a register, a read pointer, and a data reading interface. The multiplexer is communicatively connected to the register, and the data reading interface is communicatively connected to the register and the read pointer respectively; The read pointer is configured to: when a data reading request is triggered, calculate a current beat read address according to the data reading address carried in the data reading request and send it to the multiplexer; the current beat read address is used to represent the value when the read address register is about to be updated in the previous clock cycle; The multiplexer is configured to: select the target data from the next beat data of the register file or the current beat write data based on the current beat read address and send it to the register; the next beat data of the register file refers to the data stored in the register file in the next clock cycle; the current beat write data refers to the data currently being written into the first-in first-out FIFO queue; The register is configured to: perform a pipelining operation on the target data and transfer the target data to the data reading interface; The data reading interface is configured to: perform a reading operation on the target data.

6. The system according to claim 5, wherein The data reading system of the FIFO further includes: a write pointer and a comparison logic module, and the comparison logic module establishes a communication connection with the write pointer and the data reading interface; The write pointer is configured to: indicate the position where data is written into the register bank; The comparison logic module is configured to: compare the states of the read pointer and the write pointer, and generate a status signal of the FIFO, where the status signal includes an empty state or a full state; The multiplexer is further configured to: when the data reading request and the data writing request occur simultaneously and the FIFO is in the empty state, select the write data of the current cycle as the target data.

7. The system according to claim 5, characterized in that, The data reading system of the FIFO further includes: at least one multiplexing controller, and the multiplexing controller establishes a communication connection with the register bank; Each multiplexing controller is configured to: receive a control signal, and according to the control signal, select one path of input data from multiple input data and output it to the next component; the next component includes at least one of the following: the next multiplexing controller, the register bank.

8. The system according to claim 6, wherein The data reading system of the FIFO further includes: a data writing interface, and the data writing interface establishes a communication connection with the write pointer; The data writing interface is configured to output a write enable signal to control the update of the write pointer through the write enable signal; the data reading interface is configured to output a read enable signal to control the update of the read pointer through the read enable signal.

9. A computer device, comprising: A memory and a processor, where the memory stores a computer program, and is characterized in that when the processor executes the computer program, the steps of the FIFO data reading method according to any one of claims 1 to 3 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the FIFO data reading method according to any one of claims 1 to 3 are implemented.

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