Memory recovery method and device, electronic equipment and medium

Abstract

The invention relates to a memory recovery method and device, electronic equipment and a medium, and the method comprises the steps: obtaining a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent to a memory recovery device after the target processor is powered on; in the power-on recovery processing process of the target processor, determining whether a target memory needing to be controlled by the target processor is in a power-down sleep state or not; when the target memory is in the power-down sleep state, performing control register recovery processing and memory initialization processing on the target memory according to the memory wake-up signal to realize memory recovery processing; wherein in the memory recovery process, only one target processor is needed to carry out self power-on processing, and the power consumption of memory recovery is low; and the self-power-on processing and the memory recovery processing of the target processor can be performed in parallel, so that the memory recovery time is shortened, and the memory recovery efficiency is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technology, and in particular, to a memory recovery method, apparatus, electronic device, and medium. Background Art

[0002] Currently, the main memory recovery method is that, in the case where a hardware device is provided with multiple processors and a memory, when a target processor among the multiple processors is powered on, the target processor needs to perform its own power-on process, and it is necessary for the target processor to interact with the main processor among the multiple processors. The main processor performs its own power-on process and performs memory recovery processing.

[0003] In the above solution, two processors are required to perform their own power-on processes, resulting in high power consumption for memory recovery; and after the main processor completes its own power-on process, memory recovery processing can be performed, resulting in a long memory recovery time and poor memory recovery efficiency. Summary of the Invention

[0004] The present disclosure provides a memory recovery method, apparatus, electronic device, and medium.

[0005] According to a first aspect of an embodiment of the present disclosure, a memory recovery method is provided. The method includes: obtaining a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent to a memory recovery device after the target processor is powered on; during the process of the target processor performing power-on recovery processing, determining whether a target memory to be controlled by the target processor is in a power-down sleep state; in the case where the target memory is in the power-down sleep state, according to the memory wake-up signal, performing control register recovery processing and memory initialization processing on the target memory to implement memory recovery processing.

[0006] In an embodiment of the present disclosure, before performing control register recovery processing and memory initialization processing on the target memory according to the memory wake-up signal, the method further includes: determining whether a memory recovery function is in an enabled state; correspondingly, performing control register recovery processing and memory initialization processing on the target memory according to the memory wake-up signal includes: in the case where the memory recovery function is in the enabled state, performing control register recovery processing and memory initialization processing on the target memory according to the memory wake-up signal.

[0007] In one embodiment of the present disclosure, the controlling the target memory to perform control register restoration processing and memory initialization processing according to the memory wake-up signal includes: obtaining a pre-configured linked list structure and initialization logic in a non-volatile memory; at least one register address and register data storage address of the target memory are set in the linked list structure; performing data restoration processing on the at least one control register according to the register address and register data storage address of the at least one control register; and performing memory initialization processing on the target memory according to the initialization logic.

[0008] In one embodiment of the present disclosure, the performing data restoration processing on the at least one control register according to the register address and register data storage address of the at least one control register includes: for each control register in the at least one control register, obtaining the register data of the control register according to the register data storage address of the control register; and writing the register data into the register address of the control register to implement data restoration processing on the control register.

[0009] In one embodiment of the present disclosure, the linked list structure includes at least one node; for each node, when the node is not a tail node, the node stores a register data storage address, a register address, a register data length of a control register, and a link address of the next node of the node; when the node is a tail node, the node stores a register data storage address, a register address, a register data length of a control register, and a linked list end flag.

[0010] In one embodiment of the present disclosure, the method further includes: releasing the memory wake-up signal when the memory restoration processing is completed, so as to instruct the target processor to perform running processing after the power-on restoration processing is completed.

[0011] In one embodiment of the present disclosure, a plurality of processors are provided in the hardware device to which the target processor belongs; the target processor is a main processor or a slave processor among the plurality of processors; and the plurality of processors share the target memory.

[0012] According to the second aspect of the embodiments of the present disclosure, there is also provided a memory recovery device, the device includes: an acquisition module, configured to acquire a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent to a memory recovery device after the target processor is powered on; a first determination module, configured to determine whether a target memory to be controlled by the target processor is in a power-down sleep state during the power-on recovery process of the target processor; a processing module, configured to perform a control register recovery process and a memory initialization process on the target memory according to the memory wake-up signal when the target memory is in a power-down sleep state, so as to implement a memory recovery process.

[0013] In an embodiment of the present disclosure, the device further includes: a second determination module, configured to determine whether a memory recovery function is in an enabled state before performing a control register recovery process and a memory initialization process on the target memory according to the memory wake-up signal; correspondingly, the processing module is specifically configured to perform a control register recovery process and a memory initialization process on the target memory according to the memory wake-up signal when the memory recovery function is in an enabled state.

[0014] In an embodiment of the present disclosure, the processing module includes: an acquisition unit, a first processing unit, and a second processing unit; the acquisition unit is configured to acquire a pre-configured linked list structure and initialization logic in a non-volatile memory; the linked list structure is provided with register addresses and register data storage addresses of at least one control register of the target memory; the first processing unit is configured to perform a data recovery process on the at least one control register according to the register addresses and register data storage addresses of the at least one control register; the second processing unit is configured to perform a memory initialization process on the target memory according to the initialization logic.

[0015] In an embodiment of the present disclosure, the first processing unit is specifically configured to, for each of the at least one control register, acquire the register data of the control register according to the register data storage address of the control register; write the register data into the register address of the control register, so as to implement the data recovery process of the control register.

[0016] In an embodiment of the present disclosure, the linked list structure includes at least one node; for each node, when the node is not a tail node, the node stores a register data storage address and a register address, a register data length, and a link address of the next node of the node of a control register; when the node is a tail node, the node stores a register data storage address and a register address, a register data length, and a linked list end flag of a control register.

[0017] In one embodiment of the present disclosure, the apparatus further includes a release module, configured to release the memory wake-up signal when the memory recovery process is completed, so as to instruct the target processor to perform an operation process after the power-on recovery process is completed.

[0018] In one embodiment of the present disclosure, a plurality of processors are provided in the hardware device to which the target processor belongs; the target processor is the main processor or the slave processor among the plurality of processors; the plurality of processors share the target memory.

[0019] According to a third aspect of the embodiments of the present disclosure, there is also provided a memory recovery system, including: at least one processor, a target memory, and a memory recovery device; the memory recovery device is communicatively connected to the at least one processor and the target memory respectively; the memory recovery device is configured to execute the memory recovery method as described above.

[0020] According to a fourth aspect of the embodiments of the present disclosure, there is also provided an electronic device, including: a processor; a memory for storing executable instructions of the processor; wherein, the processor is configured to: implement the steps of the memory recovery method as described above.

[0021] According to a fifth aspect of the embodiments of the present disclosure, there is also provided a non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor, enabling the processor to execute the memory recovery method as described above.

[0022] According to a sixth aspect of the embodiments of the present disclosure, there is also provided a chip, including one or more interface circuits and one or more processors; the interface circuit is configured to receive a signal from a memory of an electronic device and send the signal to the processor, the signal includes computer instructions stored in the memory, when the processor executes the computer instructions, enabling the electronic device to execute the memory recovery method as described above.

[0023] The technical solutions provided by the embodiments of the present disclosure at least bring the following beneficial effects:

[0024] By obtaining a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent by the target processor to a memory recovery device after power-on; during the power-on recovery process of the target processor, determining whether a target memory to be controlled by the target processor is in a power-down sleep state; in the case where the target memory is in a power-down sleep state, according to the memory wake-up signal, performing a control register recovery process and a memory initialization process on the target memory to implement a memory recovery process; wherein, during the memory recovery process, only one target processor needs to perform its own power-on process, and the power consumption of memory recovery is low; and the self-power-on process performed by the target processor and the memory recovery process can be carried out in parallel, shortening the memory recovery time and improving the memory recovery efficiency.

[0025] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure and do not constitute an improper limitation to the present disclosure.

[0027] Figure 1 It is a flowchart of a memory recovery method according to an embodiment of the present disclosure;

[0028] Figure 2 It is a flowchart of a memory recovery method according to another embodiment of the present disclosure;

[0029] Figure 3 It is a schematic diagram of a linked list structure;

[0030] Figure 4 It is a schematic flowchart of a memory recovery device performing data recovery processing on at least one control register according to the linked list structure;

[0031] Figure 5 It is a schematic structural diagram of a memory recovery device according to an embodiment of the present disclosure;

[0032] Figure 6 It is a schematic structural diagram of a memory recovery system according to an embodiment of the present disclosure;

[0033] Figure 7 It is a block diagram of a structure of an electronic device shown according to an exemplary embodiment of the present disclosure;

[0034] Figure 8 It is a schematic structural diagram of a chip according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0035] To enable those of ordinary skill in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and do not necessarily have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present disclosure. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0037] The current memory recovery method mainly is that, in the case where a hardware device is provided with multiple processors and a memory, when the target processor among the multiple processors is powered on, the target processor needs to perform its own power-on processing, and it is necessary for the target processor to interact with the main processor among the multiple processors. The main processor performs its own power-on processing and performs memory recovery processing.

[0038] In the above solution, two processors are required to perform their own power-on processing, resulting in high power consumption for memory recovery; and after the main processor completes its own power-on processing, memory recovery processing can be performed, resulting in a long memory recovery time and poor memory recovery efficiency.

[0039] Figure 1 It is a flowchart of the memory recovery method according to an embodiment of the present disclosure. It should be noted that the memory recovery method of this embodiment can be applied to a memory recovery device, and the device can be configured in an electronic device or a chip so that the electronic device or the chip can perform the memory recovery function.

[0040] Among them, the electronic device can be any device with computing capabilities, such as a personal computer (PC for short), a mobile terminal, a server, a controller in a vehicle, a memory recovery device, etc. The mobile terminal can be, for example, a vehicle-mounted device, a mobile phone, a tablet computer, a personal digital assistant, a wearable device, etc., which are hardware devices with various operating systems, touch screens, and / or display screens.

[0041] Among them, when the electronic device is a memory recovery device, the memory recovery device can be communicatively connected to at least one processor and a target memory to perform target memory recovery processing according to the memory wake-up signal of at least one processor.

[0042] In addition, the memory recovery device may also be software in an electronic device, etc. In the following embodiments, the execution entity is taken as an example of a memory recovery device for illustration.

[0043] As Figure 1 shown, the method includes the following steps:

[0044] Step 101, obtain a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent to the memory recovery device after the target processor is powered on.

[0045] In the embodiments of the present disclosure, multiple processors may be provided in the hardware device to which the target processor belongs; the target processor is the main processor or the slave processor among the multiple processors; the multiple processors share the target memory.

[0046] In the embodiments of the present disclosure, when multiple processors are provided in the hardware device to which the target processor belongs, before step 101, all of the multiple processors in the hardware device may be in a powered-off state, or some of the multiple processors may be in a powered-off state. Before step 101, the target memory in the hardware device may be in a powered-off sleep state or a powered-on state.

[0047] Among them, for the target processor in the hardware device, when the target processor switches from the powered-off state to the powered-on state, the target processor may perform its own power-on recovery process and at the same time send a memory wake-up signal to the memory recovery device, for instructing the memory recovery device to perform memory recovery processing on the target memory according to the memory wake-up signal. Among them, the memory recovery device is a device independent of the processor and the target memory.

[0048] Step 102, during the power-on recovery process of the target processor, determine whether the target memory to be controlled by the target processor is in a powered-off sleep state.

[0049] In the embodiments of the present disclosure, if the target memory to be controlled by the target processor is not in a powered-off sleep state, there is no need to perform memory recovery processing on the target memory, and the memory recovery device may directly release the memory wake-up signal to instruct the target processor to perform running processing after the power-on recovery process is completed.

[0050] Step 103, when the target memory is in a powered-off sleep state, perform control register recovery processing and memory initialization processing on the target memory according to the memory wake-up signal to implement memory recovery processing.

[0051] Among them, performing control register restoration processing on the target memory means performing data restoration processing on the control register used to control the target memory. Among them, the control registers corresponding to the target memory may include at least one of the following: memory management register, memory buffer register, address translation buffer register, page register, permission register, etc.

[0052] Among them, performing memory initialization processing on the target memory means, in a computer program, the process of setting initial values for dynamically allocated memory or memory areas that have been allocated but not initialized. The purpose of the initialization processing is to ensure that there is no undefined or garbage data in the memory, providing a basis for the correct storage and use of data in the program.

[0053] In the embodiments of the present disclosure, the memory restoration function of the memory restoration device may be in an enabled state, or not in an enabled state. Among them, when the memory restoration function of the memory restoration device is in an enabled state, the memory restoration device can perform memory restoration processing on the target memory according to the memory wake-up signal; when the memory restoration function of the memory restoration device is not in an enabled state, it is difficult for the memory restoration device to perform memory restoration processing on the target memory. Therefore, before the memory restoration device performs control register restoration processing and memory initialization processing on the target memory according to the memory wake-up signal, the following process can also be executed: determining whether the memory restoration function is in an enabled state; correspondingly, when the memory restoration function is in an enabled state, performing control register restoration processing and memory initialization processing on the target memory according to the memory wake-up signal.

[0054] In the embodiments of the present disclosure, after step 103, the memory restoration device can also execute the following process: when the memory restoration processing is completed, release the memory wake-up signal to instruct the target processor to perform running processing after the power-on restoration processing is completed.

[0055] Among them, for the target processor to perform normal running processing, two conditions need to be met. These two conditions are respectively that the target memory to be controlled has completed memory restoration processing, and the target processor has completed power-on restoration processing. Therefore, the target processor can perform running processing after the memory restoration processing is completed and the power-on restoration processing is completed, increasing the possibility of normal running processing.

[0056] In the memory recovery method according to an embodiment of the present disclosure, a memory wake-up signal of a target processor is obtained; the memory wake-up signal is a signal sent by the target processor to a memory recovery device after the target processor is powered on; during the power-on recovery process of the target processor, it is determined whether a target memory to be controlled by the target processor is in a power-down sleep state; in the case where the target memory is in the power-down sleep state, according to the memory wake-up signal, control register recovery processing and memory initialization processing are performed on the target memory to implement memory recovery processing; wherein, during the memory recovery process, only one target processor needs to perform its own power-on process, and the power consumption of memory recovery is low; and the power-on process of the target processor and the memory recovery process can be performed in parallel, shortening the memory recovery time and improving the memory recovery efficiency.

[0057] Figure 2 FIG. 4 is a flowchart of a memory recovery method according to another embodiment of the present disclosure. It should be noted that the memory recovery method of this embodiment can be applied to a memory recovery device, and the device can be configured in an electronic device or a chip so that the electronic device or the chip can perform the memory recovery function.

[0058] Among them, the electronic device can be any device with computing capabilities, such as a personal computer (PC), a mobile terminal, a server, a controller in a vehicle, a memory recovery device, etc. The mobile terminal can be a hardware device with various operating systems, touch screens and / or display screens, such as a vehicle-mounted device, a mobile phone, a tablet computer, a personal digital assistant, a wearable device, etc.

[0059] Among them, when the electronic device is a memory recovery device, the memory recovery device can communicate with at least one processor and a target memory to perform target memory recovery processing according to the memory wake-up signal of the at least one processor.

[0060] In addition, the memory recovery device can also be software in an electronic device, etc. Among the following embodiments, the memory recovery device is taken as an example of the execution subject for description.

[0061] As Figure 2 shown, the method includes the following steps:

[0062] Step 201, obtain a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent by the target processor to a memory recovery device after the target processor is powered on.

[0063] Step 202, during the power-on recovery process of the target processor, determine whether a target memory to be controlled by the target processor is in a power-down sleep state.

[0064] Step 203, when the target memory is in the power-down sleep state, obtain the pre-configured linked list structure and initialization logic in the non-volatile memory; the register addresses and register data storage addresses of at least one control register of the target memory are set in the linked list structure.

[0065] In an embodiment of the present disclosure, the linked list structure may include at least one node; for each node, when the node is not the tail node, the node stores the register data storage address, register address, register data length of a control register, and the link address of the next node of the node; when the node is the tail node, the node stores the register data storage address, register address, register data length of a control register, and the linked list end flag.

[0066] Among them, a schematic diagram of the linked list structure may be, for example, as Figure 3 shown. In Figure 3 , the first node includes the register data storage address (source address), register address (destination address), register data length (length) of a control register, and the link address (next link address) of the next node of the node. The last node includes the register data storage address (source address), register address (destination address), register data length (length) of a control register, and the linked list end flag (0xFFFFFFFF). Among them, the content included in other nodes except the first node and the last node is similar to the content included in the first node, and will not be described in detail here.

[0067] Step 204, perform data recovery processing on at least one control register according to the register addresses and register data storage addresses of the at least one control register.

[0068] In an embodiment of the present disclosure, the process of the memory recovery device executing Step 204 may be, for each control register in the at least one control register, obtain the register data of the control register according to the register data storage address of the control register; write the register data into the register address of the control register to implement data recovery processing on the control register.

[0069] Among them, a schematic diagram of the process of the memory recovery device performing data recovery processing on at least one control register according to the linked list structure may be, for example, as Figure 4 shown, in Figure 4It may include the following steps: Step 401, start. Step 402, read 4 32-bit data starting from startaddress (i.e., the content included in the first node) into the internal working register. Step 403, according to the length value in the working register, read the source address data (register data) in the working register and write it into the destination address (register address). Step 404, determine whether the next link address in the working register is 0xFFFFFFFF (linked list end flag). If so, end; if not, execute Step 405. Step 405, read 4 32-bit data starting from the next link address into the internal working register, and then execute Step 403.

[0070] Step 205, according to the initialization logic, perform memory initialization processing on the target memory to implement memory recovery processing.

[0071] In the embodiments of the present disclosure, the initialization logic can be initialization code (memory re_init). To facilitate the initialization processing of the target memory, the initialization code can be converted to obtain multiple processing instructions recognizable by the target memory, so that the target memory can implement the memory initialization processing by executing the multiple processing instructions.

[0072] Among them, the processing instructions can be, for example, Command Prompt (CMD). Among them, the instruction format of the command prompt can be as shown in Table 1 below.

[0073] Table 1

[0074]

[0075]

[0076] In Table 1, different CMD values indicate different functions. Among them, the functions indicated by the CMD values can include at least one of the following: direct assignment, indirect assignment, register rewrite (data AND), register rewrite (data OR), judgment, delay, data addition, data subtraction, end, etc.

[0077] Among them, it should be noted that for the detailed description of Steps 201 to 202, reference can be made to Figure 1 Steps 101 to 102 in the shown embodiments, and no detailed description will be given here.

[0078] In the memory recovery method according to the embodiments of the present disclosure, a memory wake-up signal of a target processor is obtained; the memory wake-up signal is a signal sent by the target processor to a memory recovery device after power-on; during the power-on recovery process of the target processor, it is determined whether a target memory to be controlled by the target processor is in a power-down sleep state; when the target memory is in the power-down sleep state, a pre-configured linked list structure and initialization logic in a non-volatile memory are obtained; at least one register address and register data storage address of at least one control register of the target memory are set in the linked list structure; data recovery processing is performed on at least one control register according to at least one register address and register data storage address of at least one control register; memory initialization processing is performed on the target memory according to the initialization logic to implement memory recovery processing; wherein, during the memory recovery process, only one target processor needs to perform its own power-on processing, and the power consumption of memory recovery is low; and the self-power-on processing performed by the target processor and the memory recovery processing process can be performed in parallel, shortening the memory recovery time and improving the memory recovery efficiency.

[0079] Figure 5 FIG. is a schematic structural diagram of a memory recovery device according to an embodiment of the present disclosure.

[0080] As Figure 5 shown, the memory recovery device may include: an acquisition module 501, a first determination module 502, and a processing module 503.

[0081] Among them, the acquisition module 501 is configured to obtain a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent by the target processor to a memory recovery device after power-on; the first determination module 502 is configured to determine whether a target memory to be controlled by the target processor is in a power-down sleep state during the power-on recovery process of the target processor; the processing module 503 is configured to perform control register recovery processing and memory initialization processing on the target memory according to the memory wake-up signal when the target memory is in the power-down sleep state to implement memory recovery processing.

[0082] In an embodiment of the present disclosure, the device further includes: a second determination module, configured to determine whether the memory recovery function is in an enabled state before performing control register recovery processing and memory initialization processing on the target memory according to the memory wake-up signal; correspondingly, the processing module 503 is specifically configured to perform control register recovery processing and memory initialization processing on the target memory according to the memory wake-up signal when the memory recovery function is in an enabled state.

[0083] In one embodiment of the present disclosure, the processing module 503 includes: an acquisition unit, a first processing unit, and a second processing unit; the acquisition unit is configured to acquire a pre-configured linked list structure and initialization logic in a retention memory; at least one register address and register data storage address of the target memory are set in the linked list structure; the first processing unit is configured to perform data recovery processing on the at least one control register according to the register address and register data storage address of the at least one control register; the second processing unit is configured to perform memory initialization processing on the target memory according to the initialization logic.

[0084] In one embodiment of the present disclosure, the first processing unit is specifically configured to, for each of the at least one control registers, acquire the register data of the control register according to the register data storage address of the control register; write the register data into the register address of the control register to implement data recovery processing on the control register.

[0085] In one embodiment of the present disclosure, the linked list structure includes at least one node; for each node, when the node is not the tail node, one register data storage address, register address, register data length of a control register, and the link address of the next node of the node are stored in the node; when the node is the tail node, one register data storage address, register address, register data length of a control register, and a linked list end flag are stored in the node.

[0086] In one embodiment of the present disclosure, the device further includes: a release module, configured to release the memory wake-up signal when the memory recovery processing is completed, so as to instruct the target processor to perform running processing after the power-on recovery processing is completed.

[0087] In one embodiment of the present disclosure, a plurality of processors are provided in the hardware device to which the target processor belongs; the target processor is the main processor or the slave processor among the plurality of processors; the plurality of processors share the target memory.

[0088] In the memory recovery device according to an embodiment of the present disclosure, a memory wake-up signal of a target processor is obtained; the memory wake-up signal is a signal sent to a memory recovery device after the target processor is powered on; during the power-on recovery process of the target processor, it is determined whether a target memory to be controlled by the target processor is in a power-down sleep state; in the case where the target memory is in the power-down sleep state, according to the memory wake-up signal, control register recovery processing and memory initialization processing are performed on the target memory to implement memory recovery processing; wherein, during the memory recovery process, only one target processor needs to perform its own power-on process, and the power consumption of memory recovery is low; and the self-power-on process performed by the target processor and the memory recovery process can be performed in parallel, shortening the memory recovery time and improving the memory recovery efficiency.

[0089] Figure 6 It is a schematic structural diagram of a memory recovery system according to an embodiment of the present disclosure.

[0090] As Figure 6 shown, the memory recovery system may include: at least one processor 601, a target memory 602, and a memory recovery device 603;

[0091] The memory recovery device 603 is respectively communicatively connected to at least one processor 601 and the target memory 602;

[0092] The memory recovery device 603 is configured to execute the memory recovery method described in any one of the embodiments as Figures 1 to 4 above.

[0093] Among them, the processor 601 may include CPU1, CPU2, and CPU3. At least one processor 601 is communicatively connected to the memory recovery device 603 through an Advanced High-performance Bus (AHB); the memory recovery device 603 is also communicatively connected to the target memory through the AHB bus. In addition, at least one processor 601 is also communicatively connected to the target memory through the AHB bus.

[0094] Among them, the target memory 602 may be provided with a corresponding control register (MEMORY_CONTROLER) for controlling the target memory.

[0095] Among them, the memory recovery device 603 may be provided with a register recovery component (Memory Protectioncontroller recover, MEMORY_PC_RECOVER) and a memory initialization component (MEMORY_REINIT_CTRL). Among them, the register recovery component is configured to perform register data recovery processing; the memory initialization component is configured to perform memory initialization processing.

[0096] In the memory recovery system according to an embodiment of the present disclosure, it includes at least one processor, a target memory, and a memory recovery device; the memory recovery device is communicatively connected to at least one processor and the target memory respectively; the memory recovery device is configured to determine whether the target memory to be controlled by the target processor is in a power-down sleep state during the power-on recovery process of the target processor; in the case where the target memory is in a power-down sleep state, according to the memory wake-up signal, perform control register recovery processing and memory initialization processing on the target memory to implement memory recovery processing; wherein, during the memory recovery process, only one target processor needs to perform its own power-on processing, and the power consumption of memory recovery is low; and the self-power-on processing performed by the target processor and the memory recovery processing process can be carried out in parallel, shortening the memory recovery time and improving the memory recovery efficiency.

[0097] According to a fourth aspect of the embodiments of the present disclosure, there is also provided an electronic device, including: a processor; a memory for storing processor-executable instructions, wherein the processor is configured to: implement the memory recovery method as described above.

[0098] To implement the above embodiments, the present disclosure also proposes a non-transitory computer-readable storage medium.

[0099] Wherein, when the instructions in the storage medium are executed by the processor, the processor is enabled to execute the memory recovery method as described above.

[0100] To implement the above embodiments, the present disclosure also provides a computer program product.

[0101] Wherein, when the computer program product is executed by the processor of the electronic device, the electronic device is enabled to execute the method as described above.

[0102] Figure 7 It is a structural block diagram of an electronic device shown according to an exemplary embodiment. Figure 7 The shown electronic device is only an example and should not bring any limitation to the functions and usage scope of the embodiments of the present disclosure.

[0103] Such as Figure 7As shown, the electronic device 1000 includes a processor 111, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 112 or a program loaded from a memory 116 into a random access memory (RAM) 113. In the RAM 113, various programs and data required for the operation of the electronic device 1000 are also stored. The processor 111, the ROM 112, and the RAM 113 are connected to each other via a bus 114. An input / output (I / O) interface 115 is also connected to the bus 114.

[0104] The following components are connected to the I / O interface 115: a memory 116 including a hard disk, etc.; and a communication section 117 including a network interface card such as a local area network (LAN) card, a modem, etc., and the communication section 117 performs communication processing via a network such as the Internet; a drive 118 is also connected to the I / O interface 115 as needed.

[0105] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program carried on a computer-readable medium, and the computer program includes program codes for performing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from a network via the communication section 117. When the computer program is executed by the processor 111, the above functions defined in the method of the present disclosure are performed.

[0106] In an exemplary embodiment, a storage medium including instructions is also provided, such as a memory including instructions, and the above instructions can be executed by the processor 111 of the electronic device 1000 to complete the above method. Optionally, the storage medium can be a non-transitory computer-readable storage medium. For example, the non-transitory computer-readable storage medium can be a ROM, a random access memory (RAM), a CD-ROM, a magnetic tape, a floppy disk, and an optical data storage device, etc.

[0107] In the present disclosure, a computer-readable storage medium may be any tangible medium that contains or stores a program, which can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the foregoing. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on a computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical fiber, RF, etc., or any suitable combination of the foregoing.

[0108] Figure 8 FIG. is a schematic structural diagram of a chip according to an embodiment of the present disclosure. As Figure 8 shown, the chip includes a processor 801 and an interface circuit 802. Among them, the number of processors 801 may be one or more, and the number of interface circuits 802 may be one or more.

[0109] Optionally, the chip further includes a memory 803 for storing necessary computer programs and data; the interface circuit 802 is configured to receive signals from the memory 803 and send signals to the processor 801. The signals include computer instructions stored in the memory 803. When the processor 801 executes the computer instructions, the electronic device is caused to execute the memory recovery method described in the foregoing embodiments of the present disclosure.

[0110] In addition, the term "exemplary" is used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as "exemplary" is not necessarily to be construed as advantageous over other aspects or designs. Instead, the use of the term exemplary is intended to present concepts in a concrete manner. As used herein, the term "or" is intended to mean an inclusive "or" rather than an exclusive "or". That is, unless otherwise specified or clear from the context, "X applies A or B" is intended to mean any arrangement in a natural inclusive arrangement. That is, if X applies A; X applies B; or X applies both A and B, then "X applies A or B" is satisfied in any of the foregoing instances. Additionally, unless otherwise specified or clear from the context referring to the singular form, the articles "a" and "an" as used in this application and the appended claims are generally understood to mean "one or more".

[0111] Similarly, although the present disclosure has been shown and described with respect to one or more implementations, equivalent variations and modifications will occur to those skilled in the art upon reading and understanding this specification and the drawings. The present disclosure includes all such modifications and variations and is limited only by the scope of the claims. Specifically with respect to the various functions performed by the components described above (e.g., elements, resources, etc.), unless otherwise indicated, the terms used to describe such components are intended to correspond to any component (functionally equivalent) that performs the specific function of the described component, even if not structurally equivalent to the disclosed structure. Additionally, although a particular feature of the present disclosure may have been disclosed with respect to only one of several implementations, such a feature may, as may be desired and advantageous for any given or particular application, be combined with one or more other features of other implementations. Further, with respect to the use of "comprising," "having," "including," "containing," or variations thereof in the detailed description or claims, such terms are intended to be inclusive in a manner similar to the term "including."

[0112] Other embodiments of the present disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include known or customary techniques in the art that are not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are pointed out by the following claims.

[0113] It should be understood that the present disclosure is not limited to the exact structures described above and shown in the drawings, and various modifications and changes may be made without departing from its scope. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A memory recovery method, characterized in that, The method includes: Obtaining a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent to a memory recovery device after the target processor is powered on; During the power-on recovery process of the target processor, determining whether a target memory to be controlled by the target processor is in a power-down sleep state; When the target memory is in a power-down sleep state, according to the memory wake-up signal, performing a control register recovery process and a memory initialization process on the target memory to implement a memory recovery process.

2. The method according to claim 1, wherein Before performing the control register recovery process and the memory initialization process on the target memory according to the memory wake-up signal, the method further includes: determining whether a memory recovery function is in an enabled state; Correspondingly, performing the control register recovery process and the memory initialization process on the target memory according to the memory wake-up signal includes: When the memory recovery function is in an enabled state, performing the control register recovery process and the memory initialization process on the target memory according to the memory wake-up signal.

3. The method according to claim 1 or 2, characterized in that, Performing the control register recovery process and the memory initialization process on the target memory according to the memory wake-up signal includes: Obtaining a pre-configured linked list structure and initialization logic in a non-volatile memory; the linked list structure is provided with register addresses and register data storage addresses of at least one control register of the target memory; According to the register addresses and register data storage addresses of the at least one control register, performing a data recovery process on the at least one control register; According to the initialization logic, performing a memory initialization process on the target memory.

4. The method according to claim 3, characterized in that, Performing the data recovery process on the at least one control register according to the register addresses and register data storage addresses of the at least one control register includes: For each control register in the at least one control register, obtaining the register data of the control register according to the register data storage address of the control register; Writing the register data into the register address of the control register to implement the data recovery process of the control register.

5. The method according to claim 3, characterized in that, The linked list structure includes at least one node; For each node, when the node is not a tail node, the node stores a register data storage address, a register address, a register data length of a control register, and a link address of the next node of the node; When the node is a tail node, the node stores a register data storage address, a register address, a register data length of a control register, and a linked list end flag.

6. The method according to claim 1, characterized in that The method further includes: When the memory recovery process is completed, releasing the memory wake-up signal to instruct the target processor to perform an operation process after the power-on recovery process is completed.

7. The method according to any one of claims 1 to 6, characterized in that, A plurality of processors are provided in a hardware device to which the target processor belongs; The target processor is a main processor or a slave processor among the plurality of processors; The plurality of processors share the target memory.

8. A memory recovery device, characterized in that, The device includes: An acquisition module, configured to acquire a memory wake-up signal of a target processor; the memory wake-up signal is a signal sent by the target processor to a memory recovery device after the target processor is powered on; A first determination module, configured to determine whether a target memory to be controlled by the target processor is in a power-down sleep state during the power-on recovery process of the target processor; A processing module, configured to, when the target memory is in a power-down sleep state, perform a control register recovery process and a memory initialization process on the target memory according to the memory wake-up signal, so as to implement a memory recovery process.

9. A memory recovery system, characterized in that, The system includes: At least one processor, a target memory, and a memory recovery device; The memory recovery device is respectively communicatively connected to at least one processor and the target memory; The memory recovery device is configured to execute the memory recovery method according to any one of claims 1 to 7.

10. An electronic device, characterized in that, Including: A processor; A memory for storing executable instructions of the processor; Wherein, the processor is configured to: Implement the steps of the memory recovery method according to any one of claims 1 to 7.

11. A non-transitory computer-readable storage medium, when the instructions in the storage medium are executed by a processor, enabling the processor to execute the memory recovery method according to any one of claims 1 to 7.

12. A chip, characterized in that, Including one or more interface circuits and one or more processors; the interface circuit is configured to receive a signal from a memory of an electronic device and send the signal to the processor, the signal includes computer instructions stored in the memory, when the processor executes the computer instructions, enabling the electronic device to execute the memory recovery method according to any one of claims 1 to 7.

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