FPGA array adaptive dynamic scheduling method and device and computer readable storage medium

Abstract

The invention provides a self-adaptive dynamic scheduling method for an FPGA (Field Programmable Gate Array) array, which comprises the following steps that: a dynamic scheduling device receives a task, allocates an FPGA board card according to initial setting, and loads a corresponding code stream file to the FPGA board card according to the initial setting; the dynamic scheduling device selects an FPGA board card of which the working state is idle in an FPGA array according to the load state of the FPGA array, and then selects an FPGA board card of which the resource occupancy rate is matched with the task requirement in the FPGA board card according to the resource occupancy rate of the selected FPGA board card; the selected FPGA board card configuration file is adjusted, and control information for controlling the selected FPGA board card is generated; and the dynamic scheduling device downloads a code stream file for realizing a specific algorithm function from the FPGA board card according to the control information and the storage position of the code stream file. The invention also provides an FPGA array adaptive dynamic scheduling device and a computer readable storage medium.

Description

Technical Field

[0001] The present invention belongs to the technical field of big data, and particularly relates to an FPGA array adaptive dynamic scheduling method, device and computer-readable storage medium. Background Art

[0002] FPGA (Field Programmable Gate Array) is a highly flexible hardware technology that can be programmed to customize its logic functions. With the rapid development of technologies such as the Internet, big data, and artificial intelligence, in data centers, the use of FPGA arrays mainly focuses on improving the computing efficiency of specific types, accelerating data processing tasks, and enhancing network functions. The types of tasks that data centers need to process are becoming increasingly diverse, including machine learning, deep learning, video processing, encryption and decryption, database queries, etc. These tasks have different requirements for computing resources, and traditional CPUs may not be able to efficiently meet all these requirements. Due to its high programmability and flexibility, FPGA arrays can be optimized for specific tasks, providing higher performance and efficiency.

[0003] As the amount of data in data centers and the number of tasks to be processed increase, energy consumption has become an important part of the operating costs of data centers. On the premise of increasing computing requirements, how to keep the data center running at high performance while reducing its energy consumption has become an important consideration. When performing specific computing tasks, FPGA arrays can provide a higher performance / power ratio compared to traditional CPUs and GPUs, which helps data centers reduce energy consumption and improve energy efficiency.

[0004] In the prior art, data centers allocate and coordinate FPGA array resources based on the latency between user hosts and FPGA arrays. When a user applies to use an FPGA array, the FPGA board with the minimum latency from the host in the FPGA resource pool is allocated to the user to achieve the allocation of FPGA array resources. This resource allocation method has the problem that the user not only has to execute their own tasks but also needs to execute the task of applying for an FPGA, which adds an extra burden to the user. Moreover, this resource allocation method has a single consideration aspect, only considering the latency, without considering the number of users and tasks and the status of the boards in the FPGA array. In reality, it is possible that some FPGA boards in the FPGA array are always at a high resource occupancy rate, while some FPGA boards are idle for a long time, which will not only lead to high energy consumption of the FPGA array but also relatively low utilization efficiency of the FPGA array.

[0005] Therefore, it is necessary to optimize the existing FPGA resource allocation method so that the invocation of the FPGA array matches the user's needs, which can not only reduce energy consumption but also improve the utilization efficiency of the FPGA array. Summary of the Invention

[0006] The present invention provides a method and device for adaptive dynamic scheduling of an FPGA array, which can efficiently schedule the FPGA array and reduce the energy consumption of the FPGA array at the same time.

[0007] The present invention also provides a computer-readable storage medium for implementing a method for adaptive dynamic scheduling of an FPGA array.

[0008] Other objects and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0009] To achieve one or part or all of the above objects or other objects, a method for adaptive dynamic scheduling of an FPGA array provided by a technical solution of the present invention is as follows: tasks sent from a data center to the FPGA array are received by a dynamic scheduling device. The dynamic scheduling device allocates FPGA boards according to initial settings and loads corresponding bitstream files to the FPGA boards according to the initial settings; the dynamic scheduling device selects FPGA boards with a working state of idle in the FPGA array according to the load state of the FPGA array, and then selects FPGA boards with a resource occupancy rate adapted to the task requirements from the selected FPGA boards according to the resource occupancy rate of the selected FPGA boards; adjusts the configuration files of the selected FPGA boards and generates control information for controlling the selected FPGA boards; searches for the storage location of the bitstream file corresponding to the task sent by the data center in the bitstream file library; the dynamic scheduling device downloads the bitstream file for implementing a specific algorithm function to the FPGA board according to the control information and according to the storage location of the bitstream file.

[0010] After tasks sent from the data center to the FPGA array are received by the dynamic scheduling device, tasks with a high matching degree with the currently available FPGA resources are preferentially scheduled, and the preferentially scheduled tasks are sent to the corresponding matching FPGA boards to execute tasks. Tasks with a low matching degree enter a queuing sequence to wait for the release of corresponding resources; if the task waiting time exceeds the set time, a preferential scheduling command forces an instruction. When there are multiple command forcing instructions, they are scheduled according to the reception order of the command forcing instructions.

[0011] After the dynamic scheduling device receives the tasks sent by the data center, it compares the network segments where the tasks are located and selects FPGA boards with a working state of idle among the boards in the same network segment; if the resource occupancy rate of the network segment where the task is located reaches the threshold, the dynamic scheduling device selects FPGA boards with a working state of idle among the boards in the network segment with the lowest resource occupancy rate in other network segments and assigns the scheduling right of the selected FPGA boards to the network segment where the task is located.

[0012] A load monitoring list is created in the dynamic scheduling device, and the load conditions of the FPGA boards are recorded in the load monitoring list. The load monitoring list records at least the number, status, implemented functions, resource size, and resource occupancy rate of each FPGA board. After receiving the task sent by the data center, the dynamic scheduling device searches for FPGA boards with an idle working status in the load monitoring list.

[0013] If there is already an FPGA board in the load monitoring list that is executing the input task, confirm the resource occupancy rate of the FPGA board that is executing the task, and select an FPGA board with a resource count that matches the task requirements within the same network segment of the task according to the size of the resource occupancy rate.

[0014] If the resource occupancy rate of the FPGA board that is executing the task is high, select other idle FPGA boards with a higher resource count in the network segment; if the resource occupancy rate of the FPGA board that is executing the task is low, select other idle FPGA boards with a lower resource count in the network segment.

[0015] The bitstream files corresponding to the tasks sent by the data center are managed through a bitstream status list. The bitstream status list includes at least the number, location, implemented tasks, and the number of FPGA boards executing the corresponding tasks of each bitstream. Search for the location where the bitstream file corresponding to the task sent by the data center is stored in the bitstream status list; after any FPGA board is configured, update the bitstream status list.

[0016] The update of the bitstream status list is indexed according to the number corresponding to any bitstream, and the number of FPGA boards executing the corresponding task of the bitstream is updated.

[0017] If the dynamic scheduling device does not receive any tasks within the set time, it is determined that the load of the FPGA array is not saturated. Search for the board status in the load monitoring list, record the numbers of the FPGA boards with an idle working status, adjust the configuration files of the corresponding FPGA boards, and start the sleep program. After the FPGA board enters the sleep state, the FPGA board does not accept task allocation; after the FPGA board is configured or enters the sleep state, it is fed back to the load monitoring list to update the working status of the FPGA board in the load monitoring list.

[0018] When a failure is detected in one of the FPGA boards, the system reloads the bitstream and performs a self-test to determine whether the failure has been resolved. If the failure is resolved, the FPGA board operates normally; if the failure is not resolved, another task bitstream is replaced and a functional self-test is performed. After the bitstream replacement test reaches the set number of times and the failure of the FPGA board is not resolved, the failure of the FPGA board is reported.

[0019] The bitstream file library is divided into a main bitstream area and a local bitstream area. The main bitstream file is configured to the static area of the FPGA logic, and the static area includes the basic functions for the FPGA to operate; the local bitstream file is configured to the reconfigurable area of the FPGA logic; when the dynamic scheduling device switches the FPGA board according to the resource occupancy rate of the FPGA, a local bitstream is loaded from the bitstream file library into the switched FPGA board to update some functions of the FPGA to adapt to the new task processing requirements.

[0020] An FPGA array adaptive dynamic scheduling device provided by another technical solution of the present invention includes: a task allocation module for allocating tasks to FPGA boards according to initial settings, and a dynamic loading module for loading corresponding bitstream files to the allocated FPGA boards according to initial settings; a load monitoring module for receiving tasks sent by the data center, comparing the network segments where the tasks are located, selecting FPGA boards with an idle working state in the same network segment, and according to the resource occupancy rate of the selected FPGA boards, selecting an FPGA board whose resource occupancy rate matches the task requirements, and feeding back the number of the FPGA board; a state control module for adjusting the FPGA board configuration file according to the FPGA board number fed back by the load monitoring module and the configuration requirements of the FPGA board, and generating the FPGA control information; or when the FPGA array load is not saturated, putting the corresponding idle FPGA board into sleep; a device update module storing a bitstream status list, and the device update module finds the storage location of the bitstream corresponding to the task in the bitstream file library through the bitstream status list; a dynamic loading module for starting a loading process to download the bitstream file of the specified algorithm function to the corresponding FPGA board according to the received FPGA board control information and the bitstream position corresponding to the task, configuring the FPGA board, or starting the sleep of the corresponding FPGA board; after the FPGA is configured, the task allocation module updates the status of the FPGA boards in the FPGA array and feeds it back to the load monitoring module.

[0021] The load monitoring module creates a load monitoring list to monitor the load conditions of the FPGA array. The load monitoring list records at least the following information for each FPGA board: number, status, implemented functions, resource size, and resource occupancy rate. After the load monitoring module selects the FPGA boards with an idle working status within the same network segment, it finds that there are already FPGA boards in the load monitoring list that are executing the task. It confirms the resource occupancy rate of the FPGA board. If the resource occupancy rate of the FPGA board that is currently executing the task is high, it selects other idle FPGA boards with a higher resource count within the network segment. If the resource occupancy rate of the FPGA board that is currently executing the task is low, it selects other idle FPGA boards with a lower resource count within the network segment.

[0022] A computer-readable storage medium provided by another technical solution of the present invention stores program code, and the program code is called by a processor to execute a method for adaptive dynamic scheduling of an FPGA array for a data center as described above.

[0023] Compared with the prior art, the beneficial effects of the present invention mainly include: The adaptive dynamic scheduling method and device of the FPGA array of the present invention can adaptively schedule the boards in the FPGA array resource pool. The present invention can monitor the working status of the FPGA boards in the resource pool and select FPGA boards with resource occupancy rates and resource counts that meet the requirements to execute specific tasks according to the requirements for the working status and resource occupancy rate of the FPGA boards issued by the resource center. At the same time, the present invention can also put the FPGA boards that have been idle in the FPGA array for a long time into sleep mode, reducing the power consumption of the FPGA array. Therefore, the adaptive dynamic scheduling method and device of the FPGA array of the present invention can not only meet the efficient resource scheduling but also reduce the power consumption of the FPGA array.

[0024] To make the above and other objects, features, and advantages of the present invention more obvious and understandable, the following specifically enumerates preferred embodiments and, in conjunction with the accompanying drawings, makes a detailed description as follows. Description of the Drawings

[0025] To more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the accompanying drawings required for the description of the embodiments. Obviously, the following-described accompanying drawings are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0026] Figure 1 It is a flowchart of the adaptive dynamic scheduling method for the FPGA array of the present invention.

[0027] Figure 2This is the architecture diagram of the data center and the FPGA array for the FPGA array adaptive dynamic scheduling device of the present invention.

[0028] Figure 3 This is the flowchart for the FPGA array adaptive dynamic scheduling device of the present invention to adaptively update the FPGA board.

[0029] Figure 4 This is the schematic diagram of the load monitoring list of the present invention.

[0030] Figure 5 This is the schematic diagram of the bitstream status list of the present invention. Detailed implementation manners

[0031] Regarding the foregoing and other technical contents, features and effects of the present invention, they will be clearly presented in the following detailed description of a preferred embodiment in conjunction with the reference drawings. The directional terms mentioned in the following embodiments, such as: up, down, left, right, front or back, etc., are only references to the directions of the attached drawings. Therefore, the directional terms used are for illustration and not for limiting the present invention.

[0032] Embodiment 1 Embodiment 1. A method for FPGA array adaptive dynamic scheduling. Tasks sent from the data center to the FPGA array are received by the dynamic scheduling device. The dynamic scheduling device allocates FPGA boards according to the initial settings and loads the corresponding bitstream files onto the FPGA boards according to the initial settings; the dynamic scheduling device selects the FPGA boards with an idle working state in the FPGA array according to the load status of the FPGA array, and then selects the FPGA boards with a resource occupancy rate in the selected FPGA boards that is adapted to the task requirements according to the resource occupancy rate of the selected FPGA boards; adjusts the configuration files of the selected FPGA boards and generates control information for controlling the selected FPGA boards; searches for the storage location of the bitstream file corresponding to the task sent by the data center in the bitstream file library; the dynamic scheduling device downloads the bitstream file for implementing specific algorithm functions to the FPGA board according to the control information and according to the storage location of the bitstream file.

[0033] The following is a specific description in conjunction with the drawings: See Figure 2 , the cloud data center server array sends tasks to the FPGA array through the data circulation path. Between the cloud data center server array and the FPGA array, a dynamic scheduling device receives the tasks and adaptively selects the FPGA boards that meet the requirements according to the task requirements for the FPGA boards. Refer to Figure 1 The flowchart of the FPGA array adaptive dynamic scheduling method. The FPGA array adaptive dynamic scheduling method of Embodiment 1 includes the following steps: Step S1: The task sent by the data center to the FPGA array is received and parsed by the dynamic scheduling device. According to the load status of the FPGA array, the dynamic scheduling device queries the FPGA boards with an idle working status in the same network segment from the load monitoring list, and selects the FPGA boards that match the task requirements based on the resource occupancy rate and the number of resources of the idle boards, and then feeds back the numbers of the optional FPGA boards.

[0034] After the dynamic scheduling device receives the task sent by the data center, the dynamic scheduling device first allocates FPGA boards according to the initial settings, and loads the corresponding bitstream files to the FPGA boards according to the initial settings. The allocation ratio for allocating FPGA boards in the initial settings can be evenly allocated according to the predicted number of tasks or evenly or equally allocated according to the task categories. After the dynamic scheduling device configures the FPGA according to the initial settings, during the subsequent task processing, the dynamic scheduling device dynamically adjusts the configuration of the FPGA array according to the tasks and the load conditions.

[0035] The bitstream file is a binary file used to configure the FPGA. It contains the configuration information of all programmable resources inside the FPGA, including the settings of logic units, connection methods, configurations of I / O pins, etc. The bitstream file is generated by FPGA design software, which synthesizes, places and routes the user's design description (usually a hardware description language such as Verilog or VHDL) to generate the corresponding bitstream file. The bitstream file configures all the transistors inside the FPGA chip in the form of binary data.

[0036] Step 1 specifically includes the following steps: Step S1-1: To facilitate the management of the load conditions of the FPGA array, a load monitoring list is created. The dynamic scheduling device monitors the load of the FPGA array based on the created load monitoring list, and records the load conditions of the FPGA boards in the load monitoring list. As Figure 4 shown, the load monitoring list records at least the following information for each FPGA board: number, status, implemented functions, resource size, and resource occupancy rate; where the number of the board includes a high-order value and a low-order value, the high-order value represents the network segment where the board is located, and the low-order value represents the board sequence number within the same network segment ( Figure 4Taking the board card numbered 001002 as an example, "001" in the first half represents the network segment, and "002" in the second half represents the sequence number of the board card within the 001 network segment); The status of the board card is divided into three types: working, idle, and sleeping; The main functions of the board card when working include: large-capacity memory access, high-performance image processing, a large number of floating-point operations, a high-speed encryption and decryption engine, a high number of I / Os and interfaces; The resource size of the board card is divided into three levels: high, medium, and low; The resource occupancy rate of the board card is divided into three levels: high, medium, and low. At the same time, the load monitoring list can also record the power consumption of the board card. In the first embodiment, the resource occupancy rate ≤ 30% is low, 30% < resource occupancy rate ≤ 70% is medium, and the resource occupancy rate > 70% is high.

[0037] Step S1-2: After the dynamic scheduling device receives the task sent by the data center, it searches in the load monitoring list for a board card with an idle status in the same network segment where the task is located, and feeds back the board card number of the FPGA.

[0038] If the resource occupancy rate of the network segment where the task is located reaches the threshold (which can be set according to the specific situation of the FPGA array, for example, set to 80%), the dynamic scheduling device selects an FPGA board card with an idle working status in the network segment with the lowest resource occupancy rate among other network segments, and assigns the scheduling right of the selected FPGA board card to the network segment where the task is located (that is, the selected FPGA board card is removed from the status maintenance table of the original network segment and updated into the status maintenance table of the network segment where the task is located for task scheduling in the network segment where the task is located. This process does not change the network segment belonging of the FPGA board card, but only changes the scheduling authority of the FPGA board card).

[0039] Step S1-3: If there is already a board card in the load monitoring list that is executing the currently input task, it is necessary to confirm the resource occupancy rate of the board card that is executing the task. If the resource occupancy rate shows high, select a board card with a higher level of resources among the idle board cards. If the resource occupancy rate shows low, select a board card with a lower level of resources among the idle FPGA board cards, and feed back the board card number of the FPGA. The resources of different FPGA board cards themselves determine the performance upper limit of the board card. When the resource occupancy rate of the board card is high, it is easy to affect the performance of the board card. Selecting a board card with high FPGA resources itself can reduce the resource occupancy rate of the board card, thereby reducing the impact on performance; When the resource occupancy rate is low, the board card resources have little impact on the performance of the board card. At this time, selecting a board card with low resources can avoid wasting the board card resources.

[0040] After the tasks sent by the data center to the FPGA array are received by the dynamic scheduling device, the tasks with a high matching degree with the currently available FPGA resources are preferentially scheduled, and the preferentially scheduled tasks are sent to the corresponding matching FPGA boards to execute the corresponding tasks. The tasks with a low matching degree enter the queuing sequence to wait for the release of the corresponding resources. If the waiting time of a certain task exceeds the set time, a preferential scheduling command forces an instruction. When there are multiple command forcing instructions, they are scheduled according to the receiving order of the command forcing instructions. By adjusting the priority of task scheduling, the resource situation of the FPGA array can be fully utilized.

[0041] Step S2: According to the feedback FPGA board numbers, adjust the configuration files of these FPGA boards, and at the same time generate control information for controlling these FPGA boards.

[0042] Step S3: Search for the storage location of the bitstream file corresponding to the task sent by the data center, and download the bitstream file to the corresponding FPGA board according to the storage location of the bitstream file and the FPGA board control information, and configure these selected FPGA boards. The specific steps are as follows: Step S3-1: Create a bitstream status list for managing bitstream files. The bitstream files are uniformly stored in the bitstream file library. The created bitstream status list includes at least the number, location, implemented task, and the number of FPGA boards for executing the corresponding task of each bitstream. The bitstream status list is shown in Figure 5 the schematic diagram.

[0043] Step S3-2: Search for the storage location of the bitstream file corresponding to the task sent by the data center in the bitstream status list; Step S3-3: According to the board control information and the storage location of the bitstream file corresponding to the task, start the bitstream loading program for the specified numbered FPGA board, download the bitstream file with the specified algorithm function to the corresponding FPGA board. After the FPGA board is configured, it can complete specific tasks according to the downloaded bitstream file; Among them, the bitstream file library is divided into a main bitstream area and a local bitstream area. The main bitstream file is configured to the static area of the FPGA logic resources. The static area of the FPGA logic resources includes the basic functions of FPGA operation. The local bitstream file is configured to the reconfigurable area of the FPGA logic resources; when the dynamic scheduling device switches FPGA boards according to the resource occupancy rate of the FPGA, load the local bitstream from the bitstream file library into the switched FPGA board to update part of the functions of the FPGA to adapt to the new task processing requirements. By configuring the local bitstream file, the time required for reconfiguring the FPGA board resources when processing different tasks can be reduced.

[0044] Step S3-4: Feed back the information of the configured FPGA board to the bitstream status list, index according to the bitstream number, find the number of FPGA boards corresponding to a specific bitstream that execute corresponding tasks, and update it.

[0045] If a fault is detected in a certain FPGA board during the FPGA board configuration process, the system reloads the bitstream and performs a self-detection test to determine whether the fault is cleared. If the fault is cleared, the FPGA board works normally; if the fault is not cleared, the dynamic scheduling device loads other task bitstreams into the faulty FPGA and performs a function self-check; after the bitstream replacement test reaches the set number of times and the fault of the FPGA board is not cleared, report the fault of the FPGA board, and the bitstream status list is dynamically updated during this process.

[0046] Step S4: If the dynamic scheduling device does not receive any tasks within the set time, it is determined that the load of the FPGA array is not saturated. Search the board status in the load monitoring list, record the FPGA board numbers with the working status of idle, adjust the corresponding FPGA board configuration files, and start the sleep program of the FPGA boards with the working status of idle. After the FPGA boards enter the sleep state, they do not accept task assignments.

[0047] Step S5: For the configured FPGA boards and the FPGA boards that start the sleep program, feed back the status of these FPGA boards to the load monitoring list and update the working status of the FPGA boards in the load monitoring list.

[0048] Embodiment 2 Embodiment 2 provides an FPGA array adaptive dynamic scheduling device. The dynamic scheduling device is used to receive tasks sent by a server array in a cloud data center. The dynamic scheduling device has a task allocation module. The task allocation module allocates FPGA boards according to initial settings. The dynamic loading module loads corresponding bitstream files to the allocated FPGA boards according to the initial settings. The load monitoring module receives tasks sent by the data center and compares the network segments where the tasks are located, selects FPGA boards with an idle working state within the same network segment, and based on the resource occupancy rate of the selected FPGA boards, selects an FPGA board whose resource occupancy rate is suitable for the task requirements, and feeds back the number of the FPGA board. The status control module adjusts the FPGA board configuration file according to the FPGA board number and the configuration requirements of the FPGA board fed back by the load monitoring module, and generates the FPGA control information; or when the load of the FPGA array is not saturated, puts the corresponding idle FPGA board into sleep. The device update module stores a bitstream status list. The device update module finds the storage location of the bitstream corresponding to the task in the bitstream file library through the bitstream status list. The dynamic loading module starts a loading process, configures the FPGA board, or starts the sleep of the corresponding FPGA board according to the received FPGA board control information and the bitstream location corresponding to the task. After the FPGA is configured, the task allocation module updates the status of the FPGA boards in the FPGA array and feeds it back to the load monitoring module.

[0049] The load monitoring module creates a load monitoring list to monitor the load situation of the FPGA array. The load monitoring list records at least the following information for each FPGA board: number, status, implemented functions, resource size, and resource occupancy rate. After the load monitoring module selects the FPGA boards with an idle working state within the same network segment, it finds that there are already FPGA boards executing the task in the load monitoring list. It confirms the resource occupancy rate of the FPGA board. If the resource occupancy rate of the FPGA board currently executing the task is high, it selects other idle FPGA boards with a higher resource level within the network segment. If the resource occupancy rate of the FPGA board currently executing the task is low, it selects other idle FPGA boards with a lower resource level within the network segment.

[0050] An FPGA array adaptive dynamic scheduling device provided in Embodiment 2 is used to execute the steps of an FPGA array adaptive dynamic scheduling method in Embodiment 1.

[0051] Embodiment 3 Embodiment 3 provides a computer-readable storage medium, in which program code is stored, and the program code is called by a processor to execute a method for adaptive dynamic scheduling of an FPGA array for a data center in Embodiment 1.

[0052] The above has introduced in detail an FPGA array adaptive dynamic scheduling method, device, and computer-readable storage medium provided by the present invention. Specific examples are used herein to elaborate on the structure and working principle of the present invention. The description of the above embodiments is only used to help understand the method and core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the scope of protection of the claims of the present invention.

Claims

1. An FPGA array adaptive dynamic scheduling method, characterized in that The tasks sent from the data center to the FPGA array are received by the dynamic scheduling device. The dynamic scheduling device allocates FPGA boards according to the initial settings and loads the corresponding bitstream files to the FPGA boards according to the initial settings; The dynamic scheduling device selects the FPGA boards with an idle working state in the FPGA array according to the load status of the FPGA array, and then selects the FPGA boards with a resource occupancy rate in line with the task requirements among the selected FPGA boards according to the resource occupancy rate of the selected FPGA boards; Adjust the configuration file of the selected FPGA board and generate control information for controlling the selected FPGA board; Search for the storage location of the bitstream file corresponding to the task sent by the data center in the bitstream file library; The dynamic scheduling device downloads the bitstream file for implementing specific algorithm functions to the FPGA board according to the control information and according to the storage location of the bitstream file.

2. The adaptive dynamic scheduling method for an FPGA array according to claim 1, characterized in that After the tasks sent from the data center to the FPGA array are received by the dynamic scheduling device, the tasks with a high matching degree with the currently available FPGA resources are preferentially scheduled, and the preferentially scheduled tasks are sent to the corresponding matching FPGA boards to execute the tasks. The tasks with a low matching degree enter the queuing sequence to wait for the release of the corresponding resources; If the task waiting time exceeds the set time, a preferential scheduling command is forced. When there are multiple command forcing instructions, they are scheduled according to the receiving order of the command forcing instructions.

3. A method for adaptive dynamic scheduling of an FPGA array according to claim 1, characterized in that, After the dynamic scheduling device receives the tasks sent by the data center, it compares the network segments where the tasks are located and selects the FPGA boards with an idle working state among the boards in the same network segment; If the resource occupancy rate of the network segment where the task is located reaches the threshold, the dynamic scheduling device selects the FPGA boards with an idle working state among the boards in the network segment with the lowest resource occupancy rate in other network segments, and assigns the scheduling right of the selected FPGA boards to the network segment where the task is located.

4. The adaptive dynamic scheduling method for an FPGA array according to claim 3, characterized in that A load monitoring list is created in the dynamic scheduling device, and the load conditions of the FPGA boards are recorded in the load monitoring list. The load monitoring list records at least the number, status, implemented functions, resource size, and resource occupancy rate of each FPGA board; After the dynamic scheduling device receives the tasks sent by the data center, it searches for the FPGA boards with an idle working state in the load monitoring list.

5. The adaptive dynamic scheduling method for an FPGA array according to claim 4, characterized in that If there are already FPGA boards in the load monitoring list that are executing the input tasks, confirm the resource occupancy rate of the FPGA boards that are executing the tasks, and select the FPGA boards with a resource count in line with the task requirements in the same network segment as the task according to the size of the resource occupancy rate.

6. The adaptive dynamic scheduling method for an FPGA array according to claim 5, wherein If the resource occupancy rate of the FPGA board that is executing the task is high, select other idle FPGA boards with a higher resource count in the network segment; If the resource occupancy rate of the FPGA board that is executing the task is low, select other idle FPGA boards with a lower resource count in the network segment.

7. An FPGA array adaptive dynamic scheduling method according to claim 1, characterized in that, The bitstream files corresponding to the tasks sent by the data center are managed through a bitstream status list, and the bitstream status list at least includes the number, location, implemented task, and the number of FPGA boards executing the corresponding task of each bitstream; Search for the location where the bitstream file corresponding to the task sent by the data center is stored in the bitstream status list; After any one of the FPGA boards is configured, update the bitstream status list.

8. An FPGA array adaptive dynamic scheduling method according to claim 7, characterized in that For the update of the bitstream status list, index according to the number corresponding to any one of the bitstreams, and update the number of FPGA boards executing the task corresponding to the bitstream.

9. The adaptive dynamic scheduling method for an FPGA array according to claim 4, characterized in that If the dynamic scheduling device does not receive any tasks within the set time, it is determined that the load of the FPGA array is not saturated. Search the board status in the load monitoring list, record the FPGA board numbers with the working status of idle, adjust the corresponding FPGA board configuration files, and start the sleep program. After the FPGA board enters the sleep state, the FPGA board does not accept task allocation; After the FPGA board is configured or enters the sleep state, feedback to the load monitoring list to update the working status of the FPGA board in the load monitoring list.

10. A method for adaptive dynamic scheduling of an FPGA array according to claim 1, characterized in that, When a failure occurs in a certain FPGA board is detected, the system reloads the bitstream and performs a self-detection test to determine whether the failure is resolved. If the failure is resolved, the FPGA board works normally; If the failure is not resolved, replace it with other task bitstreams and perform a function self-check; After the bitstream replacement test reaches the set number of times and the failure of the FPGA board is not resolved, report the failure of the FPGA board.

11. The adaptive dynamic scheduling method for an FPGA array according to claim 1, wherein The bitstream file library is divided into a main bitstream area and a local bitstream area. The main bitstream file is configured to the static area of the FPGA logic, and the static area includes the basic functions for the FPGA to run; The local bitstream file is configured to the reconfigurable area of the FPGA logic; When the dynamic scheduling device switches the FPGA board according to the resource occupancy rate of the FPGA, load the local bitstream from the bitstream file library into the switched FPGA board to update some functions of the FPGA to adapt to the new task processing requirements.

12. An FPGA array adaptive dynamic scheduling device, characterized in that, Including: A task allocation module that allocates tasks to FPGA boards according to the initial settings. The dynamic loading module loads the corresponding bitstream files to the allocated FPGA boards according to the initial settings; A load monitoring module that receives tasks sent by the data center and compares the network segments where the tasks are located, selects FPGA boards with the working status of idle in the same network segment, and selects the FPGA board whose resource occupancy rate matches the task requirements among the selected FPGA boards, and feedbacks the FPGA board numbers; A status control module that adjusts the FPGA board configuration file according to the FPGA board numbers and the configuration requirements of the FPGA board feedback by the load monitoring module, and generates the FPGA control information; or when the load of the FPGA array is not saturated, put the corresponding idle FPGA boards into sleep; The device update module stores a bitstream status list. The device update module locates the storage position of the bitstream corresponding to the task in the bitstream file library through the bitstream status list; The dynamic loading module starts a loading process to download the bitstream file with the specified algorithm function to the corresponding FPGA board according to the received FPGA board control information and the bitstream position corresponding to the task, configures the FPGA board, or starts the sleep of the corresponding FPGA board; After the FPGA is configured, the task allocation module updates the status of the FPGA boards in the FPGA array and feeds it back to the load monitoring module.

13. An FPGA array adaptive dynamic scheduling device according to claim 12, characterized in that, The load monitoring module creates a load monitoring list to monitor the load conditions of the FPGA array. The load monitoring list records at least the following information for each FPGA board: number, status, implemented functions, resource size, and resource occupancy rate; After the load monitoring module selects the FPGA boards with an idle working status in the same network segment, it finds that there are already FPGA boards in the load monitoring list that are executing the task; Confirm the resource occupancy rate of the FPGA board; If the resource occupancy rate of the FPGA board that is executing the task is high, select other idle FPGA boards with a higher resource level in the network segment; If the resource occupancy rate of the FPGA board that is executing the task is low, select other idle FPGA boards with a lower resource level in the network segment.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores program code, and the program code is called by a processor to execute an FPGA array adaptive dynamic scheduling method according to any one of claims 1-11.

Images