Storage resource dynamic allocation method and device, computer device and storage medium

Abstract

The application discloses a storage resource dynamic allocation method and device, computer equipment and a storage medium, relates to the technical field of computers, and comprises obtaining storage load data of each virtual function and generating load prediction data, combining a dynamic reserved space allocation strategy to realize adaptive adjustment of a physical block resource state, changing a traditional static allocation and lag monitoring mode, and constructing a resource scheduling mechanism with real-time performance and predictability. The performance fluctuation problem caused by static reserved space allocation, software monitoring delay and the lack of prediction ability in a single input / output virtualization scene is solved, the technical effects of improving storage resource dynamic scheduling efficiency, enhancing the adaptive capacity of the system to sudden load, reducing the delay jitter amplitude, and balancing flash wear through fine management are achieved.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a method, apparatus, computer equipment, and storage medium for dynamic allocation of storage resources. Background Technology

[0002] In cloud computing and edge computing, solid-state drives (SSDs) divide physical storage resources into multiple virtual functions through single-core input / output virtualization (SIP) technology, allowing virtual machines to directly access the underlying hardware and reducing virtualization resource consumption. However, in this environment, SSD reserved space management faces three major challenges: garbage collection by high-load virtual functions preempts resources, causing latency spikes for low-priority virtual functions; a fixed reserved space ratio cannot adapt to sudden changes in input / output operation rates and bandwidth requirements between virtual functions; and uneven flash memory wear leads to an increase in bad blocks, resulting in longer error correction latency and throughput fluctuations. Traditional management mechanisms are insufficient to meet the stringent service quality requirements of cloud computing.

[0003] Existing technologies have several shortcomings in quality of service management in single-root input / output virtualization scenarios: fixed reserved space allocation can lead to resource contention, causing high-load virtual functions to experience large latency fluctuations and low-priority virtual functions to exceed latency thresholds; software polling control methods have high monitoring latency and consume CPU resources, resulting in an inability to respond to sudden loads in a timely manner; static quality of service policies cannot adapt to changes in load type and do not consider flash memory health status, affecting quality of service; hardware acceleration monitoring lacks fine-grained management at the virtual function level, relies on preset rules, and is difficult to learn complex load patterns. Summary of the Invention

[0004] This application provides a method, apparatus, computer equipment, and storage medium for dynamic allocation of storage resources, in order to at least solve the problem of performance fluctuations caused by static reserved space allocation, software monitoring latency, and lack of predictive capabilities in single-root input / output virtualization scenarios in related technologies.

[0005] This application provides a method for dynamically allocating storage resources, including:

[0006] Obtain storage load data collected by each virtual function;

[0007] Load prediction data is generated based on storage load data, and the corresponding reserved space allocation strategy is determined based on the load prediction data.

[0008] The resource status of physical blocks in the dynamic reserved space resource pool is adjusted according to the reserved space allocation strategy to obtain the updated reserved space resource status.

[0009] This application also provides a storage resource dynamic allocation device, including:

[0010] The acquisition module is used to acquire storage load data collected by each virtual function;

[0011] The generation module is used to generate load prediction data based on storage load data, and determine the corresponding reserved space allocation strategy based on the load prediction data.

[0012] The adjustment module is used to adjust the resource status of physical blocks in the dynamic reserved space resource pool according to the reserved space allocation strategy, so as to obtain the updated reserved space resource status.

[0013] This application also provides an electronic device, including: a memory for storing a computer program; and a processor for implementing the steps of any of the above-described dynamic allocation methods for storage resources when executing the computer program.

[0014] This application also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, it implements the steps of any of the above-described dynamic allocation methods for storage resources.

[0015] This application also provides a computer program product, including a computer program that, when executed by a processor, implements the steps of any of the above-described dynamic allocation methods for storage resources.

[0016] This application, by adopting a method of acquiring virtual functional storage load data in real time and generating predictive data, combined with a dynamic reserved space allocation strategy to achieve adaptive adjustment of physical block resource status, changes the lag of traditional static reserved space allocation and software polling monitoring, and constructs a resource scheduling mechanism that combines real-time performance and predictability. Therefore, it can solve technical problems such as resource contention caused by static allocation in single-root input / output virtualization scenarios, response lag caused by software monitoring delays, and load fluctuations caused by lack of predictive capabilities. It achieves the technical effects of improving the efficiency of dynamic scheduling of storage resources, enhancing the system's adaptability to sudden loads, reducing latency jitter, and balancing flash memory wear through fine-grained resource management. Attached Figure Description

[0017] To more clearly illustrate the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 A flowchart illustrating a method for dynamically allocating storage resources according to an embodiment of this application;

[0019] Figure 2A schematic diagram of the architecture of the SSD dynamic reserved space allocation module provided in the embodiments of this application;

[0020] Figure 3 This is a schematic diagram of the architecture of an NVMeSSD system provided in an embodiment of this application;

[0021] Figure 4 A schematic diagram of the process logic of the machine learning dynamic prediction module provided in an embodiment of this application;

[0022] Figure 5 A structural block diagram of the storage resource dynamic allocation device provided in the embodiments of this application;

[0023] Figure 6 This is a schematic diagram of the hardware structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the protection scope of this application.

[0025] It should be noted that, in the description of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. The terms "first," "second," etc., in this application are used to distinguish similar objects and are not used to describe a specific order or sequence.

[0026] To enable those skilled in the art to better understand the present application, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0027] The specific application environment architecture or specific hardware architecture on which the dynamic allocation method for storage resources depends is described here.

[0028] Embodiments of this application provide a method for dynamically allocating storage resources. Figure 1 This is a flowchart of a dynamic allocation method for storage resources according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps:

[0029] Step S101: Obtain the storage load data collected by each virtual function.

[0030] It's important to note that a Virtual Function (VF) is a logical functional unit in storage systems and other scenarios that can independently perform resource allocation and performance statistics. Each VF can be viewed as an independent small storage entity, used to differentiate between different storage usage scenarios or users. Storage load data reflects the runtime load of the storage system, including information such as operation frequency, bandwidth, garbage collection frequency, and raw bit error rate, used for subsequent analysis of storage system status, load prediction, and optimization of resource allocation.

[0031] In this embodiment of the application, the method for collecting storage load data includes:

[0032] For operation frequency acquisition: A dedicated hardware counter is configured for each virtual function. The counter increments when the input / output command corresponding to the virtual function is completed. To obtain the number of operations per second, a 1ms timer inside the FPGA is used to periodically latch the current counter value. After latching, the counter is cleared, and then the operation frequency of the virtual function is obtained through calculation (the latched value corresponds to the number of operations within 1ms, multiplied by 1000 to get the number of operations per second).

[0033] For bandwidth and garbage collection frequency acquisition: Bandwidth is monitored via the data bus. A lightweight DMA controller is embedded in the FPGA to count the amount of data (in bytes) transferred by each virtual function's read / write data stream within a 1ms time window. This data volume is then converted into a bandwidth value in Gbps. Garbage collection frequency is measured by connecting the FPGA pin to the garbage collection trigger signal line of the flash memory conversion layer. Using the FPGA's edge detection circuit, the number of times the garbage collection trigger signal is triggered within a 1ms window is counted; this number is the garbage collection frequency (times / ms).

[0034] For raw bit error rate (RBER) acquisition: Before LDPC decoding, capture the raw data of the NAND page (including ECC check bits) and simultaneously acquire the error correction data after LDPC decoding. Compare these two types of data, count the number of bit errors, and then calculate the raw bit error rate (RBER).

[0035] Step S102: Generate load prediction data based on storage load data, and determine the corresponding reserved space allocation strategy based on the load prediction data.

[0036] It should be noted that load forecasting data is derived from inferring future load conditions of the storage system (such as trends in operation frequency and bandwidth) and is used to predict storage resource demand. The reserved space allocation strategy (OP allocation strategy) is a scheme determined based on load forecasting results to adjust the allocation of physical block resources in the dynamic reserved space resource pool to adapt to changes in storage load.

[0037] In this embodiment, the specific process for generating load prediction data includes: acquiring historical storage load data and corresponding historical state values ​​from the previous time step; combining the storage load data with the historical storage load data to obtain state control parameters; using the state control parameters to perform fusion calculations on the storage load data and historical state values ​​to obtain the current state value; and determining the corresponding load prediction data based on the current state value. The specific process for determining the corresponding reserved space allocation strategy based on the load prediction data includes: constructing a state space based on the load prediction data and a preset load type; selecting an allocation ratio adjustment action that matches the state space from a preset action space, executing the allocation ratio adjustment action, and obtaining feedback information; converting the feedback information into a strategy optimization signal, and iteratively updating the allocation ratio adjustment action using the strategy optimization signal until the feedback information meets preset conditions, thereby obtaining the reserved space allocation strategy.

[0038] Step S103: Adjust the resource status of physical blocks in the dynamic reserved space resource pool according to the reserved space allocation strategy to obtain the updated reserved space resource status.

[0039] It should be noted that the dynamic reserved space resource pool includes a global resource pool and independent resource pools corresponding to each virtual function (VF). The global resource pool is used to uniformly manage the physical block resources of the storage system. It has a global state mapping table that records the status identifier (idle or allocated) of physical blocks. The independent resource pool corresponding to each virtual function allocates resources from the global resource pool and has a resource allocation linked list that records the capacity information of each physical block under that virtual function. Adjusting the resource status is based on the reserved space allocation strategy, changing the allocation status of physical blocks in the dynamic reserved space resource pool, such as allocating idle blocks in the global resource pool to virtual functions, or releasing blocks that are no longer needed by virtual functions back to the global resource pool.

[0040] In this embodiment, the resource status of physical blocks in the dynamic reserved space resource pool is adjusted according to the reserved space allocation strategy to obtain the updated reserved space resource status. The specific process includes: determining the amount of reserved space resources to be released according to the reserved space allocation strategy; determining the number of physical blocks according to the amount of reserved space resources to be released; querying the global state mapping table for consecutive free physical blocks that meet the number of physical blocks, and using the consecutive free physical blocks as target physical blocks; if there are no consecutive free physical blocks that meet the number of physical blocks, allocating multiple non-consecutive free physical blocks according to the number of physical blocks, and using the non-consecutive free physical blocks as target physical blocks; removing the capacity information of the target physical blocks from the resource allocation chain, and marking the target physical blocks as allocated in the global state mapping table.

[0041] In this embodiment of the application, the storage load data includes data of multiple preset load types, including operation frequency type, bandwidth type, recycling frequency type, and bit error rate type. The method for collecting storage load data includes the following steps A1-A4:

[0042] Step A1: Configure a hardware counter for each virtual function, increment the count value when the input / output command is completed, and convert the count value into the operation frequency.

[0043] Specifically, the hardware counter is a dedicated 32-bit hardware counter for each virtual function, used to count the number of operations related to the virtual function. Input / output commands (I / O commands): These are read, write, and other operation instructions executed by the storage system on the virtual function; corresponding feedback is provided upon command completion. Operation frequency (IOPS): This is the number of input / output operations per second, reflecting the operational activity level of the virtual function.

[0044] For each virtual function (VF), an independent 32-bit hardware counter is allocated at the hardware level (such as in an FPGA-based hardware environment). This counter serves as the basic hardware unit specifically for counting the number of operations performed by that virtual function. When the input / output (I / O) command corresponding to the virtual function is completed (e.g., a read or write command is executed and a completion signal is sent back to the completion queue CQ), the hardware counter automatically increments to record the I / O operation. Using a 1ms timer within the FPGA, the counter value is latched when the timer reaches 1ms, locking and saving the current counter value. The counter is then cleared to count the number of operations performed in the next 1ms. Since the latched value represents the number of I / O operations completed by the virtual function within 1ms, multiplying it by 1000 (1 second contains 1000 1ms intervals) yields the number of I / O operations performed by that virtual function per second, i.e., the operation frequency (IOPS). In this way, by configuring a dedicated hardware counter for each virtual function, using I / O command completion events to trigger counting, and combining timer latching and calculation, the operation frequency of the virtual function can be collected.

[0045] Step A2: Monitor the amount of data transmitted within the time window and the number of times the garbage collection trigger signal is triggered, convert the amount of data transmitted into a bandwidth value, and use the number of triggers as the garbage collection frequency.

[0046] Specifically, a time window refers to a pre-defined continuous time interval for data collection, specifically 1ms in this text, serving as a time standard for calculating the amount of data transferred and the number of garbage collection triggers. The amount of data transferred is the number of bytes transmitted via the data bus during read / write operations by the Virtual Function (VF) within the time window. The garbage collection trigger signal is emitted by the Flash Translation Layer (FTL) to trigger garbage collection (GC) operations, indicating that garbage collection of storage units is required. Bandwidth is an indicator of data transfer rate, reflecting the number of data bits transmitted per unit time. The garbage collection frequency is the number of times the garbage collection trigger signal is triggered within a unit of time (i.e., the time window, here 1ms), reflecting the frequency of garbage collection operations.

[0047] On one hand, a lightweight DMA (Direct Memory Access) controller is embedded in the hardware environment (such as an FPGA) to monitor the read / write data flow of each virtual function (VF). Within a set 1ms time window, the number of bytes of read / write data flowing through the data bus for that virtual function is counted; this is the amount of data transmitted. The counted number of bytes is then converted to a bandwidth value in Gbps using the formula "bandwidth = data volume × 8 (converted to bits) / 1ms".

[0048] On the other hand, by connecting the FPGA pins to the GC start signal line of the Flash Translation Layer (FTL), the edge detection circuit of the FPGA detects the edge changes of the garbage collection trigger signal generated by the GC start signal line within a 1ms time window. Each valid edge detected (representing one garbage collection trigger) is counted once. The number of triggers counted within this time window (1ms) is the garbage collection frequency (unit: times / ms). In this way, by monitoring the amount of data transferred and calculating the bandwidth through the DMA controller, and by using the pin connection and edge detection to count the number of garbage collection triggers, the bandwidth value and garbage collection frequency are collected.

[0049] Step A3: Obtain the raw data before channel decoding and the error correction data after channel decoding, and calculate the corresponding raw bit error rate based on the raw data and the error correction data.

[0050] Specifically, the raw data before channel decoding is stored in NAND flash memory and is unprocessed by low-density parity-check (LDPC) decoding. It contains user data and ECC check bits and may contain bit errors generated during transmission or storage. The error-corrected data after channel decoding is the raw data after LDPC decoding, with errors corrected using error correction algorithms. The raw bit error rate (RBER) is a metric that measures the proportion of bit errors in the raw data to the total number of bits, used to evaluate the reliability of the storage medium and the quality of data transmission.

[0051] First, before LDPC decoding, the raw data of the NAND page is captured via a hardware interface (such as the interface between the FPGA and the LDPC decoding module). This data contains user-stored information and ECC check bits used for error detection and correction. After LDPC decoding is complete, the error-corrected output data, i.e., the error-corrected data after channel decoding, is obtained.

[0052] Next, the original data and the error-corrected data are compared bit by bit, and the number of inconsistent bit positions is counted, i.e., the number of bit errors. The total number of bits in the original data (including all user data and ECC check bits) is determined. The corresponding original bit error rate (RBER) is calculated using the following formula: RBER = Number of Bit Errors / Total Number of Bits, where RBER is the original bit error rate; the number of bit errors is the number of inconsistent bit positions between the original data and the error-corrected data; and the total number of bits is the total number of bits including user data and ECC check bits.

[0053] Step A4: Construct storage load data using operation frequency, bandwidth value, garbage collection frequency, and raw bit error rate.

[0054] The acquired data, such as operation frequency, bandwidth value, garbage collection frequency, and raw bit error rate, are initially summarized by each virtual function to form a raw data set containing indicators of various dimensions. This raw data set is the storage load data.

[0055] In this embodiment, after acquiring the storage load data collected by each virtual function, the hardware acceleration engine is used to perform real-time feature enhancement processing on the storage load data. Specifically, the hardware acceleration engine is integrated into the FPGA and includes a tensor accelerator and a real-time filtering module. First, raw data such as operation frequency, bandwidth, GC frequency, and RBER are input into the tensor accelerator. Cross-dimensional weighted fusion is then performed through a hardware multiplier array within the FPGA. The weight matrix is ​​dynamically updated by an online learning module according to different load scenarios; for example, the weight ratio of operation frequency is automatically increased for high IOPS scenarios. Then, the finite impulse response filter bank configured in the FPGA is used... The fused data is bandpass filtered, and the cutoff frequency of the filter is dynamically adjusted according to the physical characteristics of the NAND flash memory. For example, when severe flash memory wear is detected, the cutoff frequency of high-frequency noise is automatically reduced to suppress random errors introduced by storage medium fluctuations. Finally, a hardware-implemented principal component analysis dimensionality reduction algorithm is used, which accelerates eigenvalue decomposition through a lookup table in the FPGA, compressing the 4-dimensional original data into a 2-dimensional key feature vector. One dimension represents the load intensity, which is positively correlated with IOPS and bandwidth, and the other dimension represents the storage health, which is negatively correlated with RBER and GC frequency. This completes the real-time feature enhancement processing of the storage load data, resulting in compressed load feature data.

[0056] In this embodiment of the application, generating a load prediction value based on storage load data includes the following steps B1-B4:

[0057] Step B1: Obtain the historical storage load data and corresponding historical status values ​​from the previous time step.

[0058] Specifically, the previous time step refers to the time interval preceding the current point in time (e.g., if the current processing time is t, then the previous time step is t-1), used to define the time range of historical data. Historical storage load data refers to the storage load data collected and processed by the storage system in the previous time step, including multi-dimensional indicators such as operation frequency, bandwidth value, garbage collection frequency, and raw bit error rate. Historical state values ​​are the hidden states generated by the Long Short-Term Memory (LSTM) network when processing data in the previous time step. ) and memory unit state ( ), used to convey timing dependency information.

[0059] Step B2: Combine the storage load data with the historical storage load data to obtain the status control parameters.

[0060] Specifically, the state control parameters include: a new information retention ratio coefficient, a historical information forgetting ratio coefficient, and candidate memory values. The new information retention ratio coefficient corresponds to the input gate output value of the Long Short-Term Memory (LSTM) network, used to control the inflow ratio of new information, and its value ranges from [0,1]. The historical information forgetting ratio coefficient corresponds to the forgetting gate output value of the LSTM network, used to control the forgetting ratio of historical information, and its value ranges from [0,1]. The candidate memory value corresponds to the candidate memory unit output value of the LSTM network, used to generate memory information to be updated.

[0061] First, the current storage load data (e.g., [IOPS_t, bandwidth_t, GC frequency_t, RBER_t]) is concatenated with the historical storage load data (e.g., [IOPS_{t-1}, bandwidth_{t-1}, GC frequency_{t-1}, RBER_{t-1}]) to form an 8-dimensional input vector. .

[0062] Secondly, the input vector Compared with historical state values respectively with the input gate weight matrix Perform matrix multiplication, then process the input through the sigmoid activation function to obtain the input gate output value. (i.e., the new information retention ratio coefficient), the formula is:

[0063]

[0064] in, A percentage coefficient is retained for new information; Use the Sigmoid activation function; The input gate weight matrix; These are historical state values; The input vector; This is an input gate bias term. The closer to 1, the higher the proportion of historical information retained.

[0065] Input vector Compared with historical state values respectively with the forget gate weight matrix Perform matrix multiplication, then pass the sigmoid activation function to obtain the output value of the forget gate. (i.e., the historical information forgetting rate coefficient), the formula is:

[0066]

[0067] in, This is the historical information forgetting rate coefficient; Use the Sigmoid activation function; This is the forget gate weight matrix; These are historical state values; The input vector; This is a term related to the forgetting gate paranoia. The closer it is to 0, the higher the proportion of forgotten historical information.

[0068] Input vector Compared with historical state values respectively with the candidate memory unit weight matrix Perform matrix multiplication and process the data using the Tanh activation function to obtain candidate memory values. This value is used for subsequent updates of memory units, and the formula is:

[0069]

[0070] in, Candidate memory values; Use the Tanh activation function; The candidate memory unit weight matrix; These are historical state values; The input vector; This is a candidate memory unit bias term.

[0071] Finally, the current storage load data is combined with the historical storage load data, and then processed by matrix operations and activation functions of the LSTM gating mechanism to generate new information retention ratio coefficients, historical information forgetting ratio coefficients, and candidate memory values, which serve as state control parameters for controlling the flow of information.

[0072] Step B3: Use the status control parameters to perform a fusion calculation on the storage load data and historical status values ​​to obtain the current status value.

[0073] Specifically, the current state value is the updated state of the memory unit after integrating current and historical information. and hidden state This serves as the output state of the LSTM at the current time step.

[0074] First, utilize the historical information forgetting rate coefficient. Status of historical memory units Weighting is applied to determine the degree to which historical information is retained: Utilizing new information to retain the proportion coefficient Candidate memory values We perform weighted analysis to determine the inflow of new information: Adding the two parts together yields the updated memory cell state. The formula is:

[0075]

[0076] in, This is the updated memory cell state; This is the historical information forgetting rate coefficient; This is the state of a historical memory unit; A percentage coefficient is retained for new information; Candidate memory values; This is element-wise multiplication.

[0077] This process achieves selective forgetting of historical memories and selective storage of new information through the synergistic effect of the forgetting gate and the input gate.

[0078] Secondly, the output gate coefficient Through input vector With historical hidden state respectively with the output gate weight matrix The matrix multiplication, combined with the Sigmoid activation function, is used to control the state of memory cells. The output ratio is given by the formula:

[0079]

[0080] in, For output gate coefficients; Use the Sigmoid activation function; This is the output gate weight matrix; These are historical state values; The input vector; This is the output gate bias term.

[0081] Finally, the updated memory cell state Apply the Tanh activation function, map it to the interval [-1, 1], and then compare it with the output gate coefficient. Multiply to obtain the current hidden state. The formula is:

[0082]

[0083] in, Currently hidden; For output gate coefficients; This is element-wise multiplication; Use the Tanh activation function; This is the updated memory cell state.

[0084] Current hidden state With the updated memory cell state All values ​​are current state values, which include both the temporal characteristics of the current load data and the dependencies of historical states.

[0085] Step B4: Determine the corresponding load prediction data based on the current state value.

[0086] It should be noted that the current state value is the current hidden state of the Long Short-Term Memory (LSTM) network after the update at the current time step. and the updated memory cell state It integrates the time-series characteristics of current and historical storage load data. The load prediction data is the storage load prediction result for a future period of time (e.g., 10ms) after processing the current state value by the LSTM model, including predicted values ​​of indicators such as operation frequency (IOPS), bandwidth value, and garbage collection frequency.

[0087] Specifically, firstly, the hidden states in the current state value. The storage load data already includes time-dependent characteristics (such as trends in operation frequency and bandwidth fluctuation patterns), so it can be directly... As input to the output layer of the LSTM model, no additional feature extraction is required. Secondly, the output layer of the LSTM model is a fully connected layer, and its weight matrix... With hidden state Matrix multiplication is performed, followed by processing with a linear activation function (or a suitable activation function, such as ReLU, selected based on the prediction objective) to obtain predicted values ​​for each load metric. If load data for multiple time steps (e.g., the next 10ms) needs to be predicted, a recursive prediction method can be used: the predicted value of the current time step is used as one of the input features for the next time step, combined with new storage load data, and then input into the LSTM again, iteratively generating predicted values ​​for subsequent time steps. For example, first predict the load 1ms later, then combine this predicted value with the current state to predict the load 2ms later, until a 10ms prediction sequence is completed. Through these steps, the LSTM model utilizes the temporal features inherent in the current state value, and the output layer calculates and generates future load prediction data, providing data support for the formulation of subsequent reserved space allocation strategies.

[0088] In this embodiment of the application, the corresponding reserved space allocation strategy is determined based on load forecast data, including the following steps C1-C3:

[0089] Step C1: Construct a state space based on load prediction data and preset load types.

[0090] Specifically, in a deep reinforcement learning network (DQN), the state space is a multi-dimensional vector space used to describe the current state of the storage system. It includes load prediction data, real-time state parameters, etc., and serves as input to the decision model. The process includes:

[0091] First, obtain the load prediction values ​​for the next 10ms generated by the LSTM model, such as the predicted operation frequency, bandwidth, and garbage collection frequency. These data reflect the future load trend of the storage system. Then, obtain the raw bit error rate (RBER) in real time from the hardware monitoring engine. This parameter is used to evaluate the reliability of the storage medium and is a key real-time indicator of the state space.

[0092] Secondly, the preset load types (operating frequency type, bandwidth type, recovery frequency type, bit error rate type) are converted into numerical codes. For example, the operating frequency type is divided into "high", "medium" and "low" according to the load characteristics, and encoded as 3, 2 and 1 respectively, forming the load type code.

[0093] The load prediction data, raw bit error rate, and load type are encoded and concatenated into a state space vector. The specific form is as follows:

[0094]

[0095] This vector integrates future load prediction, current storage status, and load feature classification to form the input state space of the deep reinforcement learning model, which has 8 dimensions (taking the example parameters as an example).

[0096] Step C2: Select an allocation ratio adjustment action from the preset action space that matches the state space, execute the allocation ratio adjustment action, and obtain feedback information.

[0097] It should be noted that the preset action space is a predefined set of actions for adjusting the reserved space allocation ratio (OP allocation ratio). It includes a series of discrete adjustment steps (such as ±2%, ±5%, etc.) to represent the adjustment method for the allocation ratio of Virtual Functions (VFs) reserved space resources. The allocation ratio adjustment action is a specific adjustment operation selected from the preset action space, such as increasing or decreasing the reserved space allocation ratio of a certain Virtual Function (VF) by 2% or 5%, used to change the physical block allocation status of the dynamic reserved space resource pool. Feedback information refers to real-time metrics related to the reserved space allocation effect returned after executing the allocation ratio adjustment action, including latency standard deviation, reserved space resource utilization, and Quality of Service (QoS) stability, used to evaluate the effectiveness of the action.

[0098] Specifically, firstly, the state space vector Inputting the pre-trained DQN network, the network outputs the Q-value (action value) for each action, which is reflected in the state space. Next action The expected long-term reward. Actions are selected from a pre-defined action space: the action with the highest Q-value is chosen with probability (utilizing the existing optimal strategy), for example, the action that maximizes the allocation ratio adjustment of the Q-value. (e.g., +2%).

[0099] Secondly, based on the selected action The adjustment direction (expansion or contraction) and proportion of reserved space resource allocation are determined. For example, if the action is "+2%", then physical block resources equivalent to 2% of the current capacity of the target virtual function are allocated from the global reserved space resource pool to the independent resource pool of the target virtual function. Through the dynamic reserved space resource pool management mechanism, the allocation or release of physical blocks is executed: if it is expansion, the target physical block is selected from the free blocks in the global resource pool, and the global state mapping table and the resource allocation linked list of the virtual function are updated. If it is contraction, a portion of the physical blocks in the independent resource pool corresponding to the virtual function are released to the global resource pool, and consecutive free blocks are merged to reduce fragmentation.

[0100] Finally, after the action is executed, the hardware monitoring engine collects new storage load data (IOPS, bandwidth, garbage collection frequency, RBER) in real time and calculates metrics such as latency standard deviation and reserved space resource utilization (OP resource utilization).

[0101] According to the preset reward function (e.g.) ,in, For feedback information, (Weighting coefficients to balance delay stability and capacity efficiency). As feedback information for evaluating the effectiveness of the action.

[0102] Step C3: The feedback information is converted into a strategy optimization signal. The allocation ratio adjustment action is iteratively updated using the strategy optimization signal until the feedback information meets the preset conditions, thus obtaining the reserved space allocation strategy.

[0103] Specifically, the policy optimization signal is generated from feedback information and used to update the parameters of the deep reinforcement learning (DQN) model. It is usually represented by the error term of the Q value. The preset condition is a pre-defined termination iteration criterion, such as the feedback information (reward value) fluctuating less than a threshold for N consecutive rounds, or the delay standard deviation being lower than the QoS requirement.

[0104] First, according to the state space , Distribution ratio adjustment action Feedback information received and the next state Deep reinforcement learning networks approximate the optimal policy through the Q-function:

[0105]

[0106] in, The optimal Q value; For state space Next action The corresponding Q value; For state space; Actions to adjust the allocation ratio; Use the Sigmoid activation function; For feedback information; This is a discount factor (e.g., 0.99). For the next state space Next, iterate through all possible actions. The allocation strategy that maximizes the Q value is selected, reflecting the prediction of the optimal value of the future state.

[0107] Real-time monitoring of feedback information after each iteration (e.g., latency standard deviation decreases from 80μs to 45μs, reward value increases from -0.8 to -0.2). When the latency standard deviation is lower than the QoS requirement threshold (e.g., 50μs) for N consecutive rounds (e.g., N=50), or the reward value fluctuates less than the preset threshold (e.g., 10%) for M consecutive rounds (e.g., M=10), the iteration stops. The strategy corresponding to the current Q value (e.g., prioritizing the allocation of +2% resources to virtual functions with high IOPS load) is the final reserved space allocation strategy.

[0108] In this embodiment, the dynamically reserved space resource pool includes a global resource pool and independent resource pools corresponding to each virtual function; the global resource pool is provided with a global state mapping table, which is used to record the state identifier of physical blocks; the independent resource pools corresponding to virtual functions are provided with resource allocation linked lists, which are used to record the capacity information of each physical block in the independent resource pools.

[0109] Specifically, the structure of the dynamic reserved space resource pool (dynamic OP resource pool) is as follows:

[0110] Global Resource Pool: As the overall pool for resource allocation, 15% to 35% of the physical capacity is allocated as a global resource pool during storage system initialization. The physical blocks in this pool may be discontinuous due to bad block replacement or wear leveling. The global resource pool manages the status of all physical blocks through a global state mapping table (free block bitmap).

[0111] Independent resource pools for each virtual function: Each virtual function has its own independent resource pool, and its resources are dynamically allocated from the global resource pool. For example, when a virtual function needs to expand, it requests physical blocks from the global resource pool; when it shrinks, it releases the physical blocks back to the global resource pool.

[0112] The global state mapping table is implemented using a bitmap data structure, where each bit corresponds to a physical block. For example, if the global resource pool contains 1024 physical blocks, the bitmap is 1024 bits (128 bytes). During initialization, all physical blocks are marked as "0" (free) in the bitmap; when a physical block is allocated to a VF, the corresponding bit is set to "1"; after release, the bit is reset to "0". If the released block is contiguous with an adjacent free block, the bitmap is merged and marked as a larger contiguous free space.

[0113] Resource allocation linked list implementation: Each virtual function maintains a linked list (such as the OP BlockNode linked list). The linked list nodes store the physical block information allocated to that virtual function, including: the physical block's starting address (LBA or PBA), the number of consecutive blocks, and a pointer to the next node. When the global resource pool allocates a physical block to a virtual function, the allocated block information (starting address, length) is inserted at the end of the linked list; when a block is released, the corresponding node is removed from the linked list, and the global state mapping table is updated.

[0114] In this embodiment of the application, the resource status of physical blocks in the dynamic reserved space resource pool is adjusted according to the reserved space allocation strategy to obtain the updated reserved space resource status, including the following steps D1-D3:

[0115] Step D1: Determine the amount of reserved space resources to be released based on the reserved space allocation strategy.

[0116] Specifically, first, the adjustment instructions for the target virtual function are extracted from the reserved space allocation strategy, specifying the adjustment type (e.g., scaling down) and adjustment ratio (e.g., -5%). For example, if the strategy indicates that the reserved space allocation ratio for a certain virtual function needs to be reduced by 5%, then the current resource usage of the virtual function and the corresponding release ratio need to be calculated. Second, the current resource usage is calculated: traverse the resource allocation list of the target virtual function, sum the number of consecutive blocks of all nodes, and obtain the total number of physical blocks currently allocated to the virtual function. For example, if the resource allocation list of the virtual function contains two nodes with consecutive block counts of 10 and 15 respectively, then the current number of physical blocks occupied is 25. Finally, the amount of resources to be released is determined: based on the adjustment ratio and the current resource usage, the number of physical blocks to be released is calculated. For example, if the current usage is 25 blocks and the adjustment ratio is -5%, then the number of blocks to be released is 25 × 5% = 1.25, rounded up to 2 blocks (or rounded up according to the smallest allocation unit specified by the strategy, such as 1 block).

[0117] Step D2: Select the target physical block from the global state mapping table based on the amount of reserved space resources to be released.

[0118] In this embodiment of the application, selecting a target physical block from the resource allocation list of a virtual function based on the amount of reserved space resources to be released includes: determining the number of physical blocks based on the amount of reserved space resources to be released; querying the global state mapping table for consecutive free physical blocks that meet the number of physical blocks, and using the consecutive free physical blocks as the target physical blocks.

[0119] Specifically, based on the amount of reserved space resources to be released, the number of physical blocks to be selected from the global resource pool is determined. The bitmap of the global state mapping table is traversed in physical block address order, checking free blocks with a bit value of "0" bit by bit. When N or more consecutive "0" bits are found, the starting address and number of these consecutive blocks are recorded. For example, if two consecutive free blocks with addresses 100-101 are found in the bitmap, these two blocks are selected as target physical blocks. If a sufficient number of consecutive blocks are found, these blocks are marked as "1" (allocated) in the bitmap, and their starting address and length are recorded.

[0120] Step D3: Remove the capacity information of the target physical block from the resource allocation chain and mark the target physical block as allocated in the global state mapping table.

[0121] Specifically, if the reserved space allocation strategy is to release resources (such as shrinking virtual functions), the node corresponding to the physical block to be released is deleted from the resource allocation linked list of the target virtual function. For example, to release two non-contiguous blocks at addresses 50 and 200, the node corresponding to the starting address in the linked list needs to be found and removed.

[0122] If the strategy is to allocate resources (such as expanding virtual functions), the starting address, length, and other information of the selected target physical block (contiguous or non-contiguous) are inserted into the tail of the virtual function's resource allocation linked list. For example, to allocate a contiguous block from address 100 to 102, a new node of length 3 is created and added to the linked list.

[0123] When releasing resources, the corresponding physical block's bit in the global state map is marked from "1" (allocated) to "0" (free). If the released block is contiguous with adjacent free blocks, adjacent "0" bits are merged to mark a larger contiguous free space (e.g., after releasing the block at address 200, if addresses 199 and 201 are both free, the contiguous free regions marked as 199~201 are merged). When allocating resources, the target physical block's bit in the global state map is marked from "0" to "1", indicating that the resource has been allocated to a virtual function.

[0124] In this embodiment of the application, the method further includes: if there are no consecutive free physical blocks that meet the number of physical blocks, then allocate multiple non-consecutive free physical blocks according to the number of physical blocks, and use the non-consecutive free physical blocks as target physical blocks.

[0125] Specifically, if no contiguous free area meeting the required number of physical blocks is found after querying the global free block bitmap, the system will execute a non-contiguous block allocation process: First, it traverses the bitmap to find multiple scattered free physical blocks, collecting a sufficient number of non-contiguous free blocks (total number of blocks ≥ requirement N) by scanning the "0" bits (representing free blocks); then, it records the physical starting address and single block length (usually 1 block) of each non-contiguous block, and combines the information of these blocks into allocation units in sequence; finally, it inserts the node containing the non-contiguous block starting address, length, and other information into the tail of the reserved space (OP) allocation list of the virtual function (VF), and marks the corresponding bits of these blocks as "1" (allocated status) in the global free block bitmap, thereby completing the allocation of non-contiguous free physical blocks and ensuring that the reserved space expansion requirements of the virtual function (VF) are met.

[0126] In this embodiment of the application, the method further includes: obtaining the modification frequency of each data block in the independent resource pool; identifying the target data block whose modification frequency is less than a preset frequency threshold; treating the data in the target data block as cold data and migrating the cold data to the global resource pool.

[0127] Specifically, the hardware monitoring engine's performance counters and data bus monitoring module record the number of read and write operations for each data block in the independent resource pool (i.e., the virtual function (VF) independent reserved space resource pool) in real time. Specifically, the hardware counter for each virtual function (VF) increments when a data block is modified (when a write operation completes and returns to the CQ). An internal FPGA 1ms timer triggers the counter value to latch and reset to zero. By counting the number of modifications per unit time (e.g., modifications per second), the modification frequency of each data block can be obtained.

[0128] The modification frequency of each acquired data block is compared with a preset threshold (e.g., 1 time / second). If the modification frequency of a data block is lower than the threshold, it is determined to be a "cold data block". For example, if the preset threshold is 1 time / second, and the average modification frequency of a data block is less than 1 time / second in multiple consecutive statistical periods (e.g., 10 1ms windows), it is marked as a target data block and included in the cold data migration candidate set.

[0129] Next, the physical address of the target data block is located, and its data content is read. Then, a free physical block is searched in the global reserved space resource pool (global OP resource pool) (determined by the global free block bitmap). If there are consecutive free blocks, they are allocated first; otherwise, non-consecutive blocks are allocated. Finally, the cold data is written to the target block in the global pool, and the allocation list of the Virtual Function (VF) independent reserved space resource pool is updated (removing the information of migrated blocks) and the global bitmap (marking the newly allocated block as allocated). At the same time, the mapping from logical address to physical address in the FTL is updated to complete the cold data migration.

[0130] In this embodiment of the application, before constructing storage load data using operating frequency, bandwidth value, garbage collection frequency, and raw bit error rate, the method further includes: performing a sliding window average calculation on the operating frequency, bandwidth value, garbage collection frequency, and raw bit error rate to obtain initial storage load data; identifying outliers in the storage load data, and performing a filtering operation on the outliers in the storage load data to obtain storage load data.

[0131] Specifically, after the hardware monitoring engine collects data on various metrics in real time, it uses a moving average filtering algorithm with a window length of 10 for processing: for operation frequency (IOPS), bandwidth value, and garbage collection (GC) frequency, the sampling values ​​at the current moment and the previous 9 periods are summed and averaged to obtain the smoothed value; for the raw bit error rate (RBER), the number of bit errors is obtained when the LDPC decoding is completed and an interrupt is triggered, and the average value is calculated based on the statistical values ​​of the most recent 10 interrupts. Finally, initial storage load data containing IOPS, bandwidth, GC frequency, and RBER is generated to reduce the impact of short-term fluctuations on the data.

[0132] Outlier identification is based on the 3σ principle: First, the mean and standard deviation of each indicator (such as IOPS) in the initial storage load data are calculated. If the value of a certain indicator exceeds the mean plus three times the standard deviation (abnormal increase) or is lower than the mean minus three times the standard deviation (abnormal drop), it is determined to be an outlier. For the identified outliers, the mean of adjacent periods is used to replace or directly remove them. Then, the missing values ​​are supplemented by linear interpolation. Finally, the filtered storage load data is obtained, ensuring that the time series data input into the machine learning model has stability and reliability.

[0133] In this embodiment of the application, the method for determining the reserved space allocation strategy further includes: inputting storage load data into a pre-trained target machine learning model to obtain the reserved space allocation strategy;

[0134] The training method for the target machine learning model includes the following steps E1-E4:

[0135] Step E1: Obtain storage load data samples and corresponding status value samples.

[0136] Specifically, a hardware monitoring engine continuously collects multi-dimensional storage load data (such as IOPS, bandwidth, GC frequency, and RBER), and performs sliding window averaging and outlier filtering at 1ms intervals. Simultaneously, it records the system status values ​​corresponding to each data sampling moment (such as the reserved space allocation ratio for each virtual function, QoS indicators, NAND wear status, etc.). Multiple sets of historically collected time-series data (such as 1000 consecutive sampling points) and their corresponding status values ​​are organized into a training sample set, where storage load data serves as input features and status values ​​serve as supervisory signals for subsequent model training.

[0137] Step E2: Pre-train the initial long short-term memory network layer using the storage load data samples and the corresponding state value samples to obtain the target long short-term memory network.

[0138] Specifically, an offline pre-training method is used, where stored load data samples (such as IOPS and bandwidth time series) are input into the initial LSTM network. The network handles temporal dependencies through gating mechanisms (input gate, forget gate, output gate) to predict the load trend in the next 10ms. During training, the mean squared error (MSE) is used as the loss function to minimize the deviation between the predicted and actual observations. The formula for the loss function is:

[0139]

[0140] in, This is the loss value; The number of samples used to calculate the loss; The actual value; These are predicted values.

[0141] By iteratively optimizing the network weights through stochastic gradient descent (SGD) and after multiple training rounds (such as 1000 epochs), a target LSTM network that can accurately capture the changing patterns of storage load is obtained, and its output is the predicted value of future load.

[0142] Step E3: Obtain the predicted value samples output by the pre-trained Long Short-Term Memory network, and use the predicted value samples to pre-train the initial deep reinforcement learning layer to obtain the target deep reinforcement learning layer.

[0143] Specifically, the pre-trained LSTM network parameters are fixed, and its output load prediction value is combined with features such as real-time RBER and load type encoding to form a state vector, which is then input into the initial DQN network. DQN iteratively learns the optimal reserved space allocation strategy through Q-value analysis. The state space includes the predicted load, RBER, etc., and the action space is the reserved space (OP) adjustment step size (e.g., ±2%). An empirical replay mechanism is used to randomly sample state-action pairs from historical interaction data, updating the network parameters by minimizing the Q-value error (the mean squared error between the current Q-value and the target Q-value). After multiple training rounds (e.g., 5000 episodes), DQN learns to dynamically adjust the reserved space (OP) allocation based on the predicted load, resulting in the target deep reinforcement learning layer.

[0144] Step E4: Combine the target long short-term memory network and the target deep reinforcement learning layer to obtain a pre-trained target machine learning model.

[0145] The trained LSTM network is concatenated with the DQN network to form an LSTM-RL joint model: the LSTM layer receives historical load data and outputs predicted future load values; the DQN layer combines the predicted values ​​with real-time RBER and other state features to output the optimal reserved space allocation action (OP allocation action). During the online learning phase, the model receives new data every minute and fine-tunes the LSTM and DQN parameters through incremental learning to adapt to load changes. Hardware-assisted acceleration (such as NPU performing inference) enables real-time decision-making for dynamic reserved space allocation of virtual functions (VFs), improving system QoS stability.

[0146] As an example, in the actual training process, the system first collects storage load data such as IOPS, bandwidth, GC frequency, and RBER of each virtual function at a 1ms interval through the hardware monitoring engine. At the same time, it records the reserved space allocation ratio, NAND wear status, and other state values ​​at each sampling moment, thereby obtaining multiple sets of storage load data samples and their corresponding state value samples. Then, these samples are input into the initial long short-term memory network layer, and multiple rounds of iterative training are performed with mean squared error as the loss function to optimize the network weights and obtain the target long short-term memory network that can accurately predict future load trends. Next, the load prediction values ​​of the next 10ms output by the target long short-term memory network are combined with real-time RBER and other data and input into the initial deep reinforcement learning layer. The network parameters are updated iteratively using an experience replay mechanism and Q-value to train the target deep reinforcement learning layer that can output the optimal reserved space allocation action. Finally, the target long short-term memory network and the target deep reinforcement learning layer are combined to construct a pre-trained target machine learning model for subsequent dynamic reserved space resource allocation based on load prediction.

[0147] In the embodiments of this application, such as Figure 2 As shown, the architecture of the SSD dynamic reserved space allocation module consists of four core sub-modules, which work together to intelligently allocate and manage the reserved space:

[0148] Hardware monitoring engine: As the basic unit for data acquisition, it collects storage load data such as operating frequency (IOPS), bandwidth, garbage collection (GC) frequency, and raw bit error rate (RBER) of each virtual function (VF) in real time through dedicated hardware counters, DMA controllers, pin connections, and data capture before LDPC decoding, providing original basis for subsequent analysis and decision-making.

[0149] Machine learning dynamic prediction: It integrates a joint model (LSTM-DQN) that is pre-trained offline and fine-tuned online. It receives storage load data collected by the hardware monitoring engine, uses LSTM to mine time-dependent features to predict future load, and then uses DQN to learn the optimal reserved space allocation strategy to output dynamic adjustment instructions.

[0150] Dynamically Reserved Space Resource Pool: A logical structure consisting of a global resource pool and independent resource pools for each Virtual Function (VF). The global resource pool manages the physical block status through a global state mapping table (free block bitmap); the independent resource pools for each Virtual Function rely on a resource allocation linked list to record block capacity information, supporting dynamic allocation and reclamation of resources.

[0151] Resource scheduling execution module: Based on the reserved space allocation strategy dynamically predicted by machine learning, it operates on the physical block status of the dynamic reserved space resource pool. This includes selecting target physical blocks from the global resource pool, updating the resource allocation linked list and the global state mapping table, and completing scheduling actions such as resource expansion / shrinkage and cold data migration, thereby achieving dynamic adaptation of reserved space resources.

[0152] The dynamic reserved space allocation scheme in this application is implemented based on the NVMeSSD system architecture, such as... Figure 3 As shown, the components work together to support intelligent control of reserved space in multi-virtual-function (VF) scenarios. The architecture interaction logic is as follows:

[0153] Upper-layer interaction: Multiple virtual functions (VF_1~VF_N) and host physical functions (HOST_PF) connect to the NVMeSSD through the Virtual Machine Manager (VMM) and the PCIe bus to realize the issuance of storage requests and data interaction.

[0154] Hardware monitoring and data acquisition: The FPGA hardware monitoring engine configures a dedicated monitoring unit for each virtual function (VF) (such as "counter 0" and "configuration page 0" for VF_1), and collects storage load data such as IOPS, bandwidth, and RBER through state machines, timers, and error counters; the DMA module is responsible for data transmission between the virtual function (VF) and the namespace (NS_1~NS_N), opening up the load data acquisition channel.

[0155] Storage Core and Load Handling: The Flash Translation Layer (FTL) manages the logical-physical address mapping of the storage medium, and operations such as garbage collection (GC) trigger changes in load data; the "NAND Data and Management Unit" integrates the LSTM-DQN joint model, receives load data such as IOPS, bandwidth, and RBER, trains and outputs reserved space adjustment strategies.

[0156] Resource scheduling and execution: The resource scheduling module operates the reserved space resource pool (dynamic reserved space resource pool) according to the reserved space adjustment strategy, and allocates / reclaims physical blocks for the independent resource pools (VF_OP_1~VF_OP_N) of each virtual function (VF). By updating the resource allocation linked list and the global state mapping table, the dynamic adaptation of reserved space resources is realized.

[0157] In the embodiments of this application, such as Figure 4As shown, the logic of each step in the intelligent generation of reserved space allocation strategy by the machine learning dynamic prediction module is as follows: The hardware monitoring engine collects multi-dimensional storage load data (IOPS, bandwidth, GC frequency, RBER). After data preprocessing (standardization to eliminate dimensional differences, sliding window extraction of time-series features), combined with host load labels (random write / sequential read and other business modes), it is input into the LSTM prediction module to mine time-series dependencies and output the predicted values ​​of future IOPS and bandwidth. The predicted values ​​are used as state inputs to the DQN strategy decision module to learn and generate reserved space allocation adjustment actions. Finally, the resource scheduling execution module implements the strategy, completes the reserved space adjustment and cold data migration, and realizes dynamic adaptation of storage resources.

[0158] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0159] Embodiments of this application also provide a storage resource dynamic allocation device, such as... Figure 5 As shown, the device includes:

[0160] The acquisition module 51 is used to acquire the storage load data collected by each virtual function;

[0161] The generation module 52 is used to generate load prediction data based on storage load data, and determine the corresponding reserved space allocation strategy based on the load prediction data.

[0162] The adjustment module 53 is used to adjust the resource status of physical blocks in the dynamic reserved space resource pool according to the reserved space allocation strategy, so as to obtain the updated reserved space resource status.

[0163] Furthermore, the device also includes: a data acquisition module, used to configure a hardware counter for each virtual function, increment the count value when the input / output command is completed, and convert the count value into an operation frequency; monitor the amount of data transmitted within a time window and the number of times the garbage collection trigger signal is triggered, convert the amount of data transmitted into a bandwidth value, and use the number of triggers as the garbage collection frequency; acquire the raw data before channel decoding and the error correction data after channel decoding, calculate the corresponding raw bit error rate based on the raw data and error correction data; and construct storage load data using the operation frequency, bandwidth value, garbage collection frequency, and raw bit error rate.

[0164] Furthermore, the generation module 52 also includes: a first processing submodule and a second processing submodule;

[0165] The first processing submodule is used to obtain the historical storage load data and the corresponding historical state value of the previous time step; combine the storage load data with the historical storage load data to obtain the state control parameters; use the state control parameters to perform fusion calculation on the storage load data and the historical state value to obtain the current state value; and determine the corresponding load prediction data based on the current state value.

[0166] The second processing submodule is used to construct a state space based on load prediction data and preset load types; select an allocation ratio adjustment action that matches the state space from the preset action space, execute the allocation ratio adjustment action, and obtain feedback information; convert the feedback information into a strategy optimization signal, and use the strategy optimization signal to iteratively update the allocation ratio adjustment action until the feedback information meets the preset conditions, and obtain the reserved space allocation strategy.

[0167] Furthermore, the adjustment module 53 includes a third processing submodule, a fourth processing submodule, and a fifth processing submodule;

[0168] The third processing submodule is used to determine the amount of reserved space resources to be released based on the reserved space allocation strategy.

[0169] The fourth processing submodule is used to select a target physical block from the global state mapping table based on the amount of reserved space resources to be released;

[0170] The fifth processing submodule is used to remove the capacity information of the target physical block from the resource allocation chain and mark the target physical block as allocated in the global state mapping table.

[0171] Furthermore, the adjustment module 53 also includes a sixth processing submodule;

[0172] The sixth processing submodule is used to allocate multiple non-contiguous free physical blocks according to the number of physical blocks if there are no consecutive free physical blocks that meet the required number of physical blocks, and to use the non-contiguous free physical blocks as the target physical blocks.

[0173] Furthermore, the device also includes: a migration module, used to obtain the modification frequency of each data block in the independent resource pool; identify target data blocks whose modification frequency is less than a preset frequency threshold; and migrate the data in the target data blocks as cold data to the global resource pool.

[0174] Furthermore, the device also includes: a preprocessing module, used to perform a sliding window average calculation on the operating frequency, bandwidth value, garbage collection frequency and raw bit error rate to obtain initial storage load data; identify outliers in the storage load data, and perform filtering operations on the outliers in the storage load data to obtain storage load data.

[0175] Furthermore, the device also includes an input module for inputting storage load data into a pre-trained target machine learning model to obtain a reserved space allocation strategy.

[0176] Furthermore, the device also includes: a training module for acquiring storage load data samples and corresponding state value samples; pre-training an initial long short-term memory network layer using the storage load data samples and corresponding state value samples to obtain a target long short-term memory network; acquiring predicted value samples output by the pre-trained long short-term memory network and pre-training an initial deep reinforcement learning layer using the predicted value samples to obtain a target deep reinforcement learning layer; and combining the target long short-term memory network and the target deep reinforcement learning layer to obtain a pre-trained target machine learning model.

[0177] Embodiments of this application also provide an electronic device, such as... Figure 6 As shown, it includes a memory and a processor, the memory storing a computer program, and the processor being configured to run the computer program to perform the steps in any of the above embodiments of the dynamic allocation method for storage resources.

[0178] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the dynamic allocation method for storage resources when running.

[0179] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0180] The embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the dynamic allocation method for storage resources.

[0181] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described embodiments of the dynamic allocation method for storage resources.

[0182] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0183] The foregoing has provided a detailed description of the method, apparatus, computer equipment, and storage medium for dynamic allocation of storage resources provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this application without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this application.

Claims

1. A method for dynamically allocating storage resources, characterized in that, include: Obtain storage load data collected by each virtual function; Load prediction data is generated based on the storage load data, and a corresponding reserved space allocation strategy is determined based on the load prediction data. The resource status of physical blocks in the dynamic reserved space resource pool is adjusted according to the reserved space allocation strategy to obtain the updated reserved space resource status. The step of generating a load prediction value based on the storage load data includes: obtaining historical storage load data and corresponding historical state values ​​from the previous time step; combining the storage load data with the historical storage load data to obtain state control parameters; using the state control parameters to perform a fusion calculation on the storage load data and the historical state values ​​to obtain the current state value; and determining the corresponding load prediction data based on the current state value. After acquiring the storage load data collected by each virtual function, the method further includes: performing real-time feature enhancement processing on the storage load data using a hardware acceleration engine, wherein the hardware acceleration engine is integrated in an FPGA and includes a tensor accelerator and a real-time filtering module; the real-time feature enhancement processing on the storage load data using the hardware acceleration engine includes: inputting the raw data of operating frequency, bandwidth value, garbage collection frequency, and original bit error rate into the tensor accelerator, performing cross-dimensional weighted fusion through a hardware multiplier array in the FPGA, wherein the weight matrix is ​​dynamically updated by an online learning module according to different load scenarios; performing bandpass filtering on the fused data through a finite impulse response filter bank configured in the FPGA, wherein the cutoff frequency of the filter is dynamically adjusted according to the physical characteristics of the NAND flash memory; using a hardware-implemented principal component analysis dimensionality reduction algorithm, accelerating eigenvalue decomposition through a lookup table in the FPGA, compressing the 4-dimensional raw data into a 2-dimensional key feature vector to obtain compressed load feature data, wherein one dimension of the 2-dimensional key feature vector represents load intensity, which is positively correlated with operating frequency and bandwidth value, and the other dimension represents storage health, which is negatively correlated with original bit error rate and garbage collection frequency; The storage load data includes data of multiple preset load types, including operation frequency type, bandwidth type, garbage collection frequency type, and bit error rate type. The method for collecting the storage load data includes: configuring a hardware counter for each virtual function, incrementing the count value of the hardware counter when the input / output command is completed, and converting the count value into an operation frequency; monitoring the amount of data transmitted within a time window and the number of times the garbage collection trigger signal is triggered, converting the amount of data transmitted into a bandwidth value, and using the number of triggers as the garbage collection frequency; acquiring the raw data before channel decoding and the error correction data after channel decoding, calculating the corresponding raw bit error rate based on the raw data and the error correction data; and constructing storage load data using the operation frequency, the bandwidth value, the garbage collection frequency, and the raw bit error rate. The step of determining the corresponding reserved space allocation strategy based on the load prediction data includes: constructing a state space based on the load prediction data and a preset load type; selecting an allocation ratio adjustment action that matches the state space from a preset action space, executing the allocation ratio adjustment action, and obtaining feedback information; converting the feedback information into a strategy optimization signal, and using the strategy optimization signal to iteratively update the allocation ratio adjustment action until the feedback information meets a preset condition, thereby obtaining the reserved space allocation strategy. The dynamic reserved space resource pool includes a global resource pool and independent resource pools corresponding to each virtual function; the global resource pool is provided with a global state mapping table, which is used to record the state identifier of physical blocks; the independent resource pools corresponding to virtual functions are provided with resource allocation linked lists, which are used to record the capacity information of each physical block in the independent resource pools. The step of adjusting the resource status of physical blocks in the dynamic reserved space resource pool according to the reserved space allocation strategy to obtain the updated reserved space resource status includes: determining the amount of reserved space resources to be released according to the reserved space allocation strategy; selecting a target physical block from the global state mapping table based on the amount of reserved space resources to be released; removing the capacity information of the target physical block from the resource allocation chain, and marking the target physical block as allocated in the global state mapping table; The step of selecting a target physical block from the resource allocation list of the virtual function based on the amount of reserved space resources to be released includes: determining the number of physical blocks according to the amount of reserved space resources to be released; querying the global state mapping table for consecutive free physical blocks that meet the number of physical blocks, and using the consecutive free physical blocks as the target physical blocks; The method further includes: if there are no consecutive free physical blocks that meet the number of physical blocks, then allocate multiple non-consecutive free physical blocks according to the number of physical blocks, and use the non-consecutive free physical blocks as target physical blocks.

2. The method for dynamically allocating storage resources according to claim 1, characterized in that, The method further includes: Obtain the modification frequency of each data block in the independent resource pool; Identify target data blocks whose modification frequency is less than a preset frequency threshold; The data in the target data block is treated as cold data and migrated to the global resource pool.

3. The method for dynamically allocating storage resources according to claim 1, characterized in that, Before constructing storage load data using the operating frequency, the bandwidth value, the garbage collection frequency, and the raw bit error rate, the method further includes: The initial storage load data is obtained by performing a sliding window average calculation on the operating frequency, the bandwidth value, the garbage collection frequency, and the original bit error rate. Identify outliers in the storage load data and perform filtering operations on the outliers to obtain the storage load data.

4. The method for dynamically allocating storage resources according to claim 1, characterized in that, The method for determining the reserved space allocation strategy also includes: The storage load data is input into the pre-trained target machine learning model to obtain the reserved space allocation strategy; The training method for the target machine learning model includes: Obtain storage load data samples and corresponding status value samples; The initial long short-term memory network layer is pre-trained using the storage load data samples and the corresponding state value samples to obtain the target long short-term memory network. Obtain the predicted value samples output by the pre-trained long short-term memory network, and use the predicted value samples to pre-train the initial deep reinforcement learning layer to obtain the target deep reinforcement learning layer. The target long short-term memory network and the target deep reinforcement learning layer are combined to obtain a pre-trained target machine learning model.

5. A storage resource dynamic allocation device, characterized in that, include: The acquisition module is used to acquire storage load data collected by each virtual function; The generation module is used to generate load prediction data based on the storage load data, and determine the corresponding reserved space allocation strategy based on the load prediction data. The adjustment module is used to adjust the resource status of physical blocks in the dynamic reserved space resource pool according to the reserved space allocation strategy, so as to obtain the updated reserved space resource status. The acquisition module is used to perform real-time feature enhancement processing on storage load data using a hardware acceleration engine. The hardware acceleration engine is integrated into an FPGA and includes a tensor accelerator and a real-time filtering module. The real-time feature enhancement processing of storage load data using the hardware acceleration engine includes: inputting raw data (operation frequency, bandwidth value, garbage collection frequency, and original bit error rate) into the tensor accelerator; performing cross-dimensional weighted fusion through a hardware multiplier array within the FPGA, where the weight matrix is ​​dynamically updated by an online learning module according to different load scenarios; performing bandpass filtering on the fused data using a finite impulse response filter bank configured in the FPGA, where the filter cutoff frequency is dynamically adjusted based on the physical characteristics of the NAND flash memory; and using a hardware-implemented principal component analysis dimensionality reduction algorithm, accelerating eigenvalue decomposition through a lookup table within the FPGA, compressing the 4-dimensional raw data into a 2-dimensional key feature vector to obtain compressed load feature data. In this 2-dimensional key feature vector, one dimension represents load intensity, positively correlated with operation frequency and bandwidth value, and the other dimension represents storage health, negatively correlated with original bit error rate and garbage collection frequency. The device further includes: a data acquisition module, configured to configure a hardware counter for each virtual function, increment the count value using the hardware counter when the input / output command is completed, and convert the count value into an operation frequency; monitor the amount of transmitted data and the number of times the garbage collection trigger signal is triggered within a time window, convert the amount of transmitted data into a bandwidth value, and use the number of triggers as the garbage collection frequency; acquire the raw data before channel decoding and the error correction data after channel decoding, calculate the corresponding raw bit error rate based on the raw data and the error correction data; and construct storage load data using the operation frequency, the bandwidth value, the garbage collection frequency, and the raw bit error rate. The generation module further includes: a first processing submodule and a second processing submodule; The first processing submodule is used to acquire historical storage load data and corresponding historical state values ​​from the previous time step; combine the storage load data with the historical storage load data to obtain state control parameters; use the state control parameters to perform fusion calculation on the storage load data and the historical state values ​​to obtain the current state value; and determine the corresponding load prediction data based on the current state value. The second processing submodule is used to construct a state space based on the load prediction data and the preset load type; select an allocation ratio adjustment action that matches the state space from the preset action space, execute the allocation ratio adjustment action, and obtain feedback information; convert the feedback information into a strategy optimization signal, and use the strategy optimization signal to iteratively update the allocation ratio adjustment action until the feedback information meets the preset conditions, and obtain the reserved space allocation strategy. The dynamic reserved space resource pool includes a global resource pool and independent resource pools corresponding to each virtual function; the global resource pool is provided with a global state mapping table, which is used to record the state identifier of physical blocks; the independent resource pools corresponding to virtual functions are provided with resource allocation linked lists, which are used to record the capacity information of each physical block in the independent resource pools. The adjustment module includes: The third processing submodule is used to determine the amount of reserved space resources to be released according to the reserved space allocation strategy. The fourth processing submodule is used to select a target physical block from the global state mapping table based on the amount of reserved space resources to be released; The fifth processing submodule is used to remove the capacity information of the target physical block from the resource allocation chain and mark the target physical block as allocated in the global state mapping table; The step of selecting a target physical block from the resource allocation list of the virtual function based on the amount of reserved space resources to be released includes: determining the number of physical blocks according to the amount of reserved space resources to be released; querying the global state mapping table for consecutive free physical blocks that meet the number of physical blocks, and using the consecutive free physical blocks as the target physical blocks; The adjustment module further includes: The sixth processing submodule is used to allocate multiple non-contiguous free physical blocks according to the number of physical blocks if there are no consecutive free physical blocks that meet the required number of physical blocks, and to use the non-contiguous free physical blocks as target physical blocks.

6. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor for executing a computer program to implement the steps of the dynamic allocation method for storage resources as described in any one of claims 1 to 4.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, it implements the steps of the dynamic allocation method for storage resources as described in any one of claims 1 to 4.

8. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, it implements the steps of the dynamic allocation method for storage resources as described in any one of claims 1 to 4.

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