Register verification method of system-on-chip and related equipment

Abstract

The invention provides a register verification method of a system-on-chip and related equipment, and relates to the field of chip verification. The method comprises the following steps: acquiring an original register form of a to-be-tested system-on-chip; wherein the original register form comprises configuration parameters of all registers in the to-be-tested system-on-chip. And analyzing the original register form to generate a first register test form, and generating a system-level verification case for verifying all registers in the to-be-tested system-level chip according to the first register test form. And importing the system-level verification case into a central processing unit in the to-be-tested system-level chip, so that the central processing unit traverses all registers in the to-be-tested system-level chip according to the system-level verification case and verifies the registers. According to the register verification method for the system-on-chip, the register verification efficiency of the system-on-chip can be improved, the verification completeness can be improved, and errors and omission are prevented.

Description

Technical Field

[0001] The present invention relates to the technical field of chip verification, and more particularly, to a method for verifying registers of a system-on-chip and related devices. Background Art

[0002] During the chip verification process, the verification of registers ranks at the top of the verification list. Because only by first ensuring the correct function of the registers can it be ensured that the communication between hardware and hardware is "semantically consistent". If the register configuration result is different from the register configuration content, then the hardware cannot work in the desired mode, and at the same time, the register may not be able to correctly reflect the state of the hardware.

[0003] However, the number of registers in a large-scale system-on-chip (SOC) is huge, and the difficulty in verifying registers lies in how to traverse each register without dead ends for verification. Especially in the system-level verification stage, for a peripheral device to be controlled, it usually requires the central processing unit (CPU) to operate related registers, and this process involves the collaborative work of multiple modules.

[0004] Currently, the methods for register verification mainly include manual verification method and Universal Verification Methodology (UVM) register model method. The manual verification method means that the verification personnel parse out information such as the read / write attributes and reset values of each field segment of the register one by one according to the register form. In the case of a large number of registers, a large amount of code needs to be written manually for verification, which consumes the energy and time of the verification personnel and has low verification efficiency.

[0005] In an actual chip, various read / write operations on the registers are controlled by the CPU, which involves complex instruction sets and execution processes. The UVM register model method usually simulates the read / write behavior of the registers themselves, rather than the entire control logic of the CPU. Especially in a system-level verification environment, the UVM register model cannot comprehensively verify the registers, and the verification coverage rate is relatively low, which may lead to omission of defects. Moreover, the simulation memory load of the UVM register model is large, which not only slows down the verification speed but also causes a memory overflow error in the verification tool, thus terminating the verification process.

[0006] Therefore, how to perform efficient and comprehensive register verification on a system-on-chip is a technical problem that needs to be solved urgently by those skilled in the art. Summary of the Invention

[0007] The purpose of the present invention is to provide a method for verifying registers of a system-on-chip to perform efficient and comprehensive register verification on a system-on-chip.

[0008] To achieve the above object, the technical solution adopted by the present invention is as follows: The present invention provides a method for verifying registers of a system-on-chip, and the method includes: Obtaining an original register form of the system-on-chip to be tested; wherein, the original register form includes configuration parameters of all registers in the system-on-chip to be tested; Parsing the original register form to generate a first register test form, and generating a system-level verification case for verifying all registers in the system-on-chip to be tested according to the first register test form; Importing the system-level verification case into a central processing unit in the system-on-chip to be tested, so that the central processing unit traverses and verifies all registers in the system-on-chip to be tested according to the system-level verification case.

[0009] Optionally, the step of parsing the original register form to generate a first register test form, and generating a system-level verification case for verifying all registers in the system-on-chip to be tested according to the first register test form includes: Generating a first register transition form according to a preset test value and configuration parameters of each register in the original register form; wherein, the configuration parameters of the register include the address, name, bit field, read / write attribute, and first reset value of the register; Converting data in the first register transition form according to the bit width of the register, and generating the first register test form according to the configuration parameters of each register in the original register form; Obtaining a verification case template file, and generating the system-level verification case according to the first register test form and the verification case template file; wherein, the verification case template file is a code template for verifying the reset value and read / write of a single register.

[0010] Optionally, the step of generating a first register transition form according to a preset test value and configuration parameters of each register in the original register form includes: Copying data in the address column, name column, bit field column, and read / write attribute column of the original register form, and creating blank second reset value column, first write value column, and first expected value column to obtain a second register transition form; Converting multiple first reset values in the first reset value column of the original register form into second reset values in binary format, and sequentially filling the multiple second reset values into the second reset value column of the second register transition form; Convert the preset test value into a binary number, intercept the binary preset test value according to the bit width of each bit field in the second register transition form to obtain a first write value, and sequentially fill the multiple first write values into the first write value column of the second register transition form; Determine the data in the first expected value column based on the data in the first write value column, the data in the second reset value column, and the read / write attribute of the corresponding bit field, to obtain the first register transition form.

[0011] Optionally, the step of determining the data in the first expected value column based on the data in the first write value column, the data in the second reset value column, and the read / write attribute of the corresponding bit field includes: If the read / write attribute of the bit field is readable and writable, determine that the first expected value corresponding to the bit field is the same as the first write value corresponding to the bit field; If the read / write attribute of the bit field is readable but not writable, determine that the first expected value corresponding to the bit field is the same as the second reset value corresponding to the bit field.

[0012] Optionally, the step of converting the data in the first register transition form according to the bit width of the register and generating the first register test form according to the configuration parameters of each register in the original register form includes: Copy the data in the address column and name column of the original register form, and create blank columns for the fourth reset value, the third write value, and the third expected value to obtain a second register test form; Connect the binary numbers in the second reset value column of the first register transition form end to end row by row to obtain a third reset value, crop the third reset value at intervals of the bit width of each register to obtain the fourth reset value of each register, convert the binary fourth reset value into hexadecimal and sequentially fill it into the fourth reset value column of the second register test form; Connect the binary numbers in the first write value column of the first register transition form end to end row by row to obtain a second write value, crop the second write value at intervals of the bit width of each register to obtain the third write value of each register, convert the binary third write value into hexadecimal and sequentially fill it into the third write value column of the second register test form; Connect the binary numbers in the first expected value column of the first register transition form end to end row by row to obtain a second expected value, crop the second expected value at intervals of the bit width of each register to obtain the third expected value of each register, convert the binary third expected value into hexadecimal and sequentially fill it into the third expected value column of the second register test form to obtain the first register test form.

[0013] Optionally, the step of importing the system-level verification use cases into the central processing unit in the system-level chip to be tested, so that the central processing unit traverses all registers in the system-level chip to be tested according to the system-level verification use cases and performs verification includes: The central processing unit reads the actual reset value of the register, and compares the actual reset value with the fourth reset value corresponding to the register at the same address in the first register test form, so as to perform register reset value verification; The central processing unit writes the third write value in the first register test form into the register at the corresponding address, reads the actual write value of the register, and compares the actual write value with the third expected value corresponding to the register at the same address in the first register test form, so as to perform register read / write verification.

[0014] Optionally, during the process of parsing the original register form to generate the system-level verification use cases, if an error reporting signal is received, it is determined that the format of the original register form is incorrect.

[0015] The present invention has the following beneficial effects compared with the prior art: The present invention provides a method for verifying registers of a system-level chip. Based on the original register form of the entire system-level chip to be tested, the present invention automatically generates system-level verification use cases that traverse all registers in the original register form, without the need for verification personnel to manually write code, improving the verification efficiency. Since the content of the generated system-level verification use cases is derived from the original register form, the content of the system-level verification use cases is strictly synchronized with the original register form, and the method provided by the present invention is not prone to errors, improving the verification accuracy.

[0016] Moreover, in the system-level verification stage, accessing and verifying registers through the central processing unit is more in line with the actual working process of the chip. Compared with the prior art, by importing the system-level verification use cases into the central processing unit in the system-level chip to be tested, the central processing unit traverses all registers in the system-level chip to be tested according to the system-level verification use cases and performs verification, which can verify multiple-layer bus paths, is beneficial to the improvement of coverage, can more comprehensively verify each register in the system-level verification stage, improves the verification completeness, and prevents error omission. Description of the Drawings

[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0018] Figure 1 Schematic flowchart of a method for verifying registers of a system-on-chip provided by the present invention; Figure 2 Schematic diagram of sub-steps of step 200 in the present invention; Figure 3 Schematic principle diagram of a method for verifying registers of a system-on-chip provided by the present invention; Figure 4 Schematic diagram of sub-steps of step 210 in the present invention; Figure 5 Schematic diagram of sub-steps of step 220 in the present invention; Figure 6 Schematic diagram of sub-steps of step 300 in the present invention; Figure 7 Schematic structural diagram of a device for verifying registers of a system-on-chip provided by the present invention.

[0019] Reference numerals: 10 - Device for verifying registers of a system-on-chip; 11 - Acquisition module; 12 - Generation module; 13 - Verification module. Detailed implementation manners

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, but not all, of the embodiments of the present invention. Components of the embodiments of the present invention described and illustrated in the accompanying drawings here can be arranged and designed in various different configurations.

[0021] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the claimed present invention, but merely represents selected embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative efforts fall within the scope of protection of the present invention.

[0022] In the description of the present invention, it should be noted that the terms "first" and "second" and the like are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device.

[0023] Some embodiments of the present invention are described in detail below in conjunction with the accompanying drawings. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0024] As mentioned in the background technology, there are currently two main register verification methods for system-level chips: one is the manual verification method, which requires verification personnel to manually write a large amount of verification code, which not only has low verification efficiency, but is also prone to errors, resulting in low accuracy.

[0025] The other is the UVM register model method, which has the following disadvantages: (1) Low verification coverage and completeness. In actual chips, various read and write operations on registers are controlled by the CPU, involving complex instruction sets and execution processes. The UVM register model method usually simulates the read and write behavior of the register itself, rather than the control logic of the entire CPU. Especially in the system-level verification environment, the UVM register model cannot fully verify the registers, and the verification coverage is low, which may lead to defects being missed.

[0026] (2) The simulation memory load is large and the verification efficiency is low. In large-scale system-level chips, the simulation memory load of the UVM register model is large, which not only slows down the verification speed, but also causes the verification tool to have a memory overflow error, thereby terminating the verification process. In addition, in the UVM register model, a class object is created for each bit field. Since the register information is solidified during the compilation stage, once there is a change (changing the configuration value of a register, etc.), the verification platform needs to be recompiled, which consumes time.

[0027] Therefore, how to perform efficient and comprehensive register verification on a system-level chip is a technical problem that needs to be solved urgently by those skilled in the art.

[0028] To solve the above technical problems, please refer to Figure 1 The embodiment of the present invention provides a register verification method for a system-on-chip, the method comprising the following steps: Step 100: Obtain an original register table of the system-level chip under test.

[0029] The SOC chip integrates multiple functional modules, and each functional module requires multiple registers for configuration and status monitoring. A typical SOC chip may contain tens of thousands of registers. To verify all the registers in the SOC chip, it is necessary to obtain the original register form of the SOC chip to be tested. Among them, the original register form contains the configuration parameters of all the registers in the system-on-chip to be tested.

[0030] Step 200: Parse the original register form to generate a first register test form, and generate system-level verification cases for verifying all the registers in the system-on-chip to be tested according to the first register test form.

[0031] Step 300: Import the system-level verification cases into the central processing unit in the system-on-chip to be tested, so that the central processing unit traverses and verifies all the registers in the system-on-chip to be tested according to the system-level verification cases.

[0032] Based on the above steps, the present invention is based on the original register form of the entire system-on-chip to be tested, automatically generates system-level verification cases that traverse all the registers in the original register form, without the need for verification personnel to manually write code, greatly reducing the workload of verification personnel and improving the verification efficiency.

[0033] Moreover, since the content of the generated system-level verification cases comes from the original register form, the content of the system-level verification cases is strictly synchronized with the original register form. Compared with the verification personnel manually writing code, the method provided by the present invention is not prone to errors and improves the verification accuracy.

[0034] In addition, in the system-level verification environment of the SOC chip, accessing and verifying registers through the central processing unit is more in line with the actual working process of the chip. Compared with the existing UVM register model method, the present invention imports the system-level verification cases into the central processing unit in the system-on-chip to be tested, so that the central processing unit traverses and verifies all the registers in the system-on-chip to be tested according to the system-level verification cases, can verify multiple layers of bus paths, is beneficial to the improvement of coverage, can more comprehensively verify each register in the system-level verification stage, improves the verification completeness, and prevents error omission. At the same time, it also avoids the problem of large simulation memory load caused by verifying registers with the UVM register model.

[0035] To better understand the technical solution of the present invention, please refer to Figure 2 , and the following will first describe the specific steps of generating system-level verification cases according to the original register form.

[0036] That is, step 200 of parsing the original register form to generate the first register test form and generating system-level verification test cases for verifying all registers in the system-on-chip to be tested according to the first register test form includes the following steps: Step 210: Generate a first register transition form according to the preset test value and the configuration parameters of each register in the original register form.

[0037] Among them, the configuration parameters of the register include the address, name, bit field, first reset value, and read / write attribute of the register.

[0038] Exemplarily, assume that the original register form of the system-on-chip to be tested is as shown in Table 1.

[0039] Table 1 Original Register Form

[0040] As can be seen from Table 1, the system-on-chip to be tested includes two registers, namely REG1 with an address of 0x0004 and REG2 with an address of 0x0008. Among them, the bit widths of REG1 and REG2 are both 32 bits, and REG1 includes 4 bit fields with a bit width of 8 bits each, and REG2 includes 2 bit fields with a bit width of 16 bits each.

[0041] In addition, R / W indicates that the read / write attribute of the corresponding bit field is readable and writable, and RO indicates that the read / write attribute of the corresponding bit field is readable but not writable.

[0042] It should be noted that a bit field is a subfield in a register, which is used to configure and read a specific part of the register to achieve fine control of the hardware function. A bit field can be a single bit or multiple consecutive bits. The sum of the bit widths of all bit fields in a register is the bit width of the register.

[0043] Step 220: Convert the data in the first register transition form according to the bit width of the register, and generate a first register test form according to the configuration parameters of each register in the original register form.

[0044] Step 230: Obtain a verification test case template file, and generate system-level verification test cases according to the first register test form and the verification test case template file.

[0045] Among them, the verification test case template file is a code template pre-written by the verification personnel for verifying a register, and the template content includes a reset value verification part, a read / write verification part, and a comparison part.

[0046] In the embodiment of the present invention, the entire register verification process is as shown in Figure 3As shown, the present invention parses the original register form of the system-on-chip (SoC) to be tested to generate a first register test form, and then automatically generates a system-level verification case capable of verifying all registers in the SoC to be tested according to the first register test form and the verification case template file.

[0047] During the process of importing the system-level verification case into the CPU, in order to enable the CPU to better recognize the content in the system-level verification case. Optionally, the code in the system-level verification case can be first compiled into a bin file (i.e., binary file) that can be recognized by the CPU using a programming language environment (such as a C language environment), and then the bin file can be loaded into the CPU in the SoC to be tested in the form of firmware.

[0048] The CPU traverses and verifies all registers in the SoC to be tested in the form of a bus according to the system-level verification case.

[0049] By verifying all registers in the SoC to be tested through the CPU, the integrity and correctness of multiple-layer bus paths can be effectively covered, thereby improving the completeness of register verification.

[0050] Specifically, the instructions issued by the CPU according to the system-level verification case are first transmitted to the AHB bus, and the instructions are passed to the AHB matrix by virtue of the high-speed transmission characteristics of the AHB bus, and it schedules and distributes the instructions. Then, the AHB bus protocol is converted into the APB bus protocol through the AHB-APB bridge to adapt to the communication requirements of the peripherals, and finally the verification of the peripheral registers is realized.

[0051] That is to say, the instructions issued by the CPU according to the system-level verification case need to go through multiple levels such as the AHB bus, the AHB matrix, the AHB-APB bridge, and the APB bus before finally accessing the peripheral registers. This process involves multiple key links such as bus protocol conversion, address decoding, timing management, and data transmission.

[0052] By directly verifying the registers through the CPU, the following can be verified: First, whether the high-speed transmission characteristics of the AHB bus can correctly transmit instructions to ensure the integrity and consistency of data in a high-speed environment. Second, whether the scheduling and distribution function of the AHB matrix can correctly route requests according to the address to verify the concurrent access ability between multiple master devices and multiple slave devices. Third, whether the protocol conversion function of the AHB-APB bridge can accurately adapt the high-speed protocol of the AHB to the low-speed protocol of the APB and correctly handle timing and address mapping. Finally, whether the APB bus can correctly transmit instructions to the peripheral registers and return the expected response data.

[0053] Through this verification method, not only can the functions of the registers themselves be ensured to be correct, but also all levels of the entire bus path can be covered, enabling the verification of multi-level bus paths, which is beneficial to the improvement of code coverage. During the system-level verification phase, various registers can be more comprehensively verified, improving the verification completeness and preventing the omission of errors.

[0054] In addition, it should be noted that the system-level verification test cases of the present invention are generated based on the first register test form and the verification test case template file, and the first register transition form is involved in the generation process of the first register test form. To better understand the overall process of generating the system-level verification test cases, the generation process of the first register transition form will be described below.

[0055] Please refer to Figure 4 , step 210 of generating the first register transition form according to the preset test values and the configuration parameters of each register in the original register form includes the following steps: Step 211: Copy the data in the address column, name column, bit field column, and read / write attribute column of the original register form, and create blank columns for the second reset value, the first write value, and the first expected value to obtain the second register transition form.

[0056] Exemplarily, taking the original register form shown in Table 1 as an example, the second register transition form is shown in Table 2.

[0057] Table 2 Second register transition form

[0058] Step 212: Convert the multiple first reset values in the first reset value column of the original register form into second reset values in binary format, and sequentially fill the multiple second reset values into the second reset value column of the second register transition form.

[0059] Step 213: Convert the preset test value into a binary number, intercept the binary preset test value according to the bit width of each bit field in the second register transition form to obtain the first write value, and sequentially fill the multiple first write values into the first write value column of the second register transition form.

[0060] Exemplarily, assuming that the preset test value to be written is 0x5a5a5a5a, converting this preset test value into a binary number is 01011010010110100101101001011010.

[0061] It should be noted that the present invention does not limit the specific value of the preset test value, that is, the preset test value is flexible and variable.

[0062] Since the bit widths of the 4 bit fields in register REG1 in the second register transition form shown in Table 2 are all 8 bits, and the bit widths of the 2 bit fields in register REG2 are all 16 bits.

[0063] Therefore, the first write value corresponding to each bit field of REG1 is 01011010, and the first write value corresponding to each bit field of REG2 is 0101101001011010.

[0064] Step 214: Determine the data in the first expected value column based on the data in the first write value column, the data in the second reset value column, and the read / write attributes of the corresponding bit fields, to obtain the first register transition form.

[0065] Specifically, if the read / write attribute of a bit field is read / write, it is determined that the first expected value corresponding to this bit field is the same as the first write value corresponding to this bit field.

[0066] If the read / write attribute of a bit field is read-only, it is determined that the first expected value corresponding to this bit field is the same as the second reset value corresponding to this bit field.

[0067] For example, the read / write attribute of bit field [31:16] of register REG2 in Table 2 is R / W, indicating that this bit field is read / write. Then, the first expected value corresponding to bit field [31:16] is the same as the first write value, both being 0101101001011010.

[0068] The read / write attribute of bit field [15:0] of REG2 is RO, indicating that this bit field is read-only. Then, the first expected value corresponding to bit field [15:0] is the same as the second reset value, both being 1111111100000000.

[0069] After the above steps 211 to 214, the first register transition form shown in Table 3 is obtained.

[0070] Table 3 First register transition form

[0071] After obtaining the first register transition form, it is also necessary to convert the data in the first register transition form to obtain the first register test form.

[0072] Please refer to Figure 5 , the steps 220 of converting the data in the first register transition form according to the bit width of the register and generating the first register test form according to the configuration parameters of each register in the original register form include the following steps: Step 221: Copy the data in the address column and name column of the original register form, and create blank columns for the fourth reset value, the third write value, and the third expected value to obtain the second register test form.

[0073] Exemplarily, taking the original register form shown in Table 1 as an example, the second register test form is shown in Table 4.

[0074] Table 4 Second Register Test Form

[0075] Step 222: Concatenate the binary numbers in the second reset value column of the first register transition form row by row from beginning to end to obtain the third reset value. Cut the third reset value at intervals of the bit width of each register to obtain the fourth reset value for each register. Convert the binary fourth reset value to hexadecimal and fill it into the fourth reset value column of the second register test form in sequence.

[0076] Step 223: Concatenate the binary numbers in the first write value column of the first register transition form row by row from beginning to end to obtain the second write value. Cut the second write value at intervals of the bit width of each register to obtain the third write value for each register. Convert the binary third write value to hexadecimal and fill it into the third write value column of the second register test form in sequence.

[0077] Step 224: Concatenate the binary numbers in the first expected value column of the first register transition form row by row from beginning to end to obtain the second expected value. Cut the second expected value at intervals of the bit width of each register to obtain the third expected value for each register. Convert the binary third expected value to hexadecimal and fill it into the third expected value column of the second register test form in sequence to obtain the first register test form.

[0078] For better understanding, the following takes the first register transition form shown in Table 3 as an example for illustration.

[0079] Concatenate the binary numbers in the second reset value column of the first register transition form row by row from beginning to end to obtain a 64-bit third reset value: 11111111 00000000 11111111 00000000 11111111 00000000 11111111 00000000.

[0080] Concatenate the binary numbers in the first write value column of the first register transition form row by row from beginning to end to obtain a 64-bit second write value: 01011010 01011010 01011010 01011010 01011010 01011010 01011010 01011010.

[0081] Concatenate the binary numbers in the first expected value column of the first register transition form row by row from beginning to end to obtain a 64-bit second expected value: 01011010 01011010 01011010 01011010 01011010 01011010 11111111 00000000.

[0082] Since the bit widths of register REG1 and register REG2 are both 32 bits, the fourth reset values of the corresponding binaries of REG1 and REG2 are both 11111111 00000000 11111111 00000000. After converting the binary to hexadecimal, the fourth reset values corresponding to REG1 and REG2 are both 0xff00ff00.

[0083] The third write values of the corresponding binaries of REG1 and REG2 are both 01011010 01011010 01011010 01011010. After converting the binary to hexadecimal, the third reset values corresponding to REG1 and REG2 are both 0x5a5a5a5a.

[0084] The third expected value of the binary corresponding to REG1 is 01011010 01011010 01011010 01011010. After converting the binary to hexadecimal, the third expected value corresponding to REG1 is 0x5a5a5a5a.

[0085] The third expected value of the binary corresponding to REG2 is 01011010 01011010 11111111 00000000. After converting the binary to hexadecimal, the third expected value corresponding to REG2 is 0x5a5aff00.

[0086] After the above steps 221 to 224, the first register test form as shown in Table 5 is obtained.

[0087] Table 5 First register test form

[0088] Based on the first register test form and the pre-written verification test case template file, system-level verification test cases can be automatically generated. Among them, the system-level verification test cases include the code for verifying the reset values and read / write operations of all registers in the system-level chip under test.

[0089] Please refer to Figure 6Step 300 of importing system-level verification test cases into the central processing unit in the to-be-tested system-level chip, so that the central processing unit traverses all registers in the to-be-tested system-level chip according to the system-level verification test cases and performs verification, includes the following steps: Step 310: The central processing unit reads the actual reset value of the register, and compares the actual reset value with the fourth reset value corresponding to the register at the same address in the first register test form, so as to verify the register reset value.

[0090] Taking the first register test form shown in Table 5 as an example, if the actual reset value of the register REG1 with the address of 0x004 read by the central processing unit is 0xff00ff00, that is, the actual reset value of REG1 is the same as the fourth reset value of REG1, it is determined that the actual reset value of REG1 is normal. On the contrary, if the actual reset value of REG1 is different from the fourth reset value of REG1, it is determined that the actual reset value of REG1 is abnormal.

[0091] Step 320: The central processing unit writes the third write value in the first register test form into the register at the corresponding address, reads the actual write value of the register, and compares the actual write value with the third expected value corresponding to the register at the same address in the first register test form, so as to verify the register read and write.

[0092] Exemplarily, according to the first register test form shown in Table 5, the central processing unit writes the third write value 0x5a5a5a5a into the register REG2 with the address of 0x008, and reads the actual write value of REG2.

[0093] If the actual write value of REG2 is 0x5a5aff00, that is, the actual write value of REG2 is the same as the third expected value of REG2, it is determined that the read and write of REG2 are normal. On the contrary, if the actual write value of REG2 is different from the third expected value of REG2, it is determined that the read and write of REG2 are abnormal.

[0094] In the embodiment of the present invention, based on the original register form of the to-be-tested system-level chip, system-level verification test cases for verifying the reset values and read and write of all registers in the to-be-tested system-level chip can be quickly generated. Moreover, during the process of parsing the original register form to generate system-level verification test cases, if a error reporting signal is received, it is determined that the format of the original register form is incorrect, and the format of the original register form can be checked in reverse, which provides a guarantee for the accurate delivery of the original register form.

[0095] Based on the above implementation manner, please refer to Figure 7 , the embodiment of the present invention further provides a register verification device 10 for a system-level chip, including: An acquisition module 11 for acquiring the original register form of the system-on-chip to be tested. The original register form includes the configuration parameters of all registers in the system-on-chip to be tested.

[0096] A generation module 12 for parsing the original register form to generate a first register test form, and generating system-level verification test cases for verifying all registers in the system-on-chip to be tested according to the first register test form.

[0097] A verification module 13 for importing the system-level verification test cases into the central processing unit in the system-on-chip to be tested, so that the central processing unit traverses all registers in the system-on-chip to be tested according to the system-level verification test cases and performs verification.

[0098] Optionally, an embodiment of the present invention further provides an electronic device, including a processor and a memory. The memory stores a program that can be executed by the processor, and the processor can execute the program to implement the register verification method of the system-on-chip described in any one of the foregoing embodiments.

[0099] Optionally, an embodiment of the present invention further provides a storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the register verification method of the system-on-chip described in any one of the foregoing embodiments.

[0100] In summary, the present invention provides a register verification method and related devices for a system-on-chip. Based on the original register form of the entire system-on-chip to be tested, the present invention automatically generates system-level verification test cases that traverse all registers in the original register form, and the preset test values are flexibly variable. There is no need for verification personnel to manually write code, which improves the verification efficiency. Since the content of the generated system-level verification test cases comes from the original register form, the content of the system-level verification test cases is strictly synchronized with the original register form. Compared with the method of manually writing code by verification personnel, the method provided by the present invention is not prone to errors and improves the verification accuracy. Moreover, during the process of parsing the original register form to generate system-level verification test cases, if a error signal is received, it is determined that the format of the original register form is incorrect, which can inversely check the format of the original register form, providing guarantee for the accurate delivery of the original register form.

[0101] In the system-level verification environment of the SOC chip, accessing and verifying registers through the CPU is more in line with the actual working process of the chip. Compared with the UVM register model method of the prior art, in the present invention, system-level verification test cases are imported into the CPU of the system-level chip to be tested, so that the CPU traverses and verifies all registers in the system-level chip to be tested according to the system-level verification test cases, and can verify multi-layer bus paths, which is beneficial to the improvement of coverage rate. In the system-level verification stage, each register can be more comprehensively verified, the verification completeness is improved, and error omission is prevented.

[0102] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

[0103] For those skilled in the art, it is obvious that the present invention is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention, the present invention can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention is defined by the appended claims rather than the above description. Therefore, it is intended to embrace all changes falling within the meaning and scope of the equivalent elements of the claims in the present invention. Any reference signs in the claims should not be regarded as limiting the claims involved.

Claims

1. A register verification method for a system-on-chip, characterized in that, The register verification method for the system-on-chip includes: Obtain the original register form of the system-on-chip to be tested; wherein, the original register form contains the configuration parameters of all registers in the system-on-chip to be tested; Parse the original register form to generate a first register test form, and generate a system-level verification case for verifying all registers in the system-on-chip to be tested according to the first register test form; Import the system-level verification case into the central processing unit in the system-on-chip to be tested, so that the central processing unit traverses and verifies all registers in the system-on-chip to be tested according to the system-level verification case.

2. The register verification method for a system-on-chip according to claim 1, wherein The steps of parsing the original register form to generate a first register test form and generating a system-level verification case for verifying all registers in the system-on-chip to be tested according to the first register test form include: Generate a first register transition form according to the preset test value and the configuration parameters of each register in the original register form; wherein, the configuration parameters of the register include the address, name, bit field, read / write attribute, and first reset value of the register; Convert the data in the first register transition form according to the bit width of the register, and generate the first register test form according to the configuration parameters of each register in the original register form; Obtain a verification case template file, and generate the system-level verification case according to the first register test form and the verification case template file; wherein, the verification case template file is a code template for verifying the reset value and read / write of a single register.

3. The register verification method for the system-on-chip according to claim 2, wherein The steps of generating a first register transition form according to the preset test value and the configuration parameters of each register in the original register form include: Copy the data in the address column, name column, bit field column, and read / write attribute column of the original register form, and create blank second reset value column, first write value column, and first expected value column to obtain a second register transition form; Convert the multiple first reset values in the first reset value column of the original register form into second reset values in binary format, and fill the multiple second reset values into the second reset value column of the second register transition form in sequence; Convert the preset test value into a binary number, intercept the binary preset test value according to the bit width of each bit field in the second register transition form to obtain a first write value, and fill the multiple first write values into the first write value column of the second register transition form in sequence; Determine the data in the first expected value column according to the data in the first write value column, the data in the second reset value column, and the read / write attribute of the corresponding bit field to obtain the first register transition form.

4. The register verification method for the system-on-chip according to claim 3, wherein The steps of determining the data in the first expected value column according to the data in the first write value column, the data in the second reset value column, and the read / write attribute of the corresponding bit field include: If the read / write attribute of the bit field is readable and writable, determine that the first expected value corresponding to the bit field is the same as the first write value corresponding to the bit field; If the read / write attribute of the bit field is readable but not writable, it is determined that the first expected value corresponding to the bit field is the same as the second reset value corresponding to the bit field.

5. The method for verifying registers of a system-on-chip according to claim 3, wherein The steps of converting the data in the first register transition form according to the bit width of the register and generating the first register test form according to the configuration parameters of each register in the original register form include: Copy the data in the address column and name column of the original register form, and create blank columns for the fourth reset value, the third write value, and the third expected value to obtain a second register test form; Connect the binary numbers in the second reset value column of the first register transition form row by row end to end to obtain a third reset value. Cut the third reset value step by step according to the bit width of each register to obtain the fourth reset value of each register. Convert the binary fourth reset value to hexadecimal and fill it into the fourth reset value column of the second register test form in sequence; Connect the binary numbers in the first write value column of the first register transition form row by row end to end to obtain a second write value. Cut the second write value step by step according to the bit width of each register to obtain the third write value of each register. Convert the binary third write value to hexadecimal and fill it into the third write value column of the second register test form in sequence; Connect the binary numbers in the first expected value column of the first register transition form row by row end to end to obtain a second expected value. Cut the second expected value step by step according to the bit width of each register to obtain the third expected value of each register. Convert the binary third expected value to hexadecimal and fill it into the third expected value column of the second register test form in sequence to obtain the first register test form.

6. The method for verifying registers of a system-on-chip according to claim 5, wherein The steps of importing the system-level verification use case into the central processing unit in the to-be-tested system-level chip to enable the central processing unit to traverse all registers in the to-be-tested system-level chip according to the system-level verification use case and perform verification include: The central processing unit reads the actual reset value of the register, and compares the actual reset value with the fourth reset value corresponding to the register at the same address in the first register test form to perform register reset value verification; The central processing unit writes the third write value in the first register test form into the register at the corresponding address, reads the actual write value of the register, and compares the actual write value with the third expected value corresponding to the register at the same address in the first register test form to perform register read / write verification.

7. The register verification method for a system-on-chip according to claim 1, wherein During the process of parsing the original register form to generate the system-level verification use case, if a error signal is received, it is determined that the format of the original register form is incorrect.

8. A register verification device for a system-on-chip, characterized in that For a system-level chip register verification device for executing the system-level chip register verification method according to any one of claims 1-7, the system-level chip register verification device includes: An acquisition module for acquiring the original register form of the to-be-tested system-level chip; wherein, the original register form includes the configuration parameters of all registers in the to-be-tested system-level chip; A generation module, configured to parse the original register form to generate a first register test form, and generate a system-level verification case for verifying all registers in the system-on-chip to be tested according to the first register test form; A verification module, configured to import the system-level verification case into a central processing unit in the system-on-chip to be tested, so that the central processing unit traverses and verifies all registers in the system-on-chip to be tested according to the system-level verification case.

9. An electronic device, characterized in that, It includes a processor and a memory. The memory stores a program that can be executed by the processor, and the processor can execute the program to implement the register verification method for the system-on-chip according to any one of claims 1-7.

10. A storage medium, characterized in that, A computer program is stored on the storage medium, and when the computer program is executed by a processor, the register verification method for the system-on-chip according to any one of claims 1-7 is implemented.

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