PCIe-based MSIx processing method and system

Abstract

The invention relates to an MSIx processing method and device based on PCIe, computer equipment, a storage medium and a computer program product. The method comprises the following steps: a PCIe terminal sends a memory write operation to an RC root node based on a message event, wherein the memory write operation comprises address data and message data corresponding to the message event; the interrupt conversion module reads a memory write operation in the RC root node; the interrupt conversion module converts the write operation of the memory into a high-level interrupt signal and sends the high-level interrupt signal to the central processing unit; the central processor processes the message event based on the level interrupt signal. According to the method, for a central processing unit in a cluster system which does not support receiving of a memory write operation interrupt interface, compatibility is achieved after processing is conducted through the design method; and memory write operation sent to the central processing unit system by the RC root node in the cluster system is eliminated, and the data bus access bandwidth of the RC root node and the central processing unit system in the cluster system is reduced.

Description

Technical Field

[0001] This application relates to the technical field of PCIe, and in particular, to a method, device, equipment, and storage medium for MSIx processing based on PCIe. Background Art

[0002] With the continuous development of computer chip technology, server data processing systems based on PCIe slots as root clusters have a wide range of application scenarios. As a chip-level peripheral interface technology, PCIe uses point-to-point connections between various endpoint devices, and data transmission between PCIe interface devices features high bandwidth throughput and low latency.

[0003] MSIx is the abbreviation of Message Signaled Interrupt extended, and it is an interrupt request mechanism that must be supported by PCIe endpoints or PCIe cluster systems. When a PCIe endpoint device generates a message event, it needs to send a memory write operation to its connected upper-level device, and send a memory write operation to the root node RC device at the upper level through the PCIe bus. When the root node RC device receives the memory write operation from the PCIe endpoint device, it first converts the memory write operation into an Interrupt Message bus transaction and sends it to the bus connected to the central processor; after the central processor receives the Interrupt Message bus transaction through the bus, it directly obtains the interrupt vector number from the bus transaction, and then the central processor will enter the interrupt state and execute the corresponding interrupt processing.

[0004] The existing design of the central processor is completed through the open instruction set architecture of RISC-V. However, the PLIC platform system based on RISC-V does not support MSIx interrupts, and MSIx interrupts are a message interrupt mechanism that must be supported in the PCIe interconnected cluster system. Therefore, in the PCIe interconnected cluster system, the MSIx interface of the RC root node of PCIe is directly connected and integrated with the PLIC interrupt interface, and the function of MSIx cannot be realized. Summary of the Invention

[0005] Based on this, in view of the above technical problems, it is necessary to provide a method, device, computer equipment, computer-readable storage medium, and computer program product that can also implement MSIx interrupts in the PLIC platform system.

[0006] In a first aspect, this application provides a method for MSIx processing based on PCIe. The method includes:

[0007] The PCIe endpoint sends a memory write operation to the RC root node based on a message event, and the memory write operation includes address data and message data corresponding to the message event;

[0008] The interrupt conversion module reads the memory write operation in the RC root node;

[0009] The interrupt conversion module converts the memory write operation of the message event into a high-level interrupt signal and sends it to the central processor;

[0010] The central processor processes the message event based on the level interrupt signal.

[0011] In one embodiment, the upper-level device of the PCIe terminal is a transfer device, and it is characterized in that the PCIe terminal sending a memory write operation to the RC root node based on the message event includes:

[0012] The PCIe terminal sends a memory write operation to the transfer device based on the message event;

[0013] The transfer device determines whether the address data is located in a preset root node register library, and the root node register library stores registers set in the RC root node;

[0014] If the address data is located in the preset root node register library, the transfer device forwards the memory write operation of the message event to the RC root node.

[0015] In one embodiment, the terminal conversion module includes a source device number register and a source device data register, and the PCIe terminal includes an interrupt enable register. The central processor processing the message event based on the level interrupt signal includes:

[0016] After receiving the high-level interrupt signal, the central processor reads the source device number register and obtains the PCIe terminal device number;

[0017] The central processor queries the corresponding PCIe terminal based on the PCIe terminal device number and determines whether the memory write operation of the PCIe terminal is valid according to the interrupt enable register;

[0018] If the interrupt enable register is valid, the central processor reads the source device data register and processes the message event.

[0019] In one embodiment, when multiple PCIe terminals send memory write operations to the RC root node, the interrupt conversion module obtains all the memory write operations of the message events in the RC root node and sets the corresponding PCIe terminal device valid bit in the interrupt enable register of the interrupt processing module. The data corresponding to the memory write operations of the message events sent by all PCIe terminals is written into the data registers of the corresponding PCIe terminals;

[0020] After the central processor reads the source device data register and processes the message event, it further includes:

[0021] Clear the source device number register corresponding to the source device data register after it is read by the central processing unit;

[0022] When the data registers of all PCIe endpoints have been read, the interrupt valid register of the interrupt conversion module is 0, and the interrupt signal sent to the central processing unit is at a low level.

[0023] In one embodiment, when multiple PCIe endpoints send a memory write operation to the relay device, the relay device respectively determines whether the address data is located in a preset root node register bank;

[0024] If the address data is located in the preset root node register bank, the relay device forwards the memory write operation to the RC root node.

[0025] In one embodiment, the central processing unit obtaining and reading the source device data register and processing the message event includes:

[0026] The central processing unit reads the source device data register and determines the PCIe endpoint that sends the memory write operation;

[0027] Within a preset period, the central processing unit processes the message event corresponding to the PCIe endpoint that sends the memory write operation.

[0028] In a second aspect, the present application also provides a PCIe-based MSIx processing device. The device includes:

[0029] An interrupt sending module, configured to send a memory write operation including address data and message data corresponding to a message event from a PCIe endpoint to an RC root node;

[0030] An interrupt forwarding module, configured to read the memory write operation in the RC root node by the interrupt conversion module

[0031] An interrupt conversion module, configured to convert the memory write operation of the message event into a level interrupt signal and send it to the central processing unit;

[0032] An interrupt processing module, configured to process the message event by the central processing unit based on the level interrupt signal.

[0033] In a third aspect, the present application also provides a computer device. The computer device includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the following steps are implemented:

[0034] The PCIe endpoint sends a memory write operation to the RC root complex based on a message event, and the memory write operation includes address data and message data corresponding to the message event;

[0035] The interrupt conversion module reads the memory write operation in the RC root complex;

[0036] The interrupt conversion module converts the memory write operation of the message event into a high-level interrupt signal and sends it to the central processing unit;

[0037] The central processing unit processes the message event based on the level interrupt signal.

[0038] In a fourth aspect, the present application also provides a computer-readable storage medium. A computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0039] The PCIe endpoint sends a memory write operation to the RC root complex based on a message event, and the memory write operation includes address data and message data corresponding to the message event;

[0040] The interrupt conversion module reads the memory write operation in the RC root complex;

[0041] The interrupt conversion module converts the memory write operation of the message event into a high-level interrupt signal and sends it to the central processing unit;

[0042] The central processing unit processes the message event based on the level interrupt signal.

[0043] In a fifth aspect, the present application also provides a computer program product. A computer program product, including a computer program, and when the computer program is executed by a processor, the following steps are implemented:

[0044] The PCIe endpoint sends a memory write operation to the RC root complex based on a message event, and the memory write operation includes address data and message data corresponding to the message event;

[0045] The interrupt conversion module reads the memory write operation in the RC root complex;

[0046] The interrupt conversion module converts the memory write operation of the message event into a high-level interrupt signal and sends it to the central processing unit;

[0047] The central processing unit processes the message event based on the level interrupt signal.

[0048] The above PCIe-based MSIx processing method, device, computer device, storage medium, and computer program product. The PCIe terminal sends a memory write operation to the RC root node based on a message event. The memory write operation includes address data and message data corresponding to the message event. The interrupt conversion module reads the memory write operation in the RC root node. The interrupt conversion module converts the memory write operation of the message event into a high-level interrupt signal and sends it to the central processing unit. The central processing unit processes the message event based on the level interrupt signal. By adopting the above method in this application, for a central processing unit in a cluster system that does not support receiving a memory write operation interrupt interface, compatibility is achieved through this design invention. The memory write operation sent by the RC root node in the cluster system to the central processing unit system is eliminated, reducing the data bus access bandwidth between the RC root node and the central processing unit system in the cluster system. The memory write operation sent by the RC root node in the cluster system to the central processing unit system is eliminated, improving the real-time performance of the central processing unit in processing the memory write operation interrupt and the real-time performance of the central processing unit in obtaining PCIe terminal device data through the RC. The software driver does not need to use the Mask Bits and Pending Bits of the memory write operation to solve the problem of memory write operation interrupt loss, improving the complexity and execution efficiency of the driver in processing the memory write operation message interrupt sent by the PCIe terminal. Description of the Drawings

[0049] Figure 1 It is a hardware schematic diagram of a PCIe-based MSIx processing method in the prior art;

[0050] Figure 2 It is a hardware schematic diagram of a PCIe-based MSIx processing method in an embodiment;

[0051] Figure 3 It is a flowchart of a PCIe-based MSIx processing method in an embodiment;

[0052] Figure 4 It is a schematic diagram of a PCIe terminal sending a memory write operation through a relay device in an embodiment;

[0053] Figure 5 It is a flowchart of interrupt processing after a central processing unit receives a high-level interrupt in an embodiment;

[0054] Figure 6 It is a timing diagram of converting an MSIx message packet of a PCIe terminal into a high-level interrupt in an embodiment;

[0055] Figure 7 It is a structural block diagram of a PCIe-based MSIx processing device in an embodiment; Detailed Embodiments

[0056] To make the objectives, technical solutions and advantages of this application more clear and understandable, the following further elaborates on this application in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely used to explain this application and are not used to limit this application.

[0057] The PCIe-based MSIx processing method provided by the embodiments of this application. In the prior art, as Figure 1 shown, when a PCIe terminal generates a message event, it needs to send a memory write operation to its connected upper-level device through the PCIe bus. The address of the memory write operation is the data in the Message Address register, and the data of the memory write operation is the data in the MessageData register. When the upper-level device of the PCIe terminal is a transit device, the transit device recognizes that the access address is the memory space of the system, and then forwards this PCIe memory write transaction through the PCIE bus to the upper-level RC root node. When the RC root node receives the memory write operation of the message interrupt from the PCIe terminal or the transit device, it first converts the memory write operation into an Interrupt Message bus transaction and sends it to the bus connected to the CPU. After the CPU receives the Interrupt Message bus transaction through the bus, it directly obtains the interrupt vector number from this bus transaction, and then the CPU enters the interrupt state and executes the corresponding interrupt processing.

[0058] The PCIe-based MSIx processing method provided by the embodiments of this application can be applied to an application environment as Figure 2 shown. By setting an interrupt conversion module between the RC root node and the central processor, the memory write operation in the RC root node is converted into a high and low level interrupt signal, so that the central processor can be compatible with the memory write operation.

[0059] In one embodiment, as Figure 3 shown, in this embodiment, the method includes the following steps:

[0060] Step 202, the PCIe terminal sends a memory write operation to the RC root node based on the message event.

[0061] Among them, the Root Complex (root node) is a key component in a computer system, which is used to manage and coordinate various components and buses in the computer system. The root node is usually located on the motherboard and plays a role in connecting the processor, memory, expansion slots and other I / O devices. In this solution, it is used to connect the central processor and the PCIe terminal; the memory write operation includes the address data and the message data corresponding to the message event.

[0062] Step 204, the interrupt conversion module reads the memory write operation in the RC root node.

[0063] Among them, the interrupt conversion module extracts the memory write operations of message events from all memory write operations sent to the RC root node memory.

[0064] Step 206, the interrupt conversion module converts the memory write operation of the message event into a high-level interrupt signal and sends it to the central processing unit.

[0065] Among them, after the interrupt conversion module reads the memory write operation in the RC root node, it sends a high-level interrupt signal to the central processing unit until all memory write operations in the RC root node are processed by the central processing unit.

[0066] Step 208, the central processing unit processes the message event based on the level interrupt signal.

[0067] In the above PCIe-based MSIx processing method, for the central processing unit in the cluster system that does not support receiving the memory write operation interrupt interface, after being processed by this design invention, compatibility is obtained; the memory write operation sent by the RC root node in the cluster system to the central processing unit system is eliminated, reducing the data bus access bandwidth between the RC root node and the central processing unit system in the cluster system; the memory write operation sent by the RC root node in the cluster system to the central processing unit system is eliminated, improving the real-time performance of the central processing unit in processing the memory write operation interrupt and the real-time performance of the central processing unit in obtaining PCIe terminal device data through the RC; the software driver does not need to use the Mask Bits and Pending Bits of the memory write operation to solve the problem of memory write operation interrupt loss, improving the complexity and execution efficiency of the driver in processing the memory write operation message interrupt sent by the PCIe terminal.

[0068] In one embodiment, as Figure 1 and Figure 4 shown, considering that the upper-level device of the PCIe terminal may be a transit device, the connection situation between the transit device and the RC root node is disclosed, specifically including:

[0069] Step 302, the PCIe terminal sends a memory write operation to the transit device based on the message event.

[0070] Step 304, the transit device determines whether the address data is located in the preset root node register library.

[0071] Among them, the root node register bank stores registers set at the RC root node. If the address data is located in the preset root node register bank, the transfer device forwards the memory write operation to the RC root node; if the address data is outside the preset root node register bank, the transfer device does not forward the memory write operation to the RC root node and sends it according to the actual situation of the address data, which will not be discussed in detail in this solution.

[0072] In one embodiment, as Figure 5 described, the terminal conversion module includes a source device number register and a source device data register. The PCIe terminal includes an interrupt enable register. How the central processing unit processes message events according to the high-level interrupt signal, the specific processing process can be executed as follows:

[0073] Step 402, the central processing unit receives the high-level interrupt signal sent by the interrupt conversion module and starts to read the interrupt register of the interrupt conversion module.

[0074] Step 404, the central processing unit reads the source device number register and obtains the PCIe terminal device number.

[0075] Among them, the source device number register stores the identity information of the register that sends the memory write operation, and the central processing unit can query the corresponding register according to the identity information.

[0076] Step 406, the central processing unit reads the interrupt data of the MSIx message event sent by the PCIe terminal device according to the source device number register.

[0077] Among them, the central processing unit queries the corresponding PCIe terminal based on the PCIe terminal device number and judges whether the memory write operation of the PCIe terminal is valid according to the interrupt enable register. If the interrupt enable register is valid, the central processing unit reads the source device data register and processes the message event; if the interrupt enable register is invalid, the central processing unit skips this register and processes other registers.

[0078] It is worth mentioning that, as Figure 6 shown, MSIx_EPx indicates that the interrupt conversion module has received a valid memory write operation from the RC root node. The 'x' in EPx in the figure indicates which PCIe terminal's memory write operation the module has received. For example: EP5 indicates that the module has received the memory write operation of PCIe terminal 5.

[0079] EPx_vld_REG, the interrupt enable register of the PCIe terminal, where the 'x' in EPx indicates which current PCIe terminal has generated a memory write operation. For example: "1100" indicates that the current PCIe terminal 3 and PCIe terminal 2 have generated valid memory write operations;

[0080] RC2CPU_INT, the level interrupt signal sent by the interrupt conversion module to the CPU, with high level being valid. When any bit of the EPx_vld_REG is valid, this interrupt signal is at high level;

[0081] CPU_rd_REG, indicating that the central processing unit reads the interrupt conversion module after receiving RC2CPU_INT = action. In the figure above, 'EPx' indicates that the central processing unit CPU reads the EPx_vld_REG register, and EP5_D indicates that the central processing unit CPU reads the data of the message data register of EP5.

[0082] The above timing diagram is explained as follows:

[0083] In cycle T1, the interrupt conversion module received a memory write operation from the RC root node;

[0084] In cycle T2, the interrupt conversion module sets the PCIe endpoint valid register EPx_vld_REG to "100000", indicating that the memory write operation of the current PCIe endpoint 5 is valid. At the same time, it sets RC2CPU_INT to high level to notify the CPU that a valid memory write operation has occurred currently;

[0085] In cycle T3, after being triggered by the high level of RC2CPU_INT, the CPU first reads the PCIe endpoint valid register as "100000", learns that the memory write operation of PCIe endpoint 5 is valid, and will issue a read operation for the message data register;

[0086] In cycle T5, the CPU reads the data of the message data register of PCIe endpoint 5 of the interrupt conversion module;

[0087] In cycle T6, after the message data register of PCIe endpoint 5 is read, the interrupt conversion module clears the EPx_vld_REG indicating the valid signal of PCIe endpoint 5 to 0, indicating that the current memory write operation of the RC and the relevant interrupt data have been read and transmitted to the CPU.

[0088] In the above timing diagram, the processing process of the second high-level validity of RC2CPU_INT is the same as the first one in principle. The differences are as follows:

[0089] In cycle T12, the CPU reads the PCIe endpoint valid register as "001100", learns that the register write operations of PCIe endpoint 3 and PCIe endpoint 2 are valid, and will issue read operations for the message data registers of PCIe endpoint 3 and PCIe endpoint 2;

[0090] In the T14 and T16 cycles, the CPU reads the data of the message data registers of the interrupt conversion module's PCIe terminal 3 and PCIe terminal 2 respectively;

[0091] In the T15 and T17 cycles, the interrupt conversion module clears bit3 and bit2 of the EPx_vld_REG register, indicating that the register write operations and related interrupt data of the current PCIe terminal 3 and PCIe terminal 2 have been read and transferred to the CPU.

[0092] It is worth mentioning that when multiple of the said PCIe terminals send memory write operations to the RC root node, the interrupt conversion module analyzes all the memory write operations sent to the RC root node and extracts the MSIx memory write operations of the message events among them; after the central processing unit reads the source device data register and processes the message events, it also includes: clearing the source device number register corresponding to the source device data register after being read by the central processing unit; when there is no register write operation in the RC root node, the interrupt conversion module sends a low-level message to the central processing unit.

[0093] Eliminating the memory write operations sent by the RC root node in the cluster system to the central processing unit system reduces the data bus access bandwidth between the RC root node and the central processing unit system in the cluster system.

[0094] When multiple of the said PCIe terminals send memory write operations to the transit device, the transit device respectively judges whether the address data is located in the preset root node register bank; if the address data is located in the preset root node register bank, the transit device forwards the memory write operation to the RC root node.

[0095] Eliminating the memory write operations sent by the RC root node in the cluster system to the central processing unit system improves the real-time performance of the central processing unit in processing memory write operation interrupts and the real-time performance of the central processing unit in obtaining PCIe terminal device data through the RC.

[0096] When the central processing unit obtains and reads the source device data register and processes the message events, it includes: the central processing unit reads the source device data register and determines the PCIe terminal that sends the memory write operation; within a preset cycle, the central processing unit processes the message events corresponding to the PCIe terminal that sends the memory write operation.

[0097] The software driver does not need to use the Mask Bits and Pending Bits of the memory write operation to solve the problem of memory write operation interrupt loss, improving the complexity and execution efficiency of the driver in processing the memory write operation message interrupt sent by the PCIe terminal.

[0098] It should be understood that although the steps in the flowcharts involved in the above-described embodiments are sequentially shown according to the arrows, these steps are not necessarily executed sequentially in the order indicated by the arrows. Unless there is a clear indication in this article, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-described embodiments may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same moment, but can be executed at different moments. The execution order of these steps or stages is not necessarily sequential, but can be executed alternately or in turn with at least a part of other steps or steps or stages in other steps.

[0099] Based on the same inventive concept, an embodiment of the present application also provides a PCIe-based MSIx processing device for implementing the above-mentioned PCIe-based MSIx processing method. The implementation solution provided by this device to solve problems is similar to the implementation solution described in the above method. Therefore, the specific limitations in one or more of the following embodiments of the PCIe-based MSIx processing device can refer to the limitations on the PCIe-based MSIx processing method in the above text, and will not be repeated here.

[0100] In one embodiment, as Figure 7 shown, a PCIe-based MSIx processing device is provided, including: an interrupt sending module, an interrupt forwarding module, an interrupt conversion module, an interrupt processing module, a transit processing module, and a transit forwarding module, where:

[0101] In one embodiment, the interrupt sending module is further configured to send a memory write operation to the transit device by the PCIe terminal based on a message event; the transit device determines whether the address data is located in a preset root node register library, and the root node register library stores registers set in the RC root node; if the address data is located in the preset root node register library, the transit device forwards the memory write operation of the message event to the RC root node.

[0102] In one embodiment, the interrupt processing module is further configured to read the source device number register and obtain the PCIe terminal device number after the central processing unit receives a high-level interrupt signal; the central processing unit queries the corresponding PCIe terminal based on the PCIe terminal device number and determines whether the memory write operation of the PCIe terminal is valid according to the interrupt valid register; if the interrupt valid register is valid, the central processing unit reads the source device data register and processes the message event.

[0103] In one embodiment, the relay processing module is further configured to, when multiple PCIe terminals send memory write operations to the RC root node, the interrupt conversion module acquires the memory write operations of all message events in the RC root node and sets the corresponding PCIe terminal device valid bits in the interrupt valid register of the interrupt processing module. The data corresponding to the memory write operations of the message events sent by all PCIe terminals is written into the data registers of the corresponding PCIe terminals. After the central processing unit reads the source device data register and processes the message event, it further includes: clearing the source device number register corresponding to the source device data register after the central processing unit reads it; when there is no register write operation in the RC root node, the interrupt conversion module sends a low-level message to the central processing unit.

[0104] In one embodiment, the relay forwarding module is further configured to, when multiple PCIe terminals send memory write operations to the relay device, the relay device respectively determines whether the address data is located in a preset root node register bank; if the address data is located in the preset root node register bank, the relay device forwards the memory write operation to the RC root node.

[0105] In one embodiment, the relay forwarding module is further configured to the central processing unit reads the source device data register and determines the PCIe terminal that sends the memory write operation; within a preset period, the central processing unit processes the message event corresponding to the PCIe terminal that sends the memory write operation.

[0106] Each module in the above PCIe-based MSIx processing method device can be implemented in whole or in part by software, hardware, and their combination. The above modules can be embedded in the processor in the computer device in hardware form or independent of the processor, or stored in the memory in the computer device in software form, so that the processor can call and execute the operations corresponding to the above modules.

[0107] In one embodiment, a computer device is provided. The computer device may be a server. The computer device includes a processor, a memory, and a network interface connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with external terminals through a network connection. When the computer program is executed by the processor, it implements a coordinated investment method for a power transmission and energy storage system.

[0108] Those skilled in the art can understand that the block diagrams of only some structures related to the solution of this application do not constitute a limitation on the computer devices to which the solution of this application is applied. The specific computer devices may include more or fewer components than those shown in the figures, or combine some components, or have different component arrangements.

[0109] In one embodiment, a computer device is provided, which includes a memory and a processor. A computer program is stored in the memory, and when the processor executes the computer program, the steps in the above method embodiments are implemented.

[0110] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0111] In one embodiment, a computer program product is provided, which includes a computer program. When the computer program is executed by a processor, the steps in the above method embodiments are implemented.

[0112] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0113] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above methods. Among them, any reference to a memory, database, or other medium used in the embodiments provided in the present application can include at least one of non-volatile and volatile memories. Non-volatile memories can include read-only memory (ROM), magnetic tapes, floppy disks, flash memories, optical memories, high-density embedded non-volatile memories, resistive random access memories (ReRAM), magnetoresistive random access memories (MRAM), ferroelectric random access memories (FRAM), phase change memories (PCM), graphene memories, etc. Volatile memories can include random access memory (RAM) or external cache memories, etc. By way of illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM), etc. The databases involved in the embodiments provided in the present application can include at least one of relational databases and non-relational databases. Non-relational databases can include distributed databases based on blockchain, etc., without limitation. The processors involved in the embodiments provided in the present application can be general-purpose processors, central processors, graphics processors, digital signal processors, programmable logic devices, data processing logics based on quantum computing, etc., without limitation.

[0114] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0115] The above-described embodiments merely represent several implementation manners of the present application. The description thereof is relatively specific and detailed, but it should not be construed as a limitation on the patent scope of the present application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the appended claims.

Claims

1. A PCIe-based MSIx processing method, characterized in that, The method includes: The PCIe endpoint sends a memory write operation to the RC root complex based on a message event, and the memory write operation includes address data and message data corresponding to the message event; The interrupt conversion module reads the memory write operation in the RC root complex; The interrupt conversion module converts the memory write operation of the message event into a high-level interrupt signal and sends it to the central processing unit; The central processing unit processes the message event based on the level interrupt signal.

2. The method according to claim 1, wherein the upper-level device of the PCIe terminal is a relay device, characterized in that, The PCIe endpoint sending a memory write operation to the RC root complex based on a message event includes: The PCIe endpoint sends a memory write operation to the relay device based on a message event; The relay device determines whether the address data is located in a preset root complex register bank, and the root complex register bank stores registers set in the RC root complex; If the address data is located in the preset root complex register bank, the relay device forwards the memory write operation of the message event to the RC root complex.

3. The method according to claim 1, wherein The terminal conversion module includes a source device number register and a source device data register, and the PCIe endpoint includes an interrupt enable register. The central processing unit processing the message event based on the high-level interrupt signal includes: After receiving the high-level interrupt signal, the central processing unit reads the source device number register and obtains the PCIe endpoint device number; If the corresponding bit of the enable register for the PCIe endpoint to send the memory write operation is valid, the central processing unit reads the source device data register and processes the message event.

4. The method according to claim 3, wherein The method further includes: When multiple PCIe endpoints send memory write operations to the RC root complex, the interrupt conversion module obtains all the memory write operations of the message events in the RC root complex and sets the corresponding PCIe endpoint device valid bits in the interrupt enable register of the interrupt processing module. The data corresponding to the memory write operations of the message events sent by all PCIe endpoints is written into the data registers of the corresponding PCIe endpoints; After the central processing unit reads the source device data register and processes the message event, it further includes: Clearing the source device number register corresponding to the source device data register read by the central processing unit; When all the data registers of the PCIe endpoints have been read, the interrupt enable register of the interrupt conversion module is 0, and the interrupt signal sent to the central processing unit is at a low level.

5. The method according to claim 2, characterized in that, The method further includes: When multiple PCIe endpoints send memory write operations to the relay device, the relay device respectively determines whether the address data is located in the preset root complex register bank; If the address data is located in the preset root complex register bank, the relay device forwards the memory write operation to the RC root complex.

6. The method according to claim 5, characterized in that, The central processing unit obtaining and reading the source device data register and processing the message event includes: The central processing unit reads the source device data register and determines the PCIe endpoint that sends the memory write operation; Within a preset period, the central processing unit processes the message events corresponding to the PCIe endpoints that send the memory write operations.

7. A PCIe-based MSIx processing device, characterized in that, The device includes: An interrupt sending module, configured to enable a PCIe terminal to send a memory write operation including address data and message data corresponding to a message event to an RC root node based on the message event; An interrupt forwarding module, configured to enable the interrupt conversion module to read the memory write operation in the RC root node An interrupt conversion module, configured to enable the interrupt conversion module to convert the memory write operation of the message event into a level interrupt signal and send the level interrupt signal to a central processing unit; An interrupt processing module, configured to enable the central processing unit to process the message event based on the level interrupt signal.

8. A computer device, comprising a memory and a processor, the memory storing a computer program, characterized in that, When the processor executes the computer program, the steps of the method according to any one of claims 1 to 6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 6 are implemented.

10. A computer program product, comprising a computer program, characterized in that, When the computer program is executed by the processor, the steps of the method according to any one of claims 1 to 6 are implemented.

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