A design method of a wide input power range dual-frequency transistor-based rectifier

Abstract

The application provides a design method of a wide input power range dual-frequency transistor-based rectifier. The application considers the dissipation power of the output capacitor of a GaN transistor-based rectifier, establishes the relationship between the dissipation power and the output capacitor of the GaN transistor, obtains the relationship between the rectification efficiency and the output capacitor, obtains different output impedances under different input powers, and thus obtains the corresponding output impedance design space; according to the theoretical impedance design space, the output matching network and the input matching network are designed by using a branch transmission line. According to the inverse-time binary principle, a phase shift network is added between the drain and the gate to realize a self-synchronous rectifier. The radio frequency input signal and the gate input signal of the rectifier are set to be phase-shifted at two target frequencies, and the design of the phase shift network is completed accordingly. The output matching network, the input matching network and the phase shift network are optimized by using an improved multi-objective particle swarm algorithm based on a differential evolution strategy, so that the designed rectifier can maintain high efficiency in a wide input power dynamic range, and the design accuracy and efficiency can be improved.

Description

Technical Field

[0001] This invention relates to the field of wireless communication technology, and in particular to a design method for a wide input power range dual-frequency transistor-based rectifier. Background Technology

[0002] With the rapid development of wireless power transfer technology, microwave radio frequency technology is becoming increasingly important in modern life. A microwave wireless power transfer system mainly consists of a transmitter (composed of a microwave source and transmitting antenna) and a receiver (composed of a receiving antenna and rectifier circuit). The rectifier has a significant impact on the overall system's energy conversion efficiency. In practical applications, the input radio frequency power is often not a fixed value but a dynamic range due to the distance between the receiver and the signal source. This requires the rectifier to have high efficiency throughout the dynamic range of the input power.

[0003] Meanwhile, as frequency band resources are used more and more, broadband, dual-band and multi-band rectifiers can harvest more microwave energy in more bands compared with single-band rectifiers, which is crucial for next-generation wireless communication technologies. They can support multi-band communication, thereby reducing size, cost and design complexity.

[0004] Common Schottky diode-based rectifiers often have low power capacity, and voltage and current fluctuations generated by Schottky diodes under high input power can lead to semiconductor junction breakdown. Gallium nitride transistors (GaN HEMTs) offer higher efficiency (low on-resistance and fast switching), higher operating frequency, higher power density, higher stability (high breakdown voltage), smaller device size, and potential system-level cost advantages compared to traditional Schottky diodes.

[0005] In summary, to ensure the stability of the wireless power transmission system and improve the power density of wireless power transmission, a design method for a GaN transistor-based dual-frequency rectifier with a wide dynamic input power range for high-power scenarios has been developed. Summary of the Invention

[0006] The purpose of this invention is to provide a design method for a wide input power range dual-frequency transistor-based rectifier. Based on GaN transistors, a high back-off dual-frequency rectifier is designed. Considering the power dissipation of the GaN transistor output capacitor, a relationship between rectification efficiency and output capacitance is obtained by establishing the relationship between power dissipation and GaN transistor output capacitance. Different output impedances are obtained under different input powers, thus obtaining the corresponding output impedance design space. Based on the theoretical impedance design space, branch transmission lines are used to design output matching networks and input matching networks. According to the inverse-time duality principle, a phase-shifting network is added between the drain and gate to achieve a self-synchronizing rectifier. The RF input signal and gate input signal of the rectifier are phase-shifted at two target frequencies, and the phase-shifting network is designed accordingly. An improved multi-objective particle swarm optimization algorithm based on differential evolution strategy is used to optimize the output matching network, input matching network, and phase-shifting network. This allows the designed rectifier to maintain high efficiency over a wide dynamic range with high input power. Compared to traditional rectifier designs, where the output matching network needs to repeatedly adjust specific parameters based on fundamental frequency matching and harmonic control, using algorithms can significantly improve the accuracy and efficiency of the design.

[0007] To overcome the shortcomings of the prior art, the present invention adopts the following solution:

[0008] Step 1: Based on gallium nitride (GaN) HEMTs, a rectifier is constructed according to the principle of inverse-time duality (rectifiers and power amplifiers have structural and energy symmetry). The input and output terminals of the power amplifier are interchanged to form the rectifier structure: the DC drain input terminal of the power amplifier serves as the DC output terminal of the rectifier, and the output terminal of the power amplifier serves as the RF input segment of the rectifier. Simultaneously, the power amplifier's operating mode is used as the rectifier's operating mode.

[0009] Furthermore, power amplifiers can operate in various modes, including Class AB, Class F, inverse Class F, and Class B / J.

[0010] Step 2: Considering the power consumed by the gallium nitride transistor's output capacitor and the switching resistor during conduction, use normalized input power to obtain the relationship between input power and transistor output capacitance. Based on the rectification efficiency expression... The rectification efficiency is obtained at different R values. L The curve showing the change in input power (theoretical efficiency curve), P dc The drain outputs DC power (the rectifier's output power). This represents the power dissipated by the switching resistor. The output capacitor dissipates power. A suitable R is selected based on the design objectives (operating frequency, RF input power range, rectification efficiency). LBased on the equivalent circuit of a gallium nitride transistor (GaNHEMT), the theoretical impedance design space for the two target frequencies is obtained.

[0011] Furthermore, the drain output DC power V dc I represents the DC component of the voltage in the operating mode. dc R is the conduction current of the switching resistor. on R represents the on-resistance of a transistor. dc The resistance of the switching resistor; the power dissipated by the output capacitor. f represents the target operating frequency, and C out V is the output capacitance of the transistor. max This represents the maximum drain voltage; the power dissipated by the switching resistor. I max This represents the maximum value of the drain current. The relationship between input power and transistor output capacitance is: The V here d The voltage input to the drain of the transistor, i.e., C out The charging voltage.

[0012] Step 3: Based on the theoretical impedance design space, design the output matching network using branch transmission lines to match the drain output impedance of both target frequencies (f1, f2) to 50 ohms at the power back-off point. The drain output impedance remains within the theoretical impedance design space throughout the entire input power variation range (0-20dB).

[0013] The source impedance (Z) at two target frequencies was obtained using the RF simulation software ADS (Advanced Design Software). s1 Z s2 Then, the input matching network was designed to match the gate input impedance to 50 ohms. Based on the principle of inverse-time duality, a phase-shifting network was added between the drain and the gate to realize a self-synchronizing rectifier. The RF input signal and the gate input signal of the rectifier were set to be phase-shifted by 180 degrees at two target frequencies, and the phase-shifting network was designed accordingly.

[0014] Furthermore, the drain output impedance includes the fundamental impedance (Z). f1 Z f2 Harmonic impedance: In different operating modes, each frequency corresponds to a fundamental impedance and a corresponding number of harmonic impedances.

[0015] Furthermore, the output matching network consists of similar dual-frequency fundamental wave matching structures and different harmonic control topologies. Whether a harmonic control network structure is needed depends on the rectifier's operating mode. Harmonic control is used to improve the rectifier's rectification efficiency.

[0016] Step 4: Optimize the output matching network, input matching network, and phase shift network designed in Step 3 using an improved multi-objective particle swarm optimization algorithm based on differential evolution strategy. The optimization process is as follows:

[0017] The two source impedances Z at the two target frequencies f1 and f2 are... s1 and Z s2 The two fundamental impedances Z f1 Z f2 Alternatively, the phase shift value phs (180 degrees) can be used as the optimization objective for the improved multi-objective particle swarm optimization algorithm. The maximum number of iterations, Iter, can be set. Max The external storage set size is Q (stores non-dominated solutions in the population after each iteration update, i.e., solutions in the archive are better than other solutions in the current population), and the variable dimension is 2n, where n is the number of all microstrip lines in the optimized circuit. Each microstrip line has two optimizable variables: electrical length (E). i ) and characteristic impedance (Z i ).

[0018] Based on the optimization objective, randomly generate N particles and initialize the velocity variable v = [ΔE1, ΔE2, ..., ΔE] of each particle. n ,ΔZ1,ΔZ2,…,ΔZ n ] and positional variable X = [E1, E2, E3, ..., E n ,Z1,Z2,Z3…Z n Then find the local optimum variable X. pbest and the globally optimal variable X gbest Where ΔE j and ΔZ j They represent the parameters E respectively j and Z j The iteration speed.

[0019] The velocity and position variables are updated iteratively using an improved multi-objective particle swarm optimization algorithm.

[0020] New position variables are obtained from three random locations. For each dimension of these new position variables, an improved position variable is obtained by checking if it exceeds a predetermined crossover probability CR. To improve performance stability, the error fitness value is calculated using a step fitness function, resulting in an error fitness vector f(e) at two frequency points. i k =(e1,e $ If the current particle position dominates its individual optimal position X. pbest Then update the local optimal error fitness vector f(e). pbest Local optimal variable X pbest If the two positions are not mutually dominant, a locally optimal error fitness vector f(e) is randomly selected with a set probability.pbest Local optimal variable X pbest Simultaneously, the particle positions from the external storage set are placed into the grid. To avoid the algorithm getting trapped in local optima, a grid density evaluation method is used to calculate the probability of a particle being selected in all grids. Particles with higher probabilities are more likely to be selected as the best, thereby updating the global optimal error and fitness vector f(e). gbest and the globally optimal variable X gbest .

[0021] If the global optimal error fitness vector is f(e) gbest The value is already equal to 0, indicating that the current circuit parameters can meet the set targets for phase shift, impedance, etc. At this point, the globally optimal variable X will be output. gbest Additionally, if the number of iterations reaches the maximum value Iter Max It will also output the globally optimal variable X. gbest .

[0022] Furthermore, the iterative update process of the velocity variable is as follows: In the formula, The velocity variable updated for the i-th particle in the k-th iteration. Let c1 be the position variable obtained from the (k-1)th iteration update of the i-th particle, c2 be the self-learning factor, c2 be the social learning factor, ω be the particle's inertia weight, and X be the position variable obtained from the (k-1)th iteration update. pbest For local optimal variables, X gbest X is the globally optimal variable, ε is the perturbation coefficient, and R1 and R2 are two random numbers distributed between 0 and 1. X is dynamically adjusted. gbest and X pbest The effect on particles. X D1 X D$ Let be two random particle position variables in the particle swarm, used to represent the positions of other particles in the swarm. The effects of changes in particle movement.

[0023] Furthermore, the iterative update process for the position variable is as follows: In the formula, The position variable obtained by updating the i-th particle in the k-th iteration; Depend on The structure represents the position variable of the i-th particle after the (k-1)-th iteration; In the formula, F is the scaling factor, and X DQ This is another random particle position variable in the particle population; Let this be the new position variable generated by the position variables of the three random particles in the population during the (k-1)th iteration of the i-th particle. It is used to represent the better position variable obtained from other particles in the population at the (k-1)th iteration; In the formula This indicates that selection is based on whether the probability in the j-th dimension is greater than the set crossover probability CR. or Where j = j DYnd This ensures that at least one dimension is updated, avoiding invalid crossovers; express The value of the j-th dimension, The position variable obtained by updating the i-th particle in the (k-1)th iteration The value of the j-th dimension.

[0024] Furthermore, the error fitness calculation process is as follows:

[0025] Error fitness value In the formula, ratio is the ratio of the simulated parameter value obtained at the end of each particle update iteration to the input target value. The smaller the fitness value e, the closer it is to the target. On the fitness vector, the solution X... A Not worse than X B And there exists at least one dimension f of the fitness vector. j =e(j=1,2), such that f j (X A )>f j (X B X is called X. A DominateX B A non-dominated solution is a solution that is not dominated by any other solution.

[0026] Furthermore, the calculation process for the aforementioned grid density evaluation method is as follows: In the formula, Num i p refers to the number of particles in a single grid after the particle swarm is meshed. i It represents the probability of a particle being selected. The more particles in a cell, the lower the probability of a particle being selected. This helps avoid the algorithm getting stuck in local optima while improving the algorithm's running speed.

[0027] The logic code for the improved multi-objective particle swarm optimization algorithm is as follows:

[0028]

[0029] Attached Figure Description

[0030] Figure 1 For rectifier topology;

[0031] Figure 2To simplify the electrical model of transistors;

[0032] Figure 3 For different R L The corresponding theoretical efficiency curves are shown in (a) 0.9 GHz and (b) 2.4 GHz.

[0033] Figure 4 To simulate the fundamental impedance and second harmonic impedance diagrams;

[0034] Figure 5 Harmonic control networks for several operating modes;

[0035] Figure 6 Flowchart for the optimization of the improved multi-objective particle swarm optimization algorithm;

[0036] Figure 7 The output matching network before and after optimization is shown in the example;

[0037] Figure 8 To optimize the simulated output impedance of the pre- and post-output matching networks;

[0038] Figure 9 To optimize the phase-shifting network before and after;

[0039] Figure 10 To simulate phase shift (a) the phase shift of the phase shift network before and after optimization (b) the phase shift of the drain and gate;

[0040] Figure 11 The complete circuit schematic of the rectifier;

[0041] Figure 12 (a) is the rectification efficiency curve for saturated RF input power; (b) is the rectification efficiency curve for variable RF input power.

[0042] Figure 13 The drain voltage and current waveforms simulated in the intrinsic plane are shown in (a) 0.9 GHz and (b) 2.4 GHz. Detailed Implementation

[0043] The following are specific embodiments of the present invention, and the technical solutions of the present invention will be further described in conjunction with the accompanying drawings. However, the present invention is not limited to these embodiments.

[0044] In this embodiment, taking continuous B / J class operating mode as an example, a dual-frequency rectifier with operating frequencies of f1 = 0.9 GHz and f2 = 2.4 GHz was designed. This rectifier is based on commercially available CGH40010F GaN transistors and Rogers4350B dielectric substrate (ε). r =3.66, H = 30 mils).

[0045] A design method for a wide input power range dual-frequency transistor-based rectifier specifically includes the following steps:

[0046] Step 1, such as Figure 1 As shown, a rectifier is constructed based on a gallium nitride (GaN) HEMT according to the principle of inverse-time duality (the rectifier and power amplifier have structural and energy symmetry). The input and output terminals of the power amplifier are interchanged to form the rectifier structure: the DC input terminal of the power amplifier's drain serves as the DC output terminal of the rectifier, and the output terminal of the power amplifier serves as the RF input segment of the rectifier. In this embodiment, the rectifier adopts a continuous Class B / J operating mode, with the gate bias voltage V... gs Set to -3.1V to obtain the conduction angle for continuous B / J class operating modes.

[0047] Step 2: Considering the power dissipation of the transistor output capacitor, establish the relationship between the power dissipation and the transistor output capacitor, thereby establishing the relationship between the rectification efficiency and the output capacitor; based on the transistor used (CGH40010FGaN HEMT) and the dielectric substrate (Rogers4350B, ε r =3.66, H=30mils)), combined with the DC power and output capacitor dissipation power in the circuit design process, and based on the equivalent circuit of gallium nitride transistor (GaN HEMT), the theoretical efficiency curve and the theoretical impedance design space of continuous B / J class operating mode are obtained. According to the target frequency, the corresponding appropriate fundamental and second harmonic impedance values ​​are selected in the impedance design space, and then the corresponding circuit structure is designed according to the dual-frequency design theory.

[0048] The expressions for the drain current and voltage waveforms in continuous B / J class operating mode are as follows:

[0049]

[0050] V dn =-V oYp (1-cosθ)(1-αsinθ);

[0051] Among them, V oYp I is the maximum value of the voltage. oYp This represents the maximum current. α is a continuity factor, taking values ​​[-1, 1]. When α = 1, the operating mode is class-J; when α = 0, the operating mode is class-B; and when α = -1, the operating mode is class-J. -1 By introducing operating mode parameters (i.e., continuity factors), the impedance design space can be expanded as much as possible, providing greater flexibility and freedom for impedance design.

[0052] In the above formula, θ = ωt, ω = 2πf.

[0053] By ideally modeling the transistor at the current source plane, we can obtain, as follows: Figure 2 The equivalent circuit shown.

[0054] but Right now

[0055] C out =0.95+1192*[1+tanh(-0.06·V d -2.95)];

[0056] To incorporate the input power into the efficiency expression, normalized input power is used, i.e.:

[0057]

[0058] The V here d The voltage input to the drain of the transistor, i.e., C out The charging voltage;

[0059] In this embodiment, R on The value is 0.8Ω; calculate the power consumed when the switch resistor is turned on. DC power Transistor output capacitor power dissipation Rectification efficiency

[0060] In this embodiment, in order to achieve a rectification efficiency of over 60% within a 20dB input power range of 0.9GHz and 2.4GHz, a suitable R is selected. L Perform impedance design. Figure 3 In the middle, although the rectification efficiency increases with R L R increases with the increase, but in actual design, R L The choice is also limited by the actual transistor characteristics, determined by R. L The determined final load impedance value should not deviate too much from the datasheet. Based on the selected transistor's datasheet, Rij should be set at 2.4 GHz. L Set to 50Ω. Meanwhile, to minimize efficiency fluctuations between the two frequencies, a different R is needed at the other frequency. L Therefore, R was chosen at 0.9GHz. L It is 32Ω.

[0061] The theoretical impedance for continuous Class B / J operating mode is: For fundamental impedance, This represents the second harmonic impedance; based on the above two equations, the theoretical impedance design space for the two target frequencies is obtained, such as... Figure 4 As shown.

[0062] Step 3: Based on the theoretical impedance design space, design the output matching network using a branch transmission line to match the drain output impedance of both target frequencies at the power back-off point to 50 ohms. The drain output impedance remains within the theoretical impedance design space throughout the entire input power variation range (0-20dB).

[0063] The source impedances at two target frequencies were obtained using ADS (Advanced Design Software), and then the input matching network was designed to match the pair of gate complex impedances to 50 ohms. Based on the principle of inverse-time duality, a phase-shifting network was added between the drain and gate to achieve self-synchronizing rectification. The drain and gate port signals of the rectifier were set to be phase-shifted by 180° at the two target frequencies, and the phase-shifting network was designed accordingly.

[0064] The output matching network consists of similar dual-frequency fundamental matching structures and different harmonic control topologies. Whether a harmonic control network structure is needed depends on the rectifier's operating mode; for example... Figure 5 As shown, the harmonic control structure is illustrated in several operating modes. In different operating modes, each frequency corresponds to a fundamental impedance and a corresponding number of harmonic impedances.

[0065] The design process of the output matching network in this embodiment is as follows: Based on two target frequency points, the impedance design space is obtained from the fundamental and second harmonic impedance expressions at the transistor drain. The classic T-type structure (TL1, TL2, TL6) and three transmission line structure (TL3, TL4, TL9) are used to match the fundamental impedance Z at the two frequency points. f1 = (72.05 + j * 42.831)Ω and Z f2 = (23.934 + j * 24.638)Ω matched to 50Ω. Simultaneously, an output harmonic control network (TL1 + TL5 = λ / 4 at 2f1, TL1 + TL2 + TL7 = λ / 8 at 2f2) is introduced to short-circuit the second harmonics at the two frequency points, thus meeting the harmonic load impedance requirements of continuous Class B / J. Transmission line TL8 is used to compensate for the impedance change after the addition of the harmonic tuning network. Transmission line TL4 is part of the coupler. Transmission line TL3 is used to isolate transmission line TL8 and the phase shift network to prevent coupling. Transmission line TL9 is used to facilitate the placement of DC blocking capacitors.

[0066] Step 4, use as follows Figure 6 The improved multi-objective particle swarm optimization algorithm shown optimizes the output matching network, input matching network, and phase shift network designed in step three.

[0067] The optimization process of the output matching network is as follows:

[0068] Given two target frequencies f1 = 0.9 GHz and f2 = 2.4 GHz, and two fundamental impedances Z... f1 = (72.05 + j * 42.831)Ω, Z f2 = (23.934 + j * 24.638)Ω, setting the maximum number of iterations Iter Max =50, external storage set size Q=100, n=9, c1=1.5, c2=1.5, ω=0.7, F=0.8, CR=0.8, ε=0.2;

[0069]

[0070]

[0071] The output matching network before and after optimization is as follows: Figure 7 As shown, from Figure 8 The output impedance diagram of the output matching network before optimization is shown. It can be seen that while optimizing the output matching network to the two target frequencies using the above method, the fundamental impedance and second harmonic impedance of the output matching network are both within the theoretical impedance design space, which fully demonstrates the effectiveness of the designed output matching network.

[0072] Input matching network optimization: The input impedance of the rectifier circuit at the two target frequencies is obtained through source-pull, resulting in a pair of complex impedances, Z. s1 =2.7 - j * 3.8Ω and Z s2 =3.2-j*4.2Ω, using the same method as the output matching network, the input matching network is optimized by an improved multi-objective particle swarm optimization algorithm.

[0073] Phase-shifting network optimization: After optimizing the output matching network and the input matching network, the target phase shifts of the phase-shifting network at the two operating frequencies are -84° and 83°, respectively. Using the target phase shift as the optimization objective, an improved multi-objective particle swarm optimization algorithm is used to optimize the phase-shifting network; the phase-shifting networks before and after optimization are shown below. Figure 9 As shown, from Figure 10 As can be seen from (a), the optimized phase-shift network achieved the target phase shift. Figure 10 As can be seen in (b), after the phase shift network optimization is completed, the phase difference between the two frequency points at the drain and the gate is approximately 180°.

[0074] By integrating the optimized output matching network, input matching network, and phase shift network, a system is designed as follows: Figure 11 The rectifier shown.

[0075] Continuous wave signal testing was performed on the designed rectifier. A high-power signal source provided the RF input signal to the rectifier, a signal generator provided the gate bias voltage, and an electronic load was used to obtain the DC output power. The performance characteristics obtained are as follows: Figure 12 As shown, at 0.9 GHz and 2.4 GHz, with a gate bias of -3.1 V, a DC load of 85 Ω, and an input power of 40 dBm, the rectification efficiencies are 73.129% and 86.252%, respectively. When the gate bias is -3.1 V, the DC load is 85 Ω, and the RF input power is backed down by 20 dBm, the rectification efficiencies are 63.768%-73.985% and 59.117%-86.532%, respectively.

[0076] The voltage and current waveforms at two frequency points in the intrinsic plane of the transistor were simulated in ADS, such as... Figure 13 As shown, this is a half-sine waveform that conforms to the continuous B / J class operating mode.

[0077] The above description of the embodiments is merely for the purpose of helping to understand the method and core ideas of the present invention. It should be noted that those skilled in the art can make various improvements and modifications to the present invention without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of the present invention. Various modifications to these embodiments will be obvious to those skilled in the art, and the general principles defined in this application can be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the present invention will not be limited to the embodiments shown in this application, but is to be accorded the widest scope consistent with the principles and novel features disclosed in this application.

Claims

1. A design method for a wide input power range dual-frequency transistor-based rectifier, characterized in that: Specifically, the steps include the following: Step 1: Based on the gallium nitride transistor and the principle of inverse time duality, construct a rectifier by swapping the input and output terminals of the power amplifier to form the rectifier structure: the DC input terminal of the power amplifier's drain is used as the DC output terminal of the rectifier, and the output terminal of the power amplifier is used as the RF input segment of the rectifier; at the same time, the power amplifier's operating mode is used as the rectifier's operating mode. Step 2: Considering the power consumed by the output capacitor and switching resistor of the gallium nitride transistor, use the normalized input power to obtain the relationship between the input power and the transistor output capacitor. According to the expression for rectification efficiency The rectification efficiency was obtained under different load line impedances R. L The curve of P as a function of input power dc DC power is output from the drain. This represents the power dissipated by the switching resistor. To dissipate power from the output capacitor; select an appropriate R based on the design objectives. L Based on the equivalent circuit of a gallium nitride transistor, the theoretical impedance design space for the two target frequencies is obtained. Step 3: Based on the theoretical impedance design space, design the output matching network using a branch transmission line to match the drain output impedance of both target frequencies at the power back-off point to 50 ohms. The drain output impedance will always be within the theoretical impedance design space throughout the entire input power variation range. The source impedance at two target frequencies was obtained using the RF simulation software ADS. Then, the input matching network was designed to match the gate input impedance to 50 ohms. Based on the principle of inverse time duality, a phase shift network was added between the drain and the gate to realize a self-synchronizing rectifier. The RF input signal and the gate input signal of the rectifier were set to be phase-shifted by 180 degrees at the two target frequencies, and the phase shift network was designed accordingly. Step 4: Optimize the output matching network, input matching network, and phase shift network designed in Step 3 using an improved multi-objective particle swarm optimization algorithm based on differential evolution strategy; the optimization process is as follows: The two source impedances Z at the two target frequencies f1 and f2 are... s1 and Z s2 The two fundamental impedances Z f1 Z f2 Alternatively, the phase shift value phs can be used as the optimization objective of the improved multi-objective particle swarm optimization algorithm; the maximum number of iterations Iter can be set. Max External storage set size Q, variable dimension 2n, where n is the number of all microstrip lines in the optimized circuit, and each microstrip line has two optimizable variables: electrical length E. i and characteristic impedance Z i ; Based on the optimization objective, randomly generate N particles and initialize the velocity variable v = [ΔE1, ΔE2, ..., ΔE] of each particle. n ,ΔZ1,ΔZ2,…,ΔZ n ] and positional variable X = [E1, E2, E3, ..., E n ,Z1,Z2,Z3…Z n Then find the local optimum variable X. pbest and the globally optimal variable X gbest ;where ΔE j and ΔZ j They represent the parameters E respectively j and Z j The iteration speed; The velocity and position variables are iteratively updated using an improved multi-objective particle swarm optimization algorithm. New position variables are obtained from three random locations. For each dimension of these new position variables, an improved position variable is obtained by checking if it exceeds a predetermined crossover probability CR. To improve performance stability, the error fitness value is calculated using a step fitness function, resulting in an error fitness vector f(e) at two frequency points. i k = (e1, e2); if the current particle position dominates its individual optimal position X pbest Then update the local optimal error fitness vector f(e). pbest Local optimal variable X pbest If the two positions are not mutually dominant, a locally optimal error fitness vector f(e) is randomly selected with a set probability. pbest Local optimal variable X pbest Simultaneously, the particle positions from the external storage set are placed into the grid. To avoid the algorithm getting trapped in local optima, a grid density evaluation method is used to calculate the probability of a particle being selected in all grids. Particles with higher probabilities are more likely to be selected as X. gbest This is used to update the global optimal error and fitness vector f(e). gbest and the globally optimal variable X gbest ; If the global optimal error fitness vector is f(e) gbest The value is already equal to 0, indicating that the current circuit parameters can meet the set phase shift and impedance targets; at this point, the globally optimal variable X will be output. gbest Additionally, if the number of iterations reaches the maximum value Iter Max It will also output the globally optimal variable X. gbest .

2. The design method of the wide input power range dual-frequency transistor-based rectifier as described in claim 1, characterized in that: The power amplifier described has the following operating modes: Class AB, Class F, Inverse Class F, and Class B / J.

3. The design method of the wide input power range dual-frequency transistor-based rectifier as described in claim 1, characterized in that: The drain output impedance includes the fundamental impedance and harmonic impedance. In different operating modes, each frequency corresponds to a fundamental impedance and a corresponding number of harmonic impedances.

4. The design method of the wide input power range dual-frequency transistor-based rectifier as described in claim 1, characterized in that: The output matching network consists of similar dual-frequency fundamental wave matching structures and different harmonic control topologies. Whether a harmonic control network structure is needed depends on the rectifier's operating mode. Harmonic control is used to improve the rectifier's rectification efficiency.

5. The design method of the wide input power range dual-frequency transistor-based rectifier as described in claim 1, characterized in that: The iterative update process for the velocity variable is as follows: In the formula, The velocity variable updated for the i-th particle in the k-th iteration. Let c1 be the position variable obtained from the (k-1)th iteration update of the i-th particle, c2 be the self-learning factor, c2 be the social learning factor, ω be the particle's inertia weight, and X be the position variable obtained from the (k-1)th iteration update. pbest For local optimal variables, X gbest X is the globally optimal variable, ε is the perturbation coefficient, and R1 and R2 are two random numbers distributed between 0 and 1. X is dynamically adjusted. gbest and X pbest Effects on particles; X r1 X r2 Let be two random particle position variables in the particle swarm, used to represent the positions of other particles in the swarm. The effects of changes in particle movement.

6. The design method of the wide input power range dual-frequency transistor-based rectifier as described in claim 1, characterized in that: The iterative update process for the location variable is as follows: In the formula, The position variable obtained by updating the i-th particle in the k-th iteration; Depend on The structure represents the position variable of the i-th particle after the (k-1)-th iteration; In the formula, F is the scaling factor, and X r＝ This is another random particle position variable in the particle population; Let this be the new position variable generated by the position variables of the three random particles in the population during the (k-1)th iteration of the i-th particle. It is used to represent the better position variable obtained from other particles in the population at the (k-1)th iteration; In the formula This indicates that selection is based on whether the probability in the j-th dimension is greater than the set crossover probability CR. or Where j = j rand This ensures that at least one dimension is updated, avoiding invalid crossovers; express The value of the j-th dimension, The position variable obtained by updating the i-th particle in the (k-1)th iteration The value of the j-th dimension, The velocity variable is updated for the i-th particle in the k-th iteration.

7. The design method of the wide input power range dual-frequency transistor-based rectifier as described in claim 1, characterized in that: The error fitness calculation process is as follows: Error fitness value In the formula, ratio is the ratio of the simulated parameter value obtained at the end of each particle update iteration to the input target value.

8. The design method of the wide input power range dual-frequency transistor-based rectifier as described in claim 1, characterized in that: The calculation process for the aforementioned grid density evaluation method is as follows: In the formula, Num i p refers to the number of particles in a single grid after the particle swarm is meshed. i It represents the probability of a particle being selected.

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