Simulation method and device for digital-analog hybrid circuit

Abstract

The invention discloses a digital-analog hybrid circuit simulation method and device, and the method comprises the steps: reading a digital circuit source file, an analog circuit source file and circuit configuration information, carrying out the analysis, and building a mixed signal hierarchical structure which comprises a digital circuit part and an analog circuit part; determining mixed signal boundaries of the mixed signal hierarchical structure, performing optimization processing on the mixed signal boundaries according to signal connection conditions among the mixed signal boundaries, and inserting corresponding signal connection or digital-to-analog conversion units among the mixed signal boundaries; the digital-to-analog conversion unit is used for signal synchronization during simulation; and splitting the optimized mixed signal hierarchical structure to obtain a digital circuit and an analog circuit which have the same circuit structure, and generating a digital circuit netlist file and an analog circuit netlist file, so that a digital simulator and an analog simulator respectively read the corresponding netlist files for simulation. And calling a communication interface to perform signal synchronization based on the digital-to-analog conversion unit.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of circuit simulation, and in particular, to a digital-analog hybrid circuit simulation method and apparatus. Background Art

[0002] A digital-analog hybrid chip is a special type of integrated circuit (IC). It consists of analog circuits and digital circuits, and can integrate analog and digital signal processing functions on the same chip. This design allows the chip to process continuously varying analog signals and discretized digital signals within the same physical package. Among them, the analog circuit is the core part, and the digital circuit is used to control the analog circuit to implement specific algorithms. The application scenarios of digital-analog hybrid chips are very extensive:

[0003] Communication field: In wireless communication and demodulation, digital-analog hybrid chips are used to receive and process analog signals and convert them into digital signals for processing. In wired communication, such as ADSL / fiber optic modems, local area networks, and wide area networks, digital-analog hybrid chips are also required to implement the conversion of analog signals to digital signals.

[0004] Media field: For operations such as audio and video encoding and decoding, signal extraction, synthesis, and noise reduction, it is necessary to convert analog signals into digital signals for editing and management on electronic devices.

[0005] Image processing field: In the application of image sensors, digital-analog hybrid chips are responsible for converting analog signals into digital signals to improve image quality, which are commonly found in products such as digital audio players, digital audio collectors, and digital audio mixers.

[0006] Other application fields: In the automotive industry, complex digital-analog hybrid chips can be used for vehicle diagnosis, driver assistance systems, and vehicle networking technologies; in the medical field, they can be used for cardiac monitoring and medical imaging processing; in the industrial field, they may be used for applications such as motor control, robot control, and automation control.

[0007] In summary, digital-analog hybrid chips not only have extensive applications in the fields mentioned above, but also play a key role in many modern electronic devices. There is a great application demand for the simulation tool software of digital-analog hybrid chips.

[0008] In the existing technical solutions, foreign EDA companies led by Synopsys, Cadence, and Siemens EDA (Mentor Graphics) have all provided simulation verification solutions for analog and digital mixed (hereinafter referred to as AMS) circuits. For example, Synopsys uses its digital simulator VCS + analog simulator XA for AMS simulation; Cadence uses its digital simulator Xcelium + analog simulator Spectre for AMS simulation. However, these tools are based on two independent and mature digital and analog simulators and are combined by establishing a synchronization mechanism inside, including two major parts: splitting the mixed-signal circuit and data synchronization in the simulation stage. However, the existing tools have the following problems:

[0009] Existing tools all need to perform automatic or manual splitting on the hierarchical structure of the circuit design, handing over the digital modules to the digital simulator and the analog modules to the analog simulator, and establishing two independent topological structures and connection relationships for the digital simulator and the analog simulator. With the increase in the complexity of circuit design, for many circuit designs with complex hierarchical structures, such as the situation where digital modules and analog modules are nested repeatedly at multiple levels, this implementation method of splitting on the hierarchical structure will lead to fragmentation of the entire circuit design, and the same signal will be cut off multiple times in the entire circuit topology, thus increasing the complexity of circuit simulation calculation and even resulting in incorrect simulation results. A large amount of additional inspection work also needs to be done when using the simulation tool to sew and merge the cut-off circuits again, which will inevitably lead to differences between the modified circuit and the original circuit, increasing the complexity of simulator design and debugging. When the simulation result is incorrect, after the circuit structure is split, neither the digital simulator nor the analog simulator can process the entire circuit information, resulting in the inability to simply use the digital simulator or the analog simulator to reproduce the fault and thus locate the problem. Further, the existing processing method of hierarchical splitting of analog and digital mixed-signal circuits will further exacerbate the fragmentation of low-power circuit design, increasing the difficulty of simulator design and the complexity of circuit debugging. Summary of the Invention

[0010] In view of the above problems, embodiments of the present invention are proposed to provide a method and device for simulating analog and digital mixed circuits that overcome the above problems or at least partially solve the above problems.

[0011] According to one aspect of the embodiments of the present invention, a method for simulating an analog and digital mixed circuit is provided, and the method includes:

[0012] Read in the digital circuit source file, analog circuit source file, and circuit configuration information for parsing, and establish a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part;

[0013] Determine the mixed-signal boundaries of the mixed-signal hierarchical structure, optimize the mixed-signal boundaries according to the signal connection conditions between the mixed-signal boundaries, and insert corresponding signal connections or digital-to-analog conversion units between the mixed-signal boundaries; the digital-to-analog conversion unit is used for signal synchronization during simulation.

[0014] Split the optimized mixed-signal hierarchical structure to obtain a digital circuit and an analog circuit with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file. Among them, the digital circuit netlist file contains digital behavior and digital signals, and the analog circuit netlist file contains analog behavior and analog signals; the mixed-signal boundaries of the digital circuit netlist file and the analog circuit netlist file contain digital-to-analog conversion units, for the digital simulator and the analog simulator to read the corresponding netlist files for simulation respectively, and call the communication interface based on the digital-to-analog conversion unit for signal synchronization.

[0015] Optionally, reading in the digital circuit source file, the analog circuit source file, and the circuit configuration information for parsing, and establishing a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part further includes:

[0016] Use a preset circuit parsing program to read in the digital circuit source file, the analog circuit source file, and the circuit configuration information;

[0017] Parse the connection information contained in the digital circuit source file, the analog circuit source file, and the circuit configuration information, and establish a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part.

[0018] Optionally, determining the mixed-signal boundaries of the mixed-signal hierarchical structure, optimizing the mixed-signal boundaries according to the signal connection conditions between the mixed-signal boundaries, and inserting corresponding signal connections or digital-to-analog conversion units between the mixed-signal boundaries further includes:

[0019] Perform topological expansion on the mixed-signal hierarchical structure, perform signal analysis on the behavior of the circuit structure according to the topological relationship of the signals, mark the signals affected by digital behavior as digital circuits, the signals affected by analog behavior as analog circuits, and the signals affected by both digital behavior and analog behavior as mixed-signal boundaries;

[0020] According to the mixed-signal boundaries, judge whether the analog circuits of the two mixed-signal boundaries are connected to analog devices, or whether the digital circuits are connected to digital behavior;

[0021] If not, insert corresponding signal connections between the two mixed-signal boundaries;

[0022] If so, insert a digital-to-analog conversion unit between the two mixed-signal boundaries.

[0023] Optionally, the optimized hybrid signal hierarchical structure is split to obtain a digital circuit and an analog circuit with the same circuit structure, and a digital circuit netlist file and an analog circuit netlist file are generated. Further included are:

[0024] According to the flattened hybrid signal hierarchical structure after optimization processing, it is mapped into a digital circuit and an analog circuit with the same circuit structure. The analog behaviors and analog signals in the digital circuit are deleted to obtain a digital circuit that retains digital behaviors, digital signals, and the digital-to-analog conversion unit. The digital behaviors and digital signals in the analog circuit are deleted to obtain an analog circuit that retains analog behaviors, analog signals, and the digital-to-analog conversion unit;

[0025] A digital circuit netlist file is generated according to the digital circuit, and an analog circuit netlist file is generated according to the analog circuit, and they are respectively submitted to a digital simulator and an analog simulator for simulation.

[0026] Optionally, the method further includes:

[0027] Read in the digital circuit source file, the analog circuit source file, the circuit configuration information, and the power consumption design file for parsing, and establish a hybrid signal hierarchical structure including the digital circuit part and the analog circuit part, as well as a voltage domain structure including the power connection relationship;

[0028] The voltage domain structure is split to obtain a digital circuit and an analog circuit including power network information and connection module information, and a digital circuit netlist file and an analog circuit netlist file including power network information are generated; the power network information includes signal voltage, current, load strength, and / or reference voltage.

[0029] Optionally, splitting the voltage domain structure to obtain a digital circuit and an analog circuit including power network information and connection module information, and generating a digital circuit netlist file and an analog circuit netlist file including power network information further includes:

[0030] According to the voltage domain structure, the analog circuit part and the digital circuit part in the voltage domain structure are split to obtain a digital circuit including the digital circuit part and an analog circuit including the analog circuit part; wherein, the digital circuit and the analog circuit also include power network information and corresponding connection module information;

[0031] A digital circuit netlist file is generated according to the digital circuit, and an analog circuit netlist file is generated according to the analog circuit, and they are respectively submitted to a digital simulator and an analog simulator for simulation.

[0032] According to another aspect of the embodiments of the present invention, a digital-analog hybrid circuit simulation device is provided, which includes:

[0033] A building block, adapted to read in digital circuit source files, analog circuit source files, and circuit configuration information for parsing, and establish a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part;

[0034] A boundary optimization module, adapted to determine the mixed-signal boundaries of the mixed-signal hierarchical structure, optimize the mixed-signal boundaries according to the signal connection conditions between the mixed-signal boundaries, and insert corresponding signal connections or digital-to-analog conversion units between the mixed-signal boundaries; the digital-to-analog conversion unit is used for signal synchronization during simulation;

[0035] A splitting module, adapted to split the optimized mixed-signal hierarchical structure to obtain a digital circuit and an analog circuit with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file. The digital circuit netlist file contains digital behavior and digital signals, and the analog circuit netlist file contains analog behavior and analog signals; the mixed-signal boundaries of the digital circuit netlist file and the analog circuit netlist file contain digital-to-analog conversion units for the digital simulator and the analog simulator to respectively read the corresponding netlist files for simulation, and call the communication interface based on the digital-to-analog conversion units for signal synchronization.

[0036] According to another aspect of the embodiments of the present invention, there is provided a computing device, including: a processor, a memory, a communication interface, and a communication bus, and the processor, the memory, and the communication interface complete communication with each other through the communication bus;

[0037] The memory is used to store at least one executable instruction, and the executable instruction causes the processor to perform the operations corresponding to the above digital-analog hybrid circuit simulation method.

[0038] According to still another aspect of the embodiments of the present invention, there is provided a computer storage medium, and at least one executable instruction is stored in the storage medium, and the executable instruction causes the processor to perform the operations corresponding to the above digital-analog hybrid circuit simulation method.

[0039] According to yet another aspect of the embodiments of the present invention, there is provided a computer program product, including at least one executable instruction, and the executable instruction causes the processor to perform the operations corresponding to the above digital-analog hybrid circuit simulation method.

[0040] The digital-analog hybrid circuit simulation method and device provided according to the embodiments of the present invention construct a hierarchical structure of mixed signals, consider the digital-analog hybrid circuit structure and signal transmission from a global perspective, optimize the mixed signal boundary, minimize the number of inserted digital-analog conversion units, and minimize the impact of the mixed signal boundary on the circuit. Through unified circuit analysis and parsing, a digital circuit and an analog circuit with the same circuit structure are obtained, thereby ensuring the consistency and integrity of signals on the digital simulator and the analog simulator, reducing the coupling between the digital simulator and the analog simulator, facilitating the compatibility of various versions of simulators, reducing the development difficulty and system overhead of the entire simulation system, and improving the usability for users.

[0041] The above description is only an overview of the technical solutions of the embodiments of the present invention. In order to be able to understand the technical means of the embodiments of the present invention more clearly, it can be implemented according to the content of the specification. And in order to make the above and other purposes, features and advantages of the embodiments of the present invention more obvious and understandable, the following specifically describes the specific implementation manners of the embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] By reading the detailed description of the preferred embodiments below, various other advantages and benefits will become clear to those of ordinary skill in the art. The drawings are only for the purpose of showing the preferred embodiments and are not considered to be a limitation of the embodiments of the present invention. And throughout the drawings, the same reference numerals are used to represent the same components. In the drawings:

[0043] Figure 1 Shows a flowchart of a digital-analog hybrid circuit simulation method according to an embodiment of the present invention;

[0044] Figure 2 Shows a schematic diagram of constructing a hierarchical structure of mixed signals;

[0045] Figure 3 Shows a signal boundary schematic diagram;

[0046] Figure 4 Shows a signal boundary optimization schematic diagram;

[0047] Figure 5 Shows a circuit splitting schematic diagram;

[0048] Figure 6 Shows a schematic diagram of converting a circuit into a netlist file for simulation by a simulator;

[0049] Figure 7 Shows a flowchart of a digital-analog hybrid circuit simulation method according to another embodiment of the present invention;

[0050] Figure 8 Shows a voltage domain structure schematic diagram;

[0051] Figure 9 shows the schematic diagrams of the first circuit and the second circuit obtained by splitting;

[0052] Figure 10 shows the structural schematic diagram of a digital - analog hybrid circuit simulation device according to an embodiment of the present invention;

[0053] Figure 11 shows the structural schematic diagram of a computing device according to an embodiment of the present invention. Detailed implementation manners

[0054] Hereinafter, exemplary embodiments of the present invention will be described in more detail with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided so that the present invention can be more thoroughly understood and the scope of the present invention can be fully conveyed to those skilled in the art.

[0055] Figure 1 shows the flowchart of a digital - analog hybrid circuit simulation method according to an embodiment of the present invention, as Figure 1 shown, the method includes the following steps:

[0056] Step S101, read in the digital circuit source file, the analog circuit source file, and the circuit configuration information for parsing, and establish a mixed - signal hierarchical structure including the digital circuit part and the analog circuit part.

[0057] In the prior art, when dealing with digital - analog hybrid circuits, they are split manually or automatically. The digital circuit part and the analog circuit part respectively enter two different simulators, namely the digital simulator and the analog simulator, for parsing and compilation, and each forms an independent circuit structure. Whether it is the digital simulator or the analog simulator, they only process their respective partial circuits, and the fragmentation is serious. Users cannot know the complete circuit, which increases the complexity of circuit debugging. Here, both the analog simulator and the digital simulator are existing software used for circuit simulation.

[0058] Based on the above problems, in this embodiment, a preset circuit parsing program can be used to read in a digital circuit source file, an analog circuit source file, and circuit configuration information. The circuit configuration information records the classification of each circuit. For example, it records that the xx circuit is an analog circuit and uses an analog description language, and the zz circuit is a digital circuit and uses a digital description language, etc. The digital circuit source file and the analog circuit source file record information such as each component, pin, port, network, circuit description, and connection relationship in the circuit. By parsing the digital circuit source file, the analog circuit source file, and the circuit configuration information, a circuit is constructed according to the connection relationship, etc., to obtain a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part. In the mixed-signal hierarchical structure, the digital circuit part and the analog circuit part can be determined according to the circuit configuration information. The connections inside the digital circuit part and the analog circuit part, and the connections between the digital circuit part and the analog circuit part are constructed according to the various information included in the digital circuit source file and the analog circuit source file. The preset circuit parsing program can use tools such as integrated circuits, which are not limited here.

[0059] As Figure 2 shown, the circuit configuration information, the digital circuit source file (the digital behavior description source file in the figure, such as Verilog, System Verilog, VHDL, Verilog-A, Verilog-AMS, etc. Among them, Verilog-A and Verilog-AMS files can also describe analog circuits), and the analog circuit source file (the analog design source file in the figure, such as SPICE, Spectre, etc.) are read in. According to the files read in, the mixed-signal hierarchical structure on the right can be obtained. Among them, the red part is the analog circuit part, and the blue part is the digital circuit part.

[0060] Step S102, determine the mixed-signal boundaries of the mixed-signal hierarchical structure. According to the signal connection situation between the mixed-signal boundaries, optimize the mixed-signal boundaries, and insert corresponding signal connections or digital-to-analog conversion units between the mixed-signal boundaries.

[0061] After obtaining the mixed-signal hierarchical result, the mixed-signal hierarchical structure can be topologically expanded. According to the topological relationship of each signal in the mixed-signal hierarchical structure, signal analysis is performed on the behavior of the circuit structure. Mark the signals affected by digital behavior as digital circuits, the signals affected by analog behavior as analog circuits, and the signals affected by both digital behavior and analog behavior as mixed-signal boundaries. As Figure 2 shown, the red part is the analog circuit part, and the blue part is the digital circuit part. By analysis, it is determined that the signal boundaries include A, B, C, D, E, F, G, H. Further analyze each signal boundary, as Figure 3As shown, signal boundaries A, B, C, and D are connected to a unified signal I, indicating that I is affected by both digital behavior and analog behavior. I is the boundary of a mixed-signal, which has the dual attributes of digital and analog signals. Signal I will appear in both digital circuits and analog circuits. E and G are only connected to two analog behaviors, so they will only appear in analog circuits. F and H are only connected to two digital behaviors, so they will only appear in digital circuits. In summary, based on the mixed-signal boundaries, it can be determined whether the analog circuits between two mixed-signal boundaries are connected to analog devices, or whether the digital circuits are connected to digital behaviors. For example, if there are analog devices such as resistors and capacitors in the analog circuits between two mixed-signal boundaries, a digital-to-analog conversion unit is inserted between the two mixed-signal boundaries. Or, if the digital circuits between two mixed-signal boundaries are connected to digital behaviors, a digital-to-analog conversion unit is inserted between the two mixed-signal boundaries. If there are neither analog devices nor digital behaviors connected between two mixed-signal boundaries, there is no need to insert a digital-to-analog conversion unit between the two mixed-signal boundaries. Only the corresponding signal connections, digital signal connections or analog signal connections, are inserted, reducing the need for multiple digital-to-analog conversions as in the prior art and avoiding the situation where the same signal is split into multiple segments. The digital-to-analog conversion unit is used for signal synchronization during simulation, such as between a digital simulator and an analog simulator, to convert an analog signal into a digital signal, or to convert a digital signal into an analog signal, etc.

[0062] Specifically, the digital circuit source file is as follows:

[0063]

[0064]

[0065] The analog circuit source file is as follows:

[0066]

[0067] The circuit configuration information is as follows:

[0068]

[0069] By reading the above files, we get as Figure 4The hybrid signal hierarchical structure shown. Among them, it includes digital circuits such as V1 and div10, and analog circuit iana. According to the above hierarchical structure, the boundaries of each hybrid signal can be determined. For example, the signal connection includes top.vdd (digital circuit) -> top.iana.VI_P (analog circuit) -> top.iana.X2.in (digital circuit). This signal crosses the digital-analog hybrid signal boundary twice, from digital circuit -> analog circuit -> digital circuit. The prior art requires two digital-to-analog (D2A) and analog-to-digital (A2D) conversions. Through judgment in this embodiment, it can be known that in the analog circuit, the signal VI_P is not connected to any analog device, so it can be determined that the signal is a digital signal, and there is no need to add the above two digital-to-analog conversion units. Instead, a digital signal connection can be directly inserted. For the signal connection top.iana.X2.out[0] (digital circuit) -> top.iana.U2_out0 (analog circuit), the digital part is connected with an assignment operation #delay out = count, which includes digital behavior; the analog part is connected to a capacitor device C1 U2_out0 0 1p, and a digital-to-analog conversion unit D2A needs to be inserted at the hybrid signal boundary. The information connection top.iana.X1.out[3] (digital circuit) -> top.iana.U1_out3 (analog circuit) is connected to a resistor device R1 in the analog circuit, and a digital-to-analog conversion unit D2A needs to be inserted at the hybrid signal boundary. The signal connection top.iana.X2.out[1] (digital circuit) -> top.iana.U2_out1 (analog circuit) crosses the digital-analog hybrid signal boundary, and there is no analog device connected to it in the analog circuit. Therefore, there is no need to insert a digital-to-analog conversion unit. The above is for illustrative purposes, and specific settings are made according to the actual implementation situation, which is not limited here.

[0070] By optimizing the mixed-signal boundary, it is possible to avoid splitting the same signal into multiple segments and performing multiple analog-to-digital conversions, thereby solving problems such as the inability of the analog simulator to converge, inconsistent numerical values of the same signal on different segments, and performance degradation introduced by redundant analog-to-digital conversion modules. For the analog-to-digital conversion unit inserted during the optimization process, when the signal is connected to the analog device, the signal value will be affected by the analysis of the analog circuit (A2D, analog-to-digital conversion), or the signal value will affect the solution of the analog circuit (D2A, digital-to-analog conversion). Depending on the different situations of the signal value, if it is driven by the digital simulator, the signal needs to load the D2A digital-to-analog conversion event; if the signal value is read by the digital simulator, the signal needs to load the A2D analog-to-digital conversion event, etc. Signals at the hierarchical analog-to-digital boundary that do not involve the analog-to-digital conversion unit still exist in the entire circuit structure, and their corresponding logical values and analog signal states are solved by the digital simulator and the analog simulator respectively. Inside the digital circuit or the analog circuit, parts that are not connected or interact with each other can be regarded as signal points inside the digital circuit or the analog circuit during simulation, and only one type of digital or analog data state exists, which will not be elaborated here.

[0071] Step S103: Split the optimized hierarchical structure of the mixed signal to obtain two digital circuits and analog circuits with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file for the digital simulator and the analog simulator to read the corresponding netlist files for simulation respectively, and synchronize the signals based on the analog-to-digital conversion unit by calling the communication interface.

[0072] After the optimization process, the hierarchical structure of the mixed signal can be split to obtain two digital circuits and analog circuits with the same circuit structure. As Figure 5 shown, the left side is the hierarchical structure of the mixed signal, which is mapped to the two digital circuits and analog circuits with the same circuit structure on the right side. Among them, the upper part on the right side is the digital circuit. After mapping, the analog behavior and analog signals in the digital circuit are deleted to obtain a digital circuit that retains the digital behavior, digital signals, and the analog-to-digital conversion unit. The lower part on the right side is the analog circuit. The digital behavior and digital signals in the analog circuit are deleted to obtain an analog circuit that retains the analog behavior, analog signals, and the analog-to-digital conversion unit. The circuit structures of the digital circuit and the analog circuit are the same, and they are vertically mapped. The missing analog part in the digital circuit matches the analog part of the analog circuit, and the missing digital part in the analog circuit matches the digital part of the digital circuit.

[0073] After obtaining the digital circuit and the analog circuit, as Figure 6As shown, a digital circuit netlist file is generated according to the digital circuit, and an analog circuit netlist file is generated according to the analog circuit, and they are respectively submitted to a digital simulator and an analog simulator for simulation. The mixed signal boundary of the digital circuit and the analog circuit includes a digital-to-analog conversion unit. When the digital simulator performs simulation and involves the analog part, or when the analog simulator performs simulation and involves the digital part, signal synchronization is performed between the digital simulator and the analog simulator through the digital-to-analog conversion unit, so as to complete the co-simulation of the overall digital-analog hybrid circuit. During the operation of the digital simulator and the analog simulator, simulation data can be synchronized to ensure the consistency and integrity of the signal on the digital simulator and the analog simulator, and it is also convenient for debugging.

[0074] According to the digital-analog hybrid circuit simulation method provided by the embodiment of the present invention, a mixed signal hierarchical structure is constructed, the digital-analog hybrid circuit structure and signal transmission are considered from a global and overall perspective, the mixed signal boundary is optimized, the insertion of the digital-to-analog conversion unit is minimized, and the influence of the mixed signal boundary on the circuit is reduced to the greatest extent. Through unified circuit analysis and parsing, a digital circuit and an analog circuit with the same circuit structure are obtained, so as to ensure the consistency and integrity of the signal on the digital simulator and the analog simulator, reduce the coupling between the digital simulator and the analog simulator, facilitate the compatibility of various versions of simulators, reduce the development difficulty and system overhead of the entire simulation system, and improve the usability of users.

[0075] Figure 7 The flowchart of the digital-analog hybrid circuit simulation method according to another embodiment of the present invention is shown, as Figure 7 shown, the method includes the following steps:

[0076] Step S701, read in the digital circuit source file, the analog circuit source file, the circuit configuration information, and the power consumption design file for parsing, and establish a mixed signal hierarchical structure including the digital circuit part and the analog circuit part, and a voltage domain structure including the power connection relationship.

[0077] When designing a digital circuit, it usually does not contain information related to the power network, and a low-power design file is also needed as a supplement to describe the power network behavior related to the digital circuit. The analog circuit design itself already includes a description of the power behavior. For a digital-analog mixed signal circuit, the description of the power behavior may overlap or even conflict with the power behavior already existing in the analog circuit design itself. To solve this problem, in this embodiment, the power consumption design file is combined with the circuit structure, and the final digital circuit netlist file and analog circuit netlist file can include power network information, and there is no need to modify the power consumption design file according to the digital-analog mixed signal circuit structure.

[0078] Specifically, as Figure 2As shown, when reading a digital circuit source file, an analog circuit source file, and circuit configuration information using a preset circuit parsing program, a power consumption design file UPF (Unified Power Format) can be read in for parsing. The power consumption design file contains a power network, voltage domain design, power supply description, etc. Based on the power consumption design file, a voltage domain structure including a digital circuit part and an analog circuit part can be established. The voltage domain structure can be as Figure 8 shown, which includes a power management unit PMU, each red analog circuit part, and the blue digital circuit part. The green lines represent the power network, and the yellow dots represent connection modules. The voltage domain structure also includes power connection relationships, and each analog circuit part, digital circuit part, etc. are connected through the power network.

[0079] Step S702: Determine the mixed signal boundaries of the mixed signal hierarchical structure. According to the signal connection conditions between the mixed signal boundaries, optimize the mixed signal boundaries, and insert corresponding signal connections or digital-to-analog conversion units between the mixed signal boundaries.

[0080] This step refers to the description in step S102 and will not be elaborated here.

[0081] Step S703: Split the optimized mixed signal hierarchical structure, and split the voltage domain structure to obtain a digital circuit and an analog circuit including power network information and connection module information, and generate a digital circuit netlist file and an analog circuit netlist file including power network information.

[0082] For splitting the mixed signal hierarchical structure, reference can be made to the description in part of step S103 and will not be elaborated here. The obtained digital circuit and analog circuit are digital circuits and analog circuits with the same circuit structure. While splitting the mixed signal hierarchical structure, the voltage domain structure is also split. In addition to the circuit structure, the obtained digital circuit and analog circuit also include power network information and connection module information.

[0083] For the splitting of the voltage domain structure, specifically, according to Figure 8 the shown voltage domain structure, split the analog circuit part and the digital circuit part in the voltage domain structure to obtain Figure 9 the shown digital circuit and analog circuit. Among them, the left side is the analog circuit, including the analog circuit part, and the right side is the digital circuit, including the digital circuit part. The digital circuit and the analog circuit also include power network information ( Figure 9 the lines in) and corresponding connection module information ( Figure 9 the yellow dots in).

[0084] Generate a digital circuit netlist file according to the digital circuit, and generate an analog circuit netlist file according to the analog circuit. The digital circuit netlist file contains digital behavior and digital signals, and the analog circuit netlist file contains analog behavior and analog signals. The mixed-signal boundary of the digital circuit netlist file and the analog circuit netlist file contains a digital-to-analog conversion unit. In addition, the digital circuit netlist file and the analog circuit netlist file also contain power network information and corresponding connection module information. The power network information includes signal voltage, current, load strength, reference voltage, etc., which are used to transmit the power network information between the connection modules during the simulation between the digital simulator and the analog simulator, and perform digital-to-analog conversion of voltage, conversion of current signals, conversion of equivalent resistances, etc. according to the reference voltage. The connection module information corresponding to the yellow dots determines the positions where conversion is required. When the digital simulator and the analog simulator execute to the corresponding yellow dot positions, they perform conversions, etc. according to the power network information.

[0085] Further, during simulation, the analog simulator runs prior to the digital simulator, that is, the simulation time position of the analog simulator is greater than or equal to that of the digital simulator. The analog circuit of the analog simulator first performs circuit initialization. At this time, if there is an analog-to-digital conversion unit and an A2D event is sent, an A2D data conversion is sent to the digital simulator; otherwise, the time that the analog simulator is currently waiting is sent, and the digital simulator is waited for to return information. After receiving the A2D data conversion or the time that the analog simulator is currently waiting, the digital circuit of the digital simulator performs digital circuit initialization. If a D2A data conversion is required, the digital simulator sends a D2A data conversion to the analog simulator; otherwise, the scheduled time of the next event of the digital simulator is sent, and the analog simulator is waited for to return information. If the analog simulator receives a D2A data conversion, it needs to perform another initialization update based on the initial value of the digital circuit. If it does not receive it, the simulation starts. The analog simulator runs continuously and does not exceed the simulation time position specified by the scheduled time of the next event of the digital simulator. During this period, if an A2D event is received, A2D synchronization is required, an A2D data conversion is sent to the digital simulator, and the return information is waited for. If there is no A2D event, when the next moment of the analog simulator exceeds the simulation time position specified by the scheduled time of the next event of the digital simulator, the analog simulator pauses, sends the time that the analog simulator is currently waiting to the digital simulator, and waits for the return information. If the analog simulation runs to an end, an event that the analog simulator has ended is sent to the digital simulator. After receiving the A2D data conversion, the digital simulator adds an A2D event at the time specified by the analog simulator on the time axis and starts the operation of the digital simulator, and does not exceed the simulation time position specified by the time that the analog simulator is currently waiting. If the digital simulator encounters a D2A event, D2A synchronization is required, a D2A data conversion is sent to the analog simulator, and the return information is waited for. If there is no D2A event, when the digital simulator runs to the moment specified by the time that the analog simulator is currently waiting, the digital circuit simulation is paused, and the scheduled time of the next event of the digital simulator at the next moment is sent to the analog simulator. If the digital simulation runs to an end, an event that the digital simulator has ended is sent to the analog simulator. If the digital simulator has no subsequent events to process, a scheduled time of the next event of the digital simulator at a maximum moment (such as -1) is sent to ensure that the analog simulator continues to run until the analog simulator ends. The above is the communication process of the analog simulator and the digital simulator for simulation according to the digital circuit netlist file and the analog circuit netlist file. The above is for illustrative purposes and is specifically set according to the implementation situation, and is not limited here.

[0086] According to the digital - analog hybrid circuit simulation method provided by the embodiments of the present invention, a voltage domain structure including power connection relationships is constructed, and based on the voltage domain structure, splitting is performed to obtain a digital circuit including a digital circuit part and an analog circuit including an analog circuit part. Based on the digital circuit netlist file and the analog circuit netlist file corresponding to the digital circuit and the analog circuit, when the digital simulator and the analog simulator run simulations, the consistency of the power supply signal during the simulation can be ensured. During the process, there is no need to separately supplement a power consumption design file for the digital circuit, nor to modify it due to the overlap and conflict with the power supply behavior of the analog circuit.

[0087] Figure 10 The structural schematic diagram of the digital - analog hybrid circuit simulation device provided by the embodiments of the present invention is shown. As Figure 10 shown, the device includes:

[0088] A construction module 1010, adapted to read in a digital circuit source file, an analog circuit source file, and circuit configuration information for parsing, and establish a mixed - signal hierarchical structure including a digital circuit part and an analog circuit part;

[0089] A boundary optimization module 1020, adapted to determine the mixed - signal boundaries of the mixed - signal hierarchical structure, and according to the signal connection situation between the mixed - signal boundaries, perform optimization processing on the mixed - signal boundaries, and insert corresponding signal connections or digital - to - analog conversion units between the mixed - signal boundaries; the digital - to - analog conversion unit is used for signal synchronization during simulation;

[0090] A splitting module 1030, adapted to split the optimized mixed - signal hierarchical structure to obtain a digital circuit and an analog circuit with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file. Among them, the digital circuit netlist file contains digital behavior and digital signals, and the analog circuit netlist file contains analog behavior and analog signals; the mixed - signal boundaries of the digital circuit netlist file and the analog circuit netlist file include digital - to - analog conversion units, for the digital simulator and the analog simulator to respectively read the corresponding netlist files for simulation, and based on the digital - to - analog conversion unit, call the communication interface for signal synchronization.

[0091] Optionally, the construction module 1010 is further adapted to:

[0092] Read in the digital circuit source file, the analog circuit source file, and the circuit configuration information by using a preset circuit parsing program;

[0093] Parse the connection information included in the digital circuit source file, the analog circuit source file, and the circuit configuration information, and establish a mixed - signal hierarchical structure including a digital circuit part and an analog circuit part.

[0094] Optionally, the boundary optimization module 1020 is further adapted to:

[0095] Perform topological expansion on the mixed-signal hierarchical structure, conduct signal analysis on the behavior of the circuit structure based on the topological relationship of signals, mark the signals affected by digital behavior as digital circuits, the signals affected by analog behavior as analog circuits, and the signals affected by both digital and analog behavior as mixed-signal boundaries;

[0096] Based on the mixed-signal boundaries, determine whether the analog circuits of two mixed-signal boundaries are connected to analog devices, or whether the digital circuits are connected to digital behavior;

[0097] If not, insert corresponding signal connections between the two mixed-signal boundaries;

[0098] If so, insert a digital-to-analog conversion unit between the two mixed-signal boundaries.

[0099] Optionally, the splitting module 1030 is further adapted to:

[0100] Map the flattened mixed-signal hierarchical structure after optimization processing into digital and analog circuits with two identical circuit structures, delete the analog behavior and analog signals in the digital circuit to obtain a digital circuit that retains digital behavior, digital signals, and the digital-to-analog conversion unit, and delete the digital behavior and digital signals in the analog circuit to obtain an analog circuit that retains analog behavior, analog signals, and the digital-to-analog conversion unit;

[0101] Generate a digital circuit netlist file based on the digital circuit, and generate an analog circuit netlist file based on the analog circuit, and submit them to a digital simulator and an analog simulator for simulation respectively.

[0102] Optionally, the device further includes: a voltage domain splitting module 1040, which is adapted to read and parse the digital circuit source file, the analog circuit source file, the circuit configuration information, and the power consumption design file, establish a mixed-signal hierarchical structure including the digital circuit part and the analog circuit part, and a voltage domain structure including the power supply connection relationship; split the voltage domain structure to obtain a digital circuit and an analog circuit including the power network information and the connection module information, and generate a digital circuit netlist file and an analog circuit netlist file including the power network information; the power network information includes signal voltage, current, load strength, and / or reference voltage.

[0103] Optionally, the voltage domain splitting module 1040 is further adapted to:

[0104] According to the voltage domain structure, split the analog circuit part and the digital circuit part in the voltage domain structure to obtain a digital circuit including the digital circuit part and an analog circuit including the analog circuit part; wherein, the digital circuit and the analog circuit also include the power network information and the corresponding connection module information;

[0105] Generate a digital circuit netlist file according to a digital circuit, and generate an analog circuit netlist file according to an analog circuit, and submit them to a digital simulator and an analog simulator for simulation respectively.

[0106] The descriptions of the above modules refer to the corresponding descriptions in the method embodiments and will not be elaborated here.

[0107] An embodiment of the present invention also provides a non-volatile computer storage medium. The computer storage medium stores at least one executable instruction, and the executable instruction can execute the operations corresponding to the digital-analog hybrid circuit simulation method in any of the above method embodiments.

[0108] An embodiment of the present application provides a computer program product. The computer program product includes at least one executable instruction or a computer program, and the executable instruction or the computer program can cause a processor to execute the operations corresponding to the digital-analog hybrid circuit simulation method in any of the above method embodiments.

[0109] Figure 11 A schematic structural diagram of a computing device according to an embodiment of the present invention is shown. Specific embodiments of the embodiment of the present invention do not limit the specific implementation of the computing device.

[0110] As Figure 11 shown, the computing device may include: a processor 1102, a communication interface 1104, a memory 1106, and a communication bus 1108.

[0111] Among them:

[0112] The processor 1102, the communication interface 1104, and the memory 1106 communicate with each other through the communication bus 1108.

[0113] The communication interface 1104 is used to communicate with network elements of other devices such as clients or other servers.

[0114] The processor 1102 is used to execute the program 1110, and specifically can execute the relevant steps in the above digital-analog hybrid circuit simulation method embodiments.

[0115] Specifically, the program 1110 may include program code, and the program code includes computer operation instructions.

[0116] The processor 1102 may be a central processing unit (CPU), or a specific application-specific integrated circuit (ASIC), or one or more integrated circuits configured to implement the embodiments of the present invention. One or more processors included in the computing device may be of the same type of processor, such as one or more CPUs; or may be of different types of processors, such as one or more CPUs and one or more ASICs.

[0117] A memory 1106 for storing a program 1110. The memory 1106 may include high-speed RAM memory and may also include non-volatile memory, such as at least one disk memory.

[0118] The program 1110 may specifically be configured to cause the processor 1102 to execute the digital-analog hybrid circuit simulation method in any of the above method embodiments. For the specific implementation of each step in the program 1110, reference may be made to the corresponding steps and units in the above digital-analog hybrid circuit simulation embodiments, which will not be elaborated herein. Those skilled in the art can clearly understand that for the sake of convenience and brevity of description, the specific working processes of the above-described devices and modules may refer to the corresponding process descriptions in the foregoing method embodiments, which will not be repeated herein.

[0119] The algorithms or displays provided herein are not inherently related to any particular computer, virtual system, or other device. Various general-purpose systems may also be used in conjunction with the teachings provided herein. The structure required to construct such systems will be apparent from the above description. In addition, the embodiments of the present invention are not directed to any specific programming language. It should be understood that the content of the embodiments of the present invention described herein can be implemented using various programming languages, and the description of a specific language above is for the purpose of disclosing the preferred embodiments of the present invention.

[0120] In the specification provided herein, a large number of specific details are set forth. However, it is understood that the embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and technologies have not been shown in detail so as not to obscure the understanding of this specification.

[0121] Similarly, it should be understood that, in order to streamline the embodiments of the present invention and assist in understanding one or more of the various inventive aspects, in the foregoing description of the exemplary embodiments of the present invention, the various features of the embodiments of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, the disclosed method should not be construed as reflecting an intention that the claimed embodiments of the present invention require more features than are expressly recited in each claim. Rather, as reflected in the following claims, the inventive aspects lie in less than all of the features of the single embodiments disclosed previously. Thus, the claims following the detailed description hereby expressly incorporate the detailed description, where each claim itself serves as a separate embodiment of the present invention.

[0122] Those skilled in the art will appreciate that the modules in the devices in the embodiments can be adaptively changed and disposed in one or more devices different from the embodiments. The modules or units or components in the embodiments can be combined into one module or unit or component, and in addition, they can be divided into multiple sub-modules or sub-units or sub-components. Except that at least some of such features and / or processes or units are mutually exclusive, any combination can be used to combine all the features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all the processes or units of any method or device so disclosed. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) can be replaced by an alternative feature that provides the same, equivalent, or similar purpose.

[0123] In addition, those skilled in the art will be able to understand that, although some of the embodiments herein include certain features included in other embodiments rather than other features, the combination of the features of different embodiments means that it is within the scope of the present invention and forms different embodiments. For example, in the following claims, any one of the claimed embodiments can be used in any combination.

[0124] Each component embodiment of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art should understand that a microprocessor or a digital signal processor (DSP) can be used in practice to implement some or all of the functions of some or all of the components according to the embodiments of the present invention. Embodiments of the present invention can also be implemented as a device or apparatus program (e.g., a computer program and a computer program product) for performing part or all of the methods described herein. Such a program implementing embodiments of the present invention can be stored on a computer-readable medium, or can be in the form of one or more signals. Such signals can be downloaded from an Internet website, or provided on a carrier signal, or in any other form.

[0125] It should be noted that the above embodiments illustrate the embodiments of the present invention rather than limit the present invention, and those skilled in the art can design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in the claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. Embodiments of the present invention can be implemented by means of hardware including several different elements and by means of a suitably programmed computer. In the unit claims listing several devices, several of these devices can be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not denote any order. These words can be interpreted as names. The steps in the above embodiments, unless otherwise specified, should not be construed as limiting the order of execution.

Claims

1. A digital-analog hybrid circuit simulation method, characterized in that the method Including: Read in the digital circuit source file, analog circuit source file, and circuit configuration information for parsing, and establish a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part; Determine the mixed-signal boundaries of the mixed-signal hierarchical structure, and optimize the mixed-signal boundaries according to the signal connection conditions between the mixed-signal boundaries, and insert corresponding signal connections or digital-to-analog conversion units between the mixed-signal boundaries; the digital-to-analog conversion unit is used for signal synchronization during simulation; Split the optimized mixed-signal hierarchical structure to obtain a digital circuit and an analog circuit with the same circuit structure, and generate a digital circuit netlist file and an analog circuit netlist file. Among them, the digital circuit netlist file contains digital behavior and digital signals, and the analog circuit netlist file contains analog behavior and analog signals; the mixed-signal boundaries of the digital circuit netlist file and the analog circuit netlist file include the digital-to-analog conversion unit, for the digital simulator and the analog simulator to read the corresponding netlist files for simulation respectively, and call the communication interface based on the digital-to-analog conversion unit for signal synchronization.

2. The method according to claim 1, wherein The step of reading in the digital circuit source file, analog circuit source file, and circuit configuration information for parsing, and establishing a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part further includes: Use a preset circuit parsing program to read in the digital circuit source file, analog circuit source file, and circuit configuration information; Parse the connection information contained in the digital circuit source file, analog circuit source file, and circuit configuration information, and establish a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part.

3. The method according to claim 1, characterized in that, The step of determining the mixed-signal boundaries of the mixed-signal hierarchical structure, and optimizing the mixed-signal boundaries according to the signal connection conditions between the mixed-signal boundaries, and inserting corresponding signal connections or digital-to-analog conversion units between the mixed-signal boundaries further includes: Perform topological expansion on the mixed-signal hierarchical structure, perform signal analysis on the behavior of the circuit structure according to the topological relationship of the signals, mark the signals affected by digital behavior as digital circuits, mark the signals affected by analog behavior as analog circuits, and mark the signals affected by both digital behavior and analog behavior as mixed-signal boundaries; According to the mixed-signal boundaries, judge whether the analog circuits of the two mixed-signal boundaries are connected to analog devices, or whether the digital circuits are connected to digital behavior; If not, insert corresponding signal connections between the two mixed-signal boundaries; If so, insert a digital-to-analog conversion unit between the two mixed-signal boundaries.

4. The method according to claim 1, characterized in that, The step of splitting the optimized mixed-signal hierarchical structure to obtain a digital circuit and an analog circuit with the same circuit structure, and generating a digital circuit netlist file and an analog circuit netlist file further includes: According to the flattened mixed-signal hierarchical structure after optimization processing, it is mapped into a digital circuit and an analog circuit with the same circuit structure. The analog behaviors and analog signals in the digital circuit are deleted to obtain a digital circuit that retains digital behaviors, digital signals, and the digital-to-analog conversion unit. The digital behaviors and digital signals in the analog circuit are deleted to obtain an analog circuit that retains analog behaviors, analog signals, and the digital-to-analog conversion unit; Generate a digital circuit netlist file according to the digital circuit, and generate an analog circuit netlist file according to the analog circuit, and submit them to a digital simulator and an analog simulator for simulation respectively.

5. The method according to any one of claims 1-4, characterized in that The method further includes: Read in the digital circuit source file, analog circuit source file, circuit configuration information, and power consumption design file for parsing, and establish a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part, and a voltage domain structure including power supply connection relationships; Split the voltage domain structure to obtain a digital circuit and an analog circuit including power supply network information and connection module information, and generate a digital circuit netlist file and an analog circuit netlist file including power supply network information; the power supply network information includes signal voltage, current, load strength, and / or reference voltage.

6. The method according to claim 5, wherein The splitting of the voltage domain structure to obtain a digital circuit and an analog circuit including power supply network information and connection module information, and generating a digital circuit netlist file and an analog circuit netlist file including power supply network information further includes: According to the voltage domain structure, split the analog circuit part and the digital circuit part in the voltage domain structure to obtain a digital circuit including the digital circuit part and an analog circuit including the analog circuit part; wherein, the digital circuit and the analog circuit also include power supply network information and corresponding connection module information; Generate a digital circuit netlist file according to the digital circuit, and generate an analog circuit netlist file according to the analog circuit, and submit them to a digital simulator and an analog simulator for simulation respectively.

7. A digital-analog hybrid circuit simulation device, characterized in that The device includes: A construction module, adapted to read in the digital circuit source file, analog circuit source file, and circuit configuration information for parsing, and establish a mixed-signal hierarchical structure including a digital circuit part and an analog circuit part; A boundary optimization module, adapted to determine the mixed-signal boundary of the mixed-signal hierarchical structure, optimize the mixed-signal boundary according to the signal connection situation between the mixed-signal boundaries, and insert corresponding signal connections or digital-to-analog conversion units between the mixed-signal boundaries; the digital-to-analog conversion unit is used for signal synchronization during simulation; A splitting module, suitable for splitting an optimized hybrid signal hierarchical structure to obtain a digital circuit and an analog circuit with the same circuit structure, and generating a digital circuit netlist file and an analog circuit netlist file. The digital circuit netlist file contains digital behaviors and digital signals, and the analog circuit netlist file contains analog behaviors and analog signals. The hybrid signal boundary of the digital circuit netlist file and the analog circuit netlist file includes the digital-to-analog conversion unit, for a digital simulator and an analog simulator to respectively read the corresponding netlist files for simulation, and based on the digital-to-analog conversion unit, call a communication interface for signal synchronization.

8. A computing device, characterized in that, Comprising: A processor, a memory, a communication interface and a communication bus. The processor, the memory and the communication interface complete communication with each other through the communication bus. The memory is used for storing at least one executable instruction, and the executable instruction causes the processor to perform operations corresponding to the digital-analog hybrid circuit simulation method according to any one of claims 1-6.

9. A computer storage medium, characterized in that, At least one executable instruction is stored in the storage medium, and the executable instruction causes the processor to perform operations corresponding to the digital-analog hybrid circuit simulation method according to any one of claims 1-6.

10. A computer program product, characterized in that, Comprising at least one executable instruction, and the executable instruction causes the processor to perform operations corresponding to the digital-analog hybrid circuit simulation method according to any one of claims 1-6.

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