Integrated circuit chip thermal neutron soft error source positioning method

Abstract

The invention relates to the technical field of integrated circuits, and discloses an integrated circuit chip thermal neutron soft error source positioning method, which comprises the following steps: carrying out slice analysis on a chip to obtain a geometric structure and element distribution and content data; constructing a chip simulation model based on the geometric structure and the element distribution and content data; based on the chip simulation model, taking the thermal neutrons as incident particles, and performing interaction simulation of the integrated circuit chip and the thermal neutrons; based on interaction simulation, the type, energy, motion angle and particle initial source of secondary heavy ions generated on the surface of the integrated circuit chip are analyzed, and the thermal neutron soft error source of the integrated circuit chip is positioned. According to the method, the positioning precision of the soft error source of the thermal neutrons of the chip is improved, effective support is provided for chip design, the reliability and stability of the chip are greatly improved, and the strict requirements for high performance and high reliability of the chip can be better met.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and specifically to a method for locating the source of thermal neutron soft errors in integrated circuit chips. Background Art

[0002] In the field of integrated circuits, with the continuous improvement of chip integration and the increasingly wide range of application scenarios, the reliability of integrated circuit chips faces many challenges, among which the soft error problem caused by thermal neutrons is particularly prominent.

[0003] In some special environments, chips are frequently exposed to thermal neutron radiation environments. Thermal neutrons interact with the elements in the chips to generate secondary heavy ions, which in turn cause soft errors in the chips, such as data flipping, logic errors, etc. These soft errors may cause system failures, seriously affect the normal operation of the equipment, and even lead to safety accidents.

[0004] At present, although certain progress has been made in the research on thermal neutron soft errors in integrated circuit chips, there are still significant deficiencies. On the one hand, when analyzing the source of thermal neutron soft errors in chips, existing technologies lack systematic and comprehensive methods. Some methods can only detect the surface or part of the area of the chip, and cannot penetrate into the internal layer structures of the chip, making it difficult to accurately obtain the distribution and content of trace elements, resulting in a low positioning accuracy of the source of thermal neutron soft errors. On the other hand, in terms of simulation, existing simulation models do not fully consider the actual geometric structure and element distribution of the chip, resulting in a large deviation between the simulation results and the actual situation, and unable to provide effective support for the anti-radiation design of the chip.

[0005] The Chinese invention patent "A Method and System for Simulating and Injecting Soft Error Faults in Secondary Equipment of Substations" with the application publication number CN119494248A focuses on the simulation injection and statistical analysis of soft errors at the secondary equipment level of substations, and evaluates the reliability of equipment by modifying the data of memory units and monitoring abnormal program behaviors. However, this solution does not involve the microscopic structure analysis of integrated circuit chips, does not combine the chip material composition with the thermal neutron nuclear reaction mechanism, and cannot accurately locate the initial source of soft errors from the physical level of the chip. It is limited to the simulation of equipment function-level faults and lacks in-depth tracing of the essential causes of soft errors.

[0006] Therefore, there is an urgent need for a new technical solution for locating the source of thermal neutron soft errors in integrated circuit chips to accurately analyze the internal structure of the chip, accurately determine the distribution and content of trace elements, and establish a simulation model that highly conforms to the actual situation, so as to achieve the accurate positioning of the source of thermal neutron soft errors in integrated circuit chips, improve the reliability and stability of the chips, and meet the requirements of high performance and high reliability of chips in special fields. Summary of the Invention

[0007] The purpose of this application is to provide a method for locating the sources of thermal neutron soft errors in integrated circuit chips, so as to solve the technical problems presented in the above background art.

[0008] To achieve the above object, this application discloses the following technical solutions: A method for locating the sources of thermal neutron soft errors in integrated circuit chips, the location method comprising:

[0009] S1: Perform slicing analysis on the integrated circuit chip to obtain data on the geometric structure, element distribution, and content of the chip;

[0010] S2: Based on the geometric structure and the element distribution and content data, construct a chip simulation model;

[0011] S3: Based on the chip simulation model, use thermal neutrons as incident particles to perform simulation of the interaction between the integrated circuit chip and thermal neutrons;

[0012] S4: Based on the interaction simulation, analyze the types, energies, movement angles, and initial particle sources of the secondary heavy ions generated on the surface of the integrated circuit chip to locate the sources of thermal neutron soft errors in the integrated circuit chip.

[0013] Preferably, the slicing analysis includes:

[0014] Use a scanning electron microscope to collect the geometric shapes, thicknesses, and interfacial conditions between different layers of the integrated circuit chip, and obtain the geometric structure based on the collected results.

[0015] Preferably, the slicing analysis further includes:

[0016] Use an energy-dispersive X-ray spectrometer to perform qualitative and quantitative analysis on various elements in different layers of the integrated circuit chip, and obtain the element distribution and content data based on the results of the qualitative and quantitative analysis.

[0017] Preferably, the slicing analysis further includes:

[0018] Use secondary ion mass spectrometry analysis method to perform qualitative and quantitative analysis on various trace elements in different layers of the integrated circuit chip, and expand the element distribution and content data based on the results of the qualitative and quantitative analysis.

[0019] Preferably, the construction of the chip simulation model includes:

[0020] Use Monte Carlo tools to construct a chip simulation model based on the geometric structure and the element distribution and content data.

[0021] Preferably, the location of the sources of thermal neutron soft errors in the integrated circuit chip specifically includes:

[0022] Determine the preliminary position of the thermal neutron soft error source in the integrated circuit chip in the geometric structure based on the initial source of the particles.

[0023] Preferably, the method for locating the thermal neutron soft error source of the integrated circuit chip further includes:

[0024] Verify the preliminary position based on the species, the energy, and the movement angle, and locate the thermal neutron soft error source of the chip.

[0025] Preferably, the preliminary position is determined by the following formula:

[0026]

[0027] Where S is the position determined based on the initial source of the particles, P1(S) is the probability of the thermal neutron soft error source of the integrated circuit chip, the initial position S, and P(S) is the prior probability of the thermal neutron reaction occurring at position S, and N S is the number of secondary ions generated at position S in the simulation; N total is the total number of secondary ions generated in the entire area of the chip in the simulation.

[0028] Beneficial effects: The method for locating the thermal neutron soft error source of the integrated circuit chip in this application, through slicing analysis, uses a variety of analysis means to accurately analyze the internal structure of the chip. It can not only obtain geometric structure information, but also accurately determine the element distribution and content of each layer, including key trace elements, making up for the defect that the prior art cannot deeply detect the inside of the chip; based on the chip simulation model constructed thereby, with the help of the Monte Carlo tool, the actual situation of the chip is fully considered, overcoming the problem that the prior simulation model has a large deviation from the actual situation; through a comprehensive analysis of the secondary heavy ions generated by the simulation of the interaction between the chip and thermal neutrons, the thermal neutron soft error source can be accurately located; thus improving the positioning accuracy of the thermal neutron soft error source of the chip, providing effective support for chip design, greatly enhancing the reliability and stability of the chip, and better meeting the stringent requirements for high performance and high reliability of chips in special fields. Description of the Drawings

[0029] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0030] Figure 1 It is a flowchart of the method for locating the thermal neutron soft error source of the integrated circuit chip provided by the embodiment of the present application. Detailed Embodiments

[0031] The technical solutions in the embodiments of the present application will be described clearly and completely below. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts shall fall within the protection scope of the present application.

[0032] In this article, the term "including" is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such a process, method, article or device. Without more limitations, the elements defined by the statement "including..." do not exclude the existence of other identical elements in the process, method, article or device including the said elements.

[0033] This embodiment discloses a method for locating the source of thermal neutron soft errors in an integrated circuit chip as Figure 1 shown. The location method includes:

[0034] S1: Slice and analyze the integrated circuit chip to obtain the geometric structure, element distribution and content data of the chip;

[0035] S2: Construct a chip simulation model based on the geometric structure, element distribution and content data;

[0036] S3: Based on the chip simulation model, use thermal neutrons as incident particles to perform the interaction simulation between the integrated circuit chip and thermal neutrons;

[0037] S4: Based on the interaction simulation, analyze the types, energies, movement angles of the secondary heavy ions generated on the surface of the integrated circuit chip and the initial source of the particles to locate the source of thermal neutron soft errors in the integrated circuit chip.

[0038] Through the above, the accurate acquisition of the geometric structure, element distribution and content data of the integrated circuit chip is realized through slice analysis, making up for the defect that the prior art cannot deeply detect the inside of the chip; the chip simulation model constructed based on this overcomes the problem of large deviation between the existing simulation model and the actual situation; through the comprehensive analysis of the secondary heavy ions generated by the interaction simulation between the chip and thermal neutrons, the source of thermal neutron soft errors can be accurately located; thus improving the location accuracy of the source of thermal neutron soft errors in the chip, providing effective support for chip design, greatly enhancing the reliability and stability of the chip, and better meeting the stringent requirements for high performance and high reliability of chips in special fields. It should be noted that the special fields in this embodiment can be but are not limited to the aerospace field and the nuclear energy field, etc.

[0039] Specifically, the slice analysis includes:

[0040] Using a scanning electron microscope, the geometries, thicknesses of different layers of an integrated circuit chip, and the interface conditions between layers are collected, and a geometric structure is obtained based on the collected results.

[0041] By the above, using an existing scanning electron microscope (SEM) to collect the chip geometric structure, the geometries, thicknesses of different layers of the chip, and the interlayer interface conditions are obtained through high-resolution imaging, solving the problem of incomplete analysis of the internal microstructure of the chip in the prior art, enabling the subsequent constructed simulation model to accurately reflect the actual layered structure of the chip, providing a reliable geometric parameter basis for the simulation of thermal neutrons in each layer of the chip, thereby improving the accuracy of the simulation of the interaction between the chip and thermal neutrons, and indirectly improving the accuracy of soft error source localization.

[0042] Specifically, the section analysis further includes:

[0043] Using an energy-dispersive X-ray spectrometer, qualitative and quantitative analyses are performed on various elements in different layers of the integrated circuit chip, and element distribution and content data are obtained based on the results of the qualitative and quantitative analyses.

[0044] By the above, through an existing energy-dispersive X-ray spectrometer (EDS) for qualitative and quantitative analysis of the elements in each layer of the chip, the composition ratios of various elements can be accurately determined, thus making up for the defect of missing element content data in the prior art, ensuring that the material parameters of the chip simulation model are completely matched with the actual chip, avoiding calculation errors of the thermal neutron reaction cross section caused by composition data deviation, providing true and reliable basic data for the statistics of secondary heavy ion yields in subsequent Monte Carlo simulations, and fundamentally improving the scientificity of soft error source analysis.

[0045] Specifically, the section analysis further includes:

[0046] Using secondary ion mass spectrometry analysis method, qualitative and quantitative analyses are performed on various trace elements in different layers of the integrated circuit chip, and the element distribution and content data are expanded based on the results of the qualitative and quantitative analyses.

[0047] As described above, the existing secondary ion mass spectrometry (SIM) is introduced to analyze trace elements. By utilizing its high sensitivity and three-dimensional imaging capabilities, precise positioning of elements with high thermal neutron reaction cross-sections such as boron (B) and nitrogen (N) in the chip is achieved, solving the problem of insufficient detection accuracy of trace element distribution in the prior art. It realizes further expansion of element content and distribution data, enabling the simulation model to accurately identify thermal neutrons, providing direct evidence at the microscopic level for tracing the initial source of secondary heavy ions, and significantly enhancing the pertinence of soft error source localization. It should be noted that in this embodiment, the acquisition of element content and distribution is achieved based on both EDS and SIM. However, SIM is more precise in analyzing trace elements, and trace elements have higher value for soft error localization. Therefore, based on EDS, SIM is used to further improve the accuracy of element analysis.

[0048] Specifically, the construction of the chip simulation model includes:

[0049] Using Monte Carlo tools, a chip simulation model is constructed based on geometric structure, element distribution, and content data.

[0050] As described above, an existing Monte Carlo tool is used to construct a simulation model. Based on the actual geometric structure, element content, and distribution data of the chip, refined simulation of the actual situation of thermal neutrons is realized, thus overcoming the drawback of the existing simulation model relying on simplified material parameters. By statistically calculating the nuclear reaction probabilities of thermal neutrons with each layer of elements, especially boron and nitrogen elements, accurate prediction of the types, energies, and movement trajectories of secondary heavy ions is achieved. Based on the advantages of randomness and statistics of Monte Carlo tools, it is ensured that the simulation results can truly reflect the physical processes of the chip in a thermal neutron environment, providing reliable simulation data for subsequent secondary heavy ion analysis, and enabling the soft error source localization to shift from empirical speculation to accurate traceability based on physical mechanisms.

[0051] Specifically, locating the source of thermal neutron soft errors in an integrated circuit chip specifically includes:

[0052] Based on the initial source of the particles, determine the preliminary position of the source of thermal neutron soft errors in the integrated circuit chip in the geometric structure.

[0053] As a preferred implementation manner of this embodiment, use a preset preliminary position probability calculation formula to calculate the probability P1(S) that this preliminary position is the source of thermal neutron soft errors in the integrated circuit chip. The preliminary position probability calculation formula is:

[0054]

[0055] Where:

[0056] S is the position determined based on the initial source of the particles. Exemplarily, it can be a certain layer or a certain area of the chip;

[0057] P(S) is the prior probability of a thermal neutron reaction occurring at position S. This prior probability is an empirical value formulated based on the elemental content obtained from slice analysis and the corresponding reaction cross-section, combined with common knowledge known to those skilled in the art. Exemplarily, if position S is a high cross-section area where boron elements exist, then the corresponding P(S) = 0.8;

[0058] N S is the number of secondary ions generated at position S in the simulation;

[0059] N total is the total number of secondary ions generated in the entire area of the chip in the simulation.

[0060] Through the above, based on the initial source of particles, a probability analysis of the preliminary position is carried out, providing a data basis for accurately determining the soft error position.

[0061] Specifically, locating the source of thermal neutron soft errors in an integrated circuit chip further includes:

[0062] Based on the type, energy, and movement angle, verify the preliminary position to locate the source of thermal neutron soft errors in the chip.

[0063] In a specific application of this embodiment, based on the statistics of the type, energy, movement angle, and initial source of secondary heavy ions, multi-dimensional parameters are provided for analyzing and establishing a direct correlation between thermal neutron reactions and soft errors, thus solving the deficiency of only analyzing the energy or type of particles singly. By tracing the initial source position of secondary ions, the specific position where the thermal neutron nuclear reaction occurs can be directly located. In a simple example, the initial source position can be a certain layer and area of the chip; combining the energy and movement angle of secondary heavy ions, it is judged whether the ion can reach the sensitive node and trigger a soft error. Locating the source of soft errors based on the multi-dimensional statistical results of secondary heavy ions, through the correlation of particle type, energy, movement angle, and initial source, a complete traceability logic is formed. Thus, the thermal neutron soft error is systematically traced to the specific material layer or element distribution area of the chip, and the contribution degree of each area to the soft error is quantified.

[0064] As a preferred implementation manner of this embodiment, use a preset preliminary position probability calculation formula to optimize the probability P2(S) of the preliminary position being the source of thermal neutron soft errors in the integrated circuit chip. The optimized probability calculation formula is:

[0065] P2(S) = P1(S) * P(C|S) * P(E|S) * P(θ|S)

[0066] Where:

[0067] C is the type of secondary heavy ions at position S;

[0068] E is the energy of the secondary heavy ion at position S, and at this time, the energy of the secondary heavy ion is greater than or equal to the critical energy of a preset sensitive node, and the critical energy of this sensitive node is an empirical value well-known to those skilled in the art;

[0069] θ is the movement angle at position S, and at this time, it satisfies that the movement angle of the secondary heavy ion belongs to the angular range pointing to the sensitive node, and the angular range of this sensitive node is an empirical value well-known to those skilled in the art;

[0070] P(C|S) is the conditional probability of generating corresponding types of ions when the target element is contained at position S;

[0071] P(E|S) is the probability of secondary heavy ions whose energy at position S is greater than or equal to the critical energy of a preset sensitive node;

[0072] P(θ|S) is the probability that the movement angle of the secondary heavy ion generated at position S belongs to the angular range pointing to the sensitive node.

[0073] In a simple example, P(S) of a boron-containing layer (position S) of a chip is 0.8, and the proportion of secondary heavy ions generated in this layer in the simulation Then the preliminary positioning probability P1(S) = 0.56, which means that based on the initial source of the particles, there is a 56% probability that this position S is the preliminary source of soft errors. Further, based on the analysis of the type, energy, and movement angle, the corresponding P(C|S) = 1; P(E|S) = 0.9, P(θ|S) = 0.6, then the verified probability P2(S) = 0.3024, which means that after verification by combining the type, energy, and movement angle of the secondary heavy ions, there is a final 30.24% probability that this position S is located as the real source of soft errors.

[0074] By the above, the probability of the preliminary position is further optimized, and fundamentally, the ability to locate the source of soft errors caused by thermal neutrons in the chip is improved.

[0075] In a simple example, in this embodiment, the integrated circuit chip is sliced and analyzed. SEM and EDS are used to determine the composition and thickness of different layers of the chip. Further, the SIM analysis method is used to determine the distribution and content of typical trace elements such as B and N. The reaction cross-sections of trace elements such as B and N with thermal neutrons are relatively high. According to the size and composition of the chip, a chip simulation model is further established using a Monte Carlo tool, with thermal neutrons as incident particles, to carry out the simulation of the interaction between the chip and thermal neutrons, and to statistically analyze information such as the type, energy, movement angle of secondary heavy ions generated on the chip surface, and the initial source of the particles. The secondary heavy ions will cause soft errors in the chip, and thus the source of soft errors caused by thermal neutrons in the chip can be located.

[0076] In summary, the method for locating the thermal neutron soft error source of the integrated circuit chip in this embodiment precisely analyzes the internal structure of the chip through slicing analysis and uses various analysis means. It can not only obtain geometric structure information, but also accurately determine the distribution and content of elements in each layer, including key trace elements, making up for the defect that the prior art cannot deeply detect the inside of the chip. Based on this, the constructed chip simulation model fully considers the actual situation of the chip with the help of Monte Carlo tools, overcoming the problem of large deviation between the existing simulation model and the actual situation. By comprehensively analyzing the secondary heavy ions generated by the simulation of the interaction between the chip and thermal neutrons, the thermal neutron soft error source can be accurately located. Thus, the positioning accuracy of the thermal neutron soft error source of the chip is improved, providing effective support for chip design, greatly enhancing the reliability and stability of the chip, and better meeting the stringent requirements for high performance and high reliability of chips in special fields.

[0077] In the embodiments provided in this application, it should be understood that the embodiments described here can be implemented in hardware, software, firmware, middleware, code, or any appropriate combination thereof. For hardware implementation, the processor can be implemented in one or more of the following units: application specific integrated circuit (ASIC), digital signal processor (DSP), digital signal processing device (DSPD), programmable logic device (PLD), field programmable gate array (FPGA), processor, controller, microcontroller, microprocessor, or other electronic units designed to implement the functions described here, or a combination thereof. For software implementation, part or all of the processes of the embodiments can be completed by a computer program instructing the relevant hardware. When implemented, the above program can be stored in a computer-readable storage medium or transmitted as one or more instructions or codes on a computer-readable storage medium. The computer-readable storage medium includes computer storage media and communication media, where the communication media includes any medium that facilitates the transmission of a computer program from one place to another. The storage media can be any available medium that can be accessed by a computer. The computer-readable storage medium can include, but is not limited to, RAM, ROM, EEPROM, CD-ROM, or other optical disk storage, magnetic disk storage media, or other magnetic storage devices, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer.

[0078] Finally, it should be noted that the above are only the preferred embodiments of this application and are not used to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, for those skilled in the art, they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included in the protection scope of this application.

Claims

1. A method for locating the source of thermal neutron soft errors in an integrated circuit chip, characterized in that, The positioning method includes: S1: Performing slicing analysis on the integrated circuit chip to obtain data on the chip's geometric structure, element distribution, and content; S2: Constructing a chip simulation model based on the geometric structure and the element distribution and content data; S3: Based on the chip simulation model, using thermal neutrons as incident particles to simulate the interaction between the integrated circuit chip and thermal neutrons; S4: Based on the interaction simulation, analyzing the types, energies, movement angles, and initial particle sources of the secondary heavy ions generated on the surface of the integrated circuit chip to locate the source of thermal neutron soft errors in the integrated circuit chip.

2. The method for locating the thermal neutron soft error source of an integrated circuit chip according to claim 1, characterized in that, The slicing analysis includes: Using a scanning electron microscope to collect the geometric shapes, thicknesses, and interface conditions between different layers of the integrated circuit chip, and obtaining the geometric structure based on the collected results.

3. The method for locating the thermal neutron soft error source of an integrated circuit chip according to claim 1, wherein The slicing analysis further includes: Using an energy-dispersive X-ray spectrometer to qualitatively and quantitatively analyze various elements in different layers of the integrated circuit chip, and obtaining the element distribution and content data based on the results of the qualitative and quantitative analysis.

4. The method for locating the thermal neutron soft error source of an integrated circuit chip according to claim 1, characterized in that The slicing analysis further includes: Using secondary ion mass spectrometry analysis method to qualitatively and quantitatively analyze various trace elements in different layers of the integrated circuit chip, and expanding the element distribution and content data based on the results of the qualitative and quantitative analysis.

5. The method for locating the thermal neutron soft error source of an integrated circuit chip according to claim 1, wherein The construction of the chip simulation model includes: Using a Monte Carlo tool to construct a chip simulation model based on the geometric structure and the element distribution and content data.

6. The method for locating the thermal neutron soft error source of an integrated circuit chip according to claim 1, wherein The locating of the source of thermal neutron soft errors in the integrated circuit chip specifically includes: Determining the preliminary position of the source of thermal neutron soft errors in the integrated circuit chip in the geometric structure based on the initial particle source.

7. The method for locating the thermal neutron soft error source of an integrated circuit chip according to claim 6, wherein The locating of the source of thermal neutron soft errors in the integrated circuit chip further includes: Based on the type, energy, and movement angle, verifying the preliminary position to locate the source of thermal neutron soft errors in the chip.

8. The method for locating the thermal neutron soft error source of an integrated circuit chip according to claim 6 or 7, characterized in that, The preliminary position is determined by the following formula: Wherein, S is the position determined based on the initial source of particles, P1(S) is the probability of the thermal neutron soft error source of the integrated circuit chip, the initial position S is the prior probability of the thermal neutron reaction occurring at position S, and N S is the number of secondary ions generated at position S in the simulation; N total is the total number of secondary ions generated in the entire area of the chip in the simulation.

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