Dynamic power consumption optimization method, electronic device and storage medium

Abstract

The present invention belongs to the field of electronic design automation technology and proposes a dynamic power consumption optimization method, electronic device, and storage medium. The method includes: obtaining a circuit design and determining a specific type of starting point in the circuit design; starting from the starting point, backward traversing the circuit design along the signal propagation direction to determine circuit branch structure information and a specific type of end point in the circuit design; starting from the end point, establishing an ODC expression, forward traversing the circuit design in the opposite direction of signal propagation, and during the forward traversal, propagating the ODC expression in the circuit design based on the circuit branch structure information until the ODC distribution of the circuit design is determined; and dynamically optimizing the circuit design based on the ODC distribution. The present invention can quickly and efficiently propagate the ODC expression throughout the entire circuit design, so that designers can optimize dynamic power consumption through the ODC distribution.

Description

Technical Field

[0001] The present invention relates to the technical field of electronic design automation, and in particular to a dynamic power consumption optimization method, electronic equipment and storage medium. Background Art

[0002] With the advancement of manufacturing technology and design technology, the design methods of electronic systems have undergone profound changes. From Computer Aided Design (CAD), Computer Aided Engineering (CAE) to Electronic Design Automation (EDA), the degree of design automation has become increasingly higher, and the complexity of design has also become increasingly stronger.

[0003] Integrated circuit (IC) EDA refers to a design methodology that uses electronic design automation software to complete the functional design, synthesis, verification, and physical design (including layout, routing, layout, and design rule checking) of very large-scale integrated circuit chips. EDA technology has become a powerful tool in modern electronic design. Without EDA support, the design and manufacture of very large-scale integrated circuits would be unimaginable. IC designers rely on EDA tools to develop complex integrated circuits with hundreds of thousands to tens of billions of transistors, reducing design deviations, improving tape-out success rates, and reducing tape-out costs.

[0004] With the advancement of chip design technology, power consumption has become increasingly important. Chip power consumption primarily consists of static power and dynamic power. Static power primarily stems from leakage current and can be optimized through transistor manufacturing processes and power management. Dynamic power is the power consumed during chip operation, including when the input state of a logic gate changes, during signal transmission, and when driving a load. Typically, dynamic power accounts for the majority of total power consumption, so the primary goal of improving chip power consumption is to reduce dynamic power.

[0005] The industry has been trying to find ways to further explore and use lower-cost methods to further reduce dynamic power consumption. In related technologies, the following methods are generally used to optimize dynamic power consumption:

[0006] Method 1: Dynamic voltage and frequency adjustment. This method dynamically adjusts voltage and frequency based on workload. Reducing frequency and voltage can significantly reduce power consumption. When the load is low, frequency and voltage are reduced, thereby improving energy efficiency.

[0007] Method 2: Multi-voltage domain management dynamically monitors the working status of different modules and adjusts the voltage dynamically according to load demand. This way, when the module is idle, the voltage can be reduced and when needed, the voltage can be increased;

[0008] Method three is to reduce switching activities through circuit design, such as optimizing the number of logic gates, eliminating redundant logic, optimizing data paths, etc., to reduce dynamic power consumption caused by logic changes.

[0009] However, the above traditional dynamic power optimization solutions have the following problems:

[0010] For method 1, dynamic voltage and frequency adjustment requires the integration of a voltage regulator module and a dynamic clock generator, which increases chip area and design cost. Frequent voltage and frequency adjustments may cause temperature fluctuations, affecting the stability of the thermal design.

[0011] For the second approach, multi-voltage domain management complicates circuit design. Designers need to consider issues such as the relationship between different voltage domains, timing matching, and signal integrity, which increases the difficulty of design and verification.

[0012] Regarding the third method, which is to reduce switching activity by changing the circuit design, this method will also increase new design difficulties because changing the logic on the data path may cause new timing problems. Summary of the Invention

[0013] The present invention provides a dynamic power consumption optimization method, electronic device, and storage medium to at least address the problem of low efficiency and difficulty in reducing chip dynamic power consumption in related technologies. The technical solution of the present invention is as follows:

[0014] According to a first aspect of the present invention, a dynamic power consumption optimization method is provided, which is applied to electronic design automation software, and includes: obtaining a circuit design and determining a starting point of a specific type in the circuit design; starting from the starting point, traversing the circuit design backward along the signal propagation direction to determine circuit branch structure information and a specific type of end point in the circuit design; starting from the end point, establishing an ODC expression, traversing the circuit design forward in the reverse signal propagation direction, and in the process of the forward traversal, propagating the ODC expression in the circuit design based on the circuit branch structure information until the ODC distribution of the circuit design is determined; and dynamically optimizing the circuit design based on the ODC distribution.

[0015] According to a second aspect of the present invention, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions, wherein the processor-executable instructions, when executed by the processor, prompt the processor to execute the dynamic power consumption optimization method according to the present invention.

[0016] According to a third aspect of the present invention, a computer-readable storage medium is provided. When instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to execute the dynamic power consumption optimization method according to the present invention.

[0017] The technical solution provided by the present invention brings at least the following beneficial effects:

[0018] The present invention can first perform a backward traversal at the starting point of the circuit design to find all the end points in the design, and then forward propagate the ODC expression from these end points. Finally, when the forward propagation is completed in the entire design, the ODC distribution of the entire design can be obtained, thereby providing the designer with an optimization direction for dynamic power consumption.

[0019] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present invention, and together with the description are used to explain the principles of the present invention, and do not constitute an improper limitation of the present invention.

[0021] Figure 1 is a flow chart illustrating a dynamic power consumption optimization method according to an exemplary embodiment of the present invention;

[0022] Figure 2 is a schematic diagram illustrating a backward traversal according to an exemplary embodiment of the present invention;

[0023] Figure 3 is a schematic diagram illustrating a forward traversal according to an exemplary embodiment of the present invention;

[0024] Figure 4 is a flowchart illustrating propagation of ODC expressions according to an exemplary embodiment of the present invention;

[0025] Figure 5 is a schematic diagram illustrating an ODC generation point according to an exemplary embodiment of the present invention;

[0026] Figure 6 is a schematic diagram illustrating a specific logic device according to an exemplary embodiment of the present invention;

[0027] Figure 7is another schematic diagram illustrating a specific logic device according to an exemplary embodiment of the present invention;

[0028] Figure 8 is a schematic diagram showing the structure of an ODC expression according to an exemplary embodiment of the present invention;

[0029] Figure 9 is a schematic diagram illustrating a non-specific logic device according to an exemplary embodiment of the present invention;

[0030] Figure 10 is a schematic diagram illustrating a fan-out type combinational logic device according to an exemplary embodiment of the present invention;

[0031] Figure 11 is a block diagram illustrating an electronic device according to an exemplary embodiment of the present invention. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the technical solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings.

[0033] It should be noted that the steps in the description and drawings of the present invention are not limited to the specific order or sequential sequence described. It should be understood that the steps used in this manner are interchangeable where appropriate, so that the embodiments of the present invention described herein can be implemented in sequences other than those illustrated or described herein. The implementations described in the following exemplary embodiments are not intended to represent all implementations consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0034] RTL (Register Transfer Level) is an important level of abstraction in digital circuit design. At this level, the design focuses primarily on the transfer of data between registers and their operation, rather than the specific circuit implementation details. In addition to the methods for reducing dynamic power consumption described in the related technologies mentioned above, clock gating can effectively reduce unnecessary dynamic power consumption in RTL-level chip design by enabling or disabling clock signals as needed. For example, a wide flop is a trigger with a wide data bus in RTL, also known as a wide (or multi-bit) trigger. The word "wide" here generally refers to the bit width of the trigger, that is, the number of bits it can store. If clock gating can be used to properly switch it, dynamic power consumption can be reduced.

[0035] ODC (Observability Don't Care) is a state in which a register's output cannot be observed by subsequent paths. Under certain conditions, if data is not visible at the output, it becomes "don't care" or "non-observable." This condition is called an ODC condition. Using the ODC conditions of related logic devices to properly control their switching effectively reduces dynamic power consumption. For example, when an ODC condition exists on a working path within a wide flop, controlling the switching of the wide flop using this condition can effectively reduce dynamic power consumption along the wide flop path. To properly use dynamic clock gating to switch the wide flop, it is necessary to identify all ODC conditions in the design. However, with today's complex designs often containing hundreds of millions of gates, efficiently and quickly identifying ODC conditions and using them to reduce dynamic power consumption has become a major challenge. The industry has been continuously searching for lower-cost solutions.

[0036] In view of the above problems, an exemplary embodiment of the present invention proposes a dynamic power consumption optimization method, an electronic device, and a computer-readable storage medium, so as to find the ODC conditions in the circuit design through a new method and propagate them throughout the design, so as to effectively reduce the dynamic power consumption of the design and provide designers with ideas for optimizing the chip, thereby solving or at least alleviating the above problems.

[0037] In a first aspect of an exemplary embodiment of the present invention, a dynamic power consumption optimization method is provided. Figures 1 to 11 Provide a detailed description.

[0038] According to an exemplary embodiment of the present invention, a dynamic power consumption optimization method is applicable to electronic design automation (EDA) software. A user terminal can load the EDA software so that the user terminal can obtain a circuit design and determine a specific type of starting point in the circuit design; starting from the starting point, the circuit design is traversed backward along the signal propagation direction to determine circuit branch structure information and a specific type of end point in the circuit design; starting from the end point, an ODC expression is established, and the circuit design is traversed forward in the reverse direction of signal propagation. During the forward traversal, the ODC expression is propagated in the circuit design based on the circuit branch structure information until the ODC distribution of the circuit design is determined; based on the ODC distribution, the circuit design is dynamically optimized for power consumption.

[0039] This method can first perform a backward traversal at the starting point of the circuit design to find all the end points in the design, and then forward propagate the ODC expression from these end points. Finally, when the forward propagation is completed in the entire design, the ODC distribution of the entire design can be obtained, thereby providing designers with optimization directions for dynamic power consumption.

[0040] The above-mentioned user terminal can be a tablet computer, a laptop computer, a digital assistant, a wearable device, etc. However, the implementation scenario of the dynamic power consumption optimization method described above is only an example scenario. The dynamic power consumption optimization method according to an exemplary embodiment of the present invention can also be applied to other application scenarios. For example, the user can request access to relevant data from the server through the network at the user terminal (for example, a mobile phone, a desktop computer, a tablet computer, etc.). The server can access the data by executing the dynamic power consumption optimization method according to an exemplary embodiment of the present invention and return the result to the user terminal. Here, the server can be an independent server, a server cluster, a cloud computing platform or a virtualization center, etc.

[0041] The following will refer to Figure 1 The specific steps of a dynamic power consumption optimization method according to an exemplary embodiment of the present invention are described below. Figure 1 As shown, the dynamic power consumption optimization method may include the following steps:

[0042] In step S110 , a circuit design may be obtained, and a starting point of a specific type in the circuit design may be determined.

[0043] Here, designers typically use HDL (Hardware Description Language) to complete circuit design. HDL describes the structure and behavior of digital system hardware in textual form. It can represent logic circuit diagrams, logical expressions, and the logical functions performed by digital logic systems, enabling modeling at multiple levels of abstract design, such as the algorithm level, register transfer level, gate level, and switch level. Furthermore, a specific type of starting point can be the primary input of a circuit design. The primary input is used to receive the main input signal in the circuit and is typically the interface of a module or circuit unit, representing the input end of the entire circuit. These inputs can be signals from other circuit modules or control signals from external systems. In addition to the primary input, a specific type of starting point can also be the input / output end of other specified logic devices, allowing for traversal of specific areas of the circuit based on actual needs. This is not a limitation of the present invention.

[0044] Next, in step S120 , the circuit design may be traversed backwards along the signal propagation direction starting from the starting point to determine circuit branch structure information and a specific type of end point in the circuit design.

[0045] Here, the circuit design can be traversed backwards through DFS (Depth-First Search), but is not limited to it. DFS is a method for traversing or searching a tree or graph. It traverses the nodes as deep as possible along the depth of the tree or graph, and then backtracks to the previous node to find the unexplored nodes and continue searching. Furthermore, a specific type of termination point can be the primary output of the circuit design. The primary output is used in the circuit to transmit the main output signals. These output signals are the results or reactions directly generated from the function of the circuit after the circuit design is completed, and are usually related to the logical operation or processing of the input signal. In addition to the primary output, a specific type of termination point can also be the input / output terminal of other specified logic devices, etc., so as to traverse the specified area of ​​the circuit according to actual needs. The present invention does not limit this.

[0046] According to an exemplary embodiment of the present invention, a circuit design may include multiple logic devices, and any two logic devices with a signal association relationship may be connected via a net. Here, the characteristic of a logic device is that it has only one output terminal, while it may have only one input terminal or multiple input terminals, and often more than one input terminal. In addition, the input and output terminals of the logic device include two states: a high-level state, in this case represented by 1; and a low-level state, in this case represented by 0. In addition to the fact that a logic device may have multiple input terminals, the output terminal of a logic device may also be connected to the input terminals of multiple other logic devices via a net with a branching structure. This makes the entire circuit design generally have a complex circuit branching structure, so that during the backward traversal of the circuit design, information about these circuit branching structures can be obtained simultaneously. Furthermore, during the backward traversal, the type checking operation described below may not be performed on the logic device before encountering the termination point, thereby speeding up the execution of the backward traversal.

[0047] For ease of understanding, refer to Figure 2 Describe the backward traversal. Figure 2 is a schematic diagram showing a backward traversal according to an exemplary embodiment of the present invention, as shown in FIG. Figure 2 As shown, the example circuit design includes multiple main inputs and main outputs, such as main input 1, main input 2, main output 1, main output 2 and main output 3. Multiple logic devices are included between the main inputs and main outputs, and each logic device is connected through a wire network based on the signal correlation relationship. Figure 2 The direction of the arrow in indicates the direction of signal propagation, and the backward traversal is performed along the direction of signal propagation.

[0048] Return to reference Figure 1,Next, in step S130, starting from the termination point, an ODC expression can be established, and the circuit design can be traversed forward in the reverse direction of signal propagation. During the forward traversal, the ODC expression can be propagated in the circuit design based on the circuit branch structure information, until the ODC distribution of the circuit design is determined.

[0049] In one possible implementation, the termination point can be the primary output of the circuit design. In this case, the initial ODC expression from the termination point is null, meaning that a null ODC expression is established from the termination point. In other possible implementations, if the termination point is not a primary output, the initial ODC expression is determined based on the actual ODC conditions of the logic device.

[0050] Figure 3 is a schematic diagram showing a forward traversal according to an exemplary embodiment of the present invention, Figure 3 The direction of the arrow in indicates the opposite direction of signal propagation, and the forward traversal is performed along the opposite direction of the signal propagation.

[0051] Figure 4 is a flow chart illustrating propagation of ODC expressions according to an exemplary embodiment of the present invention. Propagation of ODC expressions in circuit design can be performed by Figure 4 to achieve this by following the steps in .

[0052] like Figure 4 As shown, in step S410, a first ODC expression corresponding to the output terminal of the current logic device may be determined; next, in step S420, a first type check may be performed on the current logic device to determine whether the current logic device is a specific logic device.

[0053] According to an exemplary embodiment of the present invention, during the forward traversal process, a first type check can be performed on each logic device. When a logic device contains an ODC generation point, the ODC condition of the logic device can be added to the propagated ODC expression. Here, if the logic device contains a control signal, when the control signal is in a certain state, the signal change on the selection branch in another state will not affect the subsequent circuit. In this case, the other state of the control signal at this time can be called an ODC generation point.

[0054] Figure 5 is a schematic diagram showing an ODC generation point according to an exemplary embodiment of the present invention, as shown in FIG. Figure 5As shown, the example logic device includes an input terminal S1 for the control signal, input terminals d0 and d1 for the data signal, and an output terminal O. Assume that the control signal includes two states, S1 and !S1. When S1==1, O=d1. At this time, the signal change on the branch d0 selected by !S1 will not affect the output terminal, so the ODC condition corresponding to the input terminal d1 is !S1; when S1==0, O=d0. The signal change on the branch d1 selected by S1 will not affect the output terminal, so the ODC condition corresponding to the input terminal d0 is S1.

[0055] According to an exemplary embodiment of the present invention, a specific logic device may include an input terminal for receiving a control signal and at least one input terminal for receiving a data signal. That is, the specific logic device is a device including an ODC generation point, such as a multiplexer and a tri-state gate, which are devices including control signals. Such devices have a separate input terminal as a control signal. For example, when the control signal state of the multiplexer is 1, it indicates that its output is determined by only one of the input signals. At this time, the other signal is in the ODC state.

[0056] Return to reference Figure 4 In step S430, if the current logic device is a specific logic device, an ODC condition corresponding to each input terminal of the current logic device may be generated. Here, the ODC condition corresponding to each input terminal is determined by the function of the current logic device in the design.

[0057] Next, in step S440, the ODC condition corresponding to each input terminal may be combined with the first ODC expression to obtain a second ODC expression corresponding to each input terminal, and the second ODC expression may be recorded in the wire net connected to the corresponding input terminal.

[0058] Figure 6 is a schematic diagram showing a specific logic device according to an exemplary embodiment of the present invention, such as Figure 6 As shown, assuming that the current logic device is a multiplexer, its control signal is S1, the first ODC expression corresponding to the output end is ODC1, the ODC conditions corresponding to the two data signal input ends are S1 and !S1 respectively, and the control signal input end has no corresponding ODC condition, then after combination, the second ODC expressions corresponding to the two data signal input ends are ODC1|S1 and ODC1|!S1 respectively, and the second ODC expression corresponding to the control signal input end is still ODC1.

[0059] Figure 7 is another schematic diagram illustrating a specific logic device according to an exemplary embodiment of the present invention, such as Figure 7As shown, assuming that the current logic device is a tri-state gate, when there are two adjacent tri-state gates on the propagation path, their control signals are S1 and S2 respectively. At this time, the ODC conditions corresponding to the input terminals of the two tri-state gates are !S1 and !S2 respectively. If the first ODC expression propagated is ODC1, then the second ODC expression generated by combining it with the ODC conditions corresponding to the input terminals of the two tri-state gates is !S2|!S1|ODC1.

[0060] According to an exemplary embodiment of the present invention, ODC expressions can be stored in an N-ary tree structure so as to be efficiently propagated during the traversal process. Here, each node in a traditional binary tree has one data item and at most two child nodes. If each node of the tree is allowed to have more than two child nodes, then the tree is called an N-order multi-tree, or an N-ary tree. Furthermore, according to an exemplary embodiment of the present invention, the leaf nodes of the N-ary tree can correspond to the control signals of the ODC conditions, and the non-leaf nodes of the N-ary tree can correspond to logical operators, such as & for the logical operator and | for the logical operator, and ! for the non-logical operator. Whenever a new ODC condition needs to be inserted into the original ODC expression, its logical operator node and control signal node are inserted in sequence through its logical relationship with the original ODC expression.

[0061] According to an exemplary embodiment of the present invention, when combining the ODC condition corresponding to each input terminal with the first ODC expression, the following steps can be performed: for each input terminal, determining the logical relationship between the target ODC condition corresponding to the input terminal and the first ODC expression; inserting the logical operator corresponding to the logical relationship as the first root node into the N-ary tree corresponding to the first ODC expression, so that the root node of the N-ary tree corresponding to the first ODC expression is transformed into a child node of the first root node; and creating another child node of the first root node, so that the other child node corresponds to the control signal of the target ODC condition. As an example, the ODC condition corresponding to each input terminal can be combined with the first ODC expression through OR logic, so that the OR logic operator can be inserted as the first root node into the N-ary tree corresponding to the first ODC expression.

[0062] Figure 8 : is a schematic diagram showing the structure of an ODC expression according to an exemplary embodiment of the present invention, such as Figure 8As shown, when the original ODC expression A passes through the ODC occurrence point B during propagation, B needs to be inserted into the expression. The specific method is to first insert the logical relationship between A and B as a new root node, then change the original root node into a child node, and insert B as a new child node. This will result in an N-ary tree of the new ODC expression A|B. As the ODC expression continues to propagate forward, the expression is updated in the same way: a new root node is created, the root node of the original N-ary tree is used as its child node, and the ODC expression to be combined is used as a new child node to generate a new N-ary tree. When the new ODC expression is generated, it is recorded on the corresponding line network and propagated forward during the forward traversal, resulting in an N-ary tree of the ODC expression ((A|B)&C&D)&(E&F).

[0063] In addition, return reference Figure 4 In step S450, if the current logic device is a non-specific logic device, the first ODC expression can be recorded in each net connected to each input terminal of the current logic device. Here, the non-specific logic device does not include an input terminal for receiving a control signal, that is, no new ODC generation point exists in the non-specific logic device.

[0064] Figure 9 is a schematic diagram showing a non-specific logic device according to an exemplary embodiment of the present invention, such as Figure 9 As shown in the figure, when there are no new ODC generation points in the logic device, the ODC expression on the output path only needs to be propagated along the input path. Here, when a series of non-specific logic devices form a multi-input single-output structure, assuming the ODC expression at the output end is ODC1, the ODC expression on the output path only needs to be split and propagated along each input path. In this case, the ODC expression at each input end remains ODC1.

[0065] Return to reference Figure 4As described above, in step S410, the first ODC expression corresponding to the output end of the current logic device can be determined. Here, step S410 can be implemented in the following specific manner: performing a second type check on the current logic device to determine whether the current logic device is a fan-out type combinational logic device; in the case that the current logic device is a fan-out type combinational logic device, merging multiple ODC expressions recorded in the wire net connected to the output end of the current logic device to obtain the first ODC expression. Furthermore, the output end of the fan-out type combinational logic device is connected to the input ends and / or termination points of multiple other logic devices through the wire net. Furthermore, when merging the multiple ODC expressions recorded in the wire net connected to the output end of the current logic device, the multiple ODC expressions can be merged through the AND logic, thereby creating a second root node, so that the second root node corresponds to the logical operator of the AND logic; the root node of the N-ary tree corresponding to each ODC expression in the multiple ODC expressions is converted into a child node of the second root node.

[0066] Figure 10 is a schematic diagram showing a fan-out type combinational logic device according to an exemplary embodiment of the present invention, as shown in FIG. Figure 10 As shown in the figure, for a fan-out type combinational logic device, the signal representing a single path will become multiple paths containing the same signal after propagation. Assuming that the ODC expressions of its three output ends are ODC1, ODC2 and ODC3 respectively, the ODC expression of its input end is the result of merging the ODC expressions on these three paths, that is, ODC1&ODC2&ODC3.

[0067] Furthermore, according to an exemplary embodiment of the present invention, when the current logic device is a non-fan-out combinational logic device, an ODC expression recorded in a net connected to an output terminal of the current logic device may be used as a first ODC expression. Here, the output terminal of the non-fan-out combinational logic device is connected to an input terminal or a termination point of another logic device through a net.

[0068] Return to reference Figure 1 In step S140, the circuit design may be dynamically optimized for power consumption based on the ODC distribution.

[0069] In one possible implementation, the circuit design hierarchy can be the register transfer level, a specific type of starting point can be the circuit design's main input, and a specific type of ending point can be the circuit design's main output. Therefore, based on the ODC distribution from the main input to the main output of the circuit design, clock gating logic can be inserted into the circuit design to optimize the dynamic power consumption of the entire circuit design. For example, after all forward passes are completed, the ODC distribution of the entire design can be obtained. Subsequently, the ODC expression at the wide flop output can be converted into enable logic. This enable logic can shut down the wide flop when the ODC condition is met, thereby improving the circuit structure and saving dynamic power consumption.

[0070] According to an exemplary embodiment of the present invention, still taking wide flop as an example, backward propagation can be first performed in the design to find all starting points in the design, and then forward propagation can be performed from these starting points. During the propagation process, the traversed logic devices are judged. If it is a specific logic device, its ODC condition is inserted into the ODC expression. The expression will continue to analyze each logic device as the forward propagation continues. When a wide flop is encountered, the ODC expression is stored in the corresponding container, indicating that the wide flop can be controlled by the ODC expression. Finally, when the forward propagation is completed in the entire design, the ODC distribution of the entire design can be obtained, so that the designer can control the switching of the wide flop through the ODC distribution, thereby effectively reducing the dynamic power consumption on the wide flop path.

[0071] According to the dynamic power consumption optimization method of an exemplary embodiment of the present invention, backward traversal can be performed from a specific type of starting point until a specific type of ending point is encountered. After the backward traversal encounters the ending point, forward traversal is performed. In the process of forward traversal, the ODC condition of the specific logic device is obtained, that is, in the process of forward traversal starting from the ending point, the type of each traversed logic device is judged. If it is a specific logic device, its ODC condition is stored in the ODC expression and continues to be passed. When the ODC expression is propagated in the process of forward traversal, the ODC expression can be updated according to the type of logic device encountered. When the forward traversal of all ending points is completed, the ODC distribution of the entire design can be obtained, thereby providing the designer with the optimization direction of dynamic power consumption.

[0072] In a second aspect of an exemplary embodiment of the present invention, an electronic device is provided, comprising: a processor; and a memory for storing processor-executable instructions, wherein the processor-executable instructions, when executed by the processor, prompt the processor to execute the dynamic power consumption optimization method according to the exemplary embodiment of the present invention.

[0073] Figure 11 FIG is a block diagram showing an electronic device according to an exemplary embodiment of the present invention. Figure 11 As shown, the electronic device 10 includes a processor 101 and a memory 102 for storing processor-executable instructions. Here, when the processor-executable instructions are executed by the processor, the processor is prompted to perform the dynamic power consumption optimization method according to an exemplary embodiment of the present invention.

[0074] As an example, the electronic device 10 does not necessarily need to be a single device, but may also be any collection of devices or circuits capable of executing the above-mentioned instructions (or instruction sets) individually or in combination. The electronic device 10 may also be part of an integrated control system or system manager, or may be configured as a server that is interconnected with a local or remote (e.g., via wireless transmission) interface.

[0075] In electronic device 10, processor 101 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller, or a microprocessor. By way of example and not limitation, processor 101 may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0076] The processor 101 may execute instructions or codes stored in the memory 102, which may also store data. Instructions and data may also be sent and received over a network via a network interface device, which may employ any known transmission protocol.

[0077] Memory 102 may be integrated with processor 101, for example, by placing RAM or flash memory within an integrated circuit microprocessor or the like. Furthermore, memory 102 may comprise a separate device, such as an external disk drive, a storage array, or any other storage device usable by a database system. Memory 102 and processor 101 may be operatively coupled or may communicate with each other, for example, via an I / O port, a network connection, or the like, such that processor 101 can access files stored in memory 102.

[0078] In addition, the electronic device 10 may further include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, a mouse, a touch input device, etc.) All components of the electronic device 10 may be connected to each other via a bus and / or a network.

[0079] In an exemplary embodiment, a computer-readable storage medium may also be provided, and when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the dynamic power consumption optimization method as described in the above exemplary embodiment. The computer-readable storage medium may be, for example, a memory including instructions. Optionally, the computer-readable storage medium may be: read-only memory (ROM), random access memory (RAM), random access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), dynamic random access memory (DRAM), static random access memory (SRAM), flash memory, non-volatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), card storage (such as a multimedia card, secure digital (SD) card or extreme digital (XD) card), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device configured to store a computer program and any associated data, data files and data structures in a non-transitory manner and provide the computer program and any associated data, data files and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the above-mentioned computer-readable storage medium can be executed in an environment deployed in a computer device such as a client, a host, an agent device, a server, etc. In addition, in one example, the computer program and any associated data, data files and data structures are distributed on a networked computer system so that the computer program and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers.

[0080] Other embodiments of the present invention will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. The present invention is intended to cover any variations, uses, or adaptations of the present invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the invention being indicated by the claims.

[0081] In addition, it should be noted that although several examples of each step are described above with reference to specific drawings, it should be understood that the embodiments of the present invention are not limited to the combinations given in the examples, and the steps appearing in different drawings can be combined, and no exhaustive enumeration is made here.

[0082] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the claims.

Claims

1. A dynamic power consumption optimization method, applied to electronic design automation software, characterized in that: include: Obtaining a circuit design and determining a specific type of starting point in the circuit design, wherein the circuit design includes a plurality of logic devices, and any two logic devices having a signal association relationship are connected via a wire net, wherein the specific type of starting point includes a main input of the circuit design or an input / output terminal of another designated logic device; Starting from the starting point, traversing the circuit design backward along the signal propagation direction to determine circuit branch structure information and a specific type of termination point in the circuit design, wherein the specific type of termination point includes a main output of the circuit design or an input / output terminal of other specified logic devices; Starting from the termination point, establishing an ODC expression, forward traversing the circuit design in a direction opposite to the signal propagation direction, and during the forward traversal, propagating the ODC expression in the circuit design based on the circuit branch structure information until an ODC distribution of the circuit design is determined; Based on the ODC distribution, dynamic power consumption optimization is performed on the circuit design. The step of propagating the ODC expression in the circuit design includes: Determine a first ODC expression corresponding to an output terminal of the current logic device; Performing a first type check on the current logic device to determine whether the current logic device is a specific logic device, wherein the specific logic device includes an input terminal for receiving a control signal and at least one input terminal for receiving a data signal; In a case where the current logic device is a specific logic device, generating an ODC condition corresponding to each input terminal of the current logic device; The ODC condition corresponding to each input terminal is respectively combined with the first ODC expression to obtain a second ODC expression corresponding to each input terminal, and the second ODC expression is recorded in the wire net connected to the corresponding input terminal.

2. The dynamic power consumption optimization method according to claim 1, characterized in that: Propagating the ODC expression in the circuit design further includes: In the case that the current logic device is a non-specific logic device, the first ODC expression is recorded in a wire net connected to each input terminal of the current logic device, wherein the non-specific logic device does not include an input terminal for receiving a control signal.

3. The dynamic power consumption optimization method according to claim 1, wherein: Determining a first ODC expression corresponding to an output terminal of a current logic device includes: Performing a second type check on the current logic device to determine whether the current logic device is a fan-out type combinational logic device, wherein an output terminal of the fan-out type combinational logic device is connected to input terminals of multiple other logic devices and / or the termination points through a wire net; In a case where the current logic device is a fan-out type combinational logic device, multiple ODC expressions recorded in the wire net connected to the output end of the current logic device are merged to obtain the first ODC expression.

4. The dynamic power consumption optimization method according to claim 3, wherein: Determining a first ODC expression corresponding to the output terminal of the current logic device also includes: In a case where the current logic device is a non-fan-out combinational logic device, an ODC expression recorded in a wire net connected to an output terminal of the current logic device is used as the first ODC expression, wherein the output terminal of the non-fan-out combinational logic device is connected to an input terminal of another logic device or one of the termination points through a wire net.

5. The dynamic power consumption optimization method according to claim 3, wherein: The ODC expression is stored in an N-ary tree structure, wherein the leaf nodes of the N-ary tree correspond to control signals of the ODC condition, and the non-leaf nodes of the N-ary tree correspond to logical operators.

6. The dynamic power consumption optimization method according to claim 5, characterized in that: Combining the ODC condition corresponding to each input terminal with the first ODC expression respectively includes: For any one of the input terminals, determining a logical relationship between a target ODC condition corresponding to the input terminal and the first ODC expression; Inserting the logical operator corresponding to the logical relationship as a first root node into the N-ary tree corresponding to the first ODC expression, so that the root node of the N-ary tree corresponding to the first ODC expression is transformed into a child node of the first root node; Another child node of the first root node is created, so that the another child node corresponds to the control signal of the target ODC condition.

7. The dynamic power consumption optimization method according to claim 5, characterized in that: The multiple ODC expressions are merged through AND logic. The step of merging multiple ODC expressions recorded in the network connected to the output terminal of the current logic device includes: Creating a second root node such that the second root node corresponds to the logical operator of the AND logic; The root node of the N-ary tree corresponding to each ODC expression in the multiple ODC expressions is transformed into a child node of the second root node.

8. The dynamic power consumption optimization method according to any one of claims 1 to 7, characterized in that: The design level of the circuit design is the register transfer level, the starting point of the specific type is the main input of the circuit design, and the ending point of the specific type is the main output of the circuit design. The step of performing dynamic power consumption optimization on the circuit design based on the ODC distribution includes: Based on the ODC distribution between the main input and the main output of the circuit design, clock gating logic is inserted into the circuit design, thereby optimizing the dynamic power consumption of the entire circuit design.

9. An electronic device, characterized in that: include: processor; memory for storing processor-executable instructions, When the processor-executable instructions are executed by the processor, they prompt the processor to execute the dynamic power consumption optimization method according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that When the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the dynamic power consumption optimization method according to any one of claims 1 to 8.

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