Application programming interface for identifying neural network layers

Abstract

Embodiments of the present disclosure relate to an application programming interface for identifying neural network layers. Apparatus, systems, and techniques for performing API set calls to indicate gradients of neural network layers resulting from back propagation. The processor executes a process to execute a call of the set of one or more APIs by the one or more API modules to allow execution of neural network layers hosted on the client network and the traffic network in the indicated order. For example, a client network may execute a set of layers, invoke a serving network to continue reasoning, and invoke a result of receiving the reasoning to resume reasoning within the client network.

Description

Technical Field

[0001] At least one embodiment involves processing data at least in part in a remotely hosted inference network and a locally hosted network layer. For example, an API processes the transmitted inference data in the remotely hosted network and then processes the completed inference on the local system. Background Art

[0002] Hosting neural networks is resource-intensive on a host, requires many backend tasks to keep running, and also requires a large amount of memory to store each variant of the network for the client. Optimization of the hosting system and the method used by the client to access the system can be improved to eliminate these problems. Summary of the Invention

[0003] In certain aspects of the present disclosure, a processor is described. The processor includes: one or more circuits for executing an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API.

[0004] In certain aspects of the present disclosure, a system is described. The system includes: one or more processors for executing an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API.

[0005] In certain aspects of the present disclosure, a method is described. The method includes: executing an application programming interface (API) to apply one or more gradients to one or more layers of one or more neural networks indicated by the API.

[0006] In certain aspects of the present disclosure, a processor is described. The processor includes: one or more circuits for executing an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0007] In certain aspects of the present disclosure, a system is described. The system includes: one or more processors for executing an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0008] In certain aspects of the present disclosure, a method is described. The method includes: executing an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An example of a block diagram showing communication between a hosted service system and a local client system according to at least one embodiment;

[0010] Figure 2 An example of a block diagram showing a hosted system and a client system that perform forward propagation and backward propagation using a partially hosted network according to at least one embodiment;

[0011] Figure 3 An example of a block diagram showing an example of using a partially hosted network in at least one embodiment;

[0012] Figure 4 Two examples of backpropagation within a neural network including additional layers according to at least one embodiment;

[0013] Figure 5 A block diagram showing a gradient indication operation according to at least one embodiment;

[0014] Figure 6 An example of a flowchart showing examples of steps performed by a partially hosted network during forward propagation in at least one embodiment;

[0015] Figure 7 An example of a flowchart showing examples of steps performed by a partially hosted network during backward propagation in at least one embodiment;

[0016] Figure 8 An example of a block diagram of a processor within a local system segment of a partially hosted network according to at least one embodiment;

[0017] Figure 9A Shows the logic according to at least one embodiment;

[0018] Figure 9B Shows the logic according to at least one embodiment;

[0019] Figure 10 Shows the training and deployment of a neural network according to at least one embodiment;

[0020] Figure 11 An example of a data center system according to at least one embodiment;

[0021] Figure 12A An example of an autonomous vehicle according to at least one embodiment;

[0022] Figure 12B Shows according to at least one embodiment Figure 12A An example of the camera position and field of view of an autonomous vehicle;

[0023] Figure 12C is a block diagram showing an example system architecture of an autonomous vehicle according to at least one embodiment; Figure 12A of an autonomous vehicle;

[0024] Figure 12D is a diagram showing a system for communication between one or more cloud-based servers and Figure 12A an autonomous vehicle according to at least one embodiment;

[0025] Figure 13 is a block diagram showing a computer system according to at least one embodiment;

[0026] Figure 14 is a block diagram showing a computer system according to at least one embodiment;

[0027] Figure 15 shows a computer system according to at least one embodiment;

[0028] Figure 16 shows a computer system according to at least one embodiment;

[0029] Figure 17A shows a computer system according to at least one embodiment;

[0030] Figure 17B shows a computer system according to at least one embodiment;

[0031] Figure 17C shows a computer system according to at least one embodiment;

[0032] Figure 17D shows a computer system according to at least one embodiment;

[0033] Figure 17E and Figure 17F shows a shared programming model according to at least one embodiment;

[0034] Figure 18 shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0035] Figure 19A and Figure 19B shows an exemplary integrated circuit and associated graphics processor according to at least one embodiment;

[0036] Figure 20A and Figure 20B shows additional exemplary graphics processor logic according to at least one embodiment;

[0037] Figure 21Shows a computer system according to at least one embodiment;

[0038] Figure 22A Shows a parallel processor according to at least one embodiment;

[0039] Figure 22B Shows a partitioning unit according to at least one embodiment;

[0040] Figure 22C Shows a processing cluster according to at least one embodiment;

[0041] Figure 22D Shows a graphics multiprocessor according to at least one embodiment;

[0042] Figure 23 Shows a multi-graphics processing unit (GPU) system according to at least one embodiment;

[0043] Figure 24 Shows a graphics processor according to at least one embodiment;

[0044] Figure 25 Is a block diagram showing a processor microarchitecture for a processor according to at least one embodiment;

[0045] Figure 26 Shows a deep learning application processor according to at least one embodiment;

[0046] Figure 27 Is a block diagram showing an example neuromorphic processor according to at least one embodiment;

[0047] Figure 28 Shows at least a portion of a graphics processor according to one or more embodiments;

[0048] Figure 29 Shows at least a portion of a graphics processor according to one or more embodiments;

[0049] Figure 30 Shows at least a portion of a graphics processor according to one or more embodiments;

[0050] Figure 31 Is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0051] Figure 32 Is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0052] Figure 33A - Figure 33B Shows thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core;

[0053] Figure 34 illustrates a parallel processing unit (“PPU”) according to at least one embodiment;

[0054] Figure 35 illustrates a general processing cluster (“GPC”) according to at least one embodiment;

[0055] Figure 36 illustrates a memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment;

[0056] Figure 37 illustrates a streaming multiprocessor according to at least one embodiment;

[0057] Figure 38 is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0058] Figure 39 is a system diagram of an example system for training, adapting, instantiating, and deploying machine learning models in an advanced computing pipeline according to at least one embodiment;

[0059] Figure 40 includes an example illustration of an advanced computing pipeline for processing imaging data according to at least one embodiment;

[0060] Figure 41A includes an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0061] Figure 41B includes an example data flow diagram of a virtual instrument supporting a CT scanner according to at least one embodiment;

[0062] Figure 42A illustrates a data flow diagram of a process for training a machine learning model according to at least one embodiment; and

[0063] Figure 42B is an example illustration of a client - server architecture for enhancing an annotation tool using a pre - trained annotation model according to at least one embodiment. Detailed Description

[0064] In at least one embodiment, systems and methods implemented in accordance with the present disclosure are used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0065] In at least one embodiment, a hosted neural network executes a resource-intensive neural network to serve a client system. In at least one embodiment, the client system may desire to insert a neural network layer between the hosted network layers in order to achieve better optimization (or specialization) in the output calculation. In at least one embodiment, the client device may also desire to obtain gradient information within the hosted neural network, which requires backpropagation or node weights from the portion of the neural network that calculates the given output. In at least one embodiment, the client device can execute an API call to provide inference information, layer placement information, and / or layer stop information to the hosted neural network. In at least one embodiment, the inference information is data generated by inference performed by one or more neural network layers. In at least one embodiment, the layer placement information specifies the placement between one or more layers of the hosted neural network to insert the inference data. In at least one embodiment, the layer stop information is data indicating the layer in the hosted neural network where inference stops. In at least one embodiment, the hosted neural network will perform inference from the indicated start layer to the indicated stop layer. In at least one embodiment, the hosted neural network can then execute an API call indicating the inference information and the layer range. In at least one embodiment, the layer range is data indicating the neural network layer that provides the inference information for the output. In at least one embodiment, the client neural network and / or the hosted neural network can execute API calls and / or instructions to communicate information, similar to those described above, to perform backpropagation within a similar system.

[0066] In at least one embodiment, systems and methods implemented in accordance with the present disclosure are used to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API.

[0067] In the foregoing and following descriptions, various techniques are described. For purposes of explanation, specific configurations and details are set forth in order to provide a thorough understanding of the possible ways of implementing the techniques. However, it is apparent that the techniques described below may be implemented in different configurations without the specific details. Additionally, well-known features may be omitted or simplified to avoid obscuring the described techniques.

[0068] Figure 1 is a block diagram of a system 100 showing a system for communication between a hosted service system and a local client system, according to at least one embodiment. In at least one embodiment, system 100 includes a service server 102, a network 112, and / or a client device 114. In at least one embodiment, service server 102 includes a processor 104 (e.g., Figure 2 and / or Figure 8processor 218 and / or processor 802), business neural network 106, communication manager 108, and / or API module 110 (e.g., Figure 2 API module 224). In at least one embodiment, client device 114 includes processor 116 (e.g., Figure 2 and / or Figure 8 processor 208 and / or processor 802), client neural network 118, communication manager 120, and / or API module 122 (e.g., Figure 2 API module 122). In at least one embodiment, system 100 performs one or more processes, such as process 600 and / or 700 (see Figure 6 and / or Figure 7 ).

[0069] In at least one embodiment, system 100 includes a set of one or more hardware and / or software computing resources having instructions that, when executed, cause system 100 to perform one or more communication processes, such as the communication processes described herein. In at least one embodiment, system 100 is a software program executed on computer hardware, an application executed on computer hardware, and / or variants thereof. In at least one embodiment, one or more processes of system 100 are performed by any suitable processing system or unit described below (e.g., graphics processing unit (GPU), general-purpose GPU (GPGPU), parallel processing unit (PPU), central processing unit (CPU), data processing unit (DPU)) in any suitable manner including sequential, parallel, and / or variants thereof. In at least one embodiment, system 100 uses a machine learning training framework (e.g., PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks) to implement and perform the operations described herein to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, by way of example, training a neural network model includes using a server (e.g., NVIDIA DGX server) that also includes at least a GPU (e.g., AMD MI200, VEGAL10, VEGO20, and ARCTURUS), an optimizer (e.g., ADAM OPTIMIZER), or a discriminator architecture (e.g., the discriminator architecture from face-vid2vid for training using GAN loss).

[0070] In at least one embodiment, system 100 includes a set of one or more hardware and / or software computing resources having instructions that, when executed, cause system 100 to perform one or more communication processes, such as the communication processes described herein. In at least one embodiment, system 100 is a software program executed on computer hardware, an application program executed on computer hardware, and / or variants thereof. In at least one embodiment, one or more processes of system 100 are performed by any suitable processing system or unit (e.g., graphics processing unit (GPU), general-purpose GPU (GPGPU), parallel processing unit (PPU), central processing unit (CPU), data processing unit (DPU)) as described below in any suitable manner including sequential, parallel, and / or variants thereof. In at least one embodiment, system 100 uses a machine learning training framework (e.g., PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks) to implement and perform the operations described herein to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, by way of example, training a neural network model includes using a server (e.g., NVIDIA DGX server) that also includes at least GPUs (e.g., AMD MI200, VEGAL10, VEGO20, and ARCTURUS), an optimizer (e.g., ADAM OPTIMIZER), or a discriminator architecture (e.g., the discriminator architecture from face-vid2vid for training using GAN loss).

[0071] In at least one embodiment, business server 102 is a device that hosts a neural network to process information in cooperation with client device 114. In at least one embodiment, business server 102 includes processor 104, business neural network 106, communication manager 108, and / or API module 110. In at least one embodiment, business server 102 is described as a hosting computer system that hosts portions of a neural network for use by a client. In at least one embodiment, business server 102 receives one or more inputs from client device 114 via network 112. In at least one embodiment, business server 102 outputs to client device 114 via network 112.

[0072] In at least one embodiment, processor 104 and / or processor 116 (e.g., GPU, DPU, and / or CPU) are inFigure 9A - 42B shown in other ways and / or by processor 802 (see Figure 8 ).

[0073] In at least one embodiment, the service neural network 106 is a neural network (NN) executed by the service server 102. In at least one embodiment, the service neural network 106 is a pre-trained neural network for detecting text content in an image. In at least one embodiment, the service neural network 106 receives input from the client neural network 118 via the network 112. In at least one embodiment, the service neural network 106 provides output to the client neural network 118 via the network 112.

[0074] In at least one embodiment, the communication manager 108 and / or 120 may include one or more components and features for communicating across one or more networks (such as network 112). In at least one embodiment, the communication manager 108 and / or 120 is configured to communicate via any number of networks described herein. In at least one embodiment, the communication manager 108 and / or 120 is configured to manage communication information received by their respective systems (e.g., gradients, layer information, computed values, etc.) and / or communication information provided by their respective systems (e.g., gradients, layer information, computed values, etc.), where the respective systems are any of the other components that may be included in the service server 102, the client device 114, and / or the system 100. In at least one embodiment, the communication manager 108 and / or 120 may manage communication within their respective systems.

[0075] In at least one embodiment, the communication manager 108 uses the API module 110 to facilitate communication between the service neural network 106 and the client neural network 118 via the network 112. In at least one embodiment, the communication manager 108 receives input from the client neural network 118 via the network 112. In at least one embodiment, for example, an API call for the output of the client neural network 118 is made via the API module 110 and / or the API module 122. In at least one embodiment, the communication manager 108 provides output to the service neural network 106.

[0076] In at least one embodiment, the network 112 is a computing network that facilitates communication between two computing systems. In at least one embodiment, for example, the network 112 facilitates data communication between the service server 102 and the client device 114. In at least one embodiment, the network 112 receives input from the service server 102 and / or the client device 114. In at least one embodiment, the network 112 provides output to the service server 102 and / or the client device 114.

[0077] In at least one embodiment, the client device 114 is a device operated by a client that hosts a neural network to process information. In at least one embodiment, the client device 114 includes a processor 116, a client neural network 118, a communication manager 120, and / or an API module 122. In at least one embodiment, the client device 114 is described as a computer system that hosts a partial neural network for use by the client. In at least one embodiment, the client device 114 receives input from the service server 102 via the network 112. In at least one embodiment, the client device 114 outputs to the service server 102 via the network 112.

[0078] In at least one embodiment, the client neural network 118 is a neural network executed using the client device 114. In at least one embodiment, the client neural network 118 is a pre-trained neural network for detecting text content in an image. In at least one embodiment, the client neural network 118 receives input from the service neural network 106 via the network 112. In at least one embodiment, the client neural network 118 provides output to the service neural network 106 via the network 112.

[0079] In at least one embodiment, the communication manager 120 uses the API module 122 to facilitate communication between the service neural network 106 and the client neural network 118 via the network 112. In at least one embodiment, the communication manager 120 receives input from the service neural network 106 via the network 112. In at least one embodiment, for example, an API call identifies the output of the service neural network 106 via the API module 110 and / or 122. In at least one embodiment, the communication manager 120 provides output to the service neural network 106.

[0080] In at least one embodiment, the system 100 includes one or more processors to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based on one or more indications of one or more layers of one or more neural networks and / or to otherwise perform the operations described herein. In at least one embodiment, the system 100 is Figure 1 - 8 the system shown in Figure 1 - 8 the system shown in and / or otherwise includes Figure 1 - 8 the system shown in to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based on one or more indications of one or more layers of one or more neural networks and / or to otherwise perform the operations described herein. In at least one embodiment, the system 100 executes Figure 1 - 8One or more processes as shown, e.g., for performing an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, system 100 performs Figure 9A - 42B One or more processes as shown, e.g., for performing an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein.

[0081] In at least one embodiment, system 100 including one or more processors performs an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 100 is Figure 1 - 8 the system shown in Figure 1 - 8 the system shown in and / or otherwise includes Figure 1 - 8 the system shown in to perform an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 100 performs Figure 1 - 8 One or more processes as shown, e.g., for performing an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 100 performs Figure 9A - 42B One or more processes as shown, e.g., for performing an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein.

[0082] Figure 2 Shows an example of a block diagram of a system 200 that performs forward propagation and backpropagation using a partially hosted network. In at least one embodiment, system 200 includes a client input 202, a client neural network 204, an input query 216, a hosted neural network 206, and / or an output query 226. In at least one embodiment, client neural network 204 includes a processor 208 (e.g., Figure 8The processor 802) in and / or the API module 122. In at least one embodiment, the hosted neural network 206 includes a processor 218 (e.g., Figure 8 The processor 802) in. In at least one embodiment, the system 200 executes one or more processes, such as process 600 or 700 ( Figure 6 and / or Figure 7 ).

[0083] In at least one embodiment, system 200 includes a collection of one or more hardware and / or software computing resources having instructions that, when executed, cause system 200 to perform one or more communication processes, such as the communication processes described herein. In at least one embodiment, system 200 is a software program executing on computer hardware, an application executing on computer hardware, and / or variants thereof. In at least one embodiment, one or more processes of system 200 are performed by any suitable processing system or unit (e.g., a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU), a data processing unit (DPU)) described below in any suitable manner including sequential, parallel, and / or variants thereof. In at least one embodiment, system 200 uses a machine learning training framework (e.g., PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks) to implement and perform the operations described herein to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, system 200 uses a machine learning training framework (e.g., PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks) to implement and perform the operations described herein to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, by way of example, training a neural network model includes using a server (e.g., an NVIDIA DGX server) that also includes at least GPUs (e.g., AMD MI200, VEGA L10, VEGA O20, and ARCTURUS), an optimizer (e.g., ADAM OPTIMIZER), or a discriminator architecture (e.g., a discriminator architecture from face-vid2vid for training using GAN loss).

[0084] In at least one embodiment, the client input 202 is used by the processor to indicate information, such as information for describing a data set used by a neural network to perform inference. In at least one embodiment, the client input 202 is output by the memory. In at least one embodiment, the client input 202 is provided as an input to the client neural network 204.

[0085] In at least one embodiment, the client neural network 204 is a partial neural network executed by the client device. In at least one embodiment, the client neural network 204 performs inference related to the data input. In at least one embodiment, for example, the client neural network 204 can receive the output query 226 and / or the client input 202, perform the optimization calculation 212 and / or the input calculation 210, and then provide the input query 216 to the hosted neural network 206. In at least one embodiment, the client neural network 204 outputs the node weights and / or the calculated output to the hosted neural network 206 and / or the client device 114. In at least one embodiment, the client neural network 204 receives inputs from the client input 202 and / or the hosted neural network 206.

[0086] In at least one embodiment, the hosted neural network 206 is a partial neural network executed by the host device. In at least one embodiment, the hosted neural network 206 performs inference related to the data input. In at least one embodiment, for example, the hosted neural network 206 can receive the input query 216, perform the output calculation 220 and / or the node weight calculation 222, and then provide the output query 226 to the client neural network 204. In at least one embodiment, the hosted neural network 206 outputs the node weights and the calculated output to the client neural network 206. In at least one embodiment, the hosted neural network 206 receives inputs from the client neural network 204.

[0087] In at least one embodiment, the processors 208 and / or 218 (e.g., GPU, DPU, and / or CPU) are otherwise shown and / or are the processor 802 (see Figure 9A - 42B ) Figure 8 .

[0088] In at least one embodiment, the API module 214 is executed by the client neural network 204 to execute one or more instructions and / or API calls on one or more hosted neural networks (e.g., the hosted neural network 206). In at least one embodiment, the API module 214 receives inputs from the processor 208 and / or the client input 202. In at least one embodiment, the API module 214 provides an output to the processor 218. In at least one embodiment, for example, the API module 214 can provide the input query 216 to the processor 218.

[0089] In at least one embodiment, the API module 224 is executed by the hosted neural network 206 to make API calls to one or more client neural networks (e.g., client neural network 204). In at least one embodiment, the API module 224 receives input from the processor 218. In at least one embodiment, the API module 224 provides output to the processor 208. In at least one embodiment, for example, the API module 224 may provide an output query 226 to the processor 208.

[0090] In at least one embodiment, a system 200 including one or more processors executes an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or otherwise perform the operations described herein, at least in part based on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, the system 200 is Figure 1 - 8 the system shown in Figure 1 - 8 the system shown in and / or otherwise includes Figure 1 - 8 the system shown in to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or otherwise perform the operations described herein, at least in part based on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, the system 200 executes Figure 1 - 8 one or more of the processes shown in, e.g., for executing an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or otherwise perform the operations described herein, at least in part based on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, the system 200 executes Figure 9A - 42B one or more of the processes shown in, e.g., for executing an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or otherwise perform the operations described herein, at least in part based on one or more indications of one or more layers of one or more neural networks.

[0091] In at least one embodiment, a system 200 including one or more processors executes an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API (e.g., "denoising one or more audio signals using one or more neural networks based at least in part on two or more different-sized segments of one or more audio signals") and / or otherwise perform the operations described herein. In at least one embodiment, the system 200 is Figure 1 - 8 the system shown in, included inFigure 1 - 8 in the system shown in and / or otherwise includes Figure 1 - 8 the system shown in, for performing an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 200 performs Figure 1 - 8 one or more processes shown in, such as for performing an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 200 performs Figure 9A - 42B one or more processes shown in, such as for performing an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API and / or otherwise perform the operations described herein.

[0092] Figure 3 is a block diagram showing a system 300 according to at least one embodiment, for showing an example communication system that uses API calls to allow a client neural network and a hosted neural network to perform inference in series. In at least one embodiment, system 300 includes a client neural network 302, an API call 312, and a hosted neural network 314. In at least one embodiment, the client neural network 302 includes an input 304, network layers 306 and / or 308, and an output 310. In at least one embodiment, the hosted neural network 314 includes network layers 316, 318, and / or 320 and / or an output 322. In at least one embodiment, system 300 performs one or more processes, such as process 600 and / or 700 (see Figure 6 and / or Figure 7 ).

[0093] In at least one embodiment, system 300 includes a collection of one or more hardware and / or software computing resources having instructions that, when executed, cause system 300 to perform one or more communication processes, such as the communication processes described herein. In at least one embodiment, system 300 is a software program executed on computer hardware, an application program executed on computer hardware, and / or variants thereof. In at least one embodiment, one or more processes of system 300 are performed by any suitable processing system or unit (e.g., graphics processing unit (GPU), general-purpose GPU (GPGPU), parallel processing unit (PPU), central processing unit (CPU), data processing unit (DPU)) described below in any suitable manner including sequential, parallel, and / or variants thereof. In at least one embodiment, system 300 uses a machine learning training framework (e.g., PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks) to implement and perform the operations described herein to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, system 300 uses a machine learning training framework (e.g., PYTORCH, TENSORFLOW, BOOST, CAFFE, MICROSOFT COGNITIVE TOOLKIT / CNTK, MXNET, CHAINER, KERAS, DEEPLEARNING4J, and / or other training frameworks) to implement and perform the operations described herein to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, by way of example, training a neural network model includes using a server (e.g., NVIDIA DGX server) that also includes at least a GPU (e.g., AMD MI200, VEGA L10, VEGA O20, and ARCTURUS), an optimizer (e.g., ADAM OPTIMIZER), or a discriminator architecture (e.g., discriminator architecture from face-vid2vid for training using GAN loss).

[0094] In at least one embodiment, the client neural network 302 is a neural network executed by a local device for performing data inference. In at least one embodiment, for example, the client neural network 302 may provide inference outputs and / or node weights to the hosted neural network 314. In at least one embodiment, the client neural network 302 receives inputs from the hosted neural network 314 in the form of API calls 312. In at least one embodiment, the client neural network 302 provides outputs to the hosted neural network 314 in the form of API calls 312.

[0095] In at least one embodiment, the hosted neural network 314 is a neural network executed by a hosted device for performing data inference. In at least one embodiment, for example, the hosted neural network 314 may provide inference outputs and / or node weights to the client neural network 302. In at least one embodiment, the hosted neural network 314 receives inputs from the client neural network 302 in the form of API calls 312. In at least one embodiment, the hosted neural network 314 provides outputs to the client neural network 302 in the form of API calls 312.

[0096] In at least one embodiment, the API calls 312 are executed by an API module (e.g., Figure 2 the API modules 214 and / or 224 in

[0097] to provide inputs to the client neural network 302 and / or the hosted neural network 314. In at least one embodiment, the API calls 312 are data for indicating information (e.g., information used by the neural network for performing inference). In at least one embodiment, the API calls 312 are inputs to the client neural network 302 and / or the hosted neural network 314. In at least one embodiment, the API calls 312 are outputs provided by the client neural network 302 and / or the hosted neural network 314. Figure 1 、 Figure 2 and / or Figure 8 ) to perform inference. In at least one embodiment, the input 304 is provided by a local system (e.g., the client device 114, Figure 1 ) in the form of information (e.g., information used by a local neural network (e.g., the client neural networks 118 and / or 204, Figure 1 and / or Figure 2 ) to perform inference). In at least one embodiment, the input 304 is provided as an input to the client neural network 302 and / or the hosted neural network 314.

[0098] In at least one embodiment, the network layers 306, 308, 316, 318, and / or 320 are layers of weighted nodes of a neural network (e.g., the client neural network 302 and / or the hosted neural network 314). In at least one embodiment, the network layers 306, 308, 316, 318, and / or 320 are executed by a local system (e.g., Figure 1 client device 114 of Figure 1 and / or a hosted system (e.g.,

[0099] business server 102 of

[0100] to perform inference and / or node weight calculation. In at least one embodiment, for example, according to at least one embodiment, the network layer 306 may receive inference data from the network layer 316, perform inference on the data, and then provide its output to the network layer 318. In at least one embodiment, the network layers 306, 308, 316, 318, and / or 320 receive input in the form of data (e.g., inference output, node weights, and / or input data) from the API call 312. In at least one embodiment, the network layers 306, 308, 316, 318, and / or 320 provide output in the form of data (e.g., inference output and / or node weights) and / or output 322 to the network layers 306, 308, 318, and / or 320. Figure 1 - 8 the system shown in Figure 1 - 8 is included in Figure 1 - 8 the system shown in Figure 1 - 8One or more processes as shown, e.g., to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, system 300 executes Figure 9A - 42B One or more processes as shown, e.g., to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein.

[0101] In at least one embodiment, system 300 including one or more processors executes an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 300 is Figure 1 - 8 the system shown in Figure 1 - 8 the system shown in, and / or otherwise includes Figure 1 - 8 the system shown in, for executing an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 300 executes Figure 1 - 8 One or more processes as shown, e.g., for executing an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 300 executes Figure 9A - 42B One or more processes as shown, e.g., for executing an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein.

[0102] Figure 4 is a block diagram showing system 400 according to at least one embodiment, for showing two examples of an NN architecture that executes backpropagation including additional layers communicating via an API. In at least one embodiment, system 400 includes additional layers 402, 408, 424, and / or 430, and / or NN layers 404, 406, 410, 412, 422, 426, 428, and / or 432. In at least one embodiment, system 400 executes one or more processes, such as process 600 and / or 700 (see Figure 6 and / orFigure 7 )。

[0103] In at least one embodiment, system 400 includes a collection of one or more hardware and / or software computing resources having instructions that, when executed, cause system 400 to perform one or more communication processes, such as the communication processes described herein. In at least one embodiment, system 400 is a software program executed on computer hardware, an application program executed on computer hardware, and / or variants thereof. In at least one embodiment, one or more processes of system 400 are performed by any suitable processing system or unit (e.g., a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a parallel processing unit (PPU), a central processing unit (CPU), a data processing unit (DPU)) as described below in any suitable manner including sequential, parallel, and / or variants thereof. In at least one embodiment, system 400 is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, system 400 is used to execute an application programming interface (API) to cause one or more gradients to be applied to one or more parts of one or more neural networks indicated by the API and / or otherwise perform the operations described herein.

[0104] In at least one embodiment, additional layers 402, 408, 424, and / or 430 are neural network layers hosted on a client device (e.g., client device 114, Figure 1 ) connected to a business neural network (e.g., business neural network 106, Figure 1 ). In at least one embodiment, additional layers 402, 408, 424, and / or 430 perform inference as part of a neural network. In at least one embodiment, additional layers 402, 408, 424, and / or 430 receive as input output data from another additional layer, output data from NN layers (e.g., NN layers 404, 406, 410, 412, 422, 426, 428, and / or 432), and / or data input by the client device. In at least one embodiment, additional layers 402, 408, 424, and / or 430 output inference data and / or backpropagation data to another additional layer, NN layers (e.g., NN layers 404, 406, 410, 412, 422, 426, 428, and / or 432), the client device, and / or the hosting system.

[0105] In at least one embodiment, the NN layers 404, 406, 410, 412, 422, 426, 428, and / or 432 are hosted on a server associated with a client device (e.g., client device 114, Figure 1 ) connected business neural network (e.g., business neural network 106, Figure 1 ). In at least one embodiment, the NN layers 404, 406, 410, 412, 422, 426, 428, and / or 432 perform inference as part of a neural network. In at least one embodiment, the NN layers 404, 406, 410, 412, 422, 426, 428, and / or 432 receive input in the form of output data from another NN layer, output data of an additional layer (e.g., additional layers 402, 408, 424, and / or 430), and / or data input by a client device. In at least one embodiment, the NN layers 404, 406, 410, 412, 422, 426, 428, and / or 432 output inference data and / or back-propagation data to another NN layer, an additional layer (e.g., additional layers 402, 408, 424, and / or 430), a client device, and / or a hosting system.

[0106] In at least one embodiment, the system 400 including one or more processors executes an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks and / or otherwise perform operations described herein. In at least one embodiment, the system 400 is Figure 1 - 8 The system shown in Figure 1 - 8 in the system shown in and / or otherwise including Figure 1 - 8 , for executing an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks and / or otherwise perform operations described herein. In at least one embodiment, system 400 executes Figure 1 - 8 , for example, to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks and / or otherwise perform operations described herein. In at least one embodiment, system 400 executes Figure 9A - 42B , for example, to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks and / or to otherwise perform the operations described herein.

[0107] In at least one embodiment, a system 400 including one or more processors executes an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, the system 400 is Figure 1 - 8 the system shown in Figure 1 - 8 the system shown in, and / or otherwise includes Figure 1 - 8 the system shown in to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, the system 400 executes Figure 1 - 8 one or more processes shown in, e.g., to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, the system 400 executes Figure 9A - 42B one or more processes shown in, e.g., to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein.

[0108] Figure 5 is a block diagram illustrating a gradient indication operation 500 (“operation 500”) according to at least one embodiment. In at least one embodiment, operation 500 is one or more computational operations that, if executed, indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks, as described above in connection with Figure 1 and / or Figure 2 described. In at least one embodiment, operation 500 is one or more computational operations that, if executed, cause one or more gradients to be applied to one or more portions of one or more neural networks indicated by the API and / or instructions, as described above in connection with Figure 1 and / or Figure 2 described.

[0109] In at least one embodiment, the gradient indication call 502 ("call 502") is a function call executed by one or more software programs, such as kernels executed by one or more parallel processing units (PPUs), such as graphics processing units (GPUs). In at least one embodiment, call 502 is a call of instructions to cause one or more processors to perform one or more computational operations 522, 524 of the gradient indication response 520 ("response 520"). In at least one embodiment, call 502 is a call of an API to cause one or more processors to perform one or more computational operations 522, 524 of response 520.

[0110] In at least one embodiment, when called, call 502 receives one or more parameters 504, 506, 508 to indicate information about the computational operations to be performed. In at least one embodiment, when called, call 502 receives one or more parameters 504, 506, 508 to indicate information about the instructions to be performed.

[0111] In at least one embodiment, call 502 receives as input parameters 504, 506, 508 that include layer information 504. In at least one embodiment, layer information 504 is data that includes information indicating one or more layers of one or more neural networks, and this data will be used by response 820 to identify one or more gradients, such as gradient 533. In at least one embodiment, if a function call is to execute call 502, then layer information 504 is the data to be input to the function call. In at least one embodiment, if an API is to cause call 502 to be executed, then layer information 504 is the data to be input to the API.

[0112] In at least one embodiment, call 502 receives as input parameters 504, 506, 508 that include gradient information 506. In at least one embodiment, gradient information 506 is data that includes information indicating one or more gradient values corresponding to one or more layers of a neural network. In at least one embodiment, if a function call is to execute call 502, then gradient information 506 is the data to be input to the function call. In at least one embodiment, if an API is to cause call 502 to be executed, then gradient information 506 is the data to be input to the API.

[0113] In at least one embodiment, the invocation 502 receives parameters 504, 506, 508 including additional parameter 508 as input. In at least one embodiment, the additional parameter 508 is data including any other information available to operation 500. In at least one embodiment, if a function call is to execute the invocation 502, the additional parameter 508 is data to be input into the function call. In at least one embodiment, if an API is to cause the invocation 502 to be executed, the additional parameter 508 is data to be input into the API.

[0114] In at least one embodiment, the example instruction indicates an operation 500 in a parallel computing environment such as Compute Unified Device Architecture (CUDA).

[0115] In at least one embodiment, the response 520 generates parameters 522, 524 including a gradient 522 as output. In at least one embodiment, the gradient 522 is data indicating one or more gradient values corresponding to one or more layers of a neural network. In at least one embodiment, the response 520 includes an operation for identifying the gradient 522 using layer information 504 and / or gradient information 506 of the invocation 502. In at least one embodiment, the response 520 includes an operation for applying the gradient 522 to one or more layers of a neural network using layer information 504 and / or gradient information 506 of the invocation 502. In at least one embodiment, if a function call is to execute the invocation 502, the gradient 522 is data to be output in response to the function call. In at least one embodiment, if an API is to cause the invocation 502 to be executed, the gradient 522 is data to be output by the API.

[0116] In at least one embodiment, the response 520 generates parameters 522, 524 including a status 524 as output. In at least one embodiment, the status 524 is data including any other information presented by operation 500. In at least one embodiment, if a function call is to execute the invocation 502, the status 524 is data to be output in response to the function call. In at least one embodiment, if an API is to cause the invocation 502 to be executed, the status 524 is data to be output by the API. In at least one embodiment, the status 524 indicates that operation 500 has been successfully executed. In at least one embodiment, the status 524 indicates that operation 500 has not been successfully executed, or otherwise failed. In at least one embodiment, the response 520 generates other parameters as output in addition to the status 524.

[0117] Figure 6FIG. 600 is a flow chart showing a process 600 for computing an output of a neural network according to at least one embodiment. In at least one embodiment, one or more neural networks (e.g., client neural network 204 and / or hosted neural network 206) use process 600 to compute an output from one or more given inputs. In at least one embodiment, process 600 includes one or more steps: computing 602 an optimized input to upload 604 to a remotely hosted neural network that computes 606 an output based on the received input and returns 608 the output to the local neural network.

[0118] In at least one embodiment, some or all of process 600 (or any other process described herein, or variations and / or combinations thereof) is executed under the control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) to be executed jointly on one or more processors (e.g., Figure 8 processor 802). In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions for executing process 600 are not stored using only transitory signals (e.g., propagated transient electrical or electromagnetic transmissions). In at least one embodiment, a non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within a transceiver of a transitory signal. In at least one embodiment, process 600 is executed at least in part on a computer system (e.g., a computer system described elsewhere in the present disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) executes process 600.

[0119] In at least one embodiment, the processor begins process 600 (if called) to perform inference on a provided data set. In at least one embodiment, process 600 includes receiving one or more data points, e.g., from memory and / or as client input 202 (see Figure 2)。In at least one embodiment, the received 602 input is in a data format such that the processor can then iterate to the next feature (e.g., including the first feature to start). In at least one embodiment, the process then continues to upload 604 to the remotely hosted neural network. In at least one embodiment, the remotely hosted neural network then outputs via inference calculation 606 (e.g., output calculation 220, Figure 2 )。In at least one embodiment, the remotely hosted neural network then returns 608 the output from the neural network to the local neural network. In at least one embodiment, if the process 600 finishes inferring on the data set, indicates to perform inference on the data set, and / or otherwise returns an error, then the process 600 can terminate.

[0120] In at least one embodiment, the processor uses a process 600 that includes one or more steps to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, the process 600 includes Figure 1 - 8 the system shown in Figure 1 - 8 the system shown in and / or otherwise includes Figure 1 - 8 the system shown in, for executing an application programming interface (API) to indicate gradient information corresponding to one or more layers based on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, the process 600 is performed by Figure 1 - 8 one or more systems shown in, e.g., to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein. In at least one embodiment, the process 600 is performed by Figure 9A - 42B one or more systems shown in, e.g., to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based on one or more indications of one or more layers of one or more neural networks and / or otherwise perform the operations described herein.

[0121] In at least one embodiment, the processor uses a process 600 that includes one or more steps to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, the process 600 includesFigure 1 - 8 The system shown in Figure 1 - 8 the system shown in and / or otherwise includes Figure 1 - 8 the system shown in, for performing an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, process 600 is performed by Figure 1 - 8 one or more systems shown in, e.g., to perform an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, process 600 is performed by Figure 9A - 42B one or more systems shown in, e.g., to perform an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein.

[0122] Figure 7 is a flowchart showing process 700 for computing backpropagation neural network gradients for a neural network according to at least one embodiment. In at least one embodiment, one or more neural networks (e.g., client neural network 204 and / or hosted neural network 206) use process 700 to compute backpropagation neural network gradients from one or more given inference data sets. In at least one embodiment, process 700 includes one or more steps: querying 702 the optimized output for uploading to a cloud-based model, computing 704 gradients from the given output, and computing 706 the respective node weights, and then uploading 708 the computed gradients and weights to the local model.

[0123] In at least one embodiment, some or all of process 700 (or any other process described herein, or variations and / or combinations thereof) is performed under the control of one or more computer systems configured with computer-executable instructions and is implemented by hardware, software, or a combination thereof on one or more processors (e.g., Figure 8Code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) executed collectively on a processor 802). In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions for performing process 700 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within a transceiver of transient signals. In at least one embodiment, process 700 is performed at least in part on a computer system (e.g., the computer systems described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 700.

[0124] In at least one embodiment, the processor begins process 700 (if called) to perform backpropagation calculations based on the provided inference output. In at least one embodiment, process 700 includes receiving one or more 702 queries to calculate gradients. In at least one embodiment, the received 702 queries are in a data format such that the processor can then iterate to the next feature (e.g., including the first feature to start with). In at least one embodiment, process 700 then iterates to 704 calculate network gradients from the given output and 706 calculate node weights from the given output. In at least one embodiment, process 700 then iterates to 708 upload the weights and gradients to a local model (e.g., Figure 1 client device 114 in). In at least one embodiment, process 700 may terminate if it completes the calculation of weights and / or gradients, indicates the calculation of weights and / or gradients on a data set, and / or otherwise returns an error.

[0125] In at least one embodiment, the processor uses process 700, which includes one or more steps, to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or otherwise perform the operations described herein based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, process 700 includes Figure 1 - 8 the system shown in, included in Figure 1 - 8 the system shown in and / or otherwise includes Figure 1 - 8The system shown in executes an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or otherwise perform the operations described herein, at least in part based on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, process 700 is performed by Figure 1 - 8 one or more of the systems shown in , e.g., to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or otherwise perform the operations described herein, at least in part based on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, process 700 is performed by Figure 9A - 42B one or more of the systems shown in , e.g., to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or otherwise perform the operations described herein, at least in part based on one or more indications of one or more layers of one or more neural networks.

[0126] In at least one embodiment, a processor uses process 700, which includes one or more steps, to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, process 700 includes Figure 1 - 8 the systems shown in , is included in Figure 1 - 8 the systems shown in and / or otherwise includes Figure 1 - 8 the systems shown in , to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, process 700 is performed by Figure 1 - 8 one or more of the systems shown in , e.g., to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, process 700 is performed by Figure 9A - 42B one or more of the systems shown in , e.g., to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein.

[0127] Figure 8is a block diagram showing a processor 802 and modules 804 - 810 according to at least one embodiment. In at least one embodiment, system 800 includes a processor 802 and modules 804 - 810. In at least one embodiment, processor 802 executes one or more processes (such as the processes described herein) to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or perform the operations described herein, based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, processor 802 performs neural network output calculations, backpropagation calculations, and / or API call sending and receiving, such as in conjunction with Figure 1 - 8 described

[0128] In at least one embodiment, system 800 includes a processor 802 and modules 804 - 810. In at least one embodiment, processor 802 executes one or more processes (such as the processes described herein) to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API and / or perform the operations described herein. In at least one embodiment, processor 802 performs neural network output calculations, backpropagation calculations, and / or API call sending and receiving, such as in conjunction with Figure 1 - 8 described

[0129] In at least one embodiment, processor 802 includes one or more circuits for performing one or more operations as described below. In at least one embodiment, processor 802 is any suitable processing unit and / or combination of processing units, such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof, including those further described herein. In at least one embodiment, processor 802 includes one or more cloud - based neural network training modules 804, local neural network modules 806, local API modules 808, and / or enterprise neural network modules 810.

[0130] In at least one embodiment, cloud - based neural network training module 804, local neural network module 806, local API module 808, and / or enterprise neural network module 810 include one or more circuits of processor 802 and / or one or more other processors. In at least one embodiment, cloud - based neural network training module 804, local neural network module 806, local API module 808, and / or enterprise neural network module 810 are distributed among multiple processors that communicate via a bus, network, by writing to shared memory, and / or any suitable communication process (such as those described herein).

[0131] In at least one embodiment, as used in any implementation described herein, unless the context clearly dictates otherwise or is clearly contrary, a module refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functions described herein. In at least one embodiment, software is embodied as a software package, code, and / or instruction set or instructions, and "hardware" as used in any implementation described herein includes, for example, hardwired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware that stores instructions executed by the programmable circuitry, either alone or in any combination. In at least one embodiment, a module is embodied, either collectively or individually, as circuitry that forms part of a larger system (such as an integrated circuit (IC), system on a chip (SoC), etc.). In at least one embodiment, a module, together with any suitable processing unit and / or combination of processing units (such as one or more CPUs, GPUs, GPGPUs, PPUs, and / or variants thereof, including those further described herein), performs one or more processes.

[0132] In at least one embodiment, a cloud-based neural network training module 804 is a module that, if executed, causes one or more processors 802 to train one or more neural networks to perform one or more processing tasks, such as by executing an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or execute an application programming interface (API) to cause one or more gradients to be applied to one or more portions of one or more neural networks, based at least in part on one or more indications of one or more layers of the one or more neural networks. In at least one embodiment, the cloud-based neural network training module 804 causes one or more processors 802 to perform one or more processes described herein by at least including or otherwise encoding instructions that cause the one or more processors 802 to perform the one or more processes, or the instructions can otherwise be used by the one or more processors 802 to perform the one or more processes. For example, in at least one embodiment, the cloud-based neural network training module 804 causes one or more processors 802 to perform training of a hosted neural network to perform inference by inserting additional layers between hosted layers using an API.

[0133] In at least one embodiment, the local neural network module 806 is a module for causing one or more processors to generate and / or execute one or more software instructions (e.g., software instructions of an executable program, including executable code) to use a local neural network. In at least one embodiment, for example, the local neural network module 806 causes one or more processors 802 to perform inference and / or backpropagation within one or more neural network layers and / or to otherwise perform the operations described herein. In at least one embodiment, the local neural network module 806 causes one or more processors 802 to execute one or more processes (e.g., the processes described herein) by at least including or otherwise encoding instructions that cause the execution of the one or more processes or that can otherwise be used to execute the one or more processes. For example, in at least one embodiment, software causes one or more processors 802 to use one or more local neural network layers based at least in part on one or more data sets received from an API call to a hosted neural network.

[0134] In at least one embodiment, the local API module 808 is a module for causing one or more processors to generate and / or execute one or more software instructions (e.g., software instructions of an executable program, including executable code) to perform and / or receive API calls. For example, in at least one embodiment, the local API module 808 causes one or more processors 802 to perform a cloud API call to a business neural network to receive inputs in the form of neural network inference data and / or backpropagation calculation results. In at least one embodiment, the local API module causes one or more processors 802 to execute one or more processes (e.g., the processes described herein) by at least including or otherwise encoding instructions that cause the execution of the one or more processes or that can otherwise be used to execute the one or more processes. For example, in at least one embodiment, software causes one or more processors 802 to use one or more local API modules to perform one or more API calls to a client neural network to provide outputs in the form of neural inference data and / or backpropagation calculation results.

[0135] In at least one embodiment, the business neural network module 810 is a module for causing one or more processors to generate and / or execute one or more software instructions (e.g., software instructions of an executable program, including executable code) to use a business neural network. In at least one embodiment, the business neural network module 810 causes one or more processors 802 to perform inference and / or backpropagation within one or more neural network layers and / or to otherwise perform the operations described herein. In at least one embodiment, the business neural network module 810 causes one or more processors 802 to execute one or more processes (e.g., the processes described herein) by at least including or otherwise encoding instructions that cause the execution of the one or more processes or that can otherwise be used to execute the one or more processes. For example, in at least one embodiment, software causes one or more processors 802 to use one or more local neural network layers at least partially based on one or more data sets received from an API call to a local neural network.

[0136] In at least one embodiment, the system 800 executes an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or to otherwise perform the operations described herein based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, the system 800 is Figure 1 - 8 the system shown in Figure 1 - 8 the system shown in and / or otherwise includes Figure 1 - 8 the system shown in to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or to otherwise perform the operations described herein based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, the system 800 executes Figure 1 - 8 one or more of the processes shown in, e.g., to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or to otherwise perform the operations described herein based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, the system 800 includes Figure 9A - 42B one or more of the hardware shown in, e.g., for executing an application programming interface (API) to indicate gradient information corresponding to one or more layers and / or to otherwise perform the operations described herein based at least in part on one or more indications of one or more layers of one or more neural networks.

[0137] In at least one embodiment, system 800 executes an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 800 is Figure 1 - 8 the system shown in Figure 1 - 8 the system shown in, and / or otherwise includes Figure 1 - 8 the system shown in, for executing an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 800 executes Figure 1 - 8 one or more processes shown in, such as executing an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein. In at least one embodiment, system 800 includes Figure 9A - 42B one or more hardware shown in, such as for executing an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API and / or otherwise perform the operations described herein.

[0138] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of at least one embodiment. However, it will be apparent to one of ordinary skill in the art that the inventive concepts may be practiced without one or more of these specific details.

[0139] Logic

[0140] Figure 9A illustrates logic 915 according to at least one embodiment, such as described elsewhere herein, which can be used in one or more devices to perform operations such as those discussed herein. In at least one embodiment, logic 915 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 915 is inference and / or training logic. Details regarding logic 915 are provided below in conjunction with Figure 9A and / or Figure 9B In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic for providing the functions or operations described herein, where the logic can be embodied jointly or separately as circuitry forming part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., a CPU, a GPU)).

[0141] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 901, which is used to store forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 901 for storing graph code or other software to control timing and / or sequence, where weights and / or other parameter information is loaded to configure the logic, which includes integer and / or floating-point units (collectively referred to as arithmetic logic unit (ALU)). In at least one embodiment, the code (such as graph code) loads the weights or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 901 stores the weight parameters and / or input / output data of each layer of the neural network that is combined with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 901 may be included within other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory.

[0142] In at least one embodiment, any portion of code and / or data storage 901 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 901 may be cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 901 is internal or external to the processor, for example, or includes DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0143] In at least one embodiment, logic 915 may include, but is not limited to, code and / or data storage 905 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that are trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, code and / or data storage 905 stores weight parameters and / or input / output data for each layer of the neural network that is trained or used in conjunction with one or more embodiments during backpropagation of the input / output data and / or weight parameters. In at least one embodiment, logic 915 may include or be coupled to code and / or data storage 905 for storing graph code or other software to control timing and / or sequencing, where weights and / or other parameter information is loaded to configure the logic, which includes integer and / or floating-point units (collectively referred to as arithmetic logic unit (ALU)).

[0144] In at least one embodiment, the code (such as graph code) causes weight or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 905 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 905 may be cache memory, DRAM, SRAM, non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 905 is internal or external to the processor, e.g., including DRAM, SRAM, flash memory, or some other storage type, may depend on on-chip versus off-chip available storage, latency requirements of the training and / or inference functions being performed, batch size of the data used in neural network inference and / or training, or some combination of these factors.

[0145] In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be separate storage structures. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be the same storage structure. In at least one embodiment, code and / or data storage 901 and code and / or data storage 905 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 901 and code and / or data storage 905 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0146] In at least one embodiment, logic 915 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 910 (including integer and / or floating point units) for performing logical and / or mathematical operations at least in part based on and / or as directed by training and / or inference code (e.g., graph code), the results of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in activation store 920, which are a function of input / output and / or weight parameter data stored in code and / or data store 901 and / or code and / or data store 905. In at least one embodiment, the activations stored in activation store 920 are generated according to linear algebra and / or matrix-based mathematics performed by ALU 910 in response to executing instructions or other code, where the weight values stored in code and / or data store 905 and / or code and / or data store 901 are used as operands along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in code and / or data store 905 or code and / or data store 901 or other on-chip or off-chip storage.

[0147] In at least one embodiment, one or more ALUs 910 are included within one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 910 may be external to the processors or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, ALU 910 may be included within the execution units of a processor or otherwise included in an ALU bank accessible by the execution units of a processor, which execution units may be within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, code and / or data store 901, code and / or data store 905, and activation store 920 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of activation store 920 may be included together with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of a processor or system memory. Additionally, inference and / or training code may be stored together with other code accessible by the processor or other hardware logic or circuits and may be fetched and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuits of the processor.

[0148] In at least one embodiment, the activation store 920 can be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the activation store 920 can be wholly or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether the activation store 920 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the on-chip versus off-chip available storage, the latency requirements for performing training and / or inference functions, the batch size of the data used in inferring and / or training a neural network, or some combination of these factors.

[0149] In at least one embodiment, Figure 9A the logic 915 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 9A the logic 915 shown can be used in conjunction with central processing unit (“CPU”) hardware, graphics processing unit (“GPU”) hardware, or other hardware (e.g., field programmable gate array (“FPGA”)).

[0150] Figure 9B Logic 915 is shown in accordance with at least one embodiment. In at least one embodiment, the logic 915 is inference and / or training logic. In at least one embodiment, the logic 915 can include, but is not limited to, hardware logic in which computing resources are dedicated or otherwise exclusively used with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 9B the logic 915 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore or the (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment, Figure 9BThe logic 915 shown in the figure can be used in combination with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (such as field programmable gate array (FPGA)). In at least one embodiment, the logic 915 includes, but is not limited to, code and / or data storage 901 and code and / or data storage 905, which can be used to store code (such as graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 9B In at least one embodiment shown in the figure, each of the code and / or data storage 901 and the code and / or data storage 905 is respectively associated with dedicated computing resources (such as computing hardware 902 and computing hardware 906). In at least one embodiment, each of the computing hardware 902 and the computing hardware 906 includes one or more ALUs that respectively perform mathematical functions (such as linear algebra functions) only on the information stored in the code and / or data storage 901 and the code and / or data storage 905, and the results are stored in the activation storage 920.

[0151] In at least one embodiment, each of the code and / or data storage 901 and 905 and the corresponding computing hardware 902 and 906 respectively corresponds to different layers of a neural network, such that the activation obtained from one storage / computation pair 901 / 902 of the code and / or data storage 901 and the computing hardware 902 is provided as the input to the next storage / computation pair 905 / 906 of the code and / or data storage 905 and the computing hardware 906, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 901 / 902 and 905 / 906 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 915 after or in parallel with the storage / computation pairs 901 / 902 and 905 / 906.

[0152] Neural Network Training and Deployment

[0153] Figure 10Illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, a training dataset 1002 is used to train an untrained neural network 1006. In at least one embodiment, the training framework 1004 is the PyTorch framework, while in other embodiments, the training framework 1004 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j or other training frameworks. In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 and enables it to be trained using the processing resources described herein to generate a trained neural network 1008. In at least one embodiment, the weights can be randomly selected or selected by pre-training using a deep belief network. In at least one embodiment, training can be performed in a supervised, partially supervised or unsupervised manner.

[0154] In at least one embodiment, supervised learning is used to train the untrained neural network 1006, where the training dataset 1002 includes inputs paired with desired outputs for the inputs, or where the training dataset 1002 includes inputs with known outputs and the outputs of the neural network 1006 are manually graded. In at least one embodiment, the untrained neural network 1006 is trained in a supervised manner, processes the inputs from the training dataset 1002, and compares the resulting outputs with a set of expected or desired outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 1006. In at least one embodiment, the training framework 1004 adjusts the weights that control the untrained neural network 1006. In at least one embodiment, the training framework 1004 includes tools for monitoring the degree to which the untrained neural network 1006 converges to a model (such as the trained neural network 1008) suitable for generating correct answers (such as results 1014) based on input data (such as new dataset 1012). In at least one embodiment, the training framework 1004 repeatedly trains the untrained neural network 1006 while adjusting the weights to refine the output of the untrained neural network 1006 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 1004 trains the untrained neural network 1006 until the untrained neural network 1006 reaches a desired accuracy. In at least one embodiment, the trained neural network 1008 can then be deployed to implement any number of machine learning operations.

[0155] In at least one embodiment, unsupervised learning is used to train an untrained neural network 1006, where the untrained neural network 1006 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 1002 will include input data without any associated output data or "groundtruth" data. In at least one embodiment, the untrained neural network 1006 can learn groupings within the training dataset 1002 and can determine how individual inputs relate to the untrained dataset 1002. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 1008, which can perform operations useful for reducing the dimensionality of a new dataset 1012. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 1012 that deviate from the normal pattern of the new dataset 1012.

[0156] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 1002. In at least one embodiment, the training framework 1004 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 1008 to adapt to a new dataset 1012 without forgetting the knowledge injected into the trained neural network 1008 during initial training.

[0157] In at least one embodiment, the training framework 1004 is a framework that is processed in combination with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit developed, for example, by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 915 or uses logic 915 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0158] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (particularly neural network applications) for various tasks and operations, such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries, such as OpenCV, OpenCL, and / or variants thereof.

[0159] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., of a person and / or an object), monocular depth estimation, inpainting, style transfer, action recognition, coloring, and / or variants thereof.

[0160] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as the Model Optimizer. In at least one embodiment, the Model Optimizer is a command-line tool that facilitates the transformation between the training and deployment of a neural network model. In at least one embodiment, the Model Optimizer optimizes a neural network model for execution on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the Model Optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the Model Optimizer reduces the number of layers of the model. In at least one embodiment, the Model Optimizer removes layers of the model used for training. In at least one embodiment, the Model Optimizer performs various neural network operations such as modifying the input of the model (e.g., resizing the input of the model), modifying the size of the input of the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalization, standardization, quantization (e.g., converting the weights of the model from a first representation such as floating point to a second representation such as integer), and / or variants thereof.

[0161] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as the Inference Engine. In at least one embodiment, the Inference Engine is a C++ library or a library in any suitable programming language. In at least one embodiment, the Inference Engine is used to infer input data. In at least one embodiment, the Inference Engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the Inference Engine implements one or more API functions to process the intermediate representation, set the input and / or output format, and / or execute the model on one or more devices.

[0162] In at least one embodiment, OpenVINO provides various capabilities for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., execute a first set of layers on a first device (e.g., GPU) and a second set of layers on a second device (e.g., CPU)).

[0163] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or techniques described herein are implemented using OpenVINO.

[0164] Data center

[0165] Figure 11 An example data center 1100 that can use at least one embodiment is shown. In at least one embodiment, data center 1100 includes a data center infrastructure layer 1110, a framework layer 1120, a software layer 1130, and an application layer 1140.

[0166] In at least one embodiment, as Figure 11As shown, the data center infrastructure layer 1110 may include a resource coordinator 1112, grouped computing resources 1114, and node computing resources (“node C.R.”) 1116(1)-1116(N), where “N” represents a positive integer (which may be a different integer “N” than the integer used in other figures). In at least one embodiment, the node C.R. 1116(1)-1116(N) may include, but is not limited to, any number of central processing units (“CPU”) or other processors (including accelerators, field programmable gate arrays (FPGA), graphics processors, etc.), memory storage devices 1118(1)-1118(N) (such as dynamic read-only memory, solid-state storage, or disk drives), network input / output (“NW I / O”) devices, network switches, virtual machines (“VM”), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 1116(1)-1116(N) may be servers having one or more of the above computing resources.

[0167] In at least one embodiment, the grouped computing resources 1114 may include separate groupings of node C.R. housed within one or more racks (not shown), or many racks housed within data centers (also not shown) at various geographical locations. In at least one embodiment, the separate groupings of node C.R. within the grouped computing resources 1114 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0168] In at least one embodiment, the resource coordinator 1112 may configure or otherwise control one or more of the node C.R. 1116(1)-1116(N) and / or the grouped computing resources 1114. In at least one embodiment, the resource coordinator 1112 may include a software design infrastructure (“SDI”) management entity for the data center 1100. In at least one embodiment, the resource coordinator 1112 may include hardware, software, or some combination thereof.

[0169] In at least one embodiment, as Figure 11As shown, the framework layer 1120 includes a job scheduler 1122, a configuration manager 1124, a resource manager 1126, and a distributed file system 1128. In at least one embodiment, the framework layer 1120 may include a framework that supports software 1132 of the software layer 1130 and / or one or more applications 1142 of the application layer 1140. In at least one embodiment, the software 1132 or the application 1142 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 1120 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark that can utilize the distributed file system 1128 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 1122 may include a Spark driver for facilitating the scheduling of workloads supported by the various layers of the data center 1100. In at least one embodiment, the configuration manager 1124 may be capable of configuring different layers, such as the software layer 1130 and the framework layer 1120 including Spark and the distributed file system 1128 for supporting large-scale data processing. In at least one embodiment, the resource manager 1126 may be capable of managing clustered or grouped computing resources mapped to or allocated for supporting the distributed file system 1128 and the job scheduler 1122. In at least one embodiment, the clustered or grouped computing resources may include grouped computing resources 1114 at the data center infrastructure layer 1110. In at least one embodiment, the resource manager 1126 may coordinate with the resource coordinator 1112 to manage these mapped or allocated computing resources.

[0170] In at least one embodiment, the software 1132 included in the software layer 1130 may include software used by at least respective parts of the nodes C.R. 1116(1)-1116(N), the grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0171] In at least one embodiment, one or more applications 1142 included in the application layer 1140 may include one or more types of applications used by at least respective portions of nodes C.R. 1116(1)-1116(N), grouped computing resources 1114, and / or the distributed file system 1128 of the framework layer 1120. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (such as PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0172] In at least one embodiment, any one of the configuration manager 1124, the resource manager 1126, and the resource coordinator 1112 may implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve the data center operator of the data center 1100 from making potentially poor configuration decisions and may avoid underutilization and / or poorly performing portions of the data center.

[0173] In at least one embodiment, the data center 1100 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 1100. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, the resources described above with respect to the data center 1100 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0174] In at least one embodiment, the data center may use a CPU, an application specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. In addition, one or more of the above software and / or hardware resources may be configured as a service for allowing a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0175] Logic 915 is for performing inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 9A and / or Figure 9BProvide details regarding Logic 915. In at least one embodiment, Logic 915 can be used in a Figure 11 system for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0176] In at least one embodiment, one or more of the depicted systems related to the previous figures are used to implement the techniques, functions, and / or processes regarding Figure 1 - 8 described. In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to execute Figure 1 - 8 at least one aspect of the components within. In at least one embodiment, one or more of the depicted systems in the previous figure are used to implement one or more systems and / or processes such as regarding Figure 1 - 8 described, e.g., a processor that includes one or more circuits to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0177] In at least one embodiment, one or more of the depicted systems related to the previous figures are used to implement the techniques, functions, and / or processes regarding Figure 1 - 8 described. In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to execute Figure 1 - 8 at least one aspect of the components within. In at least one embodiment, one or more of the depicted systems in the previous figure are used to implement one or more systems and / or processes such as regarding Figure 1 - 8 described, e.g., a processor that includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API.

[0178] Autonomous vehicle

[0179] Figure 12AAn example of an autonomous vehicle 1200 according to at least one embodiment is shown. In at least one embodiment, the autonomous vehicle 1200 (alternatively referred to herein as "vehicle 1200") can be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, the vehicle 1200 can be a semi-trailer truck for hauling goods. In at least one embodiment, the vehicle 1200 can be an airplane, a robotic vehicle, or another type of vehicle.

[0180] The autonomous vehicle can be described according to the automation levels defined by the National Highway Traffic Safety Administration ("NHTSA") under the United States Department of Transportation and the Society of Automotive Engineers ("SAE") in "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806 issued on June 15, 2018, Standard No. J3016-201609 issued on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, the vehicle 1200 may be capable of having functions according to one or more of Levels 1 to 5 of the autonomous driving levels. For example, in at least one embodiment, the vehicle 1200 may be capable of having conditional automation (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0181] In at least one embodiment, the vehicle 1200 can include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, the vehicle 1200 can include, but is not limited to, a propulsion system 1250 such as an internal combustion engine, a hybrid device, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, the propulsion system 1250 can be connected to the driveline of the vehicle 1200, which can include, but is not limited to, a transmission for enabling the propulsion of the vehicle 1200. In at least one embodiment, the propulsion system 1250 can be controlled in response to receiving a signal from the throttle / accelerator 1252.

[0182] In at least one embodiment, when the propulsion system 1250 is operating (e.g., when the vehicle 1200 is in motion), the steering system 1254 (which may include, but is not limited to, a steering wheel) is used to steer the vehicle 1200 (e.g., along a desired path or route). In at least one embodiment, the steering system 1254 may receive a signal from the steering actuator 1256. In at least one embodiment, for fully automated (Level 5) functionality, the steering wheel may be optional. In at least one embodiment, the brake sensor system 1246 may be used to operate the vehicle brakes in response to signals received from the brake actuator 1248 and / or the brake sensors.

[0183] In at least one embodiment, one or more controllers 1236, which may include, but are not limited to, one or more systems-on-chip (“SoC”) ( Figure 12A not shown) and / or graphics processing units (“GPU”), provide signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1200. For example, in at least one embodiment, one or more controllers 1236 may send signals to operate the vehicle brakes via the brake actuator 1248, operate the steering system 1254 via one or more steering actuators 1256, and operate the propulsion system 1250 via one or more throttle / accelerators 1252. In at least one embodiment, one or more controllers 1236 may include one or more on-vehicle (e.g., integrated) computing devices that process sensor signals and output operating commands (e.g., signals representative of commands) to effect autonomous driving and / or assist a human driver in driving the vehicle 1200. In at least one embodiment, one or more controllers 1236 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may handle two or more of the above functions, two or more controllers may handle a single function, and / or any combination thereof.

[0184] In at least one embodiment, one or more controllers 1236 provide signals for controlling one or more components and / or systems of vehicle 1200 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, the sensor data may be received from sensors such as, but not limited to: one or more Global Navigation Satellite System (“GNSS”) sensors 1258 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1260, one or more ultrasonic sensors 1262, one or more LIDAR sensors 1264, one or more Inertial Measurement Unit (IMU) sensors 1266 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1296, one or more stereo cameras 1268, one or more wide-angle cameras 1270 (e.g., fisheye cameras), one or more infrared cameras 1272, one or more surround cameras 1274 (e.g., 360-degree cameras), remote cameras ( Figure 12A not shown in Figure 12A ), mid-range cameras (

[0185] not shown in Figure 12A ), one or more speed sensors 1244 (e.g., for measuring the speed of vehicle 1200), one or more vibration sensors 1242, one or more steering sensors 1240, one or more brake sensors (e.g., as part of a brake sensor system 1246), and / or other sensor types.

[0185] In at least one embodiment, one or more controllers 1236 may receive inputs (e.g., represented by input data) from the instrument panel 1232 of vehicle 1200 and provide outputs (e.g., represented by output data, display data, etc.) via a Human Machine Interface (“HMI”) display 1234, a sound signaler, a speaker, and / or via other components of vehicle 1200. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., high-definition map ( Figure 12A not shown in

[0186] In at least one embodiment, vehicle 1200 further includes a network interface 1224 that can communicate over one or more networks using one or more wireless antennas 1226 and / or one or more modems. For example, in at least one embodiment, network interface 1224 may be capable of communicating over Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1226 may also be used to enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more Low-Power Wide-Area Networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0187] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, logic 915 may be used in a Figure 12A system to perform inference or prediction operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0188] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figure 1 - 8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to perform Figure 1 - 8 at least one aspect of the components within. Figure 1 - 8 In at least one embodiment, one or more of the systems depicted in the previous figure are used to implement one or more systems and / or processes such as those described with respect to

[0189] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figure 1 - 8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to execute Figure 1 - 8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figure 1 - 8 For example, a processor that includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API.

[0190] Figure 12B Shows an example of the camera positions and fields of view of an autonomous vehicle 1200 according to at least one embodiment. Figure 12A In at least one embodiment, the cameras and their respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different positions on the vehicle 1200.

[0191] In at least one embodiment, the camera types for the cameras may include, but are not limited to, digital cameras that may be suitable for use with the components and / or systems of the vehicle 1200. In at least one embodiment, one or more cameras may operate at an automotive safety integrity level (“ASIL”) B and / or other ASIL. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120 fps, 240 fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or a combination thereof. In at least one embodiment, the color filter array may include a red clear clear clear (“RCCC”) color filter array, a red clear clear blue (“RCCB”) color filter array, a red blue green clear (“RBGC”) color filter array, a Foveon X3 color filter array, a Bayer (RGGB) sensor color filter array, a monochrome sensor color filter array, and / or other types of color filter arrays. In at least one embodiment, transparent pixel cameras, such as cameras having RCCC, RCCB, and / or RBGC color filter arrays, may be used to attempt to improve photosensitivity.

[0192] In at least one embodiment, one or more cameras can be used to perform Advanced Driver Assistance System (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and smart headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can record and provide image data (e.g., video) simultaneously.

[0193] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”) printed) assembly, to remove stray light and reflected light from within the vehicle 1200 (e.g., reflected light from the dashboard reflected in the windshield mirror) that may interfere with the camera's image data capture ability. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed custom such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side cameras, one or more cameras can also be integrated within the four pillars at each corner of the cabin.

[0194] In at least one embodiment, a camera having a field of view of portions of the environment in front of the vehicle 1200 (e.g., a forward camera) can be used for surround view to help identify the forward path and obstacles, and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 1236 and / or a control SoC. In at least one embodiment, the forward camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (such as traffic sign recognition).

[0195] In at least one embodiment, a variety of cameras can be used in a forward configuration, including for example a monocular camera platform including a CMOS (“Complementary Metal Oxide Semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1270 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 12BOnly one wide - angle camera 1270 is shown, but in other embodiments, any number (including zero) of wide - angle cameras can be on the vehicle 1200. In at least one embodiment, any number of long - range cameras 1298 (e.g., tele - stereo camera pairs) can be used for depth - based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, one or more long - range cameras 1298 can also be used for object detection and classification and basic object tracking.

[0196] In at least one embodiment, any number of stereo cameras 1268 can also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1268 can include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and a multi - core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of the environment of the vehicle 1200, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1268 can include, but are not limited to, compact stereo vision sensors, which can include, but are not limited to, two camera lenses (one on the left and one on the right) and an image - processing chip, which can measure the distance from the vehicle 1200 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1268 can be used in addition to or in place of those described herein.

[0197] In at least one embodiment, a camera with a field of view of portions of the environment including the sides of the vehicle 1200 (e.g., a side - view camera) can be used for surround - view, which provides information for creating and updating an occupancy grid and generating side - impact collision warnings. For example, in at least one embodiment, surround cameras 1274 (e.g., four surround cameras as Figure 12B shown) can be positioned on the vehicle 1200. In at least one embodiment, one or more surround cameras 1274 can include, but are not limited to, any number and combination of wide - angle cameras, one or more fisheye cameras, one or more 360 - degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of the vehicle 1200. In at least one embodiment, the vehicle 1200 can use three surround cameras 1274 (e.g., left, right, and rear), and can utilize one or more other cameras (e.g., a forward camera) as the fourth surround - view camera.

[0198] In at least one embodiment, a camera (e.g., a rearview camera) having a field of view that includes portions of the environment behind vehicle 1200 can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as one or more forward cameras (e.g., long-range camera 1298 and / or one or more mid-range cameras 1276, one or more stereo cameras 1268, one or more infrared cameras 1272, etc.), as described herein.

[0199] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, logic 915 can be used in a Figure 12B system to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0200] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figure 1 - 8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers of one or more neural networks based at least in part on one or more indications of one or more layers of the one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to execute Figure 1 - 8 at least one aspect of the components within Figure 1 - 8 In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to

[0201] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figure 1 - 8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to execute Figure 1 - 8At least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figure 1 - 8 For example, a processor that includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API.

[0202] Figure 12C Is a block diagram showing an example system architecture of an autonomous vehicle 1200 according to at least one embodiment. In at least one embodiment, Figure 12A Each of the components, features, and systems of the vehicle 1200 in Figure 12C Is shown connected via a bus 1202. In at least one embodiment, the bus 1202 may include, but is not limited to, a CAN data interface (alternatively referred to herein as the "CAN bus"). In at least one embodiment, CAN may be a network inside the vehicle 1200 to assist in controlling various features and functions of the vehicle 1200, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, the bus 1202 may be configured to have dozens or even hundreds of nodes, each with its own unique identifier (e.g., CAN ID). In at least one embodiment, the bus 1202 can be read to find the steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle state indicators. In at least one embodiment, the bus 1202 may be a CAN bus compliant with ASIL B.

[0203] In at least one embodiment, in addition to or instead of CAN, FlexRay and / or Ethernet protocols may also be used. In at least one embodiment, there may be any number of buses forming bus 1202, which may include but are not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, the first bus may be used for collision avoidance functions and the second bus may be used for actuation control. In at least one embodiment, each of the buses in bus 1202 may communicate with any component of vehicle 1200, and two or more of the buses in bus 1202 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips (“SoCs”) 1204 (e.g., SoC 1204(A) and SoC 1204(B)), each of one or more controllers 1236, and / or each computer within the vehicle may access the same input data (e.g., input from sensors of vehicle 1200) and may be connected to a common bus, such as a CAN bus.

[0204] In at least one embodiment, vehicle 1200 may include one or more controllers 1236, such as those described herein with respect to Figure 12A In at least one embodiment, controller 1236 may be used for a variety of functions. In at least one embodiment, controller 1236 may be coupled to any one of a variety of other components and systems of vehicle 1200 and may be used to control vehicle 1200, the artificial intelligence of vehicle 1200, the infotainment of vehicle 1200, and / or other functions.

[0205] In at least one embodiment, vehicle 1200 may include any number of SoCs 1204. In at least one embodiment, each of the SoCs 1204 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1206, a graphics processing unit (“one or more GPUs”) 1208, one or more processors 1210, one or more caches 1212, one or more accelerators 1214, one or more data stores 1216, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1204 may be used to control vehicle 1200 in a variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1204 may be combined with a high-definition (“HD”) map 1222 in a system (e.g., the system of vehicle 1200), and the HD map 1222 may obtain map refreshes and / or updates from one or more servers ( Figure 12C not shown in figure) via network interface 1224.

[0206] In at least one embodiment, one or more CPUs 1206 may include a CPU cluster or CPU complex (alternatively referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1206 may include multiple cores and / or secondary (“L2”) caches. For example, in at least one embodiment, one or more CPUs 1206 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, one or more CPUs 1206 may include four dual-core clusters, each with a dedicated L2 cache (e.g., 2 megabytes (MB) L2 cache). In at least one embodiment, one or more CPUs 1206 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, which allows any combination of the clusters of one or more CPUs 1206 to be active at any given time.

[0207] In at least one embodiment, one or more CPUs 1206 may implement power management functions, which may include, but are not limited to, one or more of the following features: automatically clock-gating individual hardware blocks when idle to save dynamic power; clock-gating each core clock when the core is not actively executing instructions due to executing a wait for interrupt ("WFI") / wait for event ("WFE") instruction; each core may be independently power-gated; each core cluster may be independently clock-gated when all cores are clock-gated or power-gated; and / or each core cluster may be independently power-gated when all cores are power-gated. In at least one embodiment, one or more CPUs 1206 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power states to enter for cores, clusters, and CCPLEX. In at least one embodiment, the processing cores may support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0208] In at least one embodiment, one or more GPUs 1208 may include an integrated GPU (alternatively referred to herein as "iGPU"). In at least one embodiment, one or more GPUs 1208 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1208 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1208 may include one or more streaming microprocessors, where each streaming microprocessor may include a level 1 ("L1") cache (e.g., an L1 cache with a storage capacity of at least 96 KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a storage capacity of 512 KB). In at least one embodiment, one or more GPUs 1208 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1208 may use one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1208 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0209] In at least one embodiment, one or more GPUs 1208 may be power optimized to achieve optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1208 may be fabricated on fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. By way of example and not limitation, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler) or an ordinal unit, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include independent parallel integer and floating-point data paths for providing efficient execution of workloads with a mix of computational and addressing operations. In at least one embodiment, the streaming microprocessor may include independent thread scheduling capabilities to enable more fine-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0210] In at least one embodiment, one or more GPUs 1208 may include high bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem, which in some examples is used to provide a peak memory bandwidth of approximately 900GB / second. In at least one embodiment, synchronous graphics random access memory (“SGRAM”), such as fifth-generation graphics double data rate type synchronous random access memory (“GDDR5”), may be used in addition to or in place of HBM memory.

[0211] In at least one embodiment, one or more GPUs 1208 may include unified memory technology. In at least one embodiment, address translation service ("ATS") support may be used to allow one or more GPUs 1208 to directly access the page tables of one or more CPUs 1206. In at least one embodiment, when a memory management unit ("MMU") of a GPU in one or more GPUs 1208 experiences a miss, an address translation request may be sent to one or more CPUs 1206. In response, in at least one embodiment, two CPUs in one or more CPUs 1206 may look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1208. In at least one embodiment, unified memory technology may allow a single unified virtual address space for the memories of both one or more CPUs 1206 and one or more GPUs 1208, thus simplifying the programming of one or more GPUs 1208 and the porting of applications to one or more GPUs 1208.

[0212] In at least one embodiment, one or more GPUs 1208 may include any number of access counters, which may track the access frequency of one or more GPUs 1208 to the memories of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved to the physical memory of the processor that accesses the pages most frequently, thereby improving the efficiency of sharing memory ranges among processors.

[0213] In at least one embodiment, one or more SoCs 1204 may include any number of caches 1212, including those described herein. For example, in at least one embodiment, one or more caches 1212 may include a level 3 ("L3") cache that can be used by both one or more CPUs 1206 and one or more GPUs 1208 (e.g., connected to one or more CPUs 1206 and one or more GPUs 1208). In at least one embodiment, one or more caches 1212 may include a write-back cache, which may track the state of each row, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, depending on the embodiment, the L3 cache may include 4MB of memory or more.

[0214] In at least one embodiment, one or more SoCs 1204 may include one or more accelerators 1214 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1204 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memories. In at least one embodiment, a large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1208 and offload some tasks of one or more GPUs 1208 (e.g., to free up more cycles of one or more GPUs 1208 to perform other tasks). In at least one embodiment, one or more accelerators 1214 may be used for target workloads that are stable enough to withstand acceleration (e.g., perception, convolutional neural networks (“CNNs”), recurrent neural networks (“RNNs”), etc.). In at least one embodiment, CNNs may include region-based or region convolutional neural networks (“RCNNs”) and fast RCNNs (e.g., as used for object detection) or other types of CNNs.

[0215] In at least one embodiment, one or more accelerators 1214 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for a particular set of neural network types and floating point operations and inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including supporting, for example, INT8, INT16, and FP16 data types for single-instance convolution functions for features and weights and post-processor functions. In at least one embodiment, one or more DLAs may quickly and efficiently execute neural networks, especially CNNs, on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: CNNs for object recognition and detection using data from a camera sensor; CNNs for distance estimation using data from a camera sensor; CNNs for emergency vehicle detection and identification and detection using data from a microphone; CNNs for face recognition and vehicle owner identification using data from a camera sensor; and / or CNNs for security and / or safety-related events.

[0216] In at least one embodiment, one or more DLAs may perform any function of one or more GPUs 1208, and by using inference accelerators, for example, a designer may target one or more DLAs or one or more GPUs 1208 for any function. For example, in at least one embodiment, a designer may concentrate the processing and floating point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 1208 and / or one or more accelerators 1214.

[0217] In at least one embodiment, one or more accelerators 1214 can include a Programmable Vision Accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA can be designed and configured to accelerate computer vision algorithms for Advanced Driver Assistance Systems (“ADAS”) 1238, autonomous driving, Augmented Reality (“AR”) applications, and / or Virtual Reality (“VR”) applications. In at least one embodiment, the PVA can provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA can include, for example but not limited to, any number of Reduced Instruction Set Computing (“RISC”) cores, Direct Memory Access (“DMA”), and / or any number of vector processors.

[0218] In at least one embodiment, the RISC cores can interact with an image sensor (e.g., the image sensor of any of the cameras described herein), an image signal processor, etc. In at least one embodiment, each RISC core can include any number of memories. In at least one embodiment, depending on the embodiment, the RISC cores can use any one of a variety of protocols. In at least one embodiment, the RISC cores can execute a Real-Time Operating System (“RTOS”). In at least one embodiment, one or more integrated circuit devices, Application-Specific Integrated Circuits (“ASICs”), and / or memory devices can be used to implement the RISC cores. For example, in at least one embodiment, the RISC cores can include an instruction cache and / or tightly coupled RAM.

[0219] In at least one embodiment, the DMA can enable the components of the PVA to access system memory independently of one or more CPUs 1206. In at least one embodiment, the DMA can support any number of features for optimizing the delivery to the PVA, including but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA can support up to six or more dimensions of addressing, which can include but are not limited to block width, block height, block depth, horizontal block step, vertical block step, and / or depth step.

[0220] In at least one embodiment, the vector processor may be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines) and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a single instruction multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0221] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a general computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may simultaneously execute different computer vision algorithms on one image, or even execute different algorithms on a sequence of images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory for enhancing overall system security.

[0222] In at least one embodiment, one or more accelerators 1214 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the one or more accelerators 1214. In at least one embodiment, the on-chip memory may include at least 4MB SRAM, which includes, for example but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0223] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / address / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / address / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, although other standards and protocols may be used, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard.

[0224] In at least one embodiment, one or more SoCs 1204 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of an object (e.g., within a world model) to generate a real-time visualization simulation for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0225] In at least one embodiment, one or more accelerators 1214 can have a wide range of uses for autonomous driving. In at least one embodiment, PVA can be used in key processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA at low power and low latency match well with algorithm domains that require predictable processing. In other words, PVA excels in semi-dense or dense general-purpose computing, even on small data sets that may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1200, PVA can be designed to run classical computer vision algorithms as they can be efficient in object detection and integer math operations.

[0226] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, an algorithm based on semi-global matching can be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for level 3-5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on inputs from two monocular cameras.

[0227] In at least one embodiment, PVA can be used to perform dense optical flow. For example, in at least one embodiment, PVA can process raw RADAR data (e.g., using 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, for example, PVA is used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0228] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including for example but not limited to neural networks, the output of which is a measure of the confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or represented as providing a relative “weight” of each detection compared to other detections. In at least one embodiment, the confidence measure enables the system to make further decisions, namely which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence, and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking (“AEB”) system, false positive detections would cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered a trigger for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network can take at least some subset of parameters as its input, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), the output of one or more IMU sensors 1266 related to the vehicle 1200 direction, distance, 3D position estimate of an object obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1264 or one or more RADAR sensors 1260).

[0229] In at least one embodiment, one or more SoCs 1204 can include one or more data stores 1216 (e.g., memories). In at least one embodiment, one or more data stores 1216 can be on-chip memories of one or more SoCs 1204, which can store neural networks to be executed on one or more GPUs 1208 and / or DLA. In at least one embodiment, one or more data stores 1216 can have a large enough capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, one or more data stores 1216 can include one or more L2 or L3 caches.

[0230] In at least one embodiment, one or more SoCs 1204 may include any number of processors 1210 (e.g., embedded processors). In at least one embodiment, one or more processors 1210 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions as well as related secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1204 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low-power state transitions, manage one or more SoC 1204 thermal and temperature sensors, and / or manage the power state of one or more SoCs 1204. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1204 may use the ring oscillator to detect the temperature of one or more CPUs 1206, one or more GPUs 1208, and / or one or more accelerators 1214. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1204 in a lower power state and / or place the vehicle 1200 in a driver-safe parking mode (e.g., safely park the vehicle 1200).

[0231] In at least one embodiment, one or more processors 1210 may further include a set of embedded processors that may be used as an audio processing engine, which may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0232] In at least one embodiment, one or more processors 1210 may further include an always-on processor engine that may provide the necessary hardware features to support low-power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0233] In at least one embodiment, one or more processors 1210 may further include a secure cluster engine that includes, but is not limited to, a dedicated processor subsystem for handling the security management of automotive applications. In at least one embodiment, the secure cluster engine may include, but is not limited to, two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.), and / or routing logic. In a secure mode, in at least one embodiment, two or more cores may operate in a lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1210 may further include a real-time camera engine that may include, but is not limited to, a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1210 may further include a high-dynamic range signal processor that may include, but is not limited to, an image signal processor that is a hardware engine as part of a camera processing pipeline.

[0234] In at least one embodiment, one or more processors 1210 may include a video image synthesizer that may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required for a video playback application to produce a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1270, one or more surround cameras 1274, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 1204, and the neural network is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform, but is not limited to, lip reading to activate cellular services and make phone calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are otherwise disabled.

[0235] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion occurring in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of the information provided by adjacent frames. In at least one embodiment, in the case where an image or a portion of the image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from a previous image to reduce the noise in the current image.

[0236] In at least one embodiment, the video image synthesizer may also be configured to perform stereo correction on the input stereo camera frames. In at least one embodiment, when the operating system desktop is in use, the video image synthesizer may also be used for user interface synthesis and does not require one or more GPUs 1208 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1208 are powered on and active for 3D rendering, the video image synthesizer may be used to offload one or more GPUs 1208 to improve performance and responsiveness.

[0237] In at least one embodiment, one or more of the SoCs 1204 may further include a Mobile Industry Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block for receiving video and inputs from cameras, which can be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoCs 1204 may further include an input / output controller, which can be software-controlled and can be used to receive I / O signals not committed to a specific role.

[0238] In at least one embodiment, one or more of the SoCs 1204 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoder / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1204 can be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., one or more LIDAR sensors 1264, one or more RADAR sensors 1260, etc., which can be connected via Ethernet channels), data from the bus 1202 (e.g., the speed, steering wheel position, etc. of the vehicle 1200), data from one or more GNSS sensors 1258 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more of the SoCs 1204 may further include a dedicated high-performance mass storage controller, which may include its own DMA engine and can be used to free one or more CPUs 1206 from conventional data management tasks.

[0239] In at least one embodiment, one or more SoCs 1204 can be an end-to-end platform with a flexible architecture that spans automation levels 3-5, thereby providing an integrated functional safety architecture for a platform that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1204 can be faster, more reliable, and even more energy-efficient and space-efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1214, when combined with one or more CPUs 1206, one or more GPUs 1208, and one or more data stores 1216, can provide a fast and efficient platform for level 3-5 autonomous vehicles.

[0240] In at least one embodiment, computer vision algorithms can be executed on the CPU, which can be configured using a high-level programming language (such as C) to execute various processing algorithms on various visual data. However, in at least one embodiment, the CPU generally cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real time, which are used in in-vehicle ADAS applications and actual level 3-5 autonomous vehicles.

[0241] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined to achieve level 3-5 autonomous driving functions. For example, in at least one embodiment, the CNN executed on the DLA or discrete GPU (e.g., one or more GPUs 1220) can include text and word recognition, thereby allowing traffic signs to be read and understood, including signs that the neural network has not been specifically trained for. In at least one embodiment, the DLA can also include a neural network that is capable of recognizing, interpreting, and providing semantic understanding of the signs, and passing that semantic understanding to a path planning module running on the CPU complex.

[0242] In at least one embodiment, for level 3, 4, or 5 driving, multiple neural networks can run simultaneously. For example, in at least one embodiment, a warning sign that states "Caution: flashing lights indicate icy conditions", along with the electric lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executed on the CPU complex) that when flashing lights are detected, there is an icy condition. In at least one embodiment, a third deployed neural network can operate on multiple frames to identify the flashing lights and notify the vehicle's path planning software of the presence (or absence) of the flashing lights. In at least one embodiment, all three neural networks can run simultaneously, e.g., within the DLA and / or on one or more GPUs 1208.

[0243] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from a camera sensor to identify the presence of an authorized driver and / or the owner of the vehicle 1200. In at least one embodiment, a normally open sensor processing engine can be used to unlock the vehicle when the owner approaches the driver's door and turns on the lights, and in a security mode, can be used to disable the vehicle when the owner leaves the vehicle. In this way, one or more SoCs 1204 provide protection against theft and / or carjacking.

[0244] In at least one embodiment, a CNN for emergency vehicle detection and recognition can use data from a microphone 1296 to detect and recognize an emergency vehicle siren. In at least one embodiment, one or more SoCs 1204 use a CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, a CNN running on the DLA is trained to recognize the relative approach speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to recognize emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1258. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to recognize only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1262, to execute an emergency vehicle safety routine, slow down the vehicle, drive the vehicle to the side of the road, park the vehicle, and / or idle the vehicle until the emergency vehicle has passed.

[0245] In at least one embodiment, vehicle 1200 may include one or more CPUs 1218 (e.g., one or more discrete CPUs or one or more dCPUs), which may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 1218 may include, for example, X86 processors. One or more CPUs 1218 may be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1204, and / or monitoring the status and health of one or more controllers 1236 and / or the on-chip infotainment system (“Infotainment SoC”) 1230. In at least one embodiment, SoC 1204 includes one or more interconnects, and the interconnects may include Peripheral Component Interconnect Express (PCIe).

[0246] In at least one embodiment, vehicle 1200 may include one or more GPUs 1220 (e.g., one or more discrete GPUs or one or more dGPUs), which may be coupled to one or more SoCs 1204 via a high-speed interconnect (e.g., NVIDIA's NVLINK channels). In at least one embodiment, one or more GPUs 1220 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks at least in part based on inputs from sensors of vehicle 1200 (e.g., sensor data).

[0247] In at least one embodiment, vehicle 1200 may further include a network interface 1224, which may include but is not limited to one or more wireless antennas 1226 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1224 may be used to implement wireless connections to Internet cloud services (e.g., with servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1200 and another vehicle and / or an indirect link may be established (e.g., via a network and the Internet). In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1200 with information about vehicles in the vicinity of vehicle 1200 (e.g., vehicles in front of, to the side of, and / or behind vehicle 1200). In at least one embodiment, the foregoing function may be part of the cooperative adaptive cruise control function of vehicle 1200.

[0248] In at least one embodiment, network interface 1224 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 1236 to communicate over a wireless network. In at least one embodiment, network interface 1224 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functions may be provided by a separate chip. In at least one embodiment, the network interface may include wireless capabilities for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0249] In at least one embodiment, vehicle 1200 may further include one or more data stores 1228, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1204) storage. In at least one embodiment, one or more data stores 1228 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard disks, and / or other components and / or devices that can store at least one bit of data.

[0250] In at least one embodiment, vehicle 1200 may further include one or more GNSS sensors 1258 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1258 may be used, including, for example, but not limited to, a GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0251] In at least one embodiment, vehicle 1200 may further include one or more RADAR sensors 1260. In at least one embodiment, the one or more RADAR sensors 1260 may be used by vehicle 1200 for remote vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, the one or more RADAR sensors 1260 may use the CAN bus and / or bus 1202 (e.g., for transmitting data generated by the one or more RADAR sensors 1260) to control and access object tracking data and, in some examples, may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. For example but not limited to, the one or more RADAR sensors 1260 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1260 are pulsed Doppler RADAR sensors.

[0252] In at least one embodiment, the one or more RADAR sensors 1260 may include different configurations, such as long range with a narrow field of view, short range with a wide field of view, short range side coverage, etc. In at least one embodiment, long range RADAR may be used for adaptive cruise control functions. In at least one embodiment, the long range RADAR system may provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 m (meters)). In at least one embodiment, the one or more RADAR sensors 1260 may assist in differentiating between static and moving objects and may be used by ADAS system 1238 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more of the sensors 1260 included in the long range RADAR system may include but are not limited to a monostatic multimodal RADAR having multiple (e.g., six or more) fixed RADAR antennas and high speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the surrounding environment of vehicle 1200 at a higher speed with minimal traffic interference from adjacent lanes. In at least one embodiment, the other two antennas may widen the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1200.

[0253] In at least one embodiment, by way of example, a mid - range RADAR system can include a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short - range RADAR system can include, but is not limited to, any number of RADAR sensors 1260 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system can produce two beams that continuously monitor the rear direction and blind spots in the vicinity of the vehicle. In at least one embodiment, the short - range RADAR system can be used in the ADAS system 1238 for blind spot detection and / or lane change assistance.

[0254] In at least one embodiment, the vehicle 1200 can further include one or more ultrasonic sensors 1262. In at least one embodiment, one or more ultrasonic sensors 1262 that can be positioned at the front, rear, and / or side positions of the vehicle 1200 can be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1262 can be used, and different ultrasonic sensors 1262 can be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1262 can operate at a functional safety level of ASIL B.

[0255] In at least one embodiment, the vehicle 1200 can include one or more LIDAR sensors 1264. In at least one embodiment, one or more LIDAR sensors 1264 can be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LIDAR sensors 1264 can operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1200 can include multiple (e.g., two, four, six, etc.) LIDAR sensors 1264 that can use an Ethernet channel (e.g., to provide data to a gigabit Ethernet switch).

[0256] In at least one embodiment, one or more LIDAR sensors 1264 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1264 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm - 3 cm, and support an Ethernet connection of 100 Mbps. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1264 may include small devices that can be embedded in the front, rear, sides, and / or corner positions of the vehicle 1200. In at least one embodiment, one or more LIDAR sensors 1264, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, even for low-reflectivity objects, and have a range of 200 m. In at least one embodiment, the one or more forward-mounted LIDAR sensors 1264 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0257] In at least one embodiment, LIDAR technologies such as 3D flash LIDAR may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 m around the vehicle 1200. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1200 to the object. In at least one embodiment, flash LIDAR may allow for the generation of highly accurate and distortion-free images of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, with one deployed on each side of the vehicle 1200. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera that has no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use class I (eye-safe) laser pulses of 5 nanoseconds per frame and may capture the reflected laser as 3D range point clouds and co-registered intensity data.

[0258] In at least one embodiment, vehicle 1200 may further include one or more IMU sensors 1266. In at least one embodiment, one or more IMU sensors 1266 may be located at the center of the rear axle of vehicle 1200. In at least one embodiment, one or more IMU sensors 1266 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example, in a six-axis application, one or more IMU sensors 1266 may include but are not limited to accelerometers and gyroscopes. In at least one embodiment, for example, in a nine-axis application, one or more IMU sensors 1266 may include but are not limited to accelerometers, gyroscopes, and magnetometers.

[0259] In at least one embodiment, one or more IMU sensors 1266 may be implemented as a miniature high-performance GPS-aided inertial navigation system (“GPS / INS”) that combines microelectromechanical system (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm, for providing estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1266 may enable vehicle 1200 to estimate its heading by directly observing and correlating the speed changes from GPS to one or more IMU sensors 1266 without input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1266 and one or more GNSS sensors 1258 may be combined in a single integrated unit.

[0260] In at least one embodiment, vehicle 1200 may include one or more microphones 1296 placed inside and / or around vehicle 1200. In at least one embodiment, one or more microphones 1296 may be used for emergency vehicle detection and identification.

[0261] In at least one embodiment, vehicle 1200 may further include any number of camera types, including one or more stereo cameras 1268, one or more wide-angle cameras 1270, one or more infrared cameras 1272, one or more surround cameras 1274, one or more long-range cameras 1298, one or more mid-range cameras 1276, and / or other camera types. In at least one embodiment, the cameras may be used to capture image data around the entire periphery of vehicle 1200. In at least one embodiment, the type of cameras used depends on vehicle 1200. In at least one embodiment, any combination of camera types may be used to provide the necessary coverage around vehicle 1200. In at least one embodiment, the number of cameras deployed may vary according to the embodiment. For example, in at least one embodiment, vehicle 1200 may include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras may support, by way of example but not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera was previously described in more detail with reference to Figure 12A and Figure 12B Each camera is described in more detail.

[0262] In at least one embodiment, vehicle 1200 may further include one or more vibration sensors 1242. In at least one embodiment, one or more vibration sensors 1242 may measure the vibration of components of vehicle 1200 (e.g., an axle). For example, in at least one embodiment, a change in vibration may indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1242 are used, the difference between the vibrations may be used to determine the friction or skid of the road surface (e.g., when there is a vibration difference between a powered drive axle and a freely rotating axle).

[0263] In at least one embodiment, vehicle 1200 may include an ADAS system 1238. In at least one embodiment, the ADAS system 1238 may include, in some examples but not limited to, a SoC. In at least one embodiment, the ADAS system 1238 may include, but is not limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions.

[0264] In at least one embodiment, the ACC system can use one or more RADAR sensors 1260, one or more LIDAR sensors 1264, and / or any number of cameras. In at least one embodiment, the ACC system can include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of the vehicle 1200 and automatically adjusts the speed of the vehicle 1200 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that the vehicle 1200 change lanes when needed. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0265] In at least one embodiment, the CACC system uses information from other vehicles, which can be received indirectly from other vehicles via the network interface 1224 and / or one or more wireless antennas 1226 via a wireless link or through a network connection (e.g., via the Internet). In at least one embodiment, the direct link can be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link can be provided by an infrastructure-to-vehicle (“I2V”) communication link. Generally, V2V communication provides information about the vehicle immediately in front (e.g., the vehicle immediately in front of and in the same lane as the vehicle 1200), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system can include one or both of I2V and V2V information sources. In at least one embodiment, in the case of information about the vehicle in front of a given vehicle 1200, the CACC system can be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0266] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward camera and / or one or more RADAR sensors 1260, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system can provide warnings, such as in the form of sound, visual warnings, vibration, and / or rapid braking pulses.

[0267] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes in an attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision imminent braking.

[0268] In at least one embodiment, when vehicle 1200 crosses a lane marking, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibration, to alert the driver. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system can use a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1200 begins to leave its lane, the LKA system provides steering input or braking to correct vehicle 1200.

[0269] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of the automobile. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0270] In at least one embodiment, when the vehicle 1200 detects an object outside the rear camera range while reversing, the RCTW system can provide visual, auditory, and / or tactile notifications. In at least one embodiment, the RCTW system includes an AEB system for ensuring that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1260 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0271] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems will warn the driver and allow the driver to decide whether a safety situation truly exists and take action accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1200 itself decides whether to follow the result of the main computer or the auxiliary computer (e.g., the first controller or the second controller in the controller 1236). For example, in at least one embodiment, the ADAS system 1238 can be a backup and / or auxiliary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run various software redundantly on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1238 can be provided to the supervisory MCU. In at least one embodiment, if the output from the main computer and the output from the auxiliary computer conflict, the supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0272] In at least one embodiment, the main computer can be configured to provide a confidence score to the supervisory MCU, which indicates the confidence of the main computer in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the instructions of the main computer, regardless of whether the auxiliary computer provides conflicting or inconsistent results. In at least one embodiment, in the case where the confidence score does not meet the threshold and the main computer and the auxiliary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine an appropriate result.

[0273] In at least one embodiment, the supervisory MCU may be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides an error alert, at least in part, based on outputs from the host computer and outputs from the auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU may learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU may learn when the FCW system is identifying a metallic object that is not actually a hazard, such as a drain grate or manhole cover that would trigger an alert. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU may learn to override the LDW when there is a bicyclist or pedestrian present and when lane departure is actually the safest course of action. In at least one embodiment, the supervisory MCU may include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU may be included as and / or included in components of one or more SoCs 1204.

[0274] In at least one embodiment, the ADAS system 1238 may include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer may use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU may improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementation and intentional non-identity make the overall system more fault-tolerant, especially for faults caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the host computer and the not-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU may have greater confidence that the overall result is correct, and the vulnerability in the software or hardware on the host computer will not result in a major error.

[0275] In at least one embodiment, the output of the ADAS system 1238 may be fed into the perception block of the host computer and / or the dynamic driving task block of the host computer. For example, in at least one embodiment, if the ADAS system 1238 indicates a forward collision warning due to an object directly ahead, the perception block may use that information when identifying the object. In at least one embodiment, as described herein, the auxiliary computer may have its own neural network that is trained to reduce the risk of false alarms.

[0276] In at least one embodiment, vehicle 1200 may further include an infotainment SoC 1230 (e.g., in-vehicle infotainment (IVI)). Although shown and described as an SoC, in at least one embodiment, infotainment system SoC 1230 may not be an SoC and may include, but not be limited to, two or more discrete components. In at least one embodiment, infotainment SoC 1230 may include, but not be limited to, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total covered distance, brake fuel level, oil level, door open / closed, air filter information, etc.) to vehicle 1200. For example, infotainment SoC 1230 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio control, hands-free voice control, head-up display (“HUD”), HMI display 1234, telematics device, control panel (e.g., for controlling various components, features, and / or systems and / or interacting therewith), and / or other components. In at least one embodiment, infotainment SoC 1230 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of vehicle 1200, such as information from ADAS system 1238, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0277] In at least one embodiment, infotainment SoC 1230 may include any number and type of GPU functionality. In at least one embodiment, infotainment SoC 1230 may communicate with other devices, systems, and / or components of vehicle 1200 via bus 1202. In at least one embodiment, infotainment SoC 1230 may be coupled to a supervisory MCU such that the GPU of the infotainment system may perform some autonomous driving functions in the event of a failure of one or more main controllers 1236 (e.g., the main computer and / or standby computer of vehicle 1200). In at least one embodiment, infotainment SoC 1230 may place vehicle 1200 into the driver to safe stop mode as described herein.

[0278] In at least one embodiment, vehicle 1200 may further include a dashboard 1232 (e.g., a digital dashboard, an electronic dashboard, a digital instrument panel, etc.). In at least one embodiment, the dashboard 1232 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, the dashboard 1232 may include, but is not limited to, any number and combination of a set of gauges, such as a speedometer, fuel level, oil pressure, tachometer, odometer, turn indicator, shift position indicator, one or more seat belt warning lights, one or more parking brake warning lights, one or more engine fault lights, auxiliary restraint system (e.g., airbag) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1230 and the dashboard 1232. In at least one embodiment, the dashboard 1232 may be included as part of the infotainment SoC 1230, and vice versa.

[0279] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 9A and / or Figure 9B Details regarding logic 915 are provided. In at least one embodiment, logic 915 may be in a Figure 12C system for performing inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0280] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figure 1 - 8 In at least one embodiment, at least one component of the previous figures is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figures is used to execute Figure 1 - 8 at least one aspect of the components within Figure 1 - 8 In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to

[0281] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figure 1 - 8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to execute Figure 1 - 8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figure 1 - 8 For example, a processor that includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API.

[0282] Figure 12D is according to at least one embodiment between one or more cloud-based servers and Figure 12A1200. In at least one embodiment, the system may include, but is not limited to, one or more servers 1278, one or more networks 1290, and any number and type of vehicles, including vehicle 1200. In at least one embodiment, one or more servers 1278 may include, but are not limited to, multiple GPUs 1284(A)-1284(H) (collectively referred to herein as GPUs 1284), PCIe switches 1282(A)-1282(D) (collectively referred to herein as PCIe switches 1282), and / or CPUs 1280(A)-1280(B) (collectively referred to herein as CPUs 1280). In at least one embodiment, GPUs 1284, CPUs 1280, and PCIe switches 1282 may be interconnected with a high-speed interconnect, such as, for example, but not limited to, NVLink interface 1288 and / or PCIe connection 1286 developed by NVIDIA. In at least one embodiment, the GPUs 1284 are connected via NVLink and / or NVSwitch SoCs, and the GPUs 1284 and PCIe switches 1282 are connected via PCIe interconnects. Although eight GPUs 1284, two CPUs 1280, and four PCIe switches 1282 are shown, this is not intended to be limiting. In at least one embodiment, each of the one or more servers 1278 may include, but is not limited to, any number of GPUs 1284, CPUs 1280, and / or PCIe switches 1282 in any combination. For example, in at least one embodiment, one or more servers 1278 may each include eight, sixteen, thirty-two, and / or more GPUs 1284.

[0283] In at least one embodiment, one or more servers 1278 may receive image data representing an image from a vehicle via one or more networks 1290 that shows an unexpected or changed road condition, such as a recently started road project. In at least one embodiment, one or more servers 1278 may send updated neural networks 1292 and / or map information 1294 to the vehicle via one or more networks 1290, including, but not limited to, information about traffic and road conditions. In at least one embodiment, updates to the map information 1294 may include, but are not limited to, updates to the HD map 1222, such as information about construction sites, potholes, access roads, flooding, and / or other obstacles. In at least one embodiment, the neural network 1292 and / or map information 1294 may have been generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or based at least on training performed at a data center (e.g., using one or more servers 1278 and / or other servers).

[0284] In at least one embodiment, one or more servers 1278 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by a vehicle and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data is labeled (e.g., in cases where the associated neural network benefits from supervised learning) and / or undergoes other preprocessing. In at least one embodiment, no amount of training data is labeled and / or preprocessed (e.g., in cases where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1290, and / or the machine learning model may be used by one or more servers 1278 to remotely monitor the vehicle).

[0285] In at least one embodiment, one or more servers 1278 may receive data from a vehicle and apply the data to a most recent real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1278 may include a deep learning supercomputer powered by one or more GPUs 1284 and / or a dedicated AI computer, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1278 may include a deep learning infrastructure of a data center powered by a CPU.

[0286] In at least one embodiment, the deep learning infrastructure of one or more servers 1278 may be capable of performing fast, real-time inference and may use that ability to evaluate and validate the health of the processors, software, and / or associated hardware in vehicle 1200. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1200, such as an image sequence and / or objects located in the image sequence by vehicle 1200 (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify the objects and compare them to the objects identified by vehicle 1200, and, if the results do not match and the deep learning infrastructure determines that the AI in vehicle 1200 is malfunctioning, one or more servers 1278 may send a signal to vehicle 1200 that instructs the fail-safe computer in vehicle 1200 to take control, notify the passengers, and complete a safe parking operation.

[0287] In at least one embodiment, one or more servers 1278 may include one or more GPUs 1284 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 device). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, in cases where performance is less critical, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 915 are used to execute one or more embodiments. This document describes in conjunction with Figure 9A and / or Figure 9B provides details regarding the hardware structure 915.

[0288] Computer system

[0289] Figure 13 is a block diagram showing an exemplary computer system according to at least one embodiment. The exemplary computer system can be a system with interconnected devices and components, a system-on-chip (SOC), or some combination thereof that forms a processor, which may include execution units for executing instructions. In at least one embodiment, according to the present disclosure, such as in the embodiments described herein, the computer system 1300 may include, but is not limited to, components such as a processor 1302 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, the computer system 1300 may include a processor, such as those available from Intel Corporation of Santa Clara, California processor family, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessors, although other systems (including PCs, engineering workstations, set-top boxes, etc. with other microprocessors) can also be used. In at least one embodiment, the computer system 1300 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0290] Embodiments can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular telephones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, an embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0291] In at least one embodiment, computer system 1300 can include, but is not limited to, a processor 1302 that can include, but is not limited to, one or more execution units 1308 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1300 is a single-processor desktop or server system, but in another embodiment, computer system 1300 can be a multi-processor system. In at least one embodiment, processor 1302 can include, but is not limited to, for example, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing an instruction set combination, or any other processor device such as a digital signal processor. In at least one embodiment, processor 1302 can be coupled to a processor bus 1310 that can transfer data signals between processor 1302 and other components in computer system 1300.

[0292] In at least one embodiment, processor 1302 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 1304. In at least one embodiment, processor 1302 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside external to processor 1302. Depending on the particular implementation and requirements, other embodiments can also include a combination of internal and external caches. In at least one embodiment, register file 1306 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0293] In at least one embodiment, execution unit 1308, which includes, but is not limited to, logic for performing integer and floating point operations, is also located in processor 1302. In at least one embodiment, processor 1302 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1308 may include logic for processing a packed instruction set 1309. In at least one embodiment, by including the packed instruction set 1309 in the instruction set of a general purpose processor as well as the associated circuitry to execute the instructions, operations used by many multimedia applications can be performed using packed data in processor 1302. In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, which can eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0294] In at least one embodiment, execution unit 1308 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1300 may include, but is not limited to, memory 1320. In at least one embodiment, memory 1320 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory devices. In at least one embodiment, memory 1320 may store one or more instructions 1319 and / or data 1321 represented by data signals that can be executed by processor 1302.

[0295] In at least one embodiment, the system logic chip can be coupled to the processor bus 1310 and the memory 1320. In at least one embodiment, the system logic chip can include, but is not limited to, a Memory Controller Hub (“MCH”) 1316, and the processor 1302 can communicate with the MCH 1316 via the processor bus 1310. In at least one embodiment, the MCH 1316 can provide a high-bandwidth memory path 1318 to the memory 1320 for instruction and data storage as well as for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1316 can direct data signals among the processor 1302, the memory 1320, and other components in the computer system 1300, and bridge data signals among the processor bus 1310, the memory 1320, and the system I / O interface 1322. In at least one embodiment, the system logic chip can provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1316 can be coupled to the memory 1320 via the high-bandwidth memory path 1318, and the graphics / video card 1312 can be coupled to the MCH 1316 via an Accelerated Graphics Port (“AGP”) interconnect 1314.

[0296] In at least one embodiment, the computer system 1300 can use the system I / O interface 1322 as a proprietary hub interface bus to couple the MCH 1316 to an I / O Controller Hub (“ICH”) 1330. In at least one embodiment, the ICH 1330 can provide a direct connection to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus can include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1320, the chipset, and the processor 1302. Examples can include, but are not limited to, an audio controller 1329, a Firmware Hub (“Flash BIOS”) 1328, a wireless transceiver 1326, a data storage 1324, a legacy I / O controller 1323 that includes a user input and keyboard interface 1325, a serial expansion port 1327 (such as a Universal Serial Bus (“USB”) port), and a network controller 1334. In at least one embodiment, the data storage 1324 can include a hard disk drive, a floppy disk drive, a CD-ROM device, a flash device, or other mass storage devices.

[0297] In at least one embodiment, Figure 13 a system including interconnected hardware devices or “chips” is shown, while in other embodiments, Figure 13 an exemplary SoC can be shown. In at least one embodiment, Figure 13The devices shown can be interconnected using proprietary interconnections, standardized interconnections (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1300 are interconnected using Compute Express Link (CXL) interconnections.

[0298] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 9A and / or Figure 9B Details regarding Logic 915 are provided. In at least one embodiment, Logic 915 may be used in a Figure 13 system to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0299] In at least one embodiment, one or more of the depicted systems related to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figure 1 - 8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers of one or more neural networks based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to perform Figure 1 - 8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figure 1 - 8 e.g., a processor that includes one or more circuits to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers of one or more neural networks based at least in part on one or more indications of one or more layers of one or more neural networks.

[0300] In at least one embodiment, one or more of the depicted systems related to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figure 1 - 8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to perform Figure 1 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to ​One or more systems and / or processes described, such as a processor, the processor including one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API.

[0301] ​ is a block diagram illustrating an electronic device 1400 for utilizing a processor 1410 in accordance with at least one embodiment. In at least one embodiment, the electronic device 1400 can be, for example but not limited to, a laptop computer, a tower server, a rack server, a blade server, a notebook computer, a desktop computer, a tablet computer, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0302] In at least one embodiment, the electronic device 1400 can include, but is not limited to, a processor 1410 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, the processor 1410 is coupled using a bus or interface, such as an 2 I2C bus, a system management bus (“SMBus”), a low pin count (LPC) bus, a serial peripheral interface (“SPI”), a high definition audio (“HDA”) bus, a serial advanced technology attachment (“SATA”) bus, a universal serial bus (“USB”) (versions 1, 2, 3, etc.), or a universal asynchronous receiver / transmitter (“UART”) bus. In at least one embodiment, ​ illustrates a system that includes interconnected hardware devices or “chips,” while in other embodiments, ​ an exemplary SoC can be shown. In at least one embodiment, ​ the devices shown in can be interconnected using a proprietary interconnect, a standardized interconnect (e.g., PCIe), or some combination thereof. In at least one embodiment, ​ one or more components of are interconnected using a Compute Express Link (CXL) interconnect.

[0303] In at least one embodiment, ​It may include a display 1424, a touch screen 1425, a touchpad 1430, a Near Field Communication unit (“NFC”) 1445, a sensor hub 1440, a thermal sensor 1446, an Embedded Controller (“EC”) 1435, a Trusted Platform Module (“TPM”) 1438, a BIOS / Firmware / Flash (“BIOS, FW Flash”) 1422, a DSP 1460, a drive 1420 (such as a Solid State Disk (“SSD”) or a Hard Disk Drive (“HDD”)), a Wireless Local Area Network unit (“WLAN”) 1450, a Bluetooth unit 1452, a Wireless Wide Area Network unit (“WWAN”) 1456, a Global Positioning System (GPS) unit 1455, a camera (“USB 3.0 camera”) 1454 (such as a USB 3.0 camera) and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1415 implemented in accordance with, for example, the LPDDR3 standard. These components may each be implemented in any suitable manner.

[0304] In at least one embodiment, other components may be communicatively coupled to the processor 1410 via the components described herein. In at least one embodiment, an accelerometer 1441, an Ambient Light Sensor (“ALS”) 1442, a compass 1443, and a gyroscope 1444 may be communicatively coupled to the sensor hub 1440. In at least one embodiment, a thermal sensor 1439, a fan 1437, a keyboard 1436, and a touchpad 1430 may be communicatively coupled to the EC 1435. In at least one embodiment, a speaker 1463, headphones 1464, and a microphone (“mic”) 1465 may be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1462, which may in turn be communicatively coupled to the DSP 1460. In at least one embodiment, the audio unit 1462 may include, for example but not limited to, an audio encoder / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a Subscriber Identity Module (“SIM”) 1457 may be communicatively coupled to the WWAN unit 1456. In at least one embodiment, components (such as the WLAN unit 1450, the Bluetooth unit 1452, and the WWAN unit 1456) may be implemented in a Next Generation Form Factor (“NGFF”).

[0305] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in connection with ​ and / or ​ Details regarding the logic 915 are provided. In at least one embodiment, the logic 915 may be in ​for use in a system for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0306] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to ​ In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to perform ​ at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figure are used to implement one or more systems and / or processes such as those described with respect to ​ e.g., a processor that includes one or more circuits to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0307] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to ​ In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to perform ​ at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figure are used to implement one or more systems and / or processes such as those described with respect to ​ e.g., a processor that includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API.

[0308] ​ FIG. 1500 shows a computer system 1500 according to at least one embodiment. In at least one embodiment, the computer system 1500 is configured to implement the various processes and methods described throughout this disclosure.

[0309] In at least one embodiment, computer system 1500 includes, but is not limited to, at least one central processing unit (“CPU”) 1502 that is connected to a communication bus 1510 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, computer system 1500 includes, but is not limited to, a main memory 1504 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in the main memory 1504 which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1522 provides an interface to other computing devices and networks for receiving data from other systems and sending data to other systems using computer system 1500.

[0310] In at least one embodiment, computer system 1500 includes, but is not limited to, an input device 1508, a parallel processing system 1512, and a display device 1506 in at least one embodiment, which may be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”) display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from the input device 1508 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may be located on a single semiconductor platform to form a processing system.

[0311] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with ​ and / or Figure 9B Details regarding logic 915 are provided. In at least one embodiment, logic 915 may be used in a Figure 15 system to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0312] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to execute Figures 1-8At least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 A system and / or process, such as a processor, that includes one or more circuits to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0313] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to execute Figures 1-8 At least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 A system and / or process, such as a processor, that includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API.

[0314] Figure 16 FIG. 15 shows a computer system 1600 according to at least one embodiment. In at least one embodiment, computer system 1600 includes, but is not limited to, a computer 1610 and a USB drive 1620. In at least one embodiment, computer 1610 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1610 includes, but is not limited to, servers, cloud instances, laptop computers, and desktop computers.

[0315] In at least one embodiment, the USB drive 1620 includes, but is not limited to, a processing unit 1630, a USB interface 1640, and USB interface logic 1650. In at least one embodiment, the processing unit 1630 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1630 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1630 includes an application specific integrated circuit (“ASIC”) that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1630 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1630 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0316] In at least one embodiment, the USB interface 1640 can be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 1640 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 1640 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1650 can include any number and type of logic that enables the processing unit 1630 to interface with a device (such as computer 1610) via the USB connector 1640.

[0317] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, logic 915 can be used in a Figure 16 system for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0318] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figures is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figures is used to execute Figures 1-8at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 For example, a processor includes one or more circuits to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0319] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to execute Figures 1-8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 For example, a processor includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API. s

[0320] Figure 17A An exemplary architecture is shown in which multiple GPUs 1710(1)-1710(N) are communicatively coupled to multiple multi-core processors 1705(1)-1705(M) via high-speed links 1740(1)-1740(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1740(1)-1740(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, and their values can vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 1710(1)-1710(N) include as Figure 20A and Figure 20BOne or more graphics cores (also abbreviated as "cores" herein) 2000 disclosed in [reference]. In at least one embodiment, one or more graphics cores 2000 may be referred to as a streaming multiprocessor ("SM"), stream processor ("SP"), stream processing unit ("SPU"), compute unit ("CU"), execution unit ("EU"), and / or slice, where in this context, a slice may refer to a portion of the processing resources in a processing unit (e.g., 16 cores, ray tracing units, thread directors or schedulers).

[0321] Furthermore, in at least one embodiment, two or more GPUs 1710 are interconnected by high-speed links 1729(1)-1729(2), which may be implemented using a protocol / link similar to or different from that used for high-speed links 1740(1)-1740(N). Similarly, two or more multi-core processors 1705 may be connected by a high-speed link 1728, which may be a symmetric multiprocessor (SMP) bus operating at a speed of 20 GB / s, 30 GB / s, 120 GB / s or higher. Alternatively, all communications between the various system components shown in [reference] may be accomplished using a similar protocol / link (e.g., via a common interconnect structure). Figure 17A All communications between the various system components shown in [reference].

[0322] In at least one embodiment, each multi-core processor 1705 is communicatively coupled to a processor memory 1701(1)-1701(M) via a memory interconnect 1726(1)-1726(M), respectively, and each GPU 1710(1)-1710(N) is communicatively coupled to a GPU memory 1720(1)-1720(N) via a GPU memory interconnect 1750(1)-1750(N), respectively. In at least one embodiment, the memory interconnects 1726 and 1750 may utilize similar or different memory access technologies. By way of example and not limitation, the processor memories 1701(1)-1701(M) and the GPU memory 1720 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of the processor memory 1701 may be volatile memory while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0323] As described herein, although each of the multi-core processors 1705 and GPUs 1710 may be physically coupled to specific memories 1701, 1720, respectively, and / or a unified memory architecture may be implemented, in which a virtual system address space (also referred to as the "effective address" space) is distributed among the respective physical memories. For example, processor memories 1701(1)-1701(M) may each include 64 GB of system memory address space, and GPU memories 1720(1)-1720(N) may each include 32 GB of system memory address space, such that when M = 2 and N = 4, a total of 256 GB of addressable memory results. Other values of N and M are possible.

[0324] Figure 17B Additional details of the interconnect for a multi-core processor 1707 and a graphics acceleration module 1746 are shown in accordance with one exemplary embodiment. In at least one embodiment, the graphics acceleration module 1746 may include one or more GPU chips integrated on a line card that is coupled to the processor 1707 via a high-speed link 1740 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1746 may alternatively be integrated on a package or chip with the processor 1707.

[0325] In at least one embodiment, the processor 1707 includes a plurality of cores 1760A-1760D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1761A-1761D and one or more caches 1762A-1762D. In at least one embodiment, the cores 1760A-1760D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1762A-1762D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1756 may be included within the caches 1762A-1762D and shared by groups of cores 1760A-1760D. For example, one embodiment of the processor 1707 includes 24 cores, each having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1707 and the graphics acceleration module 1746 are connected to a system memory 1714, which may include Figure 17A the processor memories 1701(1)-1701(M) therein.

[0326] In at least one embodiment, coherence for data and instructions stored in respective caches 1762A - 1762D, 1756, and system memory 1714 is maintained via an inter-core communication over coherence bus 1764. In at least one embodiment, for example, each cache may have cache coherence logic / circuit associated therewith to communicate over coherence bus 1764 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented over coherence bus 1764 to snoop cache accesses.

[0327] In at least one embodiment, proxy circuit 1725 communicatively couples graphics acceleration module 1746 to coherence bus 1764, thereby allowing graphics acceleration module 1746 to participate in the cache coherence protocol as a peer to cores 1760A - 1760D. In particular, in at least one embodiment, interface 1735 provides a connection to proxy circuit 1725 via high-speed link 1740, and interface 1737 connects graphics acceleration module 1746 to high-speed link 1740.

[0328] In at least one embodiment, accelerator integrated circuit 1736 provides cache management, memory access, context management, and interrupt management services on behalf of the plurality of graphics processing engines 1731(1)-1731(N) of graphics acceleration module 1746. In at least one embodiment, graphics processing engines 1731(1)-1731(N) may each include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1731(1)-1731(N) of graphics acceleration module 1746 includes one or more graphics cores 2000 as discussed in conjunction with Figure 20A and Figure 20B In at least one embodiment, graphics processing engines 1731(1)-1731(N) may alternatively include different types of graphics processing engines within a GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, graphics acceleration module 1746 may be a GPU having a plurality of graphics processing engines 1731(1)-1731(N), or graphics processing engines 1731(1)-1731(N) may be individual GPUs integrated on a common package, line card, or chip.

[0329] In at least one embodiment, the accelerator integrated circuit 1736 includes a memory management unit (MMU) 1739 for performing various memory management functions such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes a memory access protocol for accessing system memory 1714. In at least one embodiment, the MMU 1739 may also include a translation lookaside buffer ("TLB") (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, the cache 1738 may store commands and data for efficient access by the graphics processing engines 1731(1)-1731(N). In at least one embodiment, an acquisition unit 1744 may be used to keep the data stored in the cache 1738 and the graphics memories 1733(1)-1733(M) coherent with the core caches 1762A-1762D, 1756, and the system memory 1714. As previously described, this may be representative of the cache 1738 and the memories 1733(1)-1733(M) being implemented via the proxy circuit 1725 (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 1762A-1762D, 1756 to the cache 1738 and receiving updates from the cache 1738).

[0330] In at least one embodiment, a set of registers 1745 stores context data of threads executed by the graphics processing engines 1731(1)-1731(N), and a context management circuit 1748 manages the thread contexts. For example, the context management circuit 1748 may perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where the first thread is saved and the second thread is stored so that the second thread can be executed by the graphics processing engine). For example, when performing a context switch, the context management circuit 1748 may store the current register values into a specified area in memory (e.g., identified by a context pointer). Then, the register values may be restored when returning to the context. In at least one embodiment, an interrupt management circuit 1747 receives and processes interrupts received from system devices.

[0331] In at least one embodiment, the MMU 1739 converts virtual / valid addresses from the graphics processing engine 1731 into real / physical addresses in the system memory 1714. In at least one embodiment, the accelerator integrated circuit 1736 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1746 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1746 can be dedicated to a single application executing on the processor 1707 or can be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 1731(1)-1731(N) are shared among multiple applications or virtual machines (VMs). In at least one embodiment, resources can be subdivided into "slices" based on the processing requirements and priorities associated with the VMs and / or applications and are allocated to different VMs and / or applications.

[0332] In at least one embodiment, the accelerator integrated circuit 1736 acts as a bridge for the system of the graphics accelerator modules 1746 and provides address translation and system memory cache services. Additionally, in at least one embodiment, the accelerator integrated circuit 1736 can provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1731(1)-1731(N).

[0333] In at least one embodiment, since the hardware resources of the graphics processing engines 1731(1)-1731(N) are explicitly mapped to the real address space seen by the host processor 1707, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1736 is the physical separation of the graphics processing engines 1731(1)-1731(N) such that they appear as independent units to the system.

[0334] In at least one embodiment, one or more graphics memories 1733(1)-1733(M) are coupled to each of the graphics processing engines 1731(1)-1731(N) respectively, and N = M. In at least one embodiment, the graphics memories 1733(1)-1733(M) store the instructions and data being processed by each of the graphics processing engines 1731(1)-1731(N). In at least one embodiment, the graphics memories 1733(1)-1733(M) can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6), or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0335] In at least one embodiment, to reduce data traffic on high-speed link 1740, a biasing technique can be used to ensure that the data stored in graphics memories 1733(1)-1733(M) is the data most frequently used by graphics processing engines 1731(1)-1731(N), and preferably is data not used (at least not frequently used) by cores 1760A-1760D. Similarly, in at least one embodiment, the biasing mechanism attempts to keep the data required by the cores (and preferably not required by graphics processing engines 1731(1)-1731(N)) in caches 1762A-1762D, 1756, and system memory 1714.

[0336] Figure 17C Another exemplary embodiment is shown in which accelerator integrated circuit 1736 is integrated within processor 1707. In this embodiment, graphics processing engines 1731(1)-1731(N) communicate directly with accelerator integrated circuit 1736 via interfaces 1737 and 1735 (again, which can be any form of bus or interface protocol) over high-speed link 1740. In at least one embodiment, accelerator integrated circuit 1736 can perform operations similar to the operations described with respect to Figure 17B but may have higher throughput due to its close proximity to coherence bus 1764 and caches 1762A-1762D, 1756. In at least one embodiment, accelerator integrated circuit supports different programming models, which include a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), and the programming models can include a programming model controlled by accelerator integrated circuit 1736 and a programming model controlled by graphics acceleration module 1746.

[0337] In at least one embodiment, graphics processing engines 1731(1)-1731(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application can funnel other application requests to graphics processing engines 1731(1)-1731(N), thereby providing virtualization within a VM / partition.

[0338] In at least one embodiment, the graphics processing engines 1731(1)-1731(N) can be shared by multiple VM / application partitions. In at least one embodiment, a shared model can use a hypervisor to virtualize the graphics processing engines 1731(1)-1731(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns the graphics processing engines 1731(1)-1731(N). In at least one embodiment, the operating system can virtualize the graphics processing engines 1731(1)-1731(N) to provide access to each process or application.

[0339] In at least one embodiment, the graphics acceleration module 1746 or individual graphics processing engines 1731(1)-1731(N) use a process handle to select process elements. In at least one embodiment, the process elements are stored in the system memory 1714 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle can be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engines 1731(1)-1731(N) (i.e., calling the system software to add the process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle can be the offset of the process element in the process element linked list.

[0340] Figure 17D An exemplary accelerator integration slice 1790 is shown. In at least one embodiment, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1736. In at least one embodiment, an application is an effective address space 1782 in the system memory 1714 that stores process elements 1783. In at least one embodiment, in response to a GPU call 1781 from an application 1780 executing on the processor 1707, the process element 1783 is stored. In at least one embodiment, the process element 1783 contains the process state of the corresponding application 1780. In at least one embodiment, the work descriptor (WD) 1784 contained in the process element 1783 can be a single job requested by the application or can contain a pointer to a job queue. In at least one embodiment, the WD 1784 is a pointer to a job request queue in the effective address space 1782 of the application.

[0341] In at least one embodiment, the graphics acceleration module 1746 and / or each of the graphics processing engines 1731(1)-1731(N) may be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure may be included for setting the process state and sending a WD 1784 to the graphics acceleration module 1746 to start a job in a virtualized environment.

[0342] In at least one embodiment, the programming model specific to a process is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1746 or an individual graphics processing engine 1731. In at least one embodiment, when the graphics acceleration module 1746 is owned by a single process, the hypervisor initializes the accelerator integrated circuit for the owned partition, and when the graphics acceleration module 1746 is assigned, the operating system initializes the accelerator integrated circuit 1736 for the owned process.

[0343] In at least one embodiment, in operation, the WD fetch unit 1791 in the accelerator integrated slice 1790 fetches the next WD 1784, which includes an indication of work to be completed by one or more of the graphics processing engines of the graphics acceleration module 1746. In at least one embodiment, the data from the WD 1784 may be stored in the register 1745 and used by the MMU 1739, the interrupt management circuit 1747, and / or the context management circuit 1748, as shown. For example, one embodiment of the MMU 1739 includes a segment / page walk circuit for accessing the segment / page table 1786 within the OS virtual address space 1785. In at least one embodiment, the interrupt management circuit 1747 may process the interrupt event 1792 received from the graphics acceleration module 1746. In at least one embodiment, when a graphics operation is executed, the virtual address 1793 generated by the graphics processing engines 1731(1)-1731(N) is translated by the MMU 1739 into a physical address.

[0344] In at least one embodiment, the register 1745 is replicated for each of the graphics processing engines 1731(1)-1731(N) and / or the graphics acceleration module 1746, and the register 1745 may be initialized by the hypervisor or the operating system. In at least one embodiment, each of these replicated registers may be included in the accelerator integrated slice 1790. Exemplary registers that may be initialized by the hypervisor are shown in Table 1.

[0345] Table 1 - Registers Initialized by the Hypervisor

[0346]

[0347]

[0348] Exemplary registers that can be initialized by the operating system are shown in Table 2.

[0349] Table 2 – Registers Initialized by the Operating System

[0350]

[0351] In at least one embodiment, each WD 1784 is specific to a particular graphics acceleration module 1746 and / or graphics processing engine 1731(1)-1731(N). In at least one embodiment, it contains all the information required for the graphics processing engine 1731(1)-1731(N) to complete its work, or it can be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0352] Figure 17E Additional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1798 in which a list of process elements 1799 is stored. In at least one embodiment, the hypervisor real address space 1798 can be accessed via a hypervisor 1796 that virtualizes the graphics acceleration module engine for the operating system 1795.

[0353] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1746. In at least one embodiment, there are two programming models in which the graphics acceleration module 1746 is shared by multiple processes and partitions, namely time-slice sharing and graphics-directed sharing.

[0354] In at least one embodiment, in this model, the system hypervisor 1796 owns the graphics acceleration module 1746 and makes its functions available to all operating systems 1795. In at least one embodiment, for the graphics acceleration module 1746 to support virtualization through the system hypervisor 1796, the graphics acceleration module 1746 may have to comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., do not require maintaining state between jobs), or the graphics acceleration module 1746 must provide a context save and restore mechanism, (2) the graphics acceleration module 1746 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1746 provides the ability to preempt job processing, and (3) when operating in a directed sharing programming model, it must be ensured that the graphics acceleration module 1746 is fair between processes.

[0355] In at least one embodiment, the application 1780 is required to use the graphics acceleration module type, work descriptor (WD), access mask register (AMR) value, and context save / restore area pointer (CSRP) to make an operating system 1795 system call. In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1746 and can take the form of a graphics acceleration module 1746 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1746.

[0356] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of the accelerator integrated circuit 1736 (not shown) and the graphics acceleration module 1746 does not support the user access mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. In at least one embodiment, the hypervisor 1796 can selectively apply the current access mask override register (AMOR) value before placing the AMR in the process element 1783. In at least one embodiment, the CSRP is one of the registers 1745 that contains the valid address of a region in the application's valid address space 1782 for the graphics acceleration module 1746 to save and restore the context state. In at least one embodiment, this pointer is optional if it is not necessary to save state between jobs or when a job is preempted. In at least one embodiment, the context save / restore area can be a fixed system memory.

[0357] Upon receiving the system call, the operating system 1795 can verify that the application 1780 has been registered and is granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the operating system 1795 uses the information shown in Table 3 to call the hypervisor 1796.

[0358] Table 3 – Operating System to Hypervisor Call Parameters

[0359]

[0360] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1796 verifies that the operating system 1795 is registered and has been granted permission to use the graphics acceleration module 1746. Then, in at least one embodiment, the hypervisor 1796 places the process element 1783 into a process element linked list corresponding to the type of the graphics acceleration module 1746. In at least one embodiment, the process element may include the information shown in Table 4.

[0361] Table 4 – Process Element Information

[0362]

[0363] In at least one embodiment, the hypervisor initializes the registers 1745 of multiple accelerator integrated slices 1790.

[0364] As Figure 17F shown, in at least one embodiment, a unified memory is used, and the unified memory can be addressed via a common virtual memory address space for accessing the physical processor memories 1701(1)-1701(N) and the GPU memories 1720(1)-1720(N). In this implementation, operations executed on the GPUs 1710(1)-1710(N) utilize the same virtual / effective memory address space to access the processor memories 1701(1)-1701(M), and vice versa, thus simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to the processor memory 1701(1), a second portion is allocated to the second processor memory 1701(N), a third portion is allocated to the GPU memory 1720(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of the processor memories 1701 and the GPU memories 1720, allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0365] In at least one embodiment, the bias / coherency management circuits 1794A-1794E within one or more MMUs 1739A-1739E ensure cache coherency between one or more host processors (e.g., 1705) and the caches of the GPUs 1710, and implement a bias technique for indicating the physical memory in which certain types of data should be stored. In at least one embodiment, although multiple instances of the bias / coherency management circuits 1794A-1794E are shown in Figure 17F , the bias / coherency circuits can be implemented within the MMUs of one or more host processors 1705 and / or within the accelerator integrated circuit 1736.

[0366] One embodiment allows the GPU memory 1720 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) technology without suffering the performance drawbacks associated with full-system cache coherence. In at least one embodiment, the ability of the GPU memory 1720 to be accessed as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the software of the host processor 1705 to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU memory 1720 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1710. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0367] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granularity structure (e.g., controlled at the granularity of memory pages), and this page-granularity structure includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in the GPU 1710 (e.g., for caching frequently / recently used entries of the bias table), the bias table may be implemented in the stolen memory ranges of one or more GPU memories 1720. Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0368] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1720 is accessed, thereby causing the following operations. In at least one embodiment, a local request from the GPU 1710 that finds its page in the GPU bias is directly forwarded to the corresponding GPU memory 1720. In at least one embodiment, a local request from the GPU that finds its page in the host bias is forwarded to the processor 1705 (e.g., via the high-speed link described herein). In at least one embodiment, a request from the processor 1705 that finds the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request pointing to a GPU bias page can be forwarded to the GPU 1710. In at least one embodiment, if the GPU is not currently using a page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a software mechanism assisted by hardware, or in a limited set of cases by a purely hardware-based mechanism.

[0369] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing the GPU to change the bias state and perform a cache flush operation in the host in certain migrations. In at least one embodiment, the cache flush operation is used for migrating from the host processor 1705 bias to the GPU bias, but not for the reverse migration.

[0370] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 1705. In at least one embodiment, to access these pages, the processor 1705 can request access from the GPU 1710, and the GPU 1710 may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between the processor 1705 and the GPU 1710, it is beneficial to ensure that the GPU bias pages are the pages required by the GPU rather than the pages required by the host processor 1705, and vice versa.

[0371] One or more hardware structures 915 are used to execute one or more embodiments. Details regarding one or more hardware structures 915 may be provided herein in conjunction with Figure 9A and / or Figure 9B provide details about one or more hardware structures 915.

[0372] Figure 18Illustrated is an exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein, which may be fabricated using one or more IP cores. In addition to those illustrated, in at least one embodiment, other logic and circuitry may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0373] Figure 18 FIG. 4 is a block diagram illustrating an exemplary system on a chip integrated circuit 1800 that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1800 includes one or more application processors 1805 (e.g., CPUs), at least one graphics processor 1810, and may additionally include an image processor 1815 and / or a video processor 1820, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1800 includes peripheral or bus logic, which includes a USB controller 1825, a UART controller 1830, an SPI / SDIO controller 1835, and an 2 S / I 2 2C controller 1840. In at least one embodiment, integrated circuit 1800 may include a display device 1845 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1850 and a mobile industry processor interface (MIPI) display interface 1855. In at least one embodiment, storage may be provided by a flash memory subsystem 1860, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1865 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1870.

[0374] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, logic 915 may be in integrated circuit 1800 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0375] In at least one embodiment, one or more of the systems depicted in connection with the preceding figures are used to implement with respect to Figures 1-8The described techniques, functions, and / or processes. In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to execute Figures 1-8 at least one aspect of the components within. In at least one embodiment, one or more systems depicted in the previous figure are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 For example, a processor includes one or more circuits to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0376] In at least one embodiment, one or more systems depicted in relation to the previous figure are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to execute Figures 1-8 at least one aspect of the components within. In at least one embodiment, one or more systems depicted in the previous figure are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 For example, a processor includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API.

[0377] Figures 19A-19B Shows an exemplary integrated circuit and associated graphics processor according to various embodiments described herein, which may be fabricated using one or more IP cores. In addition to those illustrated, in at least one embodiment other logic and circuitry may be included, including additional graphics processors / cores, peripheral interface controllers, or general processor cores.

[0378] Figures 19A-19B Is a block diagram showing an exemplary graphics processor used within a SoC according to an embodiment described herein. Figure 19A Shows an exemplary graphics processor 1910 of a system-on-chip integrated circuit according to at least one embodiment, which may be fabricated using one or more IP cores. Figure 19BShows an additional exemplary graphics processor 1940 of a system-on-chip integrated circuit according to at least one embodiment, which can be fabricated using one or more IP cores. In at least one embodiment, Figure 19A the graphics processor 1910 is a low-power graphics processor core. In at least one embodiment, Figure 19B the graphics processor 1940 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1910, 1940 can be a variant of the graphics processor 1910 of FIG. 19.

[0379] In at least one embodiment, the graphics processor 1910 includes a vertex processor 1905 and one or more fragment processors 1915A-1915N (e.g., 1915A, 1915B, 1915C, 1915D to 1915N-1, and 1915N). In at least one embodiment, the graphics processor 1910 can execute different shader programs via separate logic such that the vertex processor 1905 is optimized to execute operations for a vertex shader program, while the one or more fragment processors 1915A-1915N perform fragment (e.g., pixel) shading operations for a fragment or pixel shader program. In at least one embodiment, the vertex processor 1905 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1915A-1915N use the primitives and vertex data generated by the vertex processor 1905 to produce a frame buffer to be displayed on a display device. In at least one embodiment, the one or more fragment processors 1915A-1915N are optimized to execute a fragment shader program as provided in the OpenGL API, which can be used to perform operations similar to those of a pixel shader program provided in the Direct 3D API.

[0380] In at least one embodiment, the graphics processor 1910 additionally includes one or more memory management units (MMUs) 1920A - 1920B, one or more caches 1925A - 1925B, and one or more circuit interconnects 1930A - 1930B. In at least one embodiment, one or more MMUs 1920A - 1920B provide virtual - to - physical address mapping for the graphics processor 1910 (including for the vertex processor 1905 and / or fragment processors 1915A - 1915N), and in addition to vertex or image / texture data stored in one or more caches 1925A - 1925B, it can also reference vertex or image / texture data stored in memory. In at least one embodiment, one or more MMUs 1920A - 1920B can be synchronized with other MMUs within the system, including one or more MMUs associated with one or more application processors 1905, image processors 1915, and / or video processors 1920 of FIG. 19, such that each processor 1905 - 1920 can participate in a shared or unified virtual memory system. In at least one embodiment, one or more circuit interconnects 1930A - 1930B enable the graphics processor 1910 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0381] In at least one embodiment, the graphics processor 1940 includes one or more shader cores 1955A - 1955N (e.g., 1955A, 1955B, 1955C, 1955D, 1955E, 1955F to 1955N - 1 and 1955N) as shown, which provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1940 includes an inter - core task manager 1945, which acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1955A - 1955N and a tiling unit 1958 to accelerate tiling operations for tile - based rendering, where the rendering operation of the scene is subdivided in the image space, e.g., to take advantage of local spatial coherence within the scene or to optimize the use of internal caches. Figure 19B

[0382] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 915 are provided herein in connection with Figure 9A and / or Figure 9B In at least one embodiment, logic 915 can be in Figure 19A and / orFigure 19B in an integrated circuit for performing inference or prediction operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0383] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to perform Figures 1-8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 a processor that includes one or more circuits to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0384] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to perform Figures 1-8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 a processor that includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API.

[0385] Figures 20A-20B shows additional exemplary graphics processor logic according to embodiments described herein. In at least one embodiment, the components shown and incorporated in Figures 20A-20B are integrated into a single system, such as a graphics processing unit (GPU), a system-on-chip (SoC), or another type of processor. In at least one embodiment, Figures 20A-20B the components described are integrated into a single system, such as a graphics processing unit (GPU), a system-on-chip (SoC), or another type of processor. In at least one embodiment,Figure 20A illustrates a graphics core 2000 that may be included within Figure 18 a graphics processor 1810, and in at least one embodiment, it may be a unified shader core 1955A - 1955N as Figure 19B shown. Figure 20B illustrates a highly parallel general - purpose graphics processing unit (“GPGPU”, which may also be referred to as “graphics processing unit”) 2030 suitable for deployment on a multi - chip module in at least one embodiment. In at least one embodiment, the graphics processing unit 2030 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1800 includes a graphics core 2000, for example, for forming an integrated circuit and / or forming a SoC, where such an integrated circuit and / or such a SoC performs the operations described herein.

[0386] In at least one embodiment, the graphics core 2000 includes a shared instruction cache 2002, texture units 2018, and cache / shared memory 2020 (e.g., including L1, L2, L3, last - level cache, or other caches), which are shared among the execution resources within the graphics core 2000. In at least one embodiment, the graphics core 2000 may include multiple slices 2001A - 2001N or partitions per core, and the graphics processor may include multiple instances of the graphics core 2000. In at least one embodiment, each slice 2001A - 2001N refers to the graphics core 2000. In at least one embodiment, the slices 2001A - 2001N have sub - slices that are part of the slices 2001A - 2001N. In at least one embodiment, the slices 2001A - 2001N are independent of or dependent on other slices. In at least one embodiment, the slices 2001A - 2001N may include support logic, which includes local instruction caches 2004A - 2004N, thread schedulers (sequencers) 2006A - 2006N, thread dispatchers 2008A - 2008N, and a set of registers 2010A - 2010N. In at least one embodiment, the slices 2001A - 2001N may include a set of additional functional units (AFU 2012A - 2012N), floating - point units (FPU 2014A - 2014N), integer arithmetic logic units (ALU 2016A - 2016N), address calculation units (ACU 2013A - 2013N), double - precision floating - point units (DPFPU 2015A - 2015N), and matrix processing units (MPU 2017A - 2017N). In at least one embodiment, the MPU 2017A - 2017N is referred to as a matrix engine.

[0387] In at least one embodiment, each of the slices 2001A - 2001N includes one or more engines for floating - point and integer vector operations and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large - dataset workloads. In at least one embodiment, one or more of the slices 2001A - 2001N includes one or more vector engines for computing vectors (e.g., performing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16 - bit floating - point (also known as "FP16"), 32 - bit floating - point (also known as "FP32"), or 64 - bit floating - point (also known as "FP64"). In at least one embodiment, one or more of the slices 2001A - 2001N includes 16 vector engines, which are paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed through matrix expansion. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, e.g., 16 cores and ray - tracing units of a processor or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of a processor. In at least one embodiment, the graphics core 2000 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0388] In at least one embodiment, one or more of the slices 2001A - 2001N includes one or more ray - tracing units for computing ray - tracing operations (e.g., 16 ray - tracing units per slice in slices 2001A - 2001N). In at least one embodiment, the ray - tracing units compute ray traversal, triangle intersection, bounding - box intersection, or other ray - tracing operations.

[0389] In at least one embodiment, one or more of the slices 2001A - 2001N includes a media slice that encodes, decodes, and / or transcodes data; scales and / or converts the format of data; and / or performs video - quality operations on video data.

[0390] In at least one embodiment, one or more slices 2001A - 2001N are linked to an L2 cache and a memory structure, a link connector, a high - bandwidth memory (HBM) (e.g., HBM2e, HBM3) stack, and a media engine. In at least one embodiment, one or more slices 2001A - 2001N include a plurality of cores (e.g., 16 cores) and a plurality of ray - tracing units (e.g., 16) paired with each core. In at least one embodiment, one or more slices 2001A - 2001N have one or more L1 caches. In at least one embodiment, one or more slices 2001A - 2001N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLMs) for storing, for example, data corresponding to instructions; one or more samplers for sampling data; one or more ray - tracing units for performing ray - tracing operations; one or more geometry units for performing operations in a geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector - graphics format (e.g., a shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for buffering data; and / or one or more pixel back - ends. In at least one embodiment, slices 2001A - 2001N include a memory structure, such as an L2 cache.

[0391] In at least one embodiment, FPU 2014A - 2014N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while DPFPU 2015A - 2015N performs double - precision (64 - bit) floating - point operations. In at least one embodiment, ALU2016A - 2016N can perform variable - precision integer operations with 8 - bit, 16 - bit, and 32 - bit precision and can be configured for mixed - precision operations. In at least one embodiment, MPU 2017A - 2017N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, MPU2017A - 2017N can perform various matrix operations to accelerate machine - learning application frameworks, including enabling support for accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, AFU 2012A - 2012N can perform additional logical operations not supported by a floating - point unit or an integer unit, including trigonometric operations (e.g., sine, cosine, etc.). Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction with Figure 9A and / orFigure 9B Provide details about logic 915. In at least one embodiment, logic 915 may be used in graphics core 2000 for performing inference or prediction operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0392] In at least one embodiment, graphics core 2000 includes an interconnect and link structure sublayer attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 2000 (e.g., 8) to be interconnected with each other without bonding via load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 2000. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0393] In at least one embodiment, graphics core 2000 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where an individual die may be connected to the interconnect (e.g., an embedded multi-die interconnect bridge (EMIB)). In at least one embodiment, graphics core 2000 includes a compute tile, a memory tile (e.g., where the memory tile may be exclusively accessed by different tiles or different chip sets such as Rambo tiles), a base tile, a foundation tile, an HMB tile, a link tile, and an EMIB tile, where all tiles are encapsulated together in graphics core 2000 as part of the GPU. In at least one embodiment, graphics core 2000 may include multiple tiles in a single package (also referred to as a "multi-tile package"). In at least one embodiment, the compute tile may have 8 graphics cores 2000, an L1 cache; and the foundation tile may have a host interface to PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, the tiles are connected by face-to-face (F2F) chip-on-chip bonding with fine-pitch 36-micron microbumps (e.g., copper pillars). In at least one embodiment, graphics core 2000 includes a memory structure (which includes memory) and is a tile accessible by multiple tiles. In at least one embodiment, graphics core 2000 stores its own hardware context into memory, accesses its own hardware context in memory, or loads its own hardware context into memory, where the hardware context is a set of data loaded from registers prior to process restoration, and where the hardware context may indicate the state of the hardware (e.g., the state of the GPU).

[0394] In at least one embodiment, the graphics core 2000 includes a serializer / deserializer (SERDES) circuit that converts a serial data stream into a parallel data stream, or converts a parallel data stream into a serial data stream.

[0395] In at least one embodiment, the graphics core 2000 includes a high-speed coherent unified fabric (GPU-to-GPU), load / store units, block data transfer and synchronization semantics, and GPUs connected by an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0396] In at least one embodiment, the graphics core 2000 executes an API, where the API abstracts the hardware of the graphics core 2000 and accesses libraries with instructions to perform mathematical operations (e.g., math kernel libraries), deep neural network operations (e.g., deep neural network libraries), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0397] In at least one embodiment, one or more of the depicted systems related to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to execute Figures 1-8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 a processor that includes one or more circuits to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers based at least in part on one or more indications of one or more layers of one or more neural networks.

[0398] In at least one embodiment, one or more of the depicted systems related to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to execute Figures 1-8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8One or more systems and / or processes described, such as a processor, the processor including one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more portions of one or more neural networks indicated by the API.

[0399] Figure 20B Illustrates the GPGPU 2030 in at least one embodiment, which may be configured to enable highly parallel computing operations to be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 2030 may be directly linked to other instances of the GPGPU 2030 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, the GPGPU 2030 includes a host interface 2032 for implementing a connection to a host processor. In at least one embodiment, the host interface 2032 is a PCI Express interface. In at least one embodiment, the host interface 2032 may be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 2030 receives commands from the host processor and uses a global scheduler 2034 (which may be referred to as a thread sequencer and / or asynchronous compute engine) to allocate execution threads associated with those commands to a set of compute clusters 2036A - 2036H. In at least one embodiment, the compute clusters 2036A - 2036H share a cache memory 2038. In at least one embodiment, the cache memory 2038 may be used as a higher-level cache for the cache memories within the compute clusters 2036A - 2036H. In at least one embodiment, the compute clusters 2036A - 2036H include slices or are referred to as "slices". In at least one embodiment, the GPGPU 2030 is part of a SoC, such as part of the integrated circuit 1800 ( Figure 18 ).

[0400] In at least one embodiment, the GPGPU 2030 includes memories 2044A - 2044B, which are coupled to the compute clusters 2036A - 2036H via a set of memory controllers 2042A - 2042B (e.g., one or more controllers for HBM2e). In at least one embodiment, the memories 2044A - 2044B may include various types of memory devices, which include dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0401] In at least one embodiment, each of the compute clusters 2036A - 2036H includes a set of graphics cores, such as Figure 20AGraphics Core 2000, which can include various types of integer and floating-point logic units that can perform computational operations over a range of precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the computational clusters 2036A - 2036H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0402] In at least one embodiment, multiple instances of the GPGPU 2030 can be configured to operate as computational clusters. In at least one embodiment, the communication for synchronization and data exchange in the computational clusters 2036A - 2036H varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 2030 communicate via the host interface 2032. In at least one embodiment, the GPGPU 2030 includes an I / O hub 2039 that couples the GPGPU 2030 to a GPU link 2040, which enables a direct connection to other instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization between multiple instances of the GPGPU 2030. In at least one embodiment, the GPU link 2040 is coupled to a high-speed interconnect to send and receive data to other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 2030 are located in separate data processing systems and communicate via network devices accessible via the host interface 2032. In at least one embodiment, in addition to or in place of the host interface 2032, the GPU link 2040 can also be configured to enable a connection to a host processor.

[0403] In at least one embodiment, the GPGPU 2030 can be configured to train a neural network. In at least one embodiment, the GPGPU 2030 can be used within an inference platform. In at least one embodiment, in the case of using the GPGPU 2030 for inference, the GPGPU 2030 can include fewer computational clusters 2036A - 2036H compared to when using the GPGPU 2030 to train a neural network. In at least one embodiment, the memory technology associated with the memories 2044A - 2044B can differ between the inference and training configurations, with higher-bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 2030 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions that can be used during the inference operations of a deployed neural network.

[0404] Logic 915 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 9A and / or Figure 9B details regarding Logic 915 are provided. In at least one embodiment, Logic 915 may be used in GPGPU 2030 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0405] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers of one or more neural networks based at least in part on one or more indications of one or more layers of one or more neural networks. In at least one embodiment, at least one component of the previous figure is used to execute Figures 1-8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 e.g., a processor that includes one or more circuits to execute an application programming interface (API) to indicate gradient information corresponding to one or more layers of one or more neural networks based at least in part on one or more indications of one or more layers of one or more neural networks.

[0406] In at least one embodiment, one or more of the systems depicted in relation to the previous figures are used to implement the techniques, functions, and / or processes described with respect to Figures 1-8 In at least one embodiment, at least one component of the previous figure is used to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API. In at least one embodiment, at least one component of the previous figure is used to execute Figures 1-8 at least one aspect of the components within. In at least one embodiment, one or more of the systems depicted in the previous figures are used to implement one or more systems and / or processes such as those described with respect to Figures 1-8 e.g., a processor that includes one or more circuits to execute an application programming interface (API) to apply one or more gradients to one or more parts of one or more neural networks indicated by the API.

[0407] Figure 21is a block diagram showing a computing system 2100 in accordance with at least one embodiment. In at least one embodiment, the computing system 2100 includes a processing subsystem 2101 having one or more processors 2102 and system memory 2104 communicating via an interconnect path that may include a memory hub 2105. In at least one embodiment, the memory hub 2105 may be a separate component within a chipset component or may be integrated within one or more processors 2102. In at least one embodiment, the memory hub 2105 is coupled to an I / O subsystem 2111 via a communication link 2106. In at least one embodiment, the I / O subsystem 2111 includes an I / O hub 2107 that may enable the computing system 2100 to receive input from one or more input devices 2108. In at least one embodiment, the I / O hub 2107 may enable a display controller, which may be included in one or more processors 2102, to provide output to one or more display devices 2110A. In at least one embodiment, one or more display devices 2110A coupled to the I / O hub 2107 may include a local, internal, or embedded display device.

[0408] In at least one embodiment, the processing subsystem 2101 includes one or more parallel processors 2112 coupled to the memory hub 2105 via a bus or other communication link 2113. In at least one embodiment, the communication link 2113 may use any num...

Claims

1. A processor, comprising: One or more circuits for executing an application programming interface (API) to indicate gradient information corresponding to one or more layers of the one or more neural networks, at least in part based on one or more indications of the one or more layers of the one or more neural networks.

2. The processor according to claim 1, wherein the indication of the one or more layers includes information identifying the one or more neural networks or information identifying the one or more layers.

3. The processor according to claim 1, wherein the input to the API includes the one or more indications of the one or more layers.

4. The processor according to claim 1, wherein executing the API causes one or more gradients of the one or more neural networks to be calculated.

5. The processor according to claim 1, wherein the gradient information includes one or more gradient values of the one or more layers of the one or more neural networks.

6. The processor according to claim 1, wherein executing the API causes one or more backpropagation operations to be performed using the one or more layers.

7. The processor according to claim 1, wherein the API is executed using one or more graphics processing units (GPUs).

8. A system, comprising: One or more processors for executing an application programming interface (API) to indicate gradient information corresponding to one or more layers of the one or more neural networks, at least in part based on one or more indications of the one or more layers of the one or more neural networks.

9. The system according to claim 8, wherein the indication of the one or more layers includes information identifying the one or more neural networks or information identifying the one or more layers.

10. The system according to claim 8, wherein the input to the API includes the one or more indications of the one or more layers.

11. The system according to claim 8, wherein executing the API causes one or more gradients of the one or more neural networks to be calculated.

12. The system according to claim 8, wherein the gradient information includes one or more gradient values of the one or more layers of the one or more neural networks.

13. The system according to claim 8, wherein executing the API causes one or more backpropagation operations to be performed using the one or more layers.

14. The system according to claim 8, wherein the API is executed using one or more graphics processing units (GPUs).

15. A method, comprising: Executing an application programming interface (API) to indicate gradient information corresponding to one or more layers of the one or more neural networks, at least in part based on one or more indications of the one or more layers of the one or more neural networks.

16. The method according to claim 15, wherein the indication of the one or more layers includes information identifying the one or more neural networks or information identifying the one or more layers.

17. The method according to claim 15, wherein the input of the API includes the one or more indications of the one or more layers.

18. The method according to claim 15, wherein the API is executed to cause one or more gradients of the one or more neural networks to be calculated.

19. The method according to claim 15, wherein the gradient information includes one or more gradient values of one or more layers of the one or more neural networks.

20. The method according to claim 15, wherein the API is executed to cause one or more backpropagation operations to be performed using the one or more layers.

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