Pixel circuit and display panel

Abstract

The invention discloses a pixel circuit and a display panel. The pixel circuit comprises a scanning control module used for writing a data signal; the data storage module is used for storing data signals; the light-emitting module drives a light-emitting element based on a power supply flowing through the data storage module, the data storage module comprises a memory with a magnetoresistance effect, the data signal adjusts the impedance of the memory, and the power supply has voltage loss corresponding to the data signal after flowing through the data storage module. According to the pixel circuit, the memory with the magnetoresistance effect is used for storing the data signals, so that a capacitor and a part of switching tubes can be omitted, the occupied area of the pixel circuit is greatly reduced, and the pixel density of the display panel is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and more particularly, to a pixel circuit and a display panel. Background Art

[0002] With the development of display technology, display panels have become an indispensable part of electronic devices and are widely used in various electronic devices such as televisions, computers, mobile phones, tablet computers, e-readers, game consoles, automobiles, home appliances, and medical devices.

[0003] The pixel circuit is a key component of the display panel and is composed of a series of tiny electronic components (such as transistors) for controlling the color and brightness of each pixel in the display panel. With the development of technology and the improvement of consumer demands, the performance requirements for display panels are also getting higher and higher. Among them, pixel density (Pixel Per Inch, PPI) is an important indicator for measuring the clarity of a display panel. PPI refers to the number of pixels within one inch in length, with the unit of ppi. The higher the PPI, the finer the displayed image, the richer the colors, and the better the visual effect. However, in some electronic devices, due to size limitations, the display panel needs to have a very high PPI to meet the display requirements. Currently, the PPI of display panels is still not high enough to be applied to electronic devices with high PPI display requirements.

[0004] Therefore, it is desirable to provide an improved pixel circuit and display panel to solve the above problems. Summary of the Invention

[0005] In view of the above problems, an object of the present invention is to provide a pixel circuit and a display panel to reduce the occupied area of the pixel circuit and improve the pixel density of the display panel.

[0006] According to an aspect of the present invention, there is provided a pixel circuit, comprising: a scan control module for writing a data signal; a data storage module for storing the data signal; and a light-emitting module for driving a light-emitting element to emit light based on a power supply flowing through the data storage module, wherein the data storage module includes a memory having a magnetoresistive effect, the data signal adjusts the impedance of the memory, and the power supply has a voltage loss corresponding to the data signal after flowing through the data storage module.

[0007] Optionally, when the data signal is valid, the memory is in a low-resistance state, and the power supply drives the light-emitting element to emit light. When the data signal is invalid, the memory is in a high-resistance state, and the power supply drives the light-emitting element to stop emitting light.

[0008] Optionally, the voltage of the power supply is less than the high level of the data signal and greater than the low level of the data signal.

[0009] Optionally, the scan control module includes a first switching transistor. A first current terminal of the first switching transistor receives the data signal, a second current terminal is connected to a second terminal of the memory, and a control terminal receives a scan signal. The light-emitting module includes a current source and the light-emitting element. The current source is connected between the memory and the light-emitting element, or the current source is connected between the power supply and the memory. A control terminal of the current source receives a reference signal, a second terminal of the light-emitting element receives a common voltage, and a first terminal of the memory is connected to the power supply. When the scan signal is valid, the data signal is written into the memory. When the scan signal is invalid, the power supply drives the light-emitting element through the memory. A voltage value of the power supply is higher than a low level of the data signal and lower than a high level of the data signal.

[0010] Optionally, the scan control module includes a selector. A first terminal of the selector receives the data signal, a second terminal is connected to a second terminal of the memory, and a first terminal of the memory receives a scan signal. The light-emitting module includes a current source and the light-emitting element. A first current terminal of the current source is connected to the second terminal of the memory, a second current terminal is connected to a first terminal of the light-emitting element, and a control terminal receives a reference signal. A second terminal of the light-emitting element receives a common voltage. Wherein, when an absolute value of a voltage difference between the first terminal and the second terminal of the selector is greater than or equal to a threshold voltage, the selector is turned on. When the scan signal is valid, the data signal is written into the memory. When the scan signal is invalid, the power supply drives the light-emitting element through the memory. The scan signal is in an effective state when it is at a low level and in an invalid state when it is at a high level. A high level of the scan signal serves as the power supply.

[0011] Optionally, the selector includes a first diode and a second diode. An anode of the first diode is connected to a cathode of the second diode and receives the data signal, and an anode of the second diode is connected to a cathode of the first diode and is connected to the second terminal of the memory.

[0012] Optionally, the data signal is in an effective state when it is at a high level and in an invalid state when it is at a low level. An initial state of the memory is a high impedance state. A high level of the data signal is higher than a low level of the scan signal. When the memory drives the light-emitting element, a low level of the data signal is higher than a difference between a voltage value of the second terminal of the memory and the threshold voltage, and a difference between the high level of the data signal and the threshold voltage is lower than the voltage value of the second terminal of the memory.

[0013] Optionally, the current value of the current source is within the range of the read current of the memory and less than the write current of the memory.

[0014] Optionally, the memory is formed above or below the first switching transistor, the current source, and / or the third switching transistor, and the memory includes a magnetic tunnel junction.

[0015] According to a second aspect of the present invention, a display panel is provided, including the pixel circuit as described above.

[0016] The pixel circuit and the display panel provided by the present invention, through an innovative combination of circuit design and semiconductor devices and processes, apply a memory with a magnetoresistive effect to the pixel circuit, eliminating the capacitors in the traditional pixel circuit, greatly reducing the occupied area of the pixel circuit, effectively increasing the pixel density of the display panel, and enabling a display panel with a high pixel density (Pixel Per Inch, PPI) that is compact, reliable, and low-cost.

[0017] In some alternative embodiments, the number of switching transistors included in the pixel circuit is only three. If the problem of resetting the light-emitting element is ignored, the number of switching transistors included in the pixel circuit is only two. The pixel circuit has a low requirement for the number of switching transistors, which can further reduce the area of the pixel circuit and increase the pixel density of the display panel.

[0018] In some alternative embodiments, if a selector is used for data writing, the number of switching transistors included in the pixel circuit is only two. If the problem of resetting the light-emitting element is ignored, the number of switching transistors included in the pixel circuit is only one. The pixel circuit's requirement for the number of switching transistors is further reduced, which can further reduce the area of the pixel circuit and increase the pixel density of the display panel.

[0019] In some alternative embodiments, both the memory and the selector can be fabricated above each switching transistor as a back end of line (BEOL) process, which does not occupy the planar area of the pixel circuit, enabling the pixel circuit to achieve high PPI and high reliability. It has been proven through practice that the size of this pixel circuit can support 20 nm and below. Description of the Drawings

[0020] Through the following description of the embodiments of the present invention with reference to the drawings, the above and other objects, features, and advantages of the present invention will become clearer. In the drawings:

[0021] Figure 1 A block diagram of a pixel circuit according to an embodiment of the present invention is shown;

[0022] Figure 2 A structural diagram of a memory according to an embodiment of the present invention is shown;

[0023] Figure 3 Shows a circuit diagram of a pixel circuit according to a first embodiment of the present invention;

[0024] Figure 4 Shows a circuit diagram of a pixel circuit according to a second embodiment of the present invention;

[0025] Figure 5 Shows a circuit diagram of a pixel circuit according to a third embodiment of the present invention. Detailed Description of the Invention

[0026] The present invention will be described in more detail below with reference to the accompanying drawings. In the respective drawings, like elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown in the figures.

[0027] Many specific details of the present invention are described below, such as the structure, materials, dimensions, processing techniques and technologies of the devices, in order to understand the present invention more clearly. However, as those skilled in the art can understand, the present invention can be implemented without these specific details.

[0028] It should be understood that the connection / coupling of A and B in the embodiments of the present application means that A and B can be connected in series or in parallel, or A and B are connected through other devices, and the embodiments of the present application do not limit this.

[0029] In a traditional pixel circuit, a Dynamic Random Access Memory (DRAM) is used to store data. Each bit of data is stored in a separate capacitor. The capacitor and the access transistor together form a memory cell. The capacitor can store charge, and the transistor acts as a switch to control the reading and storage of charge. In this technical solution, a capacitor is used to directly store the data signal DATA. However, the volume of these capacitors is usually large, which is not conducive to reducing the occupied area of the pixel circuit. Moreover, the data storage of the capacitor is greatly affected by the capacitance value of the capacitor and the leakage current of the switching transistor, and the reliability is not high. In another traditional pixel circuit, a Static Random Access Memory (SRAM) is used to store data, and a bistable bipolar flip-flop is used to store each bit of data. The main disadvantage of the static random access memory is that it requires six transistors to store each bit of data, which makes the storage density of the static random access memory lower than that of the dynamic random access memory, and is even less conducive to reducing the occupied area of the pixel circuit.

[0030] In an embodiment of the present invention, a data signal is used to change the state of a memory having a magnetoresistive effect, and a light-emitting element is driven accordingly based on the state of the memory. The memory has a very small feature size, and can achieve a good trade-off in terms of speed, area, write count, and power consumption. In addition, a capacitive element required by the conventional technology can be omitted, and display driving is implemented with a small number of switching transistors, greatly reducing the occupied area of the pixel circuit and effectively increasing the pixel density (Pixel Per Inch, PPI) of the display panel.

[0031] In the following embodiments, the pixel circuit will be described in detail by taking the light-emitting element as an organic light-emitting diode (OLED) as an example. It should be understood that in actual operation, those skilled in the art can replace the organic light-emitting diode light-emitting element in the pixel circuit with other types of light-emitting elements, such as a light-emitting diode (LED), a quantum dot light-emitting diode (QLED), a micro light-emitting diode (Micro-LED), a mini light-emitting diode (Mini-LED), an organic laser diode (OLD), etc.

[0032] Embodiments of the pixel circuit and the display panel provided in the present application will be described below with reference to the accompanying drawings.

[0033] Figure 1 A block diagram of a pixel circuit according to an embodiment of the present invention is shown.

[0034] As Figure 1 shown, the pixel circuit 100 includes a scan control module 110, a data storage module 120, and a light-emitting module 130. The pixel circuit 100 drives the light-emitting element OLED in the light-emitting module 130 to emit light at least according to a data signal DATA, a scan signal SCAN, and a reference signal Vref.

[0035] The scan control module 110 is used to write the data signal DATA, and the scan control module 110 is controlled by the scan signal SCAN. For example, when the scan signal SCAN is valid, that is, in the scan stage, the scan control module 110 turns on the current path of the data signal DATA to the data storage module 120, so that the data signal DATA is written into the data storage module 120; when the scan signal SCAN is invalid, that is, in the light-emitting stage, the scan control module 110 turns off the current path of the data signal DATA to the data storage module 120.

[0036] The data storage module 120 is used to store the data signal DATA. In the embodiment of the present invention, the data storage module 120 includes a memory with a magnetoresistive effect. This memory is, for example, a magnetic random access memory (MRAM), which is a new type of non-volatile random memory using the principle of reading the magnetoresistance magnitude. The first end of the memory MRAM is connected to the power supply AVDD, and the second end is respectively connected to the scan control module 110 and the light-emitting module 130. In the scan stage, the data signal DATA is written into the data storage module 120 through the scan control module 110; in the light-emitting stage, the power supply AVDD flows through the data storage module 120 to drive the light-emitting module 130 to emit light. In some embodiments, the power supply AVDD has the same voltage value in the scan stage and the light-emitting stage. In some other embodiments, the power supply AVDD is a power supply with an adjustable voltage value, and it has different voltage values in the scan stage and the light-emitting stage.

[0037] In the embodiment of the present invention, the impedance of the memory in the data storage module 120 is adjusted by using the data signal DATA, so as to achieve the purpose of writing the data signal DATA into the data storage module 120. Therefore, the data writing method of the present invention is to store the data signal by defining the correspondence between the impedance of the memory and the data signal and using the data signal to adjust the impedance of the memory, which is completely different from the traditional technology of directly storing the data signal by using a capacitor. For example, it is defined that the data signal DATA with a low level is in an effective state, and the data signal DATA with a high level is in an invalid state. Then, the voltage of the power supply AVDD is less than the high level of the data signal DATA and greater than the low level of the data signal DATA. Therefore, when the data signal DATA is effective, the memory MRAM is in a first resistance state (such as a low resistance state); when the data signal DATA is invalid, the memory MRAM is in a second resistance state (such as a high resistance state). It should be understood that the embodiment of the present invention is not limited thereto, and those skilled in the art can modify the definition of the effective state and the invalid state of the data and the correspondence between the resistance state of the memory MRAM and the data signal DATA according to actual needs, and correspondingly adjust the pixel circuit, so that when the data signal DATA is effective, the memory MRAM is in the resistance state corresponding to the data "1", and when the data signal DATA is invalid, the memory MRAM is in the resistance state corresponding to the data "0".

[0038] The light-emitting module 130 includes a current source and a light-emitting element. The power supply AVDD flows through the data storage module 120 and the light source in sequence to drive the light-emitting element. The current source is used to control the magnitude of the current in the pixel circuit, so that the current source is turned off during the scanning stage and maintains the current in the pixel circuit during the light-emitting stage to prevent the state of the memory from changing. During the light-emitting stage, the current source maintains the current in the pixel circuit within the range of the read current of the memory, which is much smaller than the write current of the memory. The current source is controlled by a reference signal Vref, which is an analog signal and can be used to adjust the magnitude of the current of the current source. In some embodiments, the reference signal Vref is a signal with a constant voltage value, and all pixel circuits 100 in the display panel can share a reference signal Vref. In other embodiments, to prevent the current source with a small current from being mis-conducted during the scanning stage, the voltage value of the reference signal Vref can be adjusted during the scanning stage so that the current source is directly turned off. For example, during the scanning stage, the reference signal Vref is invalid, and the current path from the data storage module 120 to the light-emitting module 130 is turned off; during the light-emitting stage, the reference signal Vref is valid, the current path from the data storage module 120 to the light-emitting module 130 is turned on, and the current in the current path is maintained within the range of the read current of the memory to prevent the state of the memory from flipping. During the light-emitting stage, the power supply AVDD has a voltage loss corresponding to the data signal DATA after flowing through the data storage module 120. Therefore, there is a corresponding voltage loss when driving the light-emitting module 130 to emit light, which can cause the light-emitting element OLED to emit light corresponding to the data signal DATA. For example, when the data signal DATA is valid, the memory MRAM is in a low-resistance state, and the power supply AVDD has a small voltage loss after flowing through the memory MRAM, driving the light-emitting element OLED to emit light; when the data signal DATA is invalid, the memory MRAM is in a high-resistance state, and the current of the power supply AVDD cannot pass through the memory MRAM, so the light-emitting element OLED stops emitting light.

[0039] In an embodiment of the present invention, during the scanning stage, the scan signal SCAN is valid, and the data signal DATA is written into the data storage module 120 through the scan control module 110. The data signal DATA stores data by adjusting the impedance of the memory MRAM. During the light-emitting stage, the scan signal SCAN is invalid. After the power supply AVDD flows through the data storage module 120, there is a voltage loss corresponding to the data signal DATA. Therefore, when driving the light-emitting module 130 to emit light, there is a corresponding voltage loss, which enables the light-emitting element OLED to emit light corresponding to the data signal DATA. Therefore, the pixel circuit 100 does not directly use the memory MRAM to store the data signal DATA, but uses the data signal DATA to change the state of the memory during the scanning stage, and drives the light-emitting element OLED based on the state of the memory MRAM during the light-emitting stage. The pixel circuit 100 uses the memory MRAM with magnetoresistive effect to store the data signal DATA, which can eliminate the switch and capacitor elements required by the traditional technology, greatly reduce the occupied area of the pixel circuit 100, and effectively improve the pixel density of the display panel.

[0040] Figure 2 The structural diagram of a memory according to an embodiment of the present invention is shown.

[0041] As Figure 2 shown, the memory MRAM is a magnetic random access memory, which includes a magnetic tunnel junction 10 (Magnetic Tunnel Junction, MTJ).

[0042] A magnetic random access memory is a new type of non-volatile random access memory that uses the principle of reading the magnitude of magnetoresistance. Compared with other storage technologies, magnetic random access memory can achieve a better trade-off in terms of speed, area, write times, and power consumption. Therefore, it is considered by the industry to be one of the potential access devices for constructing the next-generation non-volatile cache and main memory.

[0043] The improvement of the performance of magnetic random access memory benefits from the continuous increase in the tunneling magnetoresistance (TMR) value of the magnetic tunnel junction 10. The magnetic tunnel junction 10 is the basic storage unit of the magnetic random access memory, including two ferromagnetic layers 11, 13 and a tunneling barrier layer 12 located between the two ferromagnetic layers 11, 13. The ferromagnetic layers 11, 13 are conductive layers, and their thickness is, for example, 1 - 2.5 nm. The tunneling barrier layer 12 is an insulating layer, and its thickness is, for example, 1 - 1.5 nm. The two ferromagnetic layers 11, 13 and the tunneling barrier layer 12 form a nano-multilayer film similar to a sandwich structure. One of the ferromagnetic layers 13 is called the reference layer (Reference Layer) or the pinned layer (Pinned Layer), and its magnetization is fixed along the easy magnetization axis direction. The other ferromagnetic layer 11 is called the free layer (Free Layer), and its magnetization has two stable orientations, parallel or antiparallel to the reference layer respectively, which will make the magnetic tunnel junction 10 in a low-resistance state or a high-resistance state. This phenomenon is called the tunneling magnetoresistance effect. The two resistance states of the magnetic tunnel junction 10 can respectively represent binary data "0" and "1", which is the basic principle for the magnetic random access memory to store data. The tunneling magnetoresistance effect can be explained by the spin-dependent tunneling theory. For ferromagnetic metals, the distribution of electron states with spin up and spin down is uneven near the Fermi level. When the magnetization directions of the reference layer and the free layer are the same, the spin directions of the electrons in the majority state in the two ferromagnetic materials are the same, the tunneling probability is higher, the tunneling current is larger, and the magnetic tunnel junction 10 presents a low-resistance state; conversely, the magnetic tunnel junction 10 presents a high-resistance state. Wires are respectively connected to the two ferromagnetic layers 11, 13 to facilitate data writing and data reading.

[0044] When writing data into the magnetic random access memory, when the current flows from the reference layer to the free layer, it first obtains the spin angular momentum in the same direction as the magnetization direction of the reference layer. When this spin-polarized current enters the free layer, it interacts with the magnetization of the free layer, resulting in the transfer of the transverse component of the spin-polarized current. Due to the conservation of angular momentum, the transferred transverse component will act on the free layer in the form of a torque, forcing its magnetization direction to approach the reference layer. This torque is called the spin transfer torque. Similarly, for the current in the opposite direction, the reflection effect of the reference layer on the spin causes the free layer magnetization to obtain an opposite torque. Therefore, the written magnetization state is determined by the current direction.

[0045] When reading data from a magnetic random access memory, it is only necessary to detect the potential difference brought by the magnetic tunnel junction 10 after passing a relatively small current. In the embodiment of the present invention, the reading current of the memory is set to a relatively small current, and the reading current of the memory can be less than or even much less than the writing current of the memory. Due to the existence of the tunneling effect, if the magnetic tunnel junction 10 is in a low-resistance state, the potential difference is very small; if the tunneling effect does not exist, it proves that the magnetic tunnel junction 10 is in a high-resistance state, and the potential difference is very large. By the magnitude of the potential difference, the state of the data stored in the magnetic tunnel junction 10 at this time can be judged, and at the same time, the data is transmitted to the system. In addition, this method of reading data is completely non-destructive and does not affect the stability of the data.

[0046] The magnetic random access memory relies on the direction of the writing current to distinguish whether the written data is "0" or "1", and those skilled in the art can set the direction of the memory according to actual needs. For example, in the first embodiment and the third embodiment of the present invention, it is defined that when the current of the magnetic random access memory flows from the first end to the second end, that is, when the current flows from top to bottom, the magnetic tunnel junction 10 is in a low-resistance state and the written data is "1"; on the contrary, when the current of the magnetic random access memory flows from the second end to the first end, that is, when the current flows from bottom to top, the magnetic tunnel junction 10 is in a high-resistance state and the written data is "0". Another example, in the second embodiment of the present invention, it is defined that when the current of the magnetic random access memory flows from the second end to the first end, that is, when the current flows from bottom to top, the magnetic tunnel junction 10 is in a low-resistance state and the written data is "1"; on the contrary, when the current of the magnetic random access memory flows from the first end to the second end, that is, when the current flows from top to bottom, the magnetic tunnel junction 10 is in a high-resistance state and the written data is "0". It should be understood that the embodiments of the present invention are not limited thereto, and those skilled in the art can change the correspondence between the resistance state of the magnetic tunnel junction 10 and the written data according to actual needs, and correspondingly adjust the conduction state of the pixel circuit in the scanning stage and / or the type of the switching transistor.

[0047] Figure 3 The circuit diagram of the pixel circuit according to the first embodiment of the present invention is shown.

[0048] As Figure 3 shown, in the pixel circuit 200, the scan control module 210 includes a first switching transistor SW1, the data storage module 220 includes a memory MRAM, and the light emitting module 230 includes a current source SW2, a third switching transistor SW3, and a light emitting element OLED.

[0049] Specifically, the first current terminal of the first switching transistor SW1 receives the data signal DATA, the second current terminal is connected to the second terminal of the memory MRAM, and the control terminal receives the scan signal SCAN. The first current terminal of the current source SW2 is connected to the second terminal of the memory MRAM, the second current terminal is connected to the first terminal (anode) of the light-emitting element OLED, and the control terminal receives the reference signal Vref. The first current terminal of the third switching transistor SW3 is connected to the first terminal of the light-emitting element OLED, the second current terminal is connected to the reference ground, and the control terminal receives the reset signal RESETB. The second terminal (cathode) of the light-emitting element OLED receives the common voltage Vcom. The first terminal of the memory MRAM is connected to the power supply VP, and the second terminal of the memory MRAM is respectively connected to the second current terminal of the first switching transistor SW1 and the first current terminal of the current source SW2. Among them, when the scan signal SCAN is valid / invalid, the data signal DATA is written into the memory MRAM. When the scan signal SCAN is invalid, the power supply VP drives the light-emitting element OLED through the memory MRAM. In some embodiments, the reference signal Vref is in an effective state during both the scan stage and the light-emitting stage to limit the current value of the current source SW2 within the range of the read current of the memory. The read current of the memory is much smaller than the write current of the memory. In other embodiments, the reference signal Vref is in an invalid state during the scan stage to turn off the current source SW2, and the reference signal Vref is in an effective state during the light-emitting stage to limit the current value of the current source SW2 within the range of the read current of the memory.

[0050] In this embodiment, it is defined that the data signal DATA with a low level is in an effective state, and the data signal DATA with a high level is in an invalid state. The voltage value of the power supply VP is higher than the low level of the data signal DATA and lower than the high level of the data signal DATA. Therefore, when the data signal DATA is effective, the current flows from the first terminal of the memory MRAM to the second terminal, and the memory MRAM is in a low-resistance state, writing the data "1"; when the data signal DATA is invalid, the current flows from the second terminal of the memory MRAM to the first terminal, and the memory MRAM is in a high-resistance state, writing the data "0". It should be understood that the embodiments of the present invention are not limited thereto. Those skilled in the art can modify the definitions of the data effective state and the invalid state and the corresponding relationship between the resistance state of the memory MRAM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly, so that when the data signal DATA is effective, the memory MRAM is in the resistance state corresponding to the data "1", and when the data signal DATA is invalid, the memory MRAM is in the resistance state corresponding to the data "0".

[0051] During the scanning stage, the scan signal SCAN is valid and the reset signal RESETB is valid. Therefore, the first switching transistor SW1 and the third switching transistor SW3 are turned on. The current source SW2 is turned off during the scanning stage. The reference signal Vref can be in an invalid state or a valid state. When the reference signal Vref is in an invalid state, the current source SW2 is turned off. When the reference signal Vref is in a valid state, the current of the current source SW2 is much smaller than the read current of the memory because it can be considered that the current source SW2 is in an off state. At this time, the first end of the memory MRAM is connected to the power supply VP, the voltage value of the power supply VP is V0, the second end of the memory MRAM receives the data signal DATA, and there is a voltage difference between the first end and the second end of the memory MRAM, so that the memory MRAM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is valid, that is, the voltage on the data line is the low level VdataL, and V0 > VdataL, the current flows from top to bottom, and the magnetic tunnel junction in the memory MRAM is in a low-resistance state, representing the written data "1"; if the data signal DATA is invalid, that is, the voltage on the data line is the high level VdataH, and V0 < VdataH, the current flows from bottom to top, and the magnetic tunnel junction in the memory MRAM is in a high-resistance state, representing the written data "0". The impedance of the memory MRAM determines whether the light-emitting element OLED can emit light during the light-emitting stage. That is, the data signal DATA is written into the memory MRAM by adjusting the impedance of the memory MRAM. The memory MRAM is disconnected from the light-emitting element OLED. The first end of the light-emitting element OLED is connected to the reference ground to reset the residual charge on the light-emitting element OLED.

[0052] During the light-emitting stage, the scan signal SCAN is invalid and the reset signal RESETB is invalid. Therefore, the first switching transistor SW1 and the third switching transistor SW3 are turned off, and the current source SW2 is turned on. At this time, the memory MRAM has an impedance corresponding to the data signal DATA, and the power supply VP is connected to the light-emitting element OLED through the memory MRAM. Therefore, after the power supply VP flows through the memory MRAM, there is a voltage loss corresponding to the data signal DATA. If the data signal DATA is valid, the memory MRAM is in a low-resistance state, and the voltage loss after the power supply VP flows through the memory MRAM is very small or almost zero, and the light-emitting element OLED can be smoothly driven to emit light; if the data signal DATA is invalid, the memory MRAM is in a high-resistance state, and the voltage loss after the power supply VP flows through the memory MRAM is very large, and the light-emitting element OLED cannot be driven to emit light.

[0053] In addition, if the light-emitting element OLED in the pixel circuit 200 has low requirements for anode reset, the issue of the need for reset of the light-emitting element OLED can be ignored, the third switching transistor SW3 can be omitted, and the number of switching transistors included in the pixel circuit 200 can be only two (the first switching transistor SW1 and the current source SW2), and the pixel circuit 200 has low requirements for the number of switching transistors.

[0054] In this embodiment, the first switching transistor SW1, the current source SW2, and the third switching transistor SW3 can be transistors of types such as bipolar junction transistors (BJTs), field-effect transistors (FETs), and insulated gate bipolar transistors (IGBTs).

[0055] As an example, the first switching transistor SW1, the current source SW2, and the third switching transistor SW3 are all P-channel metal oxide semiconductor field-effect transistors (Positive Channel Metal Oxide Semiconductor Field-Effect Transistor, PMOSFETs). When the gate-source voltage Vgs of the PMOSFET is less than or equal to the voltage threshold, that is, when its control terminal receives a low-level control signal, the current path from its first current terminal to its second current terminal is turned on; when the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, that is, when its control terminal receives a high-level control signal, the current path from its first current terminal to its second current terminal is turned off. Therefore, it is defined that the scan signal SCAN, the reference signal Vref, and the reset signal RESETB with low levels are in an effective state, and the scan signal SCAN, the reference signal Vref, and the reset signal RESETB with high levels are in an invalid state. It should be understood that the embodiments of the present invention are not limited thereto, and those skilled in the art can modify the types of the first switching transistor SW1, the current source SW2, and the third switching transistor SW3 and the specific levels of the scan signal SCAN, the reference signal Vref, and the reset signal RESETB in the effective state and the invalid state according to actual needs.

[0056] In this embodiment, during the light-emitting stage, due to the presence of the current source SW2, the current flowing through the memory is limited within the range of the read current of the memory, and this range is much smaller than the write current of the memory, so the state flip of the memory will not be caused.

[0057] Figure 4 The circuit diagram of the pixel circuit according to the second embodiment of the present invention is shown.

[0058] As Figure 4 shown, in this pixel circuit 300, the scan control module 310 includes a selector, the data storage module 320 includes a memory MRAM, and the light-emitting module 330 includes a current source SW2, a third switching transistor SW3, and a light-emitting element OLED.

[0059] Specifically, the first end of the selector receives the data signal DATA, and the second end is connected to the second end of the memory MRAM. The first current terminal of the current source SW2 is connected to the second end of the memory MRAM, the second current terminal is connected to the first end (anode) of the light-emitting element OLED, and the control terminal receives the reference signal Vref. The first current terminal of the third switching transistor SW3 is connected to the first end of the light-emitting element OLED, the second current terminal is connected to the reference ground, and the control terminal receives the reset signal RESETB. The second end (cathode) of the light-emitting element OLED receives the common voltage Vcom. The first end of the memory MRAM is connected to the scan signal SCAN, and the second end of the memory MRAM is respectively connected to the second end of the selector and the first current terminal of the current source SW2. Among them, when the scan signal SCAN is valid, the data signal DATA is written into the memory MRAM. When the scan signal SCAN is invalid, the high-level scan signal SCAN drives the light-emitting element OLED through the memory MRAM. In some embodiments, the reference signal Vref is in an effective state both in the scan stage and the light-emitting stage to limit the current value of the current source SW2 within the range of the read current of the memory, and the read current of the memory is much smaller than the write current of the memory. In other embodiments, the reference signal Vref is in an invalid state in the scan stage to turn off the current source SW2, and the reference signal Vref is in an effective state in the light-emitting stage to limit the current value of the current source SW2 within the range of the read current of the memory.

[0060] In this embodiment, the scan signal SCAN is in an effective state when it is at a low level and in an invalid state when it is at a high level. In the light-emitting stage, the high level of the scan signal SCAN is multiplexed as the power supply VP.

[0061] In this embodiment, the selector is preset with a threshold voltage. When the absolute value of the voltage difference between the first end and the second end of the selector is greater than or equal to the threshold voltage, the selector conducts. When the absolute value of the voltage difference between the first end and the second end of the selector is less than the threshold voltage, the selector cuts off. As an example, the selector includes a first diode D1 and a second diode D2. The anode of the first diode D1 is connected to the cathode of the second diode D2 and receives the data signal DATA. The anode of the second diode D2 is connected to the cathode of the first diode D1 and is connected to the second end of the memory MRAM.

[0062] Specifically, in this selector, when a positive bias voltage greater than the threshold voltage Vd is applied, the impedance is very small and the selector conducts. When the bias voltage decreases to less than the threshold voltage Vd and greater than the negative threshold voltage -Vd, the impedance is very large and the selector turns off. When the bias voltage continues to decrease to less than the negative threshold voltage -Vd, the selector starts to conduct again and the impedance is very small. In some embodiments, the selector can be any combination of traditional types of diodes such as PN diodes, Schottky diodes, or bipolar junction transistors (BJTs), or it can be an Ovonic Threshold Switch (OTS), which is similar to a phase change memory (PCM), but the difference is that its molecules do not crystallize. The bidirectional threshold switch can be realized by adding other elements (such as arsenic) that prevent crystallization to the phase change material. Each time when the voltage is removed and the temperature drops, it will return to the amorphous state and will never appear in the crystalline state, so it cannot be used as a memory but can be used as a switch.

[0063] In this embodiment, it is defined that the data signal DATA with a high level is in an effective state, the data signal DATA with a low level is in an invalid state, the low level of the scan signal SCAN is lower than the high level of the data signal DATA, and the initial state of the memory MRAM is a high impedance state; when the current of the memory MRAM flows from the second end to the first end, the memory MRAM is in a low impedance state and data "1" is written; conversely, when the current of the memory MRAM flows from the first end to the second end, the memory MRAM is in a high impedance state and the written data is "0". Therefore, when the data signal DATA is effective, the current flows from the second end to the first end of the memory MRAM, and the memory MRAM is in a low impedance state, writing data "1"; when the data signal DATA is invalid, the selector is in a cut-off state, and the memory MRAM maintains a high impedance state, writing data "0". It should be understood that the embodiments of the present invention are not limited thereto, and those skilled in the art can modify the definitions of the data effective state and the invalid state and the corresponding relationship between the impedance state of the memory MRAM and the data signal DATA according to actual needs, and adjust the pixel circuit accordingly, so that when the data signal DATA is effective, the memory MRAM is in the impedance state corresponding to data "1", and when the data signal DATA is invalid, the memory MRAM is in the impedance state corresponding to data "0".

[0064] In the initialization phase, the scan signal SCAN is invalid, and the current source SW2 and the third switching transistor SW3 are turned on. For example, if both the current source SW2 and the third switching transistor SW3 are PMOS transistors, the reference signal Vref and the reset signal RESETB are both set to a low level. Therefore, the first terminal of the memory MRAM is connected to the high-level scan signal SCAN, and the second terminal is connected to the reference ground via the current source SW2 and the third switching transistor SW3, and the memory MRAM is initialized to write the data "0".

[0065] In the scan phase, the scan signal SCAN is valid, the reference signal Vref is invalid, and the reset signal RESETB is valid. Therefore, the third switching transistor SW3 is turned on. The current source SW2 is turned off in the scan phase. The reference signal Vref can be in an invalid state or a valid state. When the reference signal Vref is in an invalid state, the current source SW2 is turned off. When the reference signal Vref is in a valid state, the current of the current source SW2 is much smaller than the read current of the memory, because it can be considered that the current source SW2 is in an off state. At this time, the first terminal of the memory MRAM is connected to the scan signal SCAN with a low level, the voltage value of the scan signal SCAN is Vp, the second terminal of the memory MRAM receives the data signal DATA, and there is a voltage difference between the first terminal and the second terminal of the memory MRAM, so that the memory MRAM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is valid, that is, the voltage on the data line is the high level VdataH, the current flows from bottom to top, and the magnetic tunnel junction in the memory MRAM is in a low-resistance state, representing the written data "1"; if the data signal DATA is invalid, that is, the voltage on the data line is the low level VdataL, the selector is in a cut-off state, and the magnetic tunnel junction in the memory MRAM maintains the initial state (high-resistance state), representing the written data "0". The impedance of the memory MRAM determines whether the light-emitting element OLED can emit light in the light-emitting phase. That is, the data signal DATA is written into the memory MRAM by adjusting the impedance of the memory MRAM. The memory MRAM is disconnected from the light-emitting element OLED. The first terminal of the light-emitting element OLED is connected to the reference ground to reset the residual charge on the light-emitting element OLED.

[0066] During the light-emitting phase, the scan signal SCAN is invalid, the reference signal Vref is valid, and the reset signal RESETB is invalid. Therefore, the third switching transistor SW3 is turned off, and the current source SW2 is turned on. At this time, the memory MRAM has an impedance corresponding to the data signal DATA, and the high-level scan signal SCAN is connected to the light-emitting element OLED through the memory MRAM. Therefore, after the high-level scan signal SCAN flows through the memory MRAM, it has a voltage loss corresponding to the data signal DATA. If the data signal DATA is valid, the memory MRAM is in a low-resistance state, and the voltage loss of the high-level scan signal SCAN after flowing through the memory MRAM is very small or almost zero, and the light-emitting element OLED can be successfully driven to emit light; if the data signal DATA is invalid, the memory MRAM is in a high-resistance state, and the voltage loss of the high-level scan signal SCAN after flowing through the memory MRAM is very large, and the light-emitting element OLED cannot be driven to emit light.

[0067] In addition, if the light-emitting element OLED in the pixel circuit 300 has low requirements for anode reset, the problem of the need for reset of the light-emitting element OLED can be ignored, and the third switching transistor SW3 can be omitted. Then, the number of switching transistors included in the pixel circuit 300 can be only one (the current source SW2), and the pixel circuit 300 has low requirements for the number of switching transistors.

[0068] In this embodiment, the current source SW2 and the third switching transistor SW3 can be transistors of types such as bipolar junction transistors (BJTs), field-effect transistors (FETs), and insulated gate bipolar transistors (IGBTs).

[0069] As an example, both the current source SW2 and the third switching transistor SW3 are P-channel metal oxide semiconductor field-effect transistors (PMOSFETs). When the gate-source voltage Vgs of the PMOSFET is less than or equal to the voltage threshold, that is, when its control terminal receives a low-level control signal, the current path from its first current terminal to its second current terminal is turned on; when the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, that is, when its control terminal receives a high-level control signal, the current path from its first current terminal to its second current terminal is turned off. Therefore, it is defined that the scan signal SCAN and the reset signal RESETB with low levels are in an effective state, and the scan signal SCAN and the reset signal RESETB with high levels are in an invalid state. It should be understood that the embodiments of the present invention are not limited thereto, and those skilled in the art can modify the types of the first switching transistor SW1, the current source SW2, and the third switching transistor SW3, as well as the specific levels of the effective state and the invalid state of the scan signal SCAN and the reset signal RESETB according to actual needs.

[0070] In this embodiment, when the memory MRAM drives the light-emitting element OLED, the low level of the data signal DATA is higher than the difference between the voltage value of the second terminal of the memory MRAM and the threshold voltage, and the difference between the high level of the data signal DATA and the threshold voltage is lower than the voltage value of the second terminal of the memory MRAM. Therefore, the selector does not conduct, and no additional current leaks through the selector. During the light-emitting stage, the current source SW2 limits the current flowing through the memory MRAM within the range of the read current of the memory. The read current of the memory is less than / much less than the write current of the memory MRAM. Therefore, the state of the memory MRAM will not flip. The "0" or "1" of the data signal can be permanently maintained in the memory MRAM, which is crucial for the stability of the driving current during display.

[0071] Figure 5 The circuit diagram of the pixel circuit according to the third embodiment of the present invention is shown.

[0072] As Figure 5 shown, in the pixel circuit 400, the scan control module includes a first switch SW1, the data storage module includes a memory MRAM, and the light-emitting module includes a current source SW2, a third switch SW3, a fourth switch SW4, and a light-emitting element OLED.

[0073] Specifically, the first current terminal of the first switching transistor SW1 receives the data signal DATA, the second current terminal is connected to the second terminal of the memory MRAM, and the control terminal receives the scan signal SCAN. The first current terminal of the current source SW2 is connected to the power supply AVDD, the second current terminal is connected to the first terminal of the memory MRAM, and the control terminal receives the reference signal Vref. The first current terminal of the third switching transistor SW3 is connected to the first terminal of the light-emitting element OLED, the second current terminal is connected to the reference ground, and the control terminal receives the reset signal RESETB. The first current terminal of the fourth switching transistor SW4 is connected to the second terminal of the memory MRAM, the second current terminal is connected to the first terminal (anode) of the light-emitting element OLED, and the control terminal receives the control signal EMB. The second terminal (cathode) of the light-emitting element OLED receives the common voltage Vcom. In this embodiment, the first terminal of the memory MRAM is connected to the power supply AVDD via the current source SW2, and the second terminal of the memory MRAM is respectively connected to the second current terminal of the first switching transistor SW1 and the first current terminal of the fourth switching transistor SW4. Among them, when the scan signal SCAN is valid / invalid, the data signal DATA is written into the memory MRAM. When the scan signal SCAN is invalid, the power supply AVDD drives the light-emitting element OLED through the memory MRAM. In this embodiment, the current source SW2 and the fourth switching transistor SW4 are both P-type transistors as an example. In the scanning stage, the reference signal Vref is at a low level, turning on the current source SW2 as a conducting switch; the control signal EMB is at a high level, turning off the fourth switching transistor SW4 to prevent the light-emitting element OLED from being turned on. In the light-emitting stage, the reference signal Vref is an analog signal with a predetermined value, adjusting the current magnitude of the current source SW2 to limit the voltage value across the memory to be less than the write voltage of the memory; the control signal EMB is at a low level, turning on the fourth switching transistor SW4 to drive the light-emitting element OLED to emit light.

[0074] In this embodiment, it is defined that the data signal DATA with a low level is in an active state, and the data signal DATA with a high level is in an inactive state. The voltage value of the power supply AVDD is higher than the low level of the data signal DATA and lower than the high level of the data signal DATA. Therefore, when the data signal DATA is active, the voltage at the first end of the memory MRAM (i.e., the voltage value of the power supply AVDD) is higher than the voltage at the second end of the memory MRAM (i.e., the low level of the data signal DATA), and the memory MRAM is in a low-resistance state, writing the data "1"; when the data signal DATA is inactive, the voltage at the first end of the memory MRAM (i.e., the voltage value of the power supply AVDD) is lower than the voltage at the second end of the memory MRAM (i.e., the high level of the data signal DATA), and the memory MRAM is in a high-resistance state, writing the data "0". It should be understood that the embodiments of the present invention are not limited thereto. Those skilled in the art can determine the direction of the memory according to actual needs, and accordingly adjust the conduction state of the pixel circuit during the scanning stage, the corresponding relationship between the high and low levels at each location in each stage, and / or the type of the switching transistor, so that when the data signal DATA is active, the memory MRAM is in a resistance state corresponding to the data "1", and when the data signal DATA is inactive, the memory MRAM is in a resistance state corresponding to the data "0".

[0075] In the scanning stage, the scan signal SCAN is valid, the reset signal RESETB is valid, the reference signal Vref is valid, and the control signal EMB is invalid. Therefore, the first switching transistor SW1, the current source SW2, and the third switching transistor SW3 are turned on, and the fourth switching transistor SW4 is turned off. At this time, the first end of the memory MRAM is connected to the power supply AVDD, the voltage value of the power supply AVDD is V0, the second end of the memory MRAM receives the data signal DATA, and there is a voltage difference between the first end and the second end of the memory MRAM, so that the memory MRAM has an impedance corresponding to the data signal DATA. For example, if the data signal DATA is valid, that is, the voltage on the data line is the low level VdataL, and V0 > VdataL, the voltage at the first end of the memory MRAM (i.e., the voltage value of the power supply AVDD) is higher than the voltage at the second end of the memory MRAM (i.e., the low level of the data signal DATA), and the memory MRAM is in a low-resistance state, representing writing the data "1"; if the data signal DATA is invalid, that is, the voltage on the data line is the high level VdataH, and V0 < VdataH, the voltage at the first end of the memory MRAM (i.e., the voltage value of the power supply AVDD) is lower than the voltage at the second end of the memory MRAM (i.e., the high level of the data signal DATA), and the memory MRAM is in a high-resistance state, representing writing the data "0". The impedance of the memory MRAM determines whether the light-emitting element OLED can emit light in the light-emitting stage. That is, the data signal DATA is written into the memory MRAM by adjusting the impedance of the memory MRAM. In the scanning stage, the memory MRAM is disconnected from the light-emitting element OLED, and the first end of the light-emitting element OLED is connected to the reference ground to reset the residual charge on the light-emitting element OLED.

[0076] In the light-emitting stage, the scan signal SCAN is invalid, the reset signal RESETB is invalid, the reference signal Vref is an analog signal for adjusting the current, and the control signal EMB is valid. Therefore, the first switching transistor SW1 and the third switching transistor SW3 are turned off, the current source SW2 controls the current in the circuit, and the fourth switching transistor SW4 is turned on. At this time, the memory MRAM has an impedance corresponding to the data signal DATA, and the power supply AVDD is connected to the light-emitting element OLED through the memory MRAM. Therefore, after the power supply AVDD flows through the memory MRAM, there is a voltage loss corresponding to the data signal DATA. If the data signal DATA is valid, the memory MRAM is in a low-resistance state, and the voltage loss after the power supply AVDD flows through the memory MRAM is very small or almost zero, and the light-emitting element OLED can be smoothly driven to emit light; if the data signal DATA is invalid, the memory MRAM is in a high-resistance state, and the voltage loss after the power supply AVDD flows through the memory MRAM is very large, and the light-emitting element OLED cannot be driven to emit light.

[0077] In addition, if the light-emitting element OLED in the pixel circuit 400 has low requirements for anode reset, the problem that the light-emitting element OLED needs to be reset can be ignored, the third switching transistor SW3 can be omitted, and the number of switching transistors included in the pixel circuit 400 can be only three (the first switching transistor SW1, the current source SW2, and the fourth switching transistor SW4), and the pixel circuit 400 has low requirements for the number of switching transistors.

[0078] In this embodiment, the first switching transistor SW1, the current source SW2, the third switching transistor SW3, and the fourth switching transistor SW4 can be transistors of types such as bipolar junction transistors (BJTs), field-effect transistors (FETs), insulated gate bipolar transistors (IGBTs), etc.

[0079] As an example, the first switching transistor SW1, the current source SW2, the third switching transistor SW3, and the fourth switching transistor SW4 are all P-channel metal oxide semiconductor field-effect transistors (Positive Channel Metal Oxide Semiconductor Field-Effect Transistor, PMOSFET). When the gate-source voltage Vgs of the PMOSFET is less than or equal to the voltage threshold, that is, when its control terminal receives a low-level control signal, the current path from its first current terminal to its second current terminal is turned on; when the gate-source voltage Vgs of the PMOSFET is greater than the voltage threshold, that is, when its control terminal receives a high-level control signal, the current path from its first current terminal to its second current terminal is turned off. Therefore, it is defined that the scan signal SCAN, the reference signal Vref, the reset signal RESETB, and the control signal EMB with low levels are in an effective state, and the scan signal SCAN, the reference signal Vref, the reset signal RESETB, and the control signal EMB with high levels are in an ineffective state. It should be understood that the embodiments of the present invention are not limited thereto, and those skilled in the art can modify the types of the first switching transistor SW1, the current source SW2, the third switching transistor SW3, and the fourth switching transistor SW4 and the specific levels of the scan signal SCAN, the reference signal Vref, the reset signal RESETB, and the control signal EMB in the effective state and the ineffective state according to actual needs.

[0080] In this embodiment, during the light-emitting stage, due to the presence of the current source SW2, the voltage across the control memory MRAM is much smaller than the write voltage, so the state of the memory will not be flipped, and the state of the memory can be stably maintained during the light-emitting stage.

[0081] In addition, due to certain deficiencies in the process of the existing memory MRAM, the on-resistance of the memory MRAM is discrete. In this embodiment, the positions of the current source SW2 and the memory MRAM are exchanged, and a fourth switching transistor SW4 is introduced, which can avoid the discreteness of the on-resistance of the memory MRAM introduced by process processing or the discreteness of writing conditions, and further avoid the inconsistency of the driving current of the pixel circuit.

[0082] In Figure 3 and Figure 4 , the memory MRAM can be formed above or below the first switching transistor SW1, the current source SW2, and / or the third switching transistor SW3. In Figure 5 , the memory MRAM can be formed above or below the first switching transistor SW1, the current source SW2, the third switching transistor SW3, and / or the fourth switching transistor SW4, which can further reduce the occupied area of the pixel circuit.

[0083] In addition, the present invention also provides a display panel, including a plurality of such as Figures 3 to 5Any one of the pixel circuits, multiple pixel circuits are arranged in an array in the display panel. One data line is shared by a column of pixel circuits, and one scan line is shared by a row of pixel circuits. All pixel circuits can share a common voltage. The type of the display panel can be any one of Low-Temperature Polysilicon Organic Light-Emitting Diode (LTPSOLED) display panel, Micro Organic Light Emitting Diode (Micro-OLED) display panel, Mini Organic Light Emitting Diode (Mimi-OLED) display panel, Micro Light Emitting Diode (Micro-LED) display panel, Passive Matrix Organic Light Emitting Diode (PassiveMatrix OLED) display panel, Active Matrix Organic Light Emitting Diode (Active Matrix OLED) display panel, Flexible Organic Light Emitting Diode (Flexible OLED) display panel, Transparent Organic Light Emitting Diode (Transparent OLED) display panel, etc. The present application does not limit this.

[0084] In summary, the present invention provides a pixel circuit and a display panel. Through an innovative combination of circuit design and semiconductor devices and processes, a memory with magnetoresistive effect is applied to the pixel circuit, eliminating the capacitors in the traditional pixel circuit, greatly reducing the occupied area of the pixel circuit, effectively increasing the pixel density of the display panel, and enabling a high-PPI display panel that is compact, reliable and low-cost.

[0085] In some alternative embodiments, the number of switching transistors included in the pixel circuit is only three. If the problem of resetting the light-emitting element is ignored, the number of switching transistors included in the pixel circuit is only two. The pixel circuit has low requirements for the number of switching transistors.

[0086] In some alternative embodiments, a selector is used for data writing, and the number of switching transistors included in the pixel circuit is only two. If the problem of resetting the light-emitting element is ignored, the number of switching transistors included in the pixel circuit is only one, and the requirement for the number of switching transistors in the pixel circuit is further reduced.

[0087] In some alternative embodiments, both the memory and the selector can be fabricated above each switching transistor as a back-end-of-line (BEOL) process, which does not occupy the planar area of the pixel circuit, enabling the pixel circuit to achieve high pixels per inch (PPI) and high reliability. It has been proven through practice that the size of this pixel circuit can support 20 nm and below.

[0088] Some examples of the pixel circuit and the display panel according to the embodiments of the present invention are described above. However, the embodiments of the present invention are not limited thereto, and there may be other ways of expansion and deformation.

[0089] For example, it should be understood that the reference ground potential in the foregoing embodiments may be replaced with other non-zero reference potentials (having a positive voltage amplitude or a negative voltage amplitude) or a controlled variable reference signal in alternative embodiments.

[0090] Meanwhile, those of ordinary skill in the art can realize that for the structures and methods of the examples described in combination with the embodiments disclosed herein, different configuration methods or adjustment methods can be used to implement the described functions for each structure or a reasonable deformation of the structure, but such implementation should not be considered to exceed the scope of this application. Moreover, it should be understood that the connection relationships between the various components of the amplifier in the foregoing figures in the embodiments of this application are illustrative examples and do not impose any limitations on the embodiments of this application.

[0091] It should be noted that in this document, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0092] As described above with reference to the embodiments of the present invention, these embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. These embodiments are selected and specifically described in this specification in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and its modifications based on the present invention. The present invention is only limited by the claims and their full scope and equivalents.

Claims

1. A pixel circuit, comprising: A scan control module for writing a data signal; A data storage module for storing the data signal; And A light-emitting module for driving a light-emitting element based on a power supply flowing through the data storage module, Wherein, the data storage module includes a memory having a magnetoresistive effect, the data signal adjusts the impedance of the memory, and the power supply has a voltage loss corresponding to the data signal after flowing through the data storage module.

2. The pixel circuit according to claim 1, wherein When the data signal is valid, the memory is in a low-resistance state, and the power supply drives the light-emitting element to emit light. When the data signal is invalid, the memory is in a high-resistance state, and the power supply drives the light-emitting element to stop emitting light.

3. The pixel circuit according to claim 1, wherein, The voltage of the power supply is less than the high level of the data signal and greater than the low level of the data signal.

4. The pixel circuit according to claim 1, wherein The scan control module includes a first switching transistor. The first current terminal of the first switching transistor receives the data signal, the second current terminal is connected to the second terminal of the memory, and the control terminal receives a scan signal. The light-emitting module includes a current source and the light-emitting element. The current source is connected between the memory and the light-emitting element, or the current source is connected between the power supply and the memory. The control terminal of the current source receives a reference signal, the second terminal of the light-emitting element receives a common voltage, and the first terminal of the memory is connected to the power supply. When the scan signal is valid, the data signal is written into the memory. When the scan signal is invalid, the power supply drives the light-emitting element through the memory. The voltage value of the power supply is higher than the low level of the data signal and lower than the high level of the data signal.

5. The pixel circuit according to claim 1, wherein, The scan control module includes a selector. The first terminal of the selector receives the data signal, the second terminal is connected to the second terminal of the memory, and the first terminal of the memory receives a scan signal. The light-emitting module includes a current source and the light-emitting element. The first current terminal of the current source is connected to the second terminal of the memory, the second current terminal is connected to the first terminal of the light-emitting element, and the control terminal receives a reference signal. The second terminal of the light-emitting element receives a common voltage. Wherein, when the absolute value of the voltage difference between the first terminal and the second terminal of the selector is greater than or equal to the threshold voltage, the selector conducts. When the scan signal is valid, the data signal is written into the memory. When the scan signal is invalid, the power supply drives the light-emitting element through the memory. The scan signal is in an effective state when it is at a low level and in an invalid state when it is at a high level. The high level of the scan signal serves as the power supply.

6. The pixel circuit according to claim 5, wherein, The selector includes a first diode and a second diode. The anode of the first diode is connected to the cathode of the second diode and receives the data signal. The anode of the second diode is connected to the cathode of the first diode and is connected to the second terminal of the memory.

7. The pixel circuit according to claim 5, wherein, The data signal is in an active state when it is at a high level, and in an inactive state when it is at a low level. The initial state of the memory is a high-impedance state. The high level of the data signal is greater than the low level of the scan signal. When the memory drives the light-emitting element, the low level of the data signal is higher than the difference between the voltage value of the second terminal of the memory and the threshold voltage, and the difference between the high level of the data signal and the threshold voltage is lower than the voltage value of the second terminal of the memory.

8. The pixel circuit according to claim 4 or 5, wherein The current value of the current source is within the range of the read current of the memory and is less than the write current of the memory.

9. The pixel circuit according to claim 4 or 5, wherein, The light-emitting module further includes a third switching transistor. The first current terminal of the third switching transistor is connected to the first terminal of the light-emitting element, the second current terminal is connected to the reference ground, and the control terminal receives a reset signal.

10. The pixel circuit according to claim 9, wherein, The memory is formed above or below the first switching transistor, the current source, and / or the third switching transistor, and the memory includes a magnetic tunnel junction.

11. A display panel, comprising the pixel circuit according to any one of claims 1 to 10.

Images