Exclusive OR-based multi-port RAM (Random Access Memory) implementation method
By building a multi-port RAM storage array based on XOR, and using XOR operations to optimize resource utilization, the problems of large resource consumption and frequency limitation are solved, efficient multi-port RAM is realized, and the data processing capabilities of network testers are improved.
Patent Information
- Application Number
- CN202510416621.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-03
- Publication Date
- 2025-07-25
AI Technical Summary
In the prior art, when building multi-port RAM, the resource consumption is high and the working frequency is limited, making it difficult to meet the needs of high-speed network testers.
By interactively obtaining the target port information, a storage array composed of multiple BRAMs is built, and an independent write bank is configured for each write port. The data write operation is performed at the time of writing using the XOR operation, and the XOR operation is performed on all write banks during reading to obtain read data.
It realizes efficient and low resource occupancy of multi-port RAM, improving data reading efficiency and system performance.
Smart Images
Figure CN120375876A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of storage technology, and in particular to a method for realizing a multi-port RAM based on XOR. Background Art
[0002] In network testers, FPGA is often used to implement message jump calculation. For systems with port rates below 200Gbps, dual-port RAM is usually used, that is, a RAM with one read port + one write port (represented as 1R1W) to implement jump calculation. When the port rate is increased to 400Gbps or even 800Gbps, since one clock cycle needs to process more than two messages, 2R2W or even 4R4W RAM is required to meet the jump calculation requirements. However, the Block RAM (BRAM) inside the FPGA usually has only two ports, so a special method must be used to build a multi-port memory.
[0003] To implement multi-port RAM, traditional methods include: using pure logic unit implementation of registers + lookup tables, which consumes a large amount of logic resources as the memory depth increases and limits the maximum operating frequency; running the internal clock of the multi-port RAM at several times the external clock, but for high-speed logic, the clock frequency is already high, and running at 2 times the frequency may exceed the maximum frequency limit of the FPGA chip; using a set of RAM arrays + the latest written data tags, which requires additional resources to store tags and perform multiplexing on the read data. As the memory depth increases, the resource overhead and multiplexer complexity increase significantly. Summary of the invention
[0004] The present invention provides a method for realizing a multi-port RAM based on XOR, so as to solve the technical problems of large resource consumption and limited operating frequency in the prior art, and achieve the technical effect of a multi-port RAM with high efficiency and low resource occupation.
[0005] The present invention provides a method for realizing a multi-port RAM based on XOR, comprising: Interactively obtain target port information, including write port quantity, write port address, read port quantity, and read port address.
[0006] According to the target port information, a storage array consisting of a plurality of BRAMs is constructed, wherein each write port corresponds to a group of independent write banks.
[0007] When data is written through any write port, the write port address and the write data are stored for one clock cycle, an XOR operation is performed in the current clock cycle according to a first preset rule, and data writing is performed according to the XOR operation result.
[0008] When reading data through any read port, perform an exclusive OR operation on all write banks in the storage array based on a second preset rule to obtain the read data.
[0009] In a feasible implementation manner, according to the target port information, construct a storage array composed of multiple BRAMs, including: Analyze the target port information, and extract the number of write ports m and the number of read ports n, where m ≥ 2 and n ≥ 2.
[0010] Discriminate the consistency between the write port address and the read port address, and according to the discrimination result of the consistency, call the storage array construction rule to construct the storage array.
[0011] In a feasible implementation manner, according to the discrimination result of the consistency, call the storage array construction rule to construct the storage array, including: If the discrimination result of the consistency shows that the addresses of the corresponding write port and read port are different, then each write bank corresponding to a write port contains at least (m - 1 + n) BRAMs, and the total number of BRAMs in the storage array is m * (m - 1 + n).
[0012] In a feasible implementation manner, according to the discrimination result of the consistency, call the storage array construction rule to construct the storage array, and further include: If the discrimination result of the consistency shows that the addresses of the corresponding write port and read port are the same, then each write bank corresponding to a write port contains (m - 1) BRAMs, and the total number of BRAMs in the storage array is m * (m - 1).
[0013] In a feasible implementation manner, perform an exclusive OR operation in the current clock cycle according to a first preset rule, and perform data writing according to the result of the exclusive OR operation, including: Perform an exclusive OR operation on the write data and the old data at the same position in the write banks corresponding to other write ports, where the result of the exclusive OR operation = write data ^ old data.
[0014] Write the result of the exclusive OR operation into a group of write banks corresponding to the write port address.
[0015] In a feasible implementation manner, when reading data through any read port, perform an exclusive OR operation on all write banks in the storage array based on a second preset rule to obtain the read data, including: Obtain the old data at the same position in the write banks corresponding to other write ports and the result of the exclusive OR operation at the same position in a group of write banks corresponding to the write port address.
[0016] Perform an inverse operation based on the exclusive OR operation on the old data and the result of the exclusive OR operation, and output the result of the inverse operation as the read data, where the result of the inverse operation = the result of the exclusive OR operation ^ the old data.
[0017] In a feasible implementation manner, if it is detected that the current read port address is the same as the stored write port address, and the timing is within one clock cycle after writing, the stored write data is directly output to the read port through a through circuit.
[0018] In summary, the present invention discloses a method for implementing a multi-port RAM based on exclusive OR, including: interactively obtaining target port information, where the target port information includes the number of write ports, write port addresses, the number of read ports, and read port addresses; constructing a storage array composed of multiple BRAMs according to the obtained target port information, and configuring a corresponding independent write bank for each write port; when writing data to any write port, storing the write port address and the written data for one clock cycle, and performing an exclusive OR operation within the current clock cycle according to a first preset rule, and completing the data writing operation according to the exclusive OR result; when reading data from any read port, performing an exclusive OR operation on all write banks in the storage array according to a second preset rule to obtain the corresponding read data. The method for implementing a multi-port RAM based on exclusive OR disclosed by the present invention solves the technical problems of large resource consumption and limited working frequency, and achieves the technical effects of an efficient and low-resource multi-port RAM. Description of the Drawings
[0019] Figure 1 is a schematic flowchart of a method for implementing a multi-port RAM based on exclusive OR according to the present invention.
[0020] Figure 2 is a schematic diagram of constructing a storage array in a method for implementing a multi-port RAM based on exclusive OR according to the present invention.
[0021] Figure 3 is another schematic diagram of constructing a storage array in a method for implementing a multi-port RAM based on exclusive OR according to the present invention. Detailed Embodiments
[0022] The above technical solutions will be described in detail below in combination with the drawings of the specification and specific embodiments to better understand the above technical solutions. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments of the present invention. It should be understood that the present invention is not limited to the example embodiments for explaining the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention. In addition, it should be noted that for the sake of description, only parts related to the present invention are shown in the drawings rather than all.
[0023] Embodiment Figure 1 Figure 1 is a schematic flowchart of a method for implementing a multi-port RAM based on exclusive OR according to the present invention. Among them, the method for implementing a multi-port RAM based on exclusive OR includes: Interactively obtain target port information, including the number of write ports, write port addresses, the number of read ports, and read port addresses.
[0024] Specifically, first, obtain target port information through user interaction or system configuration to clarify the specific parameters of the write ports and read ports of the multi-port RAM, providing a basis for the subsequent construction of the storage array. Among them, the write ports are used to write data into the RAM, and the read ports are used to read data from the RAM. These parameters determine the scale and structure of the multi-port RAM and are the basis for constructing the storage array.
[0025] For example, in a high-speed network tester, if it is necessary to simultaneously process the write and read operations of multiple data streams, 2 write ports and 2 read ports may be set, and each port corresponds to a different address range.
[0026] Construct a storage array composed of multiple BRAMs according to the target port information, where each write port corresponds to a group of independent write banks.
[0027] Specifically, BRAM (Block RAM) is a storage module inside the FPGA, which has the characteristics of high speed and configurable. The storage array refers to a storage structure formed by arranging and combining multiple BRAMs according to certain rules, used to implement the function of the multi-port RAM. The write bank refers to a group of BRAMs corresponding to each write port, used to store the data written by the write port.
[0028] In some embodiments, constructing a storage array composed of multiple BRAMs according to the target port information includes: Analyze the target port information, extract the number of write ports m and the number of read ports n, where m≥2 and n≥2; determine the consistency between the write port address and the read port address, and according to the consistency determination result, call the storage array construction rule to construct the storage array.
[0029] Specifically, according to the obtained target port information, analyze the number of write ports m and the number of read ports n, where m≥2 and n≥2; then, determine whether the write port address is consistent with the read port address. If they are consistent, that is, the determination result shows that the addresses of the write port and the read port are the same, because the read port can directly access the BRAM with the same address in the write bank for reading without the need to add additional BRAMs to support the read operation. Correspondingly, if they are inconsistent, additional BRAMs need to be added accordingly to ensure readability.
[0030] In some implementations, according to the consistency discrimination result, a storage array construction rule is called to construct the storage array, including: If the consistency discrimination result shows that the addresses of the corresponding write port and read port are different, then each write bank corresponding to a write port includes at least (m - 1 + n) BRAMs, and the total number of BRAMs in the storage array is m * (m - 1 + n).
[0031] Specifically, as Figure 2 shown, if the consistency discrimination result shows that the addresses of the corresponding write port and read port are different, then each write bank corresponding to a write port includes at least (m - 1 + n) BRAMs, and the total number of BRAMs in the storage array is m * (m - 1 + n). For example, for a 2R2W RAM, the number of write ports m = 2, the number of read ports n = 2. If the addresses of the write port and the read port are different, then each write bank corresponding to a write port contains (2 - 1 + 2) = 3 BRAMs, and the total number of BRAMs is 2 * (2 - 1 + 2) = 6.
[0032] Specifically, at this time, the above m * (m - 1 + n) BRAMs all operate in the SDPRAM mode, that is, one port can only read, one port can only write, and each port has an independent address.
[0033] In some implementations, according to the consistency discrimination result, a storage array construction rule is called to construct the storage array, and it further includes: If the consistency discrimination result shows that the addresses of the corresponding write port and read port are the same, then each write bank corresponding to a write port contains (m - 1) BRAMs, and the total number of BRAMs in the storage array is m * (m - 1).
[0034] Specifically, as Figure 3 shown, if the consistency discrimination result shows that the addresses of the corresponding write port and read port are the same, then each write bank corresponding to a write port contains (m - 1) BRAMs, and the total number of BRAMs in the storage array is m * (m - 1). For example, for a 2R2W RAM, the number of write ports m = 2. If the addresses of the write port and the read port are the same, that is, the old data is read first and then new data is written to the same address. Among them, each write port requires a write bank. Since the read and write addresses are equal, the read port does not require a separate column of RAM to implement the read operation. Then each write bank corresponding to a write port contains (2 - 1) = 1 BRAM, and the total number of BRAMs is 2 * (2 - 1) = 2.
[0035] Specifically, at this time, the above-mentioned m*(m - 1) BRAMs all operate in the TDPRAM mode. Both ports can be read and written, and each port has an independent address, which is shared by reading and writing. In other words, for each TDPRAM, one port first reads the old data and then writes the new data, and the other port is only used to read the old data.
[0036] Through the above-mentioned method of constructing the storage array, the number and arrangement of BRAMs can be flexibly adjusted according to different port configurations, effectively utilizing the resources of the FPGA. At the same time, by taking the address consistency of the write port and the read port as the basis for the construction rule, the storage structure is further optimized, unnecessary resource waste is reduced, and the efficiency and performance of the system are improved.
[0037] When writing data through any write port, the write port address and the write data are registered for one clock cycle, an exclusive OR operation is performed within the current clock cycle according to the first preset rule, and data writing is performed according to the result of the exclusive OR operation.
[0038] Specifically, registering means temporarily storing the data in a register and then processing it after delaying for one clock cycle. Since the exclusive OR design requires the read operation to precede the write operation, the write port address and data need to be registered and delayed for one clock cycle. During this period, an internal read operation is performed using the write address.
[0039] Specifically, the first preset rule refers to the rule of performing an exclusive OR operation on the write data and the old data at the same position in the write bank corresponding to other write ports when writing data. Among them, the exclusive OR operation is a logical operation, and its result is 1 when the two inputs are different and 0 when they are the same.
[0040] In some embodiments, performing an exclusive OR operation within the current clock cycle according to the first preset rule and performing data writing according to the result of the exclusive OR operation includes: Performing an exclusive OR operation on the write data and the old data at the same position in the write bank corresponding to other write ports, where the result of the exclusive OR operation = write data ^ old data; writing the result of the exclusive OR operation into a group of write banks corresponding to the write port address.
[0041] Specifically, according to the first preset rule, an exclusive OR operation is performed on the write data and the old data at the same position in the write bank corresponding to other write ports. For example, for write port 0, the newly written data WR0 (write data) is exclusive ORed with the old data (OLD_DATA) at the same position in the write bank corresponding to write port 1, resulting in: WR_DATA = WR0 ^ OLD_DATA, and further WR_DATA is written into the write bank corresponding to write port 0, where WR_DATA is the result of the exclusive OR operation.
[0042] When reading data through any read port, perform an exclusive OR (XOR) operation on all write banks in the storage array based on a second preset rule to obtain the read data.
[0043] Specifically, the second preset rule refers to the rule of performing an XOR operation on all write banks in the storage array to obtain the read data when reading data. The inverse operation refers to the process of restoring the original written data by performing an XOR operation again on the old data and the XOR operation result.
[0044] In some embodiments, when reading data through any read port, performing an XOR operation on all write banks in the storage array based on a second preset rule to obtain the read data includes: Obtain the old data at the same position in the write banks corresponding to other write ports and the XOR operation result at the same position in a group of write banks corresponding to the write port address; perform an inverse operation based on the XOR operation on the old data and the XOR operation result, and output the inverse operation result as the read data, where the inverse operation result = the XOR operation result ^ the old data.
[0045] Specifically, when reading data through any read port, first obtain the old data at the same position in the write banks corresponding to other write ports and the XOR operation result at the same position in a group of write banks corresponding to the write port address. Then, perform an inverse operation based on the XOR operation on the old data and the XOR operation result, and output the inverse operation result as the read data.
[0046] For example, for read port 0, obtain the old data (OLD_DATA) at the same position in the write bank corresponding to write port 1 and the XOR operation result (WR_DATA) at the same position in the write bank corresponding to write port 0, and perform an inverse operation to obtain the read data (RD0): RD0 = WR_DATA ^ OLD_DATA. Among them, since the XOR operation result (WR_DATA) is obtained by performing an XOR operation on the write data (WR0) and the old data (OLD_DATA), according to the commutative law and associative law of the XOR operation, it can be obtained that: (WR0 ^ OLD_DATA) ^ OLD_DATA = WR0.
[0047] Furthermore, the above process achieves the technical effect of restoring the last written data (WR0) without the need for the latest data marker and multiplexer, improving the efficiency and reliability of the read operation.
[0048] In some embodiments, if it is detected that the current read port address is the same as the stored write port address and the timing is within one clock cycle after writing, directly output the stored write data to the read port through a through circuit.
[0049] Specifically, if it is detected that the current read port address is the same as the stored write port address and the timing is within one clock cycle after writing, the stored write data can be directly output to the read port through a through-circuit. The through-circuit is a special circuit design used to directly transfer the write data to the read data port under specific conditions without going through a complex reading process.
[0050] The design of the through-circuit ensures that when reading a location in the next clock cycle after writing to the same location, the latest written data can be directly obtained, improving the real-time performance and accuracy of data reading, and further enhancing the performance and reliability of the system.
[0051] In summary, the method for implementing a multi-port RAM based on exclusive OR provided by the present invention has the following technical effects: Obtain target port information through interaction, where the target port information includes the number of write ports, write port addresses, the number of read ports, and read port addresses; construct a storage array composed of multiple BRAMs according to the obtained target port information, and configure a corresponding independent write bank for each write port; when writing data to any write port, store the write port address and the written data for one clock cycle, and perform an exclusive OR operation within the current clock cycle according to the first preset rule, and complete the data writing operation according to the exclusive OR result; when reading data from any read port, perform an exclusive OR operation on all write banks in the storage array according to the second preset rule to obtain the corresponding read data, thereby achieving the technical effects of an efficient and low-resource multi-port RAM.
[0052] It should be understood that the disclosed embodiments of the present invention and the above descriptions enable those skilled in the art to implement the present invention using the present invention. At the same time, the present invention is not limited to the above-mentioned part of the embodiments. It should be understood that those of ordinary skill in the art can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included in the protection scope of the present invention.
Claims
1. A method for implementing a multi-port RAM based on exclusive OR, characterized in that, The method comprises: Interactively obtain target port information, including write port quantity, write port address, read port quantity, and read port address; According to the target port information, a storage array consisting of a plurality of BRAMs is constructed, wherein each write port corresponds to a set of independent write banks; When writing data through any write port, the write port address and the write data are stored for one clock cycle, an XOR operation is performed in the current clock cycle according to a first preset rule, and data writing is performed according to the XOR operation result; When data is read through any read port, an XOR operation is performed on all write banks in the storage array based on a second preset rule to obtain read data.
2. The method for implementing a multi-port RAM based on exclusive OR as claimed in claim 1, wherein According to the target port information, a storage array consisting of a plurality of BRAMs is constructed, including: Parse the target port information and extract the write port number m and the read port number n, where m≥2 and n≥2; The consistency between the write port address and the read port address is determined, and according to the consistency determination result, a storage array construction rule is called to construct the storage array.
3. The implementation method of a multi-port RAM based on exclusive OR according to claim 2, characterized in that According to the consistency determination result, calling a storage array construction rule to construct the storage array includes: If the consistency determination result shows that the addresses of the corresponding write port and read port are different, the write bank corresponding to each write port contains at least (m-1+n) BRAMs, and the total number of BRAMs in the storage array is m*(m-1+n).
4. A method for implementing a multi-port RAM based on exclusive OR as claimed in claim 3, wherein, According to the consistency determination result, calling a storage array construction rule to construct the storage array further includes: If the consistency determination result shows that the addresses of the corresponding write port and read port are the same, then the write bank corresponding to each write port includes (m-1) BRAMs, and the total number of BRAMs in the storage array is m*(m-1).
5. The method for implementing a multi-port RAM based on exclusive OR according to claim 4, wherein Performing an XOR operation in the current clock cycle according to a first preset rule, and performing data writing according to the XOR operation result, including: Perform an XOR operation on the write data and the old data at the same position in the write bank corresponding to the other write ports, wherein the XOR operation result = write data ^ old data; The XOR operation result is written into a set of write banks corresponding to the write port address.
6. The method for implementing a multi-port RAM based on exclusive OR as claimed in claim 5, wherein When reading data through any read port, performing an XOR operation on all write banks in the storage array based on a second preset rule to obtain read data includes: Obtain the XOR operation result of the old data at the same position in the write bank corresponding to other write ports and the same position in a group of write banks corresponding to the write port address; An inverse operation based on the XOR operation is performed on the old data and the XOR operation result, and the inverse operation result is output as the read data, wherein the inverse operation result=the XOR operation result^old data.
7. The method for implementing a multi-port RAM based on exclusive OR according to claim 6, characterized in that The method further includes: if it is detected that the current read port address is the same as the stored write port address, and the timing is within a clock cycle after writing, then the stored write data is directly output to the read port through a pass-through circuit.