Memory with variable access granularity

Abstract

Memory with variable access granularity is disclosed. An integrated circuit memory component receives a first column access command identifying a first amount of data and a second column read command identifying a second amount of data comprised of data bits that do not exceed half of the first amount of data, as part of respective first and second memory read transactions. In response to receiving the first column access command, the integrated circuit memory component transmits a first amount of data as N parallel bit serial data signals over N external signaling links. In response to receiving the second column access command, the integrated circuit memory component transmits a second amount of data as M parallel bit serial data signals over M of the N external signaling links, where M is less than N.

Description

[0001] This application is a divisional application of a Chinese patent application with international application number PCT / US2020 / 016767, international filing date February 5, 2020, national application number 202080013731.3, and invention title "Memory with Variable Access Granularity". Technical Field

[0002] The present disclosure generally relates to data processing, and more particularly, to memory systems and their components. Brief Description of the Drawings

[0003] Various embodiments disclosed herein are shown by way of example and not limitation in the figures of the accompanying drawings, in which like reference numerals represent like elements, and in which:

[0004] Figure 1 An embodiment of a dual-channel memory component is shown that can be accessed in either of at least two transaction modes with different access granularities;

[0005] Figure 2 More details regarding transitions between the amount and parsing modes of operation are shown;

[0006] Figure 3 An embodiment of a sub-column decoder is shown that can be used to implement the Figure 2 sub-column decoder shown;

[0007] Figure 4 Exemplary row and column command packets are shown that can be used to specify sub-row activation and sub-column access, respectively, during parsing mode access;

[0008] Figure 5 An exemplary configuration register is shown that can be programmed in response to memory controller instructions and configuration data to configure the operating mode of a variable access granularity memory component;

[0009] Figure 6 An exemplary timing diagram is shown that contrasts with the amount and parsing mode operations described with reference to Figures 1 to 4 ;

[0010] Figure 7 An exemplary memory channel is shown having memory banks organized in memory array mats (mats);

[0011] Figure 8 An embodiment of a memory cell mat is shown that can be used to implement a mat in the mat-based bank architecture of Figure 7 ; and

[0012] Figure 9An alternative embodiment of a dual-channel, variable-granularity memory component having a circuit arrangement that supports merge body operations is shown. Detailed Description

[0013] In various embodiments herein, a memory controller and a memory component exchange data with variable granularity according to programming settings and / or granularity specifications. In multiple embodiments, a memory component having a native read / write data transfer granularity includes circuitry that supports partial data transfers (i.e., data amounts that are a fraction of the native-sized data amount), thereby achieving improved access efficiency (e.g., higher access energy / bit) in applications where relatively small, differently located data amounts need to be accessed. In other embodiments, two or more sets of memory banks accessed via respective / separate memory channels are accessed via a shared channel - in effect, logically merging these separate memory banks into a larger unified group and thus correspondingly reducing the amount of data that must be retrieved in each memory bank access to maintain peak data throughput. These and other features and embodiments will be discussed in more detail below.

[0014] Figure 1 An embodiment of a dual-channel memory component 100 is shown that can be accessed using either of at least two transaction modes having different access granularities: bulk mode access having a relatively coarse native granularity and parse mode access having a relatively fine (smaller amount of data) granularity. In the example described, the memory component 100 includes two identically implemented and independently operable / configurable memory channels 101 and 103 (channel A and B, which can in essence be two memory components implemented either in a single integrated circuit die or in respective dies of a multi-die integrated circuit package), such that for example a transaction described for channel A applies equally to channel B. In other embodiments, particularly where the two memory channels can operate in a merged mode (i.e., increasing the effective bank count and thus reducing the data transfer granularity required in sequential bank accesses to maintain peak data throughput), the memory channels 101 and 103 can be implemented separately.

[0015] In Figure 1 the example, each memory channel 101, 103 includes 16 memory banks 105, each bank having 2 14 rows (107) of memory cells, each row having 2 6 columns of memory cells, and each column having 2 8A memory cell and a bidirectional 16-bit data signaling interface 109. During burst mode data transfer, the data signaling interface 109 ("data interface" or "DQ interface") outputs / receives 16 bits simultaneously (in parallel) via 16 external data links (DQ) during each half cycle of the data clock signal DCK, and can thus output / receive an entire 256-bit data column over an "inter-burst interval" of 8 DCK cycles - two bits per link per DCK cycle times 8 DCK cycles times 16 DQ links.

[0016] The command interface 111 samples the command / address (CA) bits transmitted on the CA signaling path in response to consecutive rising / falling or falling / rising edges of the system clock signal (CK), such that in the illustrated 11-bit wide example, a 22-bit command / address packet is received every CK cycle. In Figure 1 the embodiment, the system clock period is four times the data clock period (t CK = 4t DCK ), such that two command / address packets can be received every 8t DCK burst mode data inter-burst interval.

[0017] The memory cells that make up the memory row 107 are single-bit dynamic random access memory cells accessed in two phases - a row activation phase (in response to a row activation CA packet), in which the data stored in the memory cell row or "data page" specified by the address is transferred to the sense amplifier bank 113, and a column access phase (in response to a column access CA packet), in which the address-selected data column within the sense amplifier bank 113 is output (column read operation, outputting "read" data) or overwritten with a similar amount of "write" data received via the data signaling interface 109. Since the data page remains resident and accessible within the sense amplifier bank 113 (or "page buffer") until the sense amplifier bank is precharged (i.e., refreshed or "unlocked" in preparation for a subsequent row activation), the principle of spatial and temporal locality can be exploited to perform multiple column access operations per row activation.

[0018] All of the above implementation details—the number of banks, rows, and columns, data and CA interface sizes, data burst sizes, CA group sizes, relative data and system clock rates, etc.—as well as those details discussed below regarding resource timing constraints, clock frequencies, time intervals, etc. are presented in this document for illustrative purposes only. In alternative embodiments, any one or all of these implementation details may be changed. Additionally, while it is assumed herein that the memory component 100 (and the alternative embodiments discussed below) has a DRAM core, in alternative variable access granularity memory embodiments, various other core storage technologies (e.g., flash memory, static random access memory, phase change memory, magnetoresistive memory, etc.) may be deployed instead of or in addition to DRAM.

[0019] Still referring to Figure 1 , the system and data clock frequencies associated with various resource timing constraints imply control sequences for sustained peak data throughput (i.e., maximum memory bandwidth). For example, repeated row activation operations targeting the same memory bank are constrained by the row cycle time (t RC ), assuming optimal in-bank access, the row cycle time implies that the data transfer interval per activation of t RC is divided by the memory bank count. In a 16-bank memory channel 101, for example, a 32 nS t RC interval allows 2 nS for data read from each memory bank. Thus, assuming a 0.125 nS t DCK (data clock period) and double data rate transmission of two bits per link per t DCK , it provides time for two 16-bit data transmissions on each DQ link of each bank; the time for two 256-bit data transmissions on a 16-bit wide data interface 109, and thus the average of two column access operations per bank (i.e., per open page (activated row) within that bank). Put another way, peak data throughput with balanced bank access (i.e., no idle time on the DQ links and accessing all banks at substantially the same rate) requires that each row activation transfer 512 bits (64 bytes (64B)) of data to / from a given memory channel—that is, a 64-byte data granularity per row activation and a 32-byte data granularity per column read / write operation.

[0020] Still referring to Figure 1, The burst mode operation reflects the relatively coarse access granularity described above, with each column access transferring a full 32-byte data burst (64 bytes are activated per row and 32 bytes are accessed per column), and on average one 64-byte burst is transferred per row activation (two column operations are activated per row). In applications where it is necessary to access relatively small, less localized data units relatively frequently (i.e., a relatively small amount of data that may be scattered across different rows of a given memory bank), the coarse burst mode access granularity results in significant energy / bit loss because the majority (or at least a substantial portion) of the read / write data is unnecessarily retrieved (memory read) or overwritten (write). In these cases, the memory component 100 or one or both of its memory channels can be switched to the parse mode - either dynamically in response to an input command or programmatically in response to a register setting - to achieve a finer-grained data access and thereby avoid wasteful retrieval and rewriting of unnecessary data. In the particular embodiment shown, the parse mode data access is scaled both in row activation and column access operations, as shown at 121 (e.g., from 16 Kb to 4 Kb), reducing the amount of activated data (and thus the effective data page size) by a factor of 4, and also reducing the column read / write data access by a factor of 4, as shown at 123 (e.g., from 256 bits to 64 bits). These 4:1 scaling factors are advanced in many of the embodiments described herein - in all cases, larger or smaller granularity scaling factors can be applied, and the memory component and control component can support multiple mode programming and / or command-specified scaling factors. In Figure 1 the embodiment, the parse mode column data amount is reduced (i.e., by a factor of 4 in the depicted example) in part by scaling the width of the data interface 109 as shown at 125. In cases where the transition between burst and parse modes is performed dynamically (i.e., e.g., on the fly via a command code), in the 4:1 burst reduction example shown, a proportional number of signaling links and corresponding signaling circuits within the DQ interface are unused / disabled - 12 out of 16 links and signaling circuits.

[0021] Figure 2 Details of the transition between burst and parse operating modes are illustrated. In the example described, the sub-column enable signal (sce) is de-asserted (sce = 0) during burst mode memory access and asserted (sce = 1) during parse mode access. First referring to the burst mode details at 151, a full data row (containing 2 8 data units of 2 6 columns, thus 2 14Rows of data bits 'n') are transferred to the sense amplifier bank (SA bank), and then a single 256-bit data column is selected during the column access operation. More specifically, the column decoding logic 153 performs a 64:1 multiplexing operation to transfer the entire 256-bit data column between one of the 64 sense amplifier groups (c00 - c63) and the selected one of the 256 column input / output (I / O) lines 155, where the data is multiplexed from the selected sense amplifier group onto the column I / O line 155 during the column read operation and demultiplexed from the column I / O line 155 into the selected sense amplifier group during the column write operation. Within the data interface 157, each of the 16 16-bit subgroups of the column I / O lines is coupled to a corresponding serializer / deserializer circuit 159, which serializes the outgoing (read) data for transmission as a stream of 16 sequential bits via the corresponding DQ pad 161 (and an external DQ signaling link), and conversely, deserializes an incoming stream of 16 write data bits (i.e., arriving via the corresponding DQ link / DQ pad) into a parallel 16-bit value on the subject column I / O line.

[0022] Turning now to the parsing mode operation shown in 181, during the row activation operation, a two-bit sub-row address "SR[1:0]" is applied to more finely parse the activated memory cells into one of four sub-rows within the row specified by the row address. In one embodiment, for example, the sub-row address is applied to (i) combine with the row address to select (and enable access from) one of the four sub-row memory cells within the row of memory cells specified by the row address, and (ii) is applied to the sense amplifier bank (SA bank) to enable data latching in one of the four groups of sense amplifiers (one of the four "sub-pages") corresponding to the sub-row selected for data transfer. By this operation, the contents of the three unselected sub-rows of memory cells are not disturbed, and the three unselected sub-pages within the sense amplifier bank remain on standby and do not require precharging - "sub-row activation", which substantially reduces the power consumption consumed by activating the entire row of memory cells.

[0023] In one embodiment, the sub-row organization is layered on top of the column organization within the memory cell array such that activation of a given sub-row constitutes activation of the corresponding portion (e.g., one of four) of the data in each column within the memory row selected by the address. Still referring to Figure 2, for example, activation of the parsing mode causes activation of cell groups 0, 1, 2, or 3 within each of the 64 column memory cells in an object memory row (activation of cell group 1 is shown by shading), and transfer of the contents of the activated cell groups within each column to the corresponding sense amplifier group. Since any one of the four cell groups can be activated in each column (according to sub - row address SR[1:0]), the data from the activated cell group is here called a “sub - column” of the data -- in this case a total of 64 bits (one - quarter of the 256 - bit mode data column).

[0024] Because the sense amplifiers corresponding to unselected sub - columns remain unlatched (ready for subsequent activation) during sub - row activation, column access after sub - row activation is restricted to the activated data sub - columns. Thus, the sub - column address value (SC[1:0]) provided to decode the column to a particular one of the 64 activated data sub - columns has a one - to - one correspondence (e.g., matches or uniquely maps to) with the sub - row address value. As described below, this correspondence has implications for the source of the sub - column address, enabling the sub - column address to be derived from the sub - row address within the memory component (e.g., a copy of the sub - row address is stored with the sub - row activation and subsequently provided to the column decoding logic 153 as the sub - column address value), or for the memory control component to provide the sub - column address in the required correspondence with the sub - row activation. In either case, when the sub - column enable signal is asserted (sce = 1), the sub - column address is applied within the sub - column decoder 187 (i.e., within the column decoding logic 153) to enable 4:1 decoding of the entire 256 - bit data column output by the 64:1 column decoder 185. In the example shown, the column address selects a 64 - bit data sub - column (i.e., sub - column ‘1’) within the data column and is passed to the four enabled I / O circuits 159 within the DQ interface 157. Those enabled I / O circuits (i.e., the shaded instances) output the corresponding 16 - bit portions of the 64 - bit data sub - column as a serial bit stream via the corresponding DQ pads 161 (i.e., the pads labeled DQ0, DQ1, DQ2, and DQ3 in the example shown).

[0025] Figure 3 is shown for use in implementing Figure 2Embodiment of the 4:1 sub-column decoder 201 of the sub-column decoder 187. As shown, selector circuits 203 are coupled between corresponding groups of column I / O lines 155 and data I / O circuits 159 - in this example, four selector circuits, each selector 203 being coupled between a corresponding group of 64 column I / O lines (four groups of 16 column I / O lines per selector) and one of four I / O circuits 159 coupled to pads DQ0 - DQ3. Referring to the detailed view 209 of selector circuit 203 (other selector circuits may be implemented identically), the sub-column enable signal (sce) is matched with sub-column address bits SC[0] and SC[1] in gates 211 and 213 respectively to convey a two-bit select signal 214 to multiplexer 215, in response to which multiplexer 215 switchably couples one of four groups of 16 column I / O lines (within the total 64 column I / O lines coupled to the selector) to the 16 lines (217) extending between the selector and the corresponding data I / O circuit. By this arrangement, when the sub-column enable signal is asserted, selector 203 couples one of the four groups of 16 column I / O lines to a corresponding one of the data I / O circuits 159 according to the sub-column address, thereby routing sub-column read data to the data I / O circuit for bit-serial transmission on the corresponding signaling link and routing sub-column write data received / parallelized by the data I / O circuit to the sub-column address-specified portion of the data sub-page (i.e., overlaying data within the sense amplifier containing the data sub-page). When the sub-column enable signal is de-asserted (e.g., logic low), the select signal 214 is driven low (i.e., '00') by gates 211 and 213 to select the 16 column I / O lines that form the corresponding I / O circuit 159 of the component dedicated to the 256 column I / O lines within full-quantity mode access. As shown, the remaining three groups of 16 column I / O lines are directly coupled to the corresponding I / O circuits 159 to convey read data to and conduct write data from them during quantity mode access.

[0026] Figure 4Exemplary row and column command packets 251 and 253 are shown, which can be used to specify sub - row activation and sub - column access respectively during parse - mode access. In one embodiment, relative to a conventional implementation, the command signaling interface is widened by one or more bits (e.g., from 10 bits to 11 bits as shown or 12 bits) to transmit additional address bits that allow sub - row activation and sub - column decoding. In other embodiments, unused bits in a pre - existing command packet protocol can be commandeered to transmit the additional address bits, avoiding CA width expansion. In implementations that support distinguishing between the bulk - mode and parse - mode operations of commands (i.e., specified via command encoding between bulk - mode and parse - mode access), the increased CA interface width and / or the unused bits within the pre - existing command protocol can provide headroom (extra command codes) for this distinction. For example, the memory control component can drive other unused bits within the row activation command packet (or additional bits passed via increased interface width) high or low to distinguish between parse and bulk - mode access.

[0027] Still referring to Figure 4 , each command / address packet (251 or 253) is sampled in response to two consecutive system clock edges (e.g., first rising then falling or vice versa), and thus, in the 11 - bit CA interface width example, contains 22 command / address bits. Assuming Figure 1 the exemplary memory configuration shown (2 4 individuals per channel, 2 14 rows per individual, 2 6 columns per row), each activation command packet 251 transmits a 1 - bit or 2 - bit activation command code, a 4 - bit bank address, a 14 - bit row address, and a 2 - bit sub - row address. In cases where a single bit is sufficient to encode the activation command (e.g., it is sufficient to assert a predetermined bit within the command packet, where the activation command constitutes the only bank - specific row command), the address and command bits total 21 out of the 22 available CA packet bits, leaving a spare bit available to transmit additional sub - row address or bank address information (e.g., indicating merged bank / channel operations as described below) or to distinguish between bulk - mode and parse - mode row activation.

[0028] In the column command packet 253, a multi - bit column command code (specifying the columns to be read in the shown example) is accompanied by a 4 - bit bank address, a 6 - bit column address, and a 2 - bit sub - column address. The relatively small address bit count (12 bits as opposed to 20 bits in the row command packet) leaves room to encode a relatively large number of column commands (e.g., read and write commands distinguished by various pre - charge options and bit - masking options) and one or more bits to specify whether a given read or write access is performed in bulk - mode or parse - mode.

[0029] As described above, in parse mode access, the sub - row and sub - column addresses can be the same (or have a one - to - one correspondence) such that, in at least some embodiments, the sub - row address provided in the parse mode row activation CA packet can be temporarily stored and then applied (or used to derive the sub - column address value) as the sub - column address value during a subsequent column access -- this action avoids transmitting sub - column address bits within the column CA packet, freeing up net space for additional command discrimination or address information (including more definitive column address information). Figure 4 This sub - row storage method is conceptually illustrated. As shown, the command decoder 271 asserts the sub - address storage signal in response to decoding a parse mode row activation command (e.g., command 251), thereby strobing the accompanying sub - row address bits into the sub - column address register (SC register) 273. When a parse mode column read or write command (e.g., command 253 without sub - column address bits) is received that is directed to activate the sub - row, the contents of the sub - column address register 273 are applied to decode (select) the data sub - column.

[0030] Figure 5 An exemplary configuration register 281 (e.g., a configuration data memory, mode register, etc.) is shown, which can be programmed in response to memory controller instructions and configuration data to configure the operation mode of a variable access granularity memory component. In the described embodiment, the configuration register 281 includes bit fields for programmably selecting between bulk mode and parse mode operations (i.e., full data volume per memory access at a coarse granularity versus partial data volume per memory access at a fine granularity), for specifying the source of the sub - column address information, and for enabling or disabling bank - merge operations. In one implementation, the specification of bulk mode operation within the configuration register 281 (e.g., setting the bit “V / R” to ‘0’) allows for parse mode operation to be selected based on the command (i.e., the command code indicates whether a given memory transaction is to be executed in bulk mode or parse mode), while the parse mode specification (V / R = 1) triggers full - time parse mode operation. In cases where the data link between the memory component and the controller is limited to the parse mode data width (e.g., in Figures 1 to 3 )), parse mode operation can be specified at system initialization (i.e., programmed in register 281) such that all subsequent memory access commands (e.g., row activation, column read / write) are executed at parse mode granularity, avoiding the need to specify / discriminate parse mode operation in the command code. In an alternative embodiment, particularly in cases where the DQ link count accommodates bulk mode operation, dynamic granularity conversion (i.e., command - based selection between bulk mode and parse mode operations) can be enabled in parse mode rather than bulk mode (e.g., all memory access commands are executed in bulk mode unless the register 281 is programmed for parse mode).

[0031] Still referring to Figure 5, the sub-column address (SCA) setting within configuration register 281 indicates the source of the sub-column address bits to be applied during parse mode column read and write operations - re-apply the sub-row address bits received in the previous row activation command (e.g., the sub-row address bits stored as shown in Figure 4 ) as sub-column address bits, or receive the sub-column address bits with a separate column access command. The channel merge setting (CHM) within configuration register 281 indicates whether the individual memory channels within the main memory component (e.g., channels A and B as shown in Figure 1 ) are to be operated individually (i.e., each as an N-bank memory device) or logically combined to double the effective bank count. In the latter case (doubling (2N) the bank count), data written or read from either of the two groups of N memory banks is transmitted over a shared set of signaling links. In multiple embodiments, the channel merge (or bank-merge) mode is implemented in conjunction with parse mode operations to further reduce the per-row activation transaction granularity required for peak data throughput (i.e., as described below). Optionally, the bank-merge mode can be implemented in conjunction with burst mode operations to reduce the number of column access operations required per row activation without compromising data throughput.

[0032] Figure 6 shows a comparative reference Figures 1 to 4 to the exemplary timing diagrams of the burst and parse mode operations described. In the example shown, CA packets are sent on the multi-link command / address path (CA) and sampled in response to the rising and falling edges of the system clock signal (i.e., each CA link per system clock cycle, t CK ), while data is transmitted on the multi-link data path (DQ) and sampled / sent in response to the rising and falling edges of the data clock signal (i.e., sampled twice or bits sent every t DCK interval per DQ link). As discussed above and as shown in Figure 6 , in parse mode, wider command / address packets can be transmitted on the command / address path than in burst mode (i.e., more bits transmitted in parallel, more specifically 11 bits instead of 10 bits in the example shown) to accommodate the additional sub-row and sub-column address bits and / or additional command code bits required to specify parse mode operations. In alternative embodiments, the command / address packet width can be consistent across different granularity modes.

[0033] Referring to Figure 6 the exemplary burst mode timing shown, the row activation command received at 305 is followed after a predetermined time (i.e., RAS to CAS delay, t RCD ) by a column access command 307 pointing to the activated row, and in this example, the column read command 307 itself is followed after a predetermined read latency (t RL)Subsequently, trigger the burst data output 309 via the DQ path. Note that, like the shadow of the activation command 305, the read command 307 and the data burst 309 indicate their corresponding relationships with the same memory bank, while the unshaded activation commands, read commands, and data transfers refer to transactions within other memory banks. Assuming the 32-byte column access granularity discussed above, transmitting a data column on a 16 DQ link consumes 8t DCK Burst interval (16-bit interval (16t BIT ), each interval having 0.5t DCK Duration), thus consuming 2t CK Interval--assuming 0.5nS t CK Interval (0.125nS t DCK Interval) of 1nS data burst interval. With a 32nS row cycle time (t RC ), the per-channel-16-bank arrangement with this constraint means a 2nS data transfer window for each row activation (i.e., for peak data throughput without resource conflicts). Therefore, on average, two column access operations are activated per row. This transaction processing arrangement is shown by the activation command at 305, two corresponding column read commands 307 and 311, and two back-to-back read data bursts at 309, 313--overall, a data granularity of 64B is activated per row.

[0034] In the parse mode operation, the same general timing (32nS t RC , 0.5nS CA receive interval, 1nS column data burst) is applied, but the amount of data activated and sent / received is reduced by 4 times. That is, instead of a 32-byte column access granularity and an average granularity of 64 bytes activated per row, 8 bytes (329, 331) are transmitted per column access 327, 331 (through four links instead of 16 links), and on average 16 bytes are activated per row.

[0035] Figure 7 An exemplary memory channel 365 with memory banks 367 organized in a memory "mat" 369 array is shown. More specifically, each 256Mb bank (2 14 memory rows per bank, 2 14 bits per memory row) is organized into 1024 (32 rows and 32 columns) memory mats 369, each mat including a 512b×512b cell array, a 512-bit sense amplifier bank, sub-row decoding logic, and sub-column decoding logic. In the specific memory bank shown, the one-hot sub-row enable value "EN SR[3:0]" (e.g., one of four sub-row enable signals asserted in accordance with decoding of a two-bit sub-row address value) is applied to each of eight groups of four pads across each row of the memory bank. With this arrangement, a parsed mode memory transaction will allow row activation of one quarter of the pads 369 within an address selected pad row (i.e., a pad row containing a row of memory cells specified by the row address), with the activated pads being offset a maximum of one another within the row (i.e., every four pads activated). The one-hot sub-row enable value "EN SC [3:0]" (i.e., one of four sub-column enable signals asserted in accordance with decoding of a two-bit sub-column address field) is likewise applied to each of the eight groups of four pads making up the address select row to enable column data to be output therefrom. For bulk mode access, all four sub-row enable signals and all four sub-column enable signals are asserted to enable full bulk access (rather than fine-grained access) within the memory bank.

[0036] Figure 8 Shows the available Figure 7 A more detailed embodiment of a memory cell pad 401 implementing pad 369 within a pad-based body architecture is shown - in this case, in the context of a DRAM memory cell 403, each memory cell having an access transistor 405 and a capacitive storage element 407, although other core storage technologies may be used in alternative embodiments. As shown, the four decoded (one-hot) sub-rows enable signals (E SR [0]-EN SR [3]) is coupled to row decoding circuitry 411 within pad 401 (the other three sub-row enable signals are also coupled to row decoding circuitry 411 within pads of corresponding row distributions) and applied to row selection logic therein (conceptually depicted as logic AND gate 415 and row driver 417). Therefore, if the sub-row address provided in the resolution mode row activation corresponds to the sub-row enable signal coupled to row decoding circuitry 411 in memory cell pad 401 (i.e., is decoded to produce an assertion), and the row address is also decoded to a cell row in the pad, then the word line in pad 401 coupled to the gate of access transistor 405 in the subject memory cell row will be turned on, thereby enabling the contents of capacitive storage element 407 to drive column bit line 420. As shown, the sub-row enable signal also enables operation of sense amplifier 421 within pad 401 (which operation is also conditioned on the row address selection of the cell row within the pad) so that the sense amplifier is enabled within a portion (one of four) of the pads within a given row during row activation.

[0037] Still reference Figure 8 , four decoded sub-column enable signals (EN SC [0]-EN SC[3]) is coupled to column decoding logic (multiplexing logic) within the pad to enable selective data output from the sense amplifier bank via the pass-gate transistor 423. More specifically, if the sub-column address provided in the parse mode column access (including the sub-column address captured for later applications as sub-column selection) corresponds to the subject memory cell pad and the row address is also decoded to a cell row within the pad, the gate 425 will assert the column enable signal at the gate of the transistor 423, enabling the subject sense amplifier bank (i.e., the sense amplifier bank within the memory cell pad selected by the sub-column address) to drive the data signal onto the column data I / O line 427 and receive data from the column data I / O line 427 - transfer the read data from the sense amplifier 421 to the data I / O interface and enable writing data from the data I / O interface to overwrite the content of the sense amplifier 21 (and drive the data back to the active memory cell row 403).

[0038] Figure 9 An alternative embodiment of a dual-channel variable granularity memory component 450 is shown having circuitry to support merged-bank operations. As in the Figure 1 embodiment, each of memory channels A and B includes 15 memory banks organized in rows and columns (e.g., showing the same size row and column counts) and data and command / address signaling interfaces. To simplify the explanation of the bank-merging operation, the data interface 451 within each channel (A and B) is shown as having a 4-bit data width according to the parse mode access - additional I / O circuitry sufficient to support burst mode data transfer (e.g., 16 bits per channel) may be present within each data interface.

[0039] Still referring to Figure 9 , a channel multiplexer 455 is provided in one or both memory channels (shown only in channel A in the described embodiment) to enable read / write data transmitted through an external data path coupled to channel A to be routed to either of the channel A / B data interfaces - effectively enabling access to each of the two memory channels through a single data interface 451 and thus implementing the logical merging of two 16-bank memory channels into a single 32-bank memory channel. In one embodiment, it is set by programming (e.g., as referred to in Figure 5The “bank - merge” operation is enabled (as discussed) so that two memory channels can operate in bank - merge mode or independently (in which case, the channel multiplexer 455 statically transfers data between the external data link and the channel A data interface). In other embodiments, for example, the bank - merge operation can be dynamically selected via a command specification (i.e., the command code indicates whether a given transaction or sequence of transactions will be executed in bank - merge mode). In any case, additional memory bank address bits can be provided within the input command / address packet (e.g., widening the CA path to 12 bits if needed to accommodate the additional address bits) to support the bank - merge operation - these additional bits select between the 16 banks of channel A or the 16 banks of channel B, while the remaining 4 bank address bits are decoded within a given channel to perform row activation and column access operations. The added bank address bits, referred to here as channel select bits, are also provided to the channel multiplexer to route data to / from the selected memory channel during column access operations.

[0040] In one embodiment, the replicated command / address packet is sent simultaneously to the CA interface within each of the two memory channels with inverted channel select bits, thereby effecting a command transaction (e.g., row activation or column read or write) within one or the other memory channel. In an alternative embodiment, the two channel interfaces can be switchably coupled together during the bank - merge operation, and a bank - merge enable bit (e.g., in a programmable register or command transfer) can flip the state of the channel select signal sent to the channel B command / address interface, enabling one channel or the other to respond to otherwise shared commands.

[0041] In one embodiment, as Figure 9 shown in the timing details 471, the memory component 450 is subject to the 32nS row cycle constraint discussed above and operates at the same system and data clock rates (i.e., 2GHz system clock, 8GHz data clock). Assuming a 4 - bit resolved mode data interface width, each resolved mode column access command is followed by a corresponding 8 - byte read or write data burst (4 bits within a 16t BIT interval, thus 8 DCK cycles or two CK cycles). When the bank - merge operation is enabled, the number of banks accessible via a given memory channel doubles from 16 to 32, and peak data throughput can be achieved with a single 8B column access in each row activation within the 32 banks (i.e., no idle time on the data path) - avoiding the need for multiple column access operations per row activation, thereby further reducing the access granularity (8B instead of 16B per row activation) and improving access efficiency (e.g., reducing access energy / bit).

[0042] It should be noted that the various circuits disclosed herein can be described using computer-aided design tools and represented (or expressed) as data and / or instructions contained in various computer-readable media according to their behavior, register transfer, logic components, transistors, layout geometries, and / or other characteristics. The formats of files and other objects in which such circuit expressions can be implemented include, but are not limited to, formats that support behavioral languages such as C, Verilog, and VHDL, formats that support register-level description languages such as RTL, and formats that support geometric description languages such as GDSII, GDSIII, GDSIV, CIF, MEBES, and any other suitable formats and languages. The computer-readable media that can contain such formatted data and / or instructions include, but are not limited to, various forms of computer storage media (e.g., optical, magnetic, or semiconductor storage media, whether distributed independently in this way or stored "in situ" in an operating system).

[0043] When received within a computer system via one or more computer-readable media, such data and / or instruction-based expressions of the above circuits can be processed by a processing entity (e.g., one or more processors) within the computer system in conjunction with the execution of one or more other computer programs including, but not limited to, a netlist generation program, a placement and routing program, etc., to generate a representation or image of the physical manifestation of such circuits. Such a representation or image can thereafter be used in device manufacturing, for example, by allowing the generation of one or more masks that are used to form the various components of the circuit in a device manufacturing process.

[0044] In the foregoing description and drawings, specific terms and drawing symbols have been set forth to provide a thorough understanding of the disclosed embodiments. In some instances, the terms and symbols may imply specific details that are not required to practice those embodiments. For example, any one of a specific number of bits, signal path width, signaling, or operating frequency, etc. may be different from those described above in alternative embodiments. Additionally, the links or other interconnections between integrated circuit devices or internal circuit elements or blocks may be shown as buses or single signal lines. Each of the buses may alternatively be a single signal line, and each of the single signal lines may alternatively be a bus. Signal and signaling links, however shown or described, may be single-ended or differential. "Programming" an integrated circuit device may include, for example but not limited to, loading control values into registers or other storage circuits within the integrated circuit device in response to host instructions (and thus controlling the operational aspects of the device and / or establishing the device configuration), or by a one-time programming operation (e.g., blowing fuses within a configuration circuit during device production), and / or connecting one or more selected pins or other contact structures of the device to a reference voltage line (also referred to as a strap) to establish a specific device configuration or operational aspect of the device. A signal driving circuit is said to "output" a signal to a signal receiving circuit when the signal driving circuit asserts (or de-asserts, if expressly stated or indicated by context) a signal on a signal line coupled between the signal driving circuit and the signal receiving circuit. The term "coupled" is used herein to denote both direct connections as well as connections through one or more intermediate circuits or structures. The terms "exemplary" and "embodiment" are used to denote examples, rather than preferences or requirements. Additionally, the terms "may" and "can" are used interchangeably to denote optional (permitted) subject matter. The absence of either term should not be construed as requiring a given function or technique.

[0045] Various modifications and alterations can be made to the embodiments presented herein without departing from the broader spirit and scope of the disclosure. For example, the features or aspects of any embodiment can be combined and applied with those of any other embodiment, or instead of their corresponding features or aspects. Accordingly, the specification and drawings are to be regarded as illustrative rather than restrictive.

Claims

1. An integrated circuit memory component, comprising: a first plurality of banks corresponding to a first memory channel; a second plurality of banks corresponding to a second memory channel; and data input / output (IO) circuitry having a first data interface and a second data interface and operative to: a first IO mode in which the first data interface and the second data interface are respectively dedicated to the first memory channel and the second memory channel such that the first data interface transfers data only to / from the first plurality of banks and the second data interface transfers data only to / from the second plurality of banks, and a second IO mode in which the first data interface transfers data to / from both the first plurality of banks and the second plurality of banks and the second data interface is disabled.

2. The integrated circuit memory component of claim 1, wherein the data IO circuitry operates in the first I / O mode when a mode control value specifies the first IO mode and operates in the second IO mode when the mode control value specifies the second IO mode.

3. The integrated circuit memory component of claim 2, further comprising a programmable register for storing the mode control value.

4. The integrated circuit memory component according to claim 2, further comprising: A command / address interface for receiving a memory access command that (i) indicates first data to be transferred via the data IO circuitry and (ii) includes a field of one or more bits as the mode control value, the field specifying the first IO mode or the second IO mode regarding the transfer of the first data.

5. The integrated circuit memory component of claim 1, wherein each bank within the first plurality of banks and the second plurality of banks includes a respective read amplifier bank and a respective plurality of rows of memory cells coupled to the respective read amplifier bank.

6. The integrated circuit memory component of claim 5, wherein each memory cell within the respective plurality of rows of memory cells is a dynamic random access memory (DRAM) cell.

7. The integrated circuit memory component of claim 1, wherein the first plurality of banks includes N banks and the second plurality of banks also includes N banks such that when the data IO circuitry is operative to operate in the second IO mode, the first data interface transfers data to / from any one or more of the 2*N banks, where N is an integer greater than 1 and * represents multiplication.

8. The integrated circuit memory component of claim 1, further comprising a first command / address interface and a second command / address interface respectively corresponding to the first memory channel and the second memory channel, the first command / address interface for (i) When the data I / O circuit device is capable of operating in the first I / O mode, receiving a first memory read / write command that indicates a memory read / write operation only within the plurality of first memory banks, and (ii) when the data I / O circuit device is capable of operating in the second I / O mode, receiving a second memory read / write command that indicates a memory read / write operation within any of the constituent memory banks of the first plurality of memory banks and the second plurality of memory banks.

9. The integrated circuit memory component according to claim 8, wherein the second command / address interface comprises: A circuit device for receiving a third memory read and write command when the data I / O circuit device is capable of operating in the first I / O mode, the third memory read / write command indicating a memory read and write operation only within the second plurality of memory banks, the integrated circuit memory component further comprising: a circuit device for disabling the second command / address interface when the data I / O circuit device is capable of operating in the second I / O mode.

10. The integrated circuit memory component according to claim 9, wherein the circuitry for disabling the second command / address interface comprises: A circuit device for also disabling the second data interface when the data I / O circuit device is capable of operating in the second I / O mode.

11. A method of operation within an integrated circuit memory component having a first memory bank corresponding to a first memory channel, a second memory bank corresponding to a second memory channel, and a data input / output (I / O) circuit device having a first data interface and a second data interface, the method comprising: Operating the data I / O circuit device in a first I / O mode in which the first data interface and the second data interface are dedicated to the first memory channel and the second memory channel, respectively, such that the first digital interface transfers data only for the first plurality of memory banks, and the second data interface transfers data only for the second plurality of memory banks; And Converting the data I / O circuit device from the first I / O mode to a second I / O mode in which the second data interface is disabled and the first data interface transfers data for both the first plurality of memory banks and the second plurality of memory banks.

12. The method according to claim 11, wherein converting the data IO circuit device from the first IO mode to the second IO mode includes: Within a programmable register of the integrated circuit memory component, overwriting a first mode control value specifying the first I / O mode with a second mode control value specifying the second I / O mode.

13. The method according to claim 11, wherein converting the data I / O circuit device from the first I / O mode to the second I / O mode includes receiving a memory access command that indicates that the first data is to be transferred via the data I / O circuit device, and the memory access command includes a field of one or more bits that specify the second I / O mode regarding the transfer of the first data.

14. The method according to claim 11, wherein each memory bank within the first plurality of memory banks and the second plurality of memory banks includes a respective read amplifier bank and a respective plurality of rows of memory cells coupled to the respective read amplifier bank.

15. The method according to claim 14, wherein each memory cell within the corresponding multi-row memory cell is a dynamic random access memory (DRAM) cell.

16. The method according to claim 11, wherein: the first plurality of banks includes N banks, and the second plurality of banks also includes N banks; and converting the data IO circuitry to the second IO mode includes enabling the first data interface to transfer data to any one or more of the 2*N banks or transfer data from any one or more of the 2*N banks, where N is an integer greater than 1, and * represents multiplication.

17. The method according to claim 11, wherein the integrated circuit memory component includes a first command / address interface and a second command / address interface corresponding to the first memory channel and the second memory channel respectively, and the method further includes receiving via the first command / address interface: a first memory read / write command, the first memory read / write command indicating: while operating the data IO circuitry in the first IO mode, a memory read / write operation only within the first plurality of banks, and a second memory read / write command, the second memory read / write command indicating: after converting the data IO circuitry to the second IO mode, a memory read / write operation within any constituent bank of the first plurality of banks and the second plurality of banks.

18. The method according to claim 17, further including: receiving a third memory read / write command via the second command / address interface, the third memory read / write command indicating: while the data IO circuitry is operable to operate in the first IO mode, a memory read / write operation only within the second plurality of banks; and after converting the data IO circuitry to the second IO mode, disabling the second command / address interface.

19. The method according to claim 11, further comprising: After converting the data IO circuitry from the first IO mode to the second IO mode, converting the data IO circuitry from the second IO mode to the first IO mode includes re-enabling the second data interface.

20. A dynamic random access memory device, comprising: a first plurality of banks, each bank including a corresponding read amplifier group and a memory cell array; a second plurality of banks, each bank including a corresponding read amplifier group and a memory cell array; a programmable register for storing an input / output (IO) mode value; and data IO circuitry having a first data interface and a second data interface and being operable in any one of a plurality of different IO modes according to different instances of the IO mode value stored in the programmable register, the different IO modes including at least: a first IO mode, in which the first data interface transfers data only for the first plurality of banks, and the second data interface transfers data only for the second plurality of banks; and Second IO mode, in which the second data interface is disabled and the first data interface transfers data for both the first plurality of memory banks and the second plurality of memory banks.

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