Memory circuit and operating method thereof

Abstract

The invention relates to a memory circuit and an operating method thereof. The memory circuit includes first and second inverters and a level shifter circuit. The first inverter is coupled to a first voltage source and is configured to generate a first input signal in response to a second input signal. The level shifter circuit is coupled to the second voltage source and is configured to generate a first signal and a second signal in response to the first input signal or the second input signal. The second inverter is configured to generate a word line signal in response to the first signal. The level shifter circuit is configured to delay a leading edge of the word line signal in response to the first signal or the second signal. A delay amount of a leading edge of the word line signal is based on a voltage difference between the first power supply voltage and the second power supply voltage. The first supply voltage has a first swing. The second supply voltage has a second swing.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to a memory circuit and an operation method thereof. Background Art

[0002] The semiconductor integrated circuit (IC) industry has produced a variety of digital devices to solve problems in many different fields. Some of these digital devices, such as memory macros, are configured for data storage. As ICs become smaller and more complex, the resistance of the wires within these digital devices is also changed, thereby affecting the operating voltage of these digital devices and the overall IC performance. Summary of the Invention

[0003] According to one aspect of the present disclosure, there is provided a memory circuit, comprising: a first inverter coupled to a first voltage source and configured to generate a first input signal in response to a second input signal, the first input signal being inverted with respect to the second input signal; a level shifter circuit coupled to at least the first inverter or a second voltage source different from the first voltage source and configured to receive at least the first input signal or the second input signal and generate a first signal and a second signal in response to at least the first input signal or the second input signal; and a second inverter configured to generate a word line signal in response to the first signal; wherein the level shifter circuit is configured to delay a leading edge of the word line signal in response to at least the first signal or the second signal, the amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage and a second power supply voltage, the first power supply voltage having a first swing and the second power supply voltage having a second swing.

[0004] According to one aspect of the present disclosure, there is provided a memory circuit, comprising: a memory cell array; and a word line driver coupled to the memory cell array, the word line driver comprising: a first inverter coupled to a first voltage source and configured to generate a first input signal in response to a second input signal, the first input signal being inverted with respect to the second input signal; a level shifter circuit coupled to at least the first inverter or a second voltage source different from the first voltage source and configured to receive at least the first input signal or the second input signal and generate a first signal and a second signal in response to at least the first input signal or the second input signal; and a second inverter configured to generate a word line signal in response to the first signal; wherein the level shifter circuit is configured to delay a leading edge of the word line signal in response to at least the first signal or the second signal, the amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage and the second power supply voltage, the first power supply voltage having a first swing and the second power supply voltage having a second swing.

[0005] According to one aspect of the present disclosure, there is provided a method of operating a memory circuit, the method comprising: generating, by a first inverter, an inverted first input signal in response to a first input signal, the first input signal being inverted with respect to the inverted first input signal; generating, by a level shifter circuit, a first signal and a second signal in response to at least the first input signal or a second input signal; delaying, by the level shifter circuit, a leading edge of a word line signal in response to at least the first signal or the second signal, the amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage and a second power supply voltage, the first power supply voltage having a first swing and the second power supply voltage having a second swing; and generating, by a second inverter, the word line signal in response to the first signal, the word line signal being inverted with respect to the first signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Aspects of the present disclosure may be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of discussion clarity, the dimensions of various features may be arbitrarily increased or decreased.

[0007] Figure 1 is a block diagram of a memory circuit according to some embodiments.

[0008] Figure 2 is a circuit diagram of a memory circuit according to some embodiments.

[0009] Figure 3 is available for use according to some embodiments Figure 1Block diagram of the memory circuit in

[0010] Figure 4 is a circuit diagram of a memory circuit according to some embodiments.

[0011] Figure 5 is a timing diagram of waveforms of a memory circuit (e.g., Figure 4 the memory circuit in

[0012] Figure 6 is a circuit diagram of a memory circuit according to some embodiments.

[0013] Figure 7 is a circuit diagram of a memory circuit according to some embodiments.

[0014] Figure 8 is a timing diagram of waveforms of a memory circuit (e.g., Figure 7 the memory circuit in

[0015] Figure 9 is a timing diagram of waveforms of a memory circuit (e.g., Figure 4 , Figure 6 or Figure 7 the memory circuit in

[0016] Figure 10 is a flowchart of a method of operating a circuit according to some embodiments. DETAILED DESCRIPTION

[0017] The following disclosure provides different embodiments or examples for implementing the features of the provided subject matter. Specific examples of components, materials, values, steps, arrangements, etc. are described below to simplify the present disclosure. Of course, these are examples and not limitations. Consider other components, materials, values, steps, arrangements, etc. For example, in the following description, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0018] In addition, spatial relative terms, such as "beneath", "below", "lower", "above", "upper", etc., may be used herein to easily describe the relationship of one element or feature shown in the figures with respect to another (one or more) element or (one or more) feature. These spatial relative terms are also intended to cover different orientations of the device in use or operation in addition to the orientation shown in the figures. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0019] According to some embodiments, a memory circuit includes a first inverter coupled to a first voltage source. In some embodiments, the first inverter is configured to generate a first input signal in response to a second input signal. In some embodiments, the first input signal is inverted with respect to the second input signal.

[0020] In some embodiments, the memory circuit further includes a level shifter circuit. In some embodiments, the level shifter circuit is coupled to at least the first inverter or a second voltage source. In some embodiments, the second voltage source is different from the first voltage source.

[0021] In some embodiments, the level shifter circuit is configured to receive at least the first input signal or the second input signal. In some embodiments, the level shifter circuit is configured to generate a first signal and a second signal in response to at least the first input signal or the second input signal.

[0022] In some embodiments, the memory circuit further includes a second inverter. In some embodiments, the second inverter is configured to generate a word line signal in response to the first signal.

[0023] In some embodiments, the level shifter circuit is configured to delay the leading edge of the word line signal in response to at least the first signal or the second signal. In some embodiments, the amount of delay of the leading edge of the word line signal is based on the voltage difference between the first power supply voltage and the second power supply voltage. In some embodiments, the first power supply voltage has a first swing, and the second power supply voltage has a second swing.

[0024] In some embodiments, by delaying the leading edge of the word line signal, the level shifter circuit has fewer early read operations than other methods, thereby improving the performance compared to other methods.

[0025] Figure 1 is a block diagram of a memory circuit 100 according to some embodiments.

[0026] For illustrative purposes, Figure 1 is simplified. In some embodiments, the memory circuit 100 includes in addition to Figure 1Various components other than those depicted, or otherwise arranged to perform the operations discussed below.

[0027] Memory circuit 100 is an IC that includes memory partitions 102A to 102D, global control circuit 100GC, and global input / output (GIO) circuit 100BL.

[0028] Each of memory partitions 102A to 102D includes memory banks 110U and 110L adjacent to word line (WL) driver circuits 110AC and local control circuits 110LC. Each of memory banks 110U and 110L includes memory cell arrays 110AR and local input / output (LIO) circuits 110BS.

[0029] A memory partition (e.g., memory partitions 102A to 102D) is a part of memory circuit 100 that includes a subset of memory devices ( Figure 1 not shown in the figure) and adjacent circuits configured to selectively access the subset of memory devices during programming and read operations. In Figure 1 the depicted embodiment, memory circuit 100 includes a total of four partitions. In some embodiments, memory circuit 100 includes a number of partitions greater than or less than 4.

[0030] GIO circuit 100BL is a circuit configured to control access to one or more electrical paths (e.g., bit lines) to each memory device of the corresponding memory bank 110U or 110L of each memory partition 102A to 102D, for example, by generating one or more bit line signals. In some embodiments, GIO circuit 100BL includes a global bit line driver circuit. In some embodiments, GIO circuit 100BL is coupled to each of memory banks 110U and 110L via corresponding global bit lines (not shown).

[0031] Global control circuit 100GC is a circuit configured to control some or all of the programming and read operations on each of memory partitions 102A to 102D, for example, by generating and / or outputting one or more control and / or enable signals.

[0032] In some embodiments, the global control circuit 100GC includes one or more analog circuits configured to perform the following operations in one or more circuit operations: interface with the memory partitions 102A to 102D such that data is programmed in one or more memory devices and / or use data received from one or more memory devices. In some embodiments, the global control circuit 100GC includes one or more global address decoder or pre-decoder circuits configured to output one or more address signals to the WL driver circuits 110AC of each of the memory partitions 102A to 102D.

[0033] Each WL driver circuit 110AC is configured to generate a word line signal on a corresponding word line WL. In some embodiments, each WL driver circuit 110AC is configured to output the word line signal on the corresponding word line WL to the adjacent memory banks 110U and 110L of the corresponding memory partitions 102A to 102D.

[0034] Each WL driver circuit 110AC includes one or more circuits 116. For ease of illustration, the circuits 116 are not shown in the memory banks 110U and 110L of the memory partitions 102B, 102C, and 102D. In some embodiments, each circuit 116 includes at least one word line driver circuit or at least one tracking word line driver circuit. In some embodiments, at least one word line driver circuit is configured to generate a word line signal WL (shown at least in Figure 2 ). In some embodiments, at least one tracking word line driver circuit is configured to generate a tracking word line signal TRKWL (shown at least in Figures 7 to 8 ). In some embodiments, each circuit 116 in the WL driver circuit 110AC is coupled to the memory devices 112 in the corresponding row of the memory cell array 110AR.

[0035] Each local control circuit 110LC is an electronic circuit configured to receive one or more address signals. Each local control circuit 110LC is configured to generate signals corresponding to a subset of adjacent memory devices identified by the one or more address signals. In some embodiments, the subset of adjacent memory devices corresponds to a memory device column. In some embodiments, each local control circuit 110LC is configured to generate each signal as a complementary signal pair. In some embodiments, each local control circuit 110LC is configured to output the signals to the corresponding word line driver circuits within the adjacent WL driver circuits 110AC of the corresponding memory partitions 102A to 102D. In some embodiments, the local control circuit 110LC includes a bank decoder circuit.

[0036] Each LIO circuit 110BS is configured to selectively access one or more bit lines of an adjacent subset of memory devices coupled to a corresponding memory cell array 110AR in response to the GIO circuit 100BL (e.g., based on one or more BL control signals). Figure 2 as shown in

[0037] Each LIO circuit 110BS includes one or more circuits 114. For ease of illustration, circuits 114 are not shown in memory banks 110U and 110L of memory partitions 102B, 102C, and 102D. In some embodiments, each circuit 114 includes at least a sense amplifier circuit or a write latch circuit. According to some embodiments, during a write operation, the write latch circuit is configured to write data to at least one memory cell 112 of a corresponding column of memory cells in the corresponding memory cell array 110AR. According to some embodiments, during a read operation, the sense amplifier circuit is configured to read data from at least one memory cell 112 of a corresponding column of memory cells in the corresponding memory cell array 110AR. In some embodiments, each circuit 114 in the LIO circuit 110BS is coupled to a memory device 112 of a corresponding column in the memory cell array 110AR.

[0038] Each memory bank 110U and 110L includes a corresponding memory cell array 110AR, the memory cell array 110AR includes memory cells or memory devices 112, and the memory cells or memory devices 112 are configured to be accessed by adjacent LIO circuits 110BS and adjacent WL driver circuits 110AC during programming and read operations.

[0039] Each memory cell array 110AR includes an array of memory devices 112 having N rows and M columns, where M and N are positive integers. The rows of cells in the memory cell array 102 are arranged in a first direction X. The columns of cells in the memory cell array 102 are arranged in a second direction Y. The second direction Y is different from the first direction X. In some embodiments, the second direction Y is perpendicular to the first direction X. In some embodiments, each memory cell array 110AR is divided into an upper region and a lower region (not shown). In some embodiments, each column of memory devices 112 in the memory cell array 110AR is coupled to a corresponding circuit 114 in the LIO circuit 110BS.

[0040] Memory devices 112 are shown in memory banks 110U and 110L of memory partition 102A. For ease of illustration, memory devices 112 are not shown in memory banks 110U and 110L of memory partitions 102B, 102C, and 102D.

[0041] A memory device 112 is an electrical, electromechanical, electromagnetic, or other device configured to store bit data represented by logic states. At least one logic state of the memory device 112 can be programmed in a write operation and detected in a read operation. In some embodiments, a logic state corresponds to a voltage level of a charge stored in a given memory device 112. In some embodiments, a logic state corresponds to a physical characteristic (e.g., voltage, current, resistance, or magnetic orientation) of a component of a given memory device 112.

[0042] In some embodiments, the memory device 112 includes one or more single-port (SP) static random access memory (SRAM) cells. In some embodiments, the memory device 112 includes one or more dual-port (DP) SRAM cells. In some embodiments, the memory device 112 includes one or more multi-port SRAM cells. Different types of memory cells in the memory device 112 are within the scope contemplated by this disclosure. In some embodiments, the memory device 112 includes one or more dynamic random access memory (DRAM) cells. In some embodiments, the memory device 112 includes one or more one-time programmable (OTP) memory devices, such as an electronic fuse (eFuse) or an antifuse device, a flash memory device, a random access memory (RAM) device, a resistive RAM device, a ferroelectric RAM device, a magnetoresistive RAM device, an erasable programmable read-only memory (EPROM) device, an electrically erasable programmable read-only memory (EEPROM) device, etc. In some embodiments, the memory device 112 is an OTP memory device including one or more OTP memory cells.

[0043] Other configurations of the memory circuit 100 are within the scope of this disclosure.

[0044] Figure 2 is a circuit diagram of a memory circuit 200 that can be used in accordance with some embodiments Figure 1 in.

[0045] The memory circuit 200 is Figure 1 an embodiment of one or more memory cells MCB in a memory cell array 110AR or Figure 1 a memory device 112 of.

[0046] The memory circuit 200 is Figure 1Examples of a portion of at least one of the memory partitions 102A, 102B, 102C, or 102D are thus omitted for similar detailed descriptions. For example, the memory circuit 200 is Figure 1 of the memory cell array 110AR and Figure 1 of the LIO circuit 110BS are thus omitted for similar detailed descriptions.

[0047] The memory circuit 200 includes memory cells 202, sense amplifiers 204, a p-type metal oxide semiconductor (PMOS) transistor P2-3, and two n-type metal oxide semiconductor (NMOS) transistors N2-5 and N2-6.

[0048] The memory cells 202 can be used as Figure 1 of the memory cell array 110AR or Figure 1 one or more memory cells MCB in at least one of the memory devices 112 are thus omitted for similar detailed descriptions. In some embodiments, the sense amplifiers 204, the PMOS transistor P2-3, and the NMOS transistors N2-5 and N2-6 can be used as Figure 1 of the LIO circuit 110BS are thus omitted for similar detailed descriptions. In some embodiments, the sense amplifiers 204 can be used as Figure 1 of the circuit 114 are thus omitted for similar detailed descriptions.

[0049] In some embodiments, the sense amplifiers 204, the PMOS transistor P2-3, and the NMOS transistors N2-5 and N2-6 can be used as Figure 1 of the GIO circuit 100BL are thus omitted for similar detailed descriptions.

[0050] The memory cells 202 are six-transistor (6T) single-port (SP) SRAM memory cells for illustration. In some embodiments, the memory cells 202 employ a number of transistors other than six. Other types of memories are within the scope of various embodiments.

[0051] The memory cells 202 include two PMOS transistors P2-1 and P2-2, and four NMOS transistors N2-1, N2-2, N2-3, and N2-4. The transistors P2-1, P2-2, N2-1, and N2-2 form a cross-latch or a pair of cross-coupled inverters. For example, the PMOS transistor P2-1 and the NMOS transistor N2-1 form a first inverter, while the PMOS transistor P2-2 and the NMOS transistor N2-2 form a second inverter.

[0052] The source terminal of each of PMOS transistors P2-1 and P2-2 is configured as a voltage source node NODE_1. Each voltage source node NODE_1 is coupled to a first voltage source VDDI. The drain terminal of PMOS transistor P2-1 is coupled to the drain terminal of NMOS transistor N2-1, the gate terminal of PMOS transistor P2-2, the gate terminal of NMOS transistor N2-2, and the source terminal of NMOS transistor N2-3, and is configured as a storage node ND.

[0053] The drain terminal of PMOS transistor P2-2 is coupled to the drain terminal of NMOS transistor N2-2, the gate terminal of PMOS transistor P2-1, the gate terminal of NMOS transistor N2-1, and the source terminal of NMOS transistor N2-4, and is configured as a storage node NDB. The source terminal of each of NMOS transistors N2-1 and N2-2 is configured as a power reference voltage node (not labeled) having a power reference voltage VSS. The source terminal of each of NMOS transistors N2-1 and N2-2 is also coupled to a reference voltage source VSS.

[0054] The word line WL is coupled to the gate terminal of each of NMOS transistors N2-3 and N2-4. The word line WL is also referred to as a write control line because NMOS transistors N2-3 and N2-4 are configured to be controlled by a word line signal WL' on the word line WL to transfer data between the bit lines BL, BLB and the corresponding nodes ND, NDB.

[0055] The drain terminal of NMOS transistor N2-3 is coupled to the bit line BL. The drain terminal of NMOS transistor N2-4 is coupled to the bit line BLB. The bit lines BL and BLB are configured as data inputs and outputs of the memory cell 202. In some embodiments, in a write operation, a logic value is applied to the bit line BL and an opposite logic value is applied to the other bit line BLB, such that the logic value on the bit lines can be written into the memory cell 202. Each of the bit lines BL and BLB is referred to as a data line because the data transmitted on the bit lines BL and BLB is written into and read from the corresponding nodes ND and NDB.

[0056] Other configurations of the memory cell 202 are within the scope of the present disclosure.

[0057] The sense amplifier 204 is coupled to the memory cell 202 through bit lines BL and BLB and NMOS transistors N2-5 and N2-6. The sense amplifier 204 is configured to sense or read the data stored in the memory cell 202 through the bit lines divided between the bit lines BL and BLB. For example, in some embodiments, the sense amplifier 204 is configured to sense or read the data stored in the memory cell 202 through the bit lines divided between the bit lines BL and BLB.

[0058] Other configurations of the sense amplifier 204 are within the scope of the present disclosure.

[0059] The PMOS transistor P2-3 is configured to equalize the voltages of the bit lines BL and BLB to an equalized bit line voltage in response to the signal BLEQB. In some embodiments, the PMOS transistor P2-3 is referred to as an "equalization circuit".

[0060] The gate of the PMOS transistor P2-3 is configured to receive the signal BLEQB. In some embodiments, the signal BLEQB is an equalization signal.

[0061] The source / drain of the PMOS transistor P2-3 is coupled to the bit line BL, the source / drain of the NMOS transistor N2-5, and the drain of the NMOS transistor N2-3.

[0062] The drain / source of the PMOS transistor P2-3 is coupled to the bit line BLB, the source / drain of the NMOS transistor N2-6, and the drain of the NMOS transistor N2-4.

[0063] Other configurations, quantities, or types of transistors in the PMOS transistor P2-3 are within the scope of the present disclosure.

[0064] In response to the select signal Wtsel, the NMOS transistor N2-5 is configured to couple / decouple the sense amplifier 204 from the memory cell 202 / bit line BL to each other.

[0065] The gate of the NMOS transistor N2-5 is configured to receive the select signal Wtsel.

[0066] The source / drain of the NMOS transistor N2-5 is coupled to the source / drain of the PMOS transistor P2-3, the bit line BL, and the drain of the NMOS transistor N2-3.

[0067] The drain / source of the NMOS transistor N2-5 is the sense amplifier 204.

[0068] In response to the select signal Wtsel, the NMOS transistor N2-6 is configured to couple / decouple the sense amplifier 204 from the memory cell 202 / bit line BLB to each other.

[0069] The gate of NMOS transistor N2-6 is configured to receive a select signal Wtsel.

[0070] The source / drain of NMOS transistor N2-6 is coupled to the drain / source of PMOS transistor P2-3, bit line BLB, and the drain of NMOS transistor N2-4.

[0071] The drain / source of NMOS transistor N2-5 is the sense amplifier 204.

[0072] Other configurations, quantities, or types of transistors in NMOS transistor N2-5 or N2-6 are within the scope of the present disclosure.

[0073] In some embodiments, the leading edge of the word line signal WL' on word line WL is aligned with the leading edge of the select line signal Wtsel. In some embodiments, the leading edge of the word line signal includes a rising edge or a falling edge.

[0074] In some embodiments, the rising edge of the word line signal WL' on word line WL is aligned with the rising edge of the select line signal Wtsel. In some embodiments, the falling edge of the word line signal on word line WL is aligned with the falling edge of the select line signal Wtsel.

[0075] Other configurations of the memory circuit 200 are within the scope of the present disclosure.

[0076] Figure 3 is a block diagram of a memory circuit 300 that can be used according to some embodiments Figure 1 in.

[0077] The memory circuit 300 is Figure 1 an embodiment of at least one partition of the memory partitions 102A, 102B, 102C, or 102D of, and thus a similar detailed description is omitted. For example, the memory circuit 300 is Figure 1 an embodiment of a row of WL driver circuits 110AC of, and thus a similar detailed description is omitted.

[0078] The memory circuit 300 is configured to receive a decoder signal DEC_X. The memory circuit 300 is configured to generate a word line signal WL' or a track word line signal TRKWL' in response to the decoder signal DEC_X. In some embodiments, the memory circuit 300 is a word line driver circuit (e.g., Figure 4 or Figure 6 ) that is configured to generate a word line signal WL' in response to the decoder signal DEC_X.

[0079] In some embodiments, the memory circuit 300 is a track word line driver circuit (e.g., Figure 7) which is configured to generate a tracking word line signal TRKWL' in response to a decoder signal DEC_X. In some embodiments, the tracking word line driver circuit is a word line driver circuit that is configured to compensate for at least one of a word line load, a signal line load, a memory cell load, or a signal swing from a faster process corner that may affect the pulse width of the word line signal and thus affect the performance of the memory circuit 300.

[0080] The post - decoder circuit 302 is coupled to the inverter 303. The post - decoder circuit 302 is configured to receive the decoder signal DEC_X. The post - decoder circuit 302 is configured to generate an input signal IN1 in response to the decoder signal DEC_X. In some embodiments, the decoder signal DEC_X is generated by Figure 1 the local control circuit 110LC, and thus a similar detailed description is omitted.

[0081] In some embodiments, the post - decoder circuit 302 includes one or more word line decoder circuits that are coupled to corresponding word lines or word line stripes and memory cells in corresponding rows of the memory cell array 110AR. In some embodiments, the post - decoder circuit 302 is configured to select memory cells in corresponding rows of the memory cell array 110AR via corresponding word line signals WL'. In some embodiments, each of the one or more word line decoder circuits includes a corresponding NAND logic gate (not shown) or NOR logic gate (not shown). Other types of word line decoder circuits in the post - decoder circuit 302 are within the scope of the present disclosure.

[0082] The input terminal of the post - decoder circuit 302 is configured to receive the decoder signal DEC_X. The input terminal of the post - decoder circuit 302 is coupled to the source of the decoder signal DEC_X (not shown).

[0083] The output terminal of the post - decoder circuit 302 is configured to output the input signal IN1. The output terminal of the post - decoder circuit 302 is coupled to the input terminal of the inverter 303.

[0084] Other configurations of the post - decoder circuit 302 are within the scope of the present disclosure.

[0085] The inverter 303 is configured to generate an input signal IN2 in response to the input signal IN1.

[0086] The input terminal of the inverter 303 is configured to receive the input signal IN1. The output terminal of the inverter 303 is configured to output the input signal IN2. In some embodiments, the input signal IN2 is an inverted version of the input signal IN1. In some embodiments, the inverter 303 is part of the level shifter 304. In some embodiments, the inverter 303 is not part of the level shifter 304.

[0087] Other configurations of the inverter 303 are within the scope of the present disclosure.

[0088] The level shifter 304 is a level shifter circuit configured to shift a signal from a first voltage domain using the power supply voltage VDD to a second voltage domain using the power supply voltage VDDM. In some embodiments, the power supply voltage VDD is less than the power supply voltage VDDM. In some embodiments, the power supply voltage VDD is greater than the power supply voltage VDDM.

[0089] The level shifter 304 is configured to receive the input signal IN2 at an input terminal (not labeled) and output the inverted input signal INB at an output terminal (not labeled). The input signal IN2 corresponds to the input signal of the level shifter 304, and the inverted input signal INB corresponds to the output signal of the level shifter 304. The level shifter 304 is configured to generate the inverted input signal INB based on the input signal IN2.

[0090] The inverted input signal INB corresponds to an inverted and level-shifted version of the input signal IN2. The decoder signal DEC_X is in the first voltage domain. The input signal IN1 and the input signal IN2 are in the first voltage domain. The inverted input signal INB is in the second voltage domain.

[0091] The input terminal of the level shifter 304 is coupled to the output terminal of the post-decoding circuit 302. The output terminal of the level shifter 304 is coupled to the input terminal of the inverter 306.

[0092] Other configurations of the level shifter 304 are within the scope of the present disclosure.

[0093] The inverter 306 is configured to generate the word line signal WL' or the trace word line signal TRKWL' in response to the inverted input signal INB.

[0094] The input terminal of the inverter 306 is configured to receive the inverted input signal INB. The output terminal of the inverter 306 is configured to output the word line signal WL' or the trace word line signal TRKWL'. In some embodiments, the word line signal WL' or the trace word line signal TRKWL' is an inverted version of the inverted input signal INB.

[0095] Other configurations of the inverter 306 are within the scope of the present disclosure.

[0096] Other configurations of the memory circuit 300 are within the scope of the present disclosure.

[0097] Figure 4 is a circuit diagram of a memory circuit 400 according to some embodiments.

[0098] The memory circuit 400 is an embodiment of the memory circuit 300, and thus similar detailed descriptions are omitted. The memory circuit 400 is Figure 1 an embodiment of a part of at least one of the memory partitions 102A, 102B, 102C, or 102D, and thus similar detailed descriptions are omitted. For example, the memory circuit 400 is Figure 1 an embodiment of a row of the WL driver circuit 110AC, and thus similar detailed descriptions are omitted.

[0099] In some embodiments, the memory circuit 400 is a dual-rail circuit implementation using signals from two different voltage domains (e.g., the word line WL' and the signal LS_IN).

[0100] The memory circuit 400 includes an inverter 402, an inverter 403, a level shifter 404, and an inverter 406. As Figure 4 and Figure 7 shown, the inverter 403 is part of the level shifter 404. In some embodiments, the inverter 403 is not part of the level shifter 404.

[0101] The inverter 402 is an embodiment of the post-decoder circuit 302, the inverter 403 is an embodiment of the inverter 303, the level shifter 404 is an embodiment of the level shifter 304, and the inverter 406 is an embodiment of the inverter 306, and thus similar detailed descriptions are omitted.

[0102] The signal LS_IN is an embodiment of the input signal IN1, the signal LS_INB is an embodiment of the input signal IN2, and the signal OUTB is an embodiment of the inverted input signal INB, and thus similar detailed descriptions are omitted.

[0103] The signals LS_IN and LS_INB are in the first voltage domain. The signals FB, OUTB, and the word line signal WL' are in the second voltage domain.

[0104] The inverter 402 includes a PMOS transistor P4-1 and an NMOS transistor N4-1.

[0105] The PMOS transistor P4-1 and the NMOS transistor N4-1 are configured as the inverter 402 and are configured to generate the signal LS_IN in response to the decoder signal DEC_X. In some embodiments, the signal LS_IN is inverted with respect to the decoder signal DEC_X.

[0106] The source of PMOS transistor P4-1 is coupled to a first voltage source having a power supply voltage VDD. In some embodiments, the power supply voltage VDD has a voltage swing ranging from VDD to VSS.

[0107] The source of NMOS transistor N4-1 is coupled to a reference voltage source VSS.

[0108] Each of the gates of PMOS transistor P4-1 and NMOS transistor N4-1 is coupled together and configured to receive a decoder signal DEC_X.

[0109] Each of the drains of PMOS transistor P4-1 and NMOS transistor N4-1 is coupled together and configured to generate a signal LS_IN.

[0110] Each of the drains of PMOS transistor P4-1, the drain of NMOS transistor N4-1, the gate of PMOS transistor P4-2, the gate of NMOS transistor N4-2, the gate of PMOS transistor PM1, and the gate of NMOS transistor NM1 is coupled together.

[0111] Other configurations of inverter 402 are within the scope of the present disclosure.

[0112] Inverter 403 includes PMOS transistor P4-2 and NMOS transistor N4-2.

[0113] PMOS transistor P4-2 and NMOS transistor N4-2 are configured as inverter 403 and configured to generate a signal LS_INB in response to the signal LS_IN. In some embodiments, the signal LS_INB is inverted with respect to the signal LS_IN.

[0114] The source of PMOS transistor P4-2 is coupled to a first voltage source having a power supply voltage VDD.

[0115] The source of NMOS transistor N4-2 is coupled to a reference voltage source VSS.

[0116] Each of the gates of PMOS transistor P4-2 and NMOS transistor N4-2 is coupled together and configured to receive the signal LS_IN.

[0117] Each of the drains of PMOS transistor P4-2 and NMOS transistor N4-2 is coupled together and configured to generate the signal LS_INB.

[0118] The drain of PMOS transistor P4-2, the drain of NMOS transistor N4-2, the gate of PMOS transistor PM4, and the gate of NMOS transistor NM2 are each coupled together.

[0119] Other configurations of the inverter 403 are within the scope of the present disclosure.

[0120] The level shifter 404 includes PMOS transistors PM1, PMOS transistors PM2, PMOS transistors PM3, PMOS transistors PM4, NMOS transistors NM1, and NMOS transistors NM2.

[0121] The source of PMOS transistor PM1 is coupled to a second voltage source having a supply voltage VDDM.

[0122] Each of the gate of PMOS transistor PM1 and the gate of NMOS transistor NM1 are coupled together and configured to receive the signal LS_IN.

[0123] Each of the drain of PMOS transistor PM1 and the source of PMOS transistor PM3 are coupled together.

[0124] The drain of PMOS transistor PM3, the drain of transistor NM1, the gate of PMOS transistor P4-3, the gate of NMOS transistor N4-3, and the gate of PMOS transistor PM2 are each coupled together.

[0125] Each of the drain of PMOS transistor PM3 and the drain of transistor NM1 are configured to generate the signal OUTB.

[0126] The gate of PMOS transistor PM3 is configured to receive the signal FB.

[0127] The gate of PMOS transistor PM3, the drain of PMOS transistor PM4, and the drain of transistor NM2 are each coupled together.

[0128] The source of transistor NM1 is coupled to a reference voltage source VSS.

[0129] The source of PMOS transistor PM2 is coupled to a second voltage source having a supply voltage VDDM. In some embodiments, the source of PMOS transistor PM2 is coupled to the source of PMOS transistor PM1.

[0130] The gate of PMOS transistor PM2 is configured to receive the signal OUTB.

[0131] Each of the drain of PMOS transistor PM2 and the source of PMOS transistor PM4 are coupled together.

[0132] The drain of each of PMOS transistor PM4 and transistor NM2 is configured to generate signal FB.

[0133] The gate of each of PMOS transistor PM4 and NMOS transistor NM2 is coupled together and configured to receive signal LS_INB.

[0134] The source of transistor NM2 is coupled to reference voltage source VSS. In some embodiments, the source of NMOS transistor NM2 is coupled to the source of NMOS transistor NM1.

[0135] In some embodiments, level shifter 404 is configured to delay the transition of signal OUTB from logic high to logic low by up to delay DEL1 due to contention (discussed further at least in Figure 5 ). In some embodiments, level shifter 404 is configured to delay the transition of signal FB from logic low to logic high by up to delay DEL1 due to contention (discussed further at least in Figure 5 ). In some embodiments, delay DEL1 can be adjusted by memory circuit 400.

[0136] In some embodiments, due to at least contention between NMOS transistor NM1 and at least one of PMOS transistor PM1 or PMOS transistor PM3, the amount of delay DEL1 is positively correlated with the difference between second voltage source VDDM and first voltage source VDD. In some embodiments, as the difference between second voltage source VDDM and first voltage source VDD increases, at least one of PMOS transistors PM1 or PM3 becomes stronger than NMOS transistor NM1, thereby increasing the amount of delay DEL1. In some embodiments, as the difference between second voltage source VDDM and first voltage source VDD decreases, the amount of delay DEL1 also decreases.

[0137] In some embodiments, by delaying the transition of signal OUTB from logic high to logic low or delaying the transition of signal FB from logic low to logic high, a delay DEL2 (shown in Figure 9 ) in the transition of word line signal WL' from logic low to logic high is caused. In other words, by delaying the transition of signal OUTB from logic high to logic low or delaying the transition of signal FB from logic low to logic high, a delay DEL2 in the rising / falling edge of word line signal WL' (as in Figure 9(as shown). In some embodiments, by delaying the rising / falling edge of the word line signal WL', the rising / falling edge of the word line signal WL' can be synchronized with the rising / falling edge of the selection signal Wtsel. In some embodiments, synchronizing the rising / falling edge of the word line signal WL' with the rising / falling edge of the selection signal Wtsel results in fewer early read operations than other methods, thereby improving performance compared to other methods. In some embodiments, when the rising / falling edge of the word line signal WL' occurs before the rising / falling edge of the selection signal Wtsel, an early read operation occurs, which may lead to misreading of the memory cell because the voltage of the bit line / bit strip may not be sufficient for read or write operations.

[0138] In some embodiments, synchronizing the rising / falling edge of the word line signal WL' with the rising / falling edge of the selection signal Wtsel emphasizes that the static noise margin (SNM) of the memory circuit 400 is the same as or better than other methods.

[0139] In some embodiments, the PMOS transistor PM1 has a size S1, the PMOS transistor PM3 has a size S2, and the NMOS transistor NM1 has a size S3. In some embodiments, at least one of the sizes S1, S2, or S3 is the same as at least another of the sizes S1, S2, or S3. In some embodiments, at least one of the sizes S1, S2, or S3 is different from at least another of the sizes S1, S2, or S3.

[0140] In some embodiments, the size of the transistor at least includes the channel width of the transistor. In some embodiments, at least one of the sizes S1, S2, S3, or S4 includes the corresponding channel width of the corresponding transistor.

[0141] In some embodiments, at least one of the PMOS transistors PM1, PM2, PM3, PM4, or PM5 is a nanosheet transistor. In some embodiments, at least one of NM1 or NM2 is a nanosheet transistor. In some embodiments, the size of the transistor at least includes the number of sheets in the transistor. In some embodiments, at least one of the sizes S1, S2, S3, or S4 includes the corresponding number of sheets of the corresponding transistor.

[0142] In some embodiments, at least one of the PMOS transistors PM1, PM2, PM3, PM4, or PM5 is a nanowire transistor. In some embodiments, at least one of the NMOS transistors NM1 or NM2 is a nanowire transistor. In some embodiments, the size of the transistor at least includes the number of wires in the transistor. In some embodiments, at least one of the sizes S1, S2, S3, or S4 includes the corresponding number of wires of the corresponding transistor.

[0143] In some embodiments, at least one of PMOS transistors PM1, PM2, PM3, PM4, or PM5 is a fin field-effect transistor (FinFET). In some embodiments, at least one of NMOS transistors NM1 or NM2 is a FinFET. In some embodiments, each FinFET has one or more fins or fingers. In some embodiments, fins are referred to as fingers.

[0144] In some embodiments, the size of a transistor includes at least the number of fins of the transistor. In some embodiments, at least one of sizes S1, S2, S3, or S4 includes the corresponding number of fins of the corresponding transistor.

[0145] Other transistor types and transistor size types are within the scope of the present disclosure.

[0146] In some embodiments, at least one of sizes S1 or S2 is different from size S3. In some embodiments, as size S1 of PMOS transistor PM1 or size S2 of PMOS transistor PM3 increases compared to size S3, the amount of delay DEL1 increases, resulting in an increase in delay DEL2 ( Figure 9 as shown). In some embodiments, as size S1 of PMOS transistor PM1 or size S2 of PMOS transistor PM3 decreases compared to size S3, the amount of delay DEL1 decreases, resulting in a decrease in delay DEL2 ( Figure 9 as shown).

[0147] In some embodiments, as size S3 of NMOS transistor NM1 increases compared to size S1 or S2, the amount of delay DEL1 decreases, resulting in a decrease in delay DEL2 ( Figure 9 as shown). In some embodiments, as size S3 of NMOS transistor NM1 decreases compared to size S1 or S2, the amount of delay DEL1 increases, resulting in an increase in delay DEL2 ( Figure 9 as shown).

[0148] Other configurations of the level shifter 404 are within the scope of the present disclosure.

[0149] The inverter 406 includes a PMOS transistor P4-3 and an NMOS transistor N4-3.

[0150] The PMOS transistor P4-3 and the NMOS transistor N4-3 are configured as the inverter 406 and are configured to generate a word line signal WL' in response to the signal OUTB. In some embodiments, the word line signal WL' is inverted with respect to the signal OUTB.

[0151] The source of the PMOS transistor P4-3 is coupled to a second voltage source having a supply voltage VDDM.

[0152] The source of NMOS transistor N4-3 is coupled to a reference voltage source VSS.

[0153] Each of the gates of PMOS transistor P4-3, the gate of NMOS transistor N4-3, and the gate of PMOS transistor PM2 are coupled together and configured to receive signal OUTB.

[0154] Each of the drains of PMOS transistor P4-3 and NMOS transistor N4-3 are coupled together and configured to generate a word line signal WL'.

[0155] Other configurations of inverter 406 are within the scope of the present disclosure.

[0156] In some embodiments, memory circuit 400 is configured such that NMOS transistor NM1 competes with at least one of PMOS transistor PM1 or PMOS transistor PM3 for the falling edge of signal OUTB or the rising edge of signal FB.

[0157] In some embodiments, memory circuit 400 is configured such that NMOS transistor NM2 does not compete with at least one of PMOS transistor PM4 or PMOS transistor PM2 for the rising edge of signal OUTB or the falling edge of signal FB.

[0158] In some embodiments, because of the competition between NMOS transistor NM1 and at least one of PMOS transistor PM1 or PMOS transistor PM3 for the falling edge of signal OUTB or the rising edge of signal FB, voltage shifter 406 or 606 is referred to as an "asymmetric voltage shifter".

[0159] In some embodiments, by configuring memory circuit 400 to adjust delay DEL1, memory circuit 400 has a more flexible memory design than other methods.

[0160] Other configurations, other types of circuit elements, or other numbers of circuit elements in memory circuit 400 are within the scope of the present disclosure.

[0161] Figure 5 is a timing diagram 500 of waveforms of a memory circuit according to some embodiments (e.g., Figure 4 memory circuit 400 in

[0162] In some embodiments, one or more read operations or write operations are applied to Figure 2 memory cell 202 of Figure 1 or at least one memory cell in a single column of memory cell array 110AR of Figure 2of the memory cell 202 or Figure 1 waveforms during one or more read operations or write operations of at least one memory cell in a single column of the memory cell array 110AR.

[0163] In some embodiments, at least Figure 1 one or more read operations or write operations of the memory banks in the memory circuit 100 are applied to at least one of the memory partitions 102A, 102B, 102C, or 102D, and the timing diagram 500 corresponds to waveforms during read operations or write operations of at least one of the memory partitions 102A, 102B, 102C, or 102D.

[0164] The timing diagram 500 includes waveforms of the signal LS_IN, the signal OUTB, the signal FB, or the word line signal WL'.

[0165] At time T0, the signal LS_IN is logic low, the signal OUTB is logic high, the signal FB is logic low, and the word line signal WL' is logic low.

[0166] At time T1, the signal LS_IN transitions from logic low to logic high. In some embodiments, in response to the signal LS_IN transitioning from logic low to logic high, the signal LS_INB ( Figure 5 not shown in

[0167] transitions from logic high to logic low. At time T1, the signal OUTB transitions from logic high to logic low, while the signal FB transitions from logic low to logic high.

[0168] In some embodiments, at time T1, in response to at least a transition of signal LS_IN from logic low to logic high or a transition of signal FB from logic low to logic high, signal OUTB transitions from logic high to logic low. For example, in response to the transition of signal LS_IN from logic low to logic high, NMOS transistor NM1 turns on and PMOS transistor PM1 begins to turn off. However, even though signal LS_IN transitions from logic low to logic high, the voltage difference between power supply voltage VDDM and power supply voltage VDD causes PMOS transistor PM1 to still be on, resulting in a competition between NMOS transistor NM1 and PMOS transistor PM1, thereby causing a delay DEL1 in the falling edge of signal OUTB. In other words, because of the competition between NMOS transistor NM1 turning on and PMOS transistor PM1 still being on, the transition of signal OUTB from logic high to logic low is delayed (e.g., delay DEL1). However, as signal FB transitions from logic low to logic high, it causes PMOS transistor PM3 to turn off, thereby allowing NMOS transistor NM1 to pull signal OUTB to logic low (e.g., reference voltage VSS), thus overcoming the competition with PMOS transistor PM1.

[0169] In some embodiments, at time T1, in response to signal OUTB transitioning from logic high to logic low and signal LS_INB transitioning from logic high to logic low, signal FB transitions from logic low to logic high. For example, in response to signal OUTB transitioning from logic high to logic low, PMOS transistor PM2 begins to turn on, thereby coupling the source of PMOS transistor PM4 to the second voltage source VDDM. Additionally, in response to signal LS_INB transitioning from logic high to logic low, NMOS transistor NM2 turns off and PMOS transistor PM4 begins to turn on. In response to PMOS transistor PM4 turning on and the source of PMOS transistor PM4 being coupled to the second voltage source VDDM, PMOS transistors PM4 and PM2 pull signal FB to logic high (e.g., to power supply voltage VDDM).

[0170] At time T2, signal OUTB is logic low.

[0171] At time T2, signal FB is logic high.

[0172] At time T2, word line signal WL' transitions from logic low to logic high. In some embodiments, at time T2, word line signal WL' transitions from logic low to logic high in response to at least signal OUTB being logic low. For example, in response to signal OUTB being logic low, NMOS transistor N4-3 turns off and PMOS transistor P4-3 turns on, thereby pulling word line signal WL' to logic high (e.g., to power supply voltage VDDM).

[0173] At time T3, the word line signal WL' is logic high.

[0174] At time T4, the signal LS_IN transitions from logic high to logic low. In some embodiments, in response to the signal LS_IN transitioning from logic high to logic low, the signal LS_INB ( Figure 5 not shown in) transitions from logic low to logic high.

[0175] At time T5, the signal OUTB transitions from logic high to logic low, while the signal FB transitions from logic low to logic high.

[0176] In some embodiments, at time T5, in response to at least the signal LS_IN transitioning from logic high to logic low or the signal FB transitioning from logic high to logic low, the signal OUTB transitions from logic low to logic high. For example, in response to the signal LS_IN transitioning from logic high to logic low, the NMOS transistor NM1 is turned off, and the PMOS transistor PM1 starts to conduct. Additionally, as the signal FB transitions from logic high to logic low, the PMOS transistor PM3 conducts, allowing the PMOS transistor PM1 to pull the signal OUTB to logic high (e.g., the supply voltage VDDM).

[0177] In some embodiments, the memory circuit 400 is configured such that the NMOS transistor NM2 does not compete with at least one of the PMOS transistor PM4 or the PMOS transistor PM2 for the rising edge of the signal OUTB or the falling edge of the signal FB.

[0178] In some embodiments, the memory circuit 400 is configured such that the NMOS transistor NM1 competes with at least one of the PMOS transistor PM1 or the PMOS transistor PM3 for the falling edge of the signal OUTB or the rising edge of the signal FB.

[0179] In some embodiments, because of the competition between the NMOS transistor NM1 and at least one of the PMOS transistor PM1 or the PMOS transistor PM3 for the falling edge of the signal OUTB or the rising edge of the signal FB, the level shifter 406 or 606 is referred to as an "asymmetric level shifter".

[0180] In some embodiments, at time T5, in response to signal OUTB transitioning from logic low to logic high and signal LS_INB transitioning from logic low to logic high, signal FB transitions from logic high to logic low. For example, in response to signal OUTB transitioning from logic low to logic high, PMOS transistor PM2 begins to turn off, thereby decoupling the source of PMOS transistor PM4 from the second voltage source VDDM. In addition, in response to signal LS_INB transitioning from logic low to logic high, NMOS transistor NM2 turns on, and PMOS transistor PM4 begins to turn off. In response to PMOS transistor PM4 turning off and NMOS transistor NM2 turning on, NMOS transistor NM2 pulls signal FB to logic low (e.g., to the reference voltage VSS).

[0181] At time T6, signal OUTB is logic high.

[0182] At time T6, signal FB is logic low.

[0183] At time T6, the word line signal WL' transitions from logic high to logic low. In some embodiments, at time T6, the word line signal WL' transitions from logic high to logic low in response to at least signal OUTB being logic high. For example, in response to signal OUTB being logic high, PMOS transistor P4-3 turns off, and NMOS transistor N4-3 turns on, thereby pulling the word line signal WL' to logic low (e.g., to the reference voltage VSS).

[0184] At time T7, the word line signal WL' is logic low.

[0185] After time T7, Figure 2 memory cell 202 of Figure 1 or at least one memory cell in a single column of memory cell array 110AR of

[0186] The next read operation or write operation of

[0187] In some embodiments, after time T7, waveform 500 is repeated and thus is similar to time T0, and thus similar detailed descriptions are omitted.

[0188] In some embodiments, although timing diagram 500 is described with respect to memory circuit 400, timing diagram 500 also applies to memory circuit 600 in a similar manner, and is not described herein for the sake of brevity.

[0189] Other configurations of timing diagram 500 are within the scope of the present disclosure.

[0190] Figure 6 is a circuit diagram of a memory circuit 600 according to some embodiments.

[0191] The memory circuit 600 is Figure 4 a variant of the memory circuit 400 of Figure 4 , and thus similar detailed descriptions are omitted. For example, the memory circuit 600 shows a non-limiting example in which the level shifter 604 replaces the

[0192] The memory circuit 600 includes an inverter 402, an inverter 403, a level shifter 604, and an inverter 406. As Figure 6 shown, the inverter 403 is part of the level shifter 604. In some embodiments, the inverter 403 is not part of the level shifter 604.

[0193] Compared with the Figure 4 memory circuit 400 of Figure 4 , the level shifter 604 replaces the level shifter 404 of the memory circuit 400 of

[0194] The level shifter 604 is Figure 4 a variant of the level shifter 404 of Figure 4 , and thus similar detailed descriptions are omitted. Compared with the level shifter 404 of

[0195] The level shifter 604 includes a PMOS transistor PM1, a PMOS transistor PM2, a PMOS transistor PM3, a PMOS transistor PM4, an NMOS transistor NM1, an NMOS transistor NM2, and a PMOS transistor PM5.

[0196] The source of the PMOS transistor PM5 is coupled to the source of the PMOS transistor PM1 and a second voltage source having a supply voltage VDDM. In some embodiments, each of the source of the PMOS transistor PM5, the source of the PMOS transistor PM1, and the source of the PMOS transistor PM2 are coupled together.

[0197] In Figure 6 , each of the gate of the PMOS transistor PM5, the gate of the PMOS transistor PM1, and the gate of the NMOS transistor NM1 are coupled together and configured to receive a signal LS_IN.

[0198] In Figure 6In [description], each of the gate of PMOS transistor PM5, the gate of PMOS transistor PM1, the gate of NMOS transistor NM1, the drain of PMOS transistor P4-1, the drain of NMOS transistor N4-1, the gate of PMOS transistor P4-2, and the gate of NMOS transistor N4-2 is coupled together.

[0199] In Figure 6 In [description], each of the drain of PMOS transistor PM5, the drain of PMOS transistor PM1, and the source of PMOS transistor PM3 is coupled together.

[0200] In some embodiments, PMOS transistor PM5 has a size S4. In some embodiments, size S4 is the same as at least one of size S1, S2, or S3. In some embodiments, size S4 is different from at least one of size S1, S2, or S3. In some embodiments, the effect of size S4 of PMOS transistor PM5 is similar to Figure 4 the effect of size S1 of PMOS transistor PM1 described in [description], and thus similar detailed description is omitted.

[0201] In some embodiments, by the level shifter 604 including PMOS transistor PM5 in parallel with PMOS transistor PM1, the delay DEL1 of the rising edge of signal OUTB or signal FB is increased. In some embodiments, increasing the delay DEL1 of the rising edge of signal OUTB or signal FB causes an increase in the delay DEL2 of the rising edge of the word line signal WL' ( Figure 9 as shown in [description]).

[0202] In some embodiments, by the level shifter 604 including PMOS transistor PM5 in parallel with PMOS transistor PM1, the delay DEL2 of the rising edge of the word line signal WL' ( Figure 9 as shown in [description]) is increased.

[0203] In some embodiments, increasing the number of PMOS transistors in parallel with PMOS transistor PM1 further increases the delay DEL1 of the rising edge of signal OUTB or signal FB, thereby further increasing the delay DEL2 of the rising edge of the word line signal WL' (as Figure 9 shown in [description]).

[0204] Although Figure 6 is described with respect to the rising edge of the word line signal WL', the details of Figure 6 also apply to the leading edge of the word line signal WL' (which also includes the falling edge of the word line signal WL'), and details are omitted for the sake of brevity.

[0205] Other configurations, other types of circuit elements, or other numbers of transistors in the level shifter 604 are within the scope of the present disclosure.

[0206] In some embodiments, the memory circuit 600 operates to achieve one or more of the benefits described herein.

[0207] Other configurations of the memory circuit 600 are within the scope of the present disclosure. In some embodiments, the memory circuit 600 operates in the same manner as the memory circuit 400, and thus Figure 5 the timing diagram 500 also applies to the memory circuit 600 and is not described herein for the sake of brevity.

[0208] Other configurations, other types of circuit elements, or other numbers of transistors in the memory circuit 600 are within the scope of the present disclosure.

[0209] Figure 7 is a circuit diagram of a memory circuit 700 according to some embodiments.

[0210] The memory circuit 700 is an embodiment of the memory circuit 300, and thus a similar detailed description is omitted. The memory circuit 700 is Figure 1 an embodiment of a part of at least one of the memory partitions 102A, 102B, 102C, or 102D of Figure 1 and thus a similar detailed description is omitted. For example, the memory circuit 700 is

[0211] The memory circuit 700 is Figure 4 a variant of the memory circuit 400 of

[0212] The memory circuit 700 includes an inverter 402, an inverter 403, a level shifter 404, and an inverter 406.

[0213] Compared with Figure 4 the memory circuit 400 of Figure 7 the signal TRKLS_IN of Figure 4 replaces the signal LS_IN of the memory circuit 400 of Figure 7 the signal TRKLS_INB of Figure 4 replaces the signal LS_INB of the memory circuit 400 of Figure 7 and the tracking word line signal TRKWL' of Figure 4the word line signal WL' of the memory circuit 400, and thus a similar detailed description is omitted.

[0214] In some embodiments, the memory circuit 700 is a dual - rail circuit implementation that uses signals from two different voltage domains (e.g., the trace word line WL' and the signal TRKLS_IN).

[0215] The signal TRKLS_IN and the signal TRKLS_INB are in the first voltage domain. The trace word line signal TRKWL' is in the second voltage domain.

[0216] The memory circuit 700 is a trace word line driver circuit that is configured to generate the trace word line signal TRKWL' in response to the decoder signal DEC_X.

[0217] In some embodiments, the memory circuit 700 operates to achieve one or more of the benefits described herein.

[0218] Other configurations, other types of circuit elements, or other numbers of transistors in the memory circuit 700 are within the scope of the present disclosure.

[0219] Figure 8 is a timing diagram 800 of waveforms of a memory circuit (e.g., Figure 7 the memory circuit 700 in

[0220] In some embodiments, one or more read operations or write operations are applied to Figure 2 the memory cells 202 of Figure 1 or at least one memory cell in a single column of the memory cell array 110AR of Figure 2 and the timing diagram 800 corresponds to the waveforms during one or more read operations or write operations of the memory cells 202 of Figure 1 or at least one memory cell in a single column of the memory cell array 110AR of

[0221] In some embodiments, at least Figure 1 one or more read operations or write operations of the memory banks in the memory circuit 100 are applied to at least one of the memory partitions 102A, 102B, 102C, or 102D, and the timing diagram 800 corresponds to the waveforms during the read operations or write operations of at least one of the memory partitions 102A, 102B, 102C, or 102D.

[0222] The timing diagram 800 includes waveforms of the signal TRKLS_IN, the signal OUTB, the signal FB, or the word line signal TRKWL.

[0223] The timing diagram 800 isFigure 5 A variant of the timing diagram 500, so similar detailed descriptions are omitted. Compared with Figure 5 the timing diagram 500 of Figure 7 the signal TRKLS_IN of the timing diagram 700 of Figure 5 replaces the signal LS_IN of the timing diagram 500 of Figure 7 and the tracking word line signal TRKWL' of the timing diagram 700 of Figure 5 replaces the word line signal WL' of the timing diagram 500 of , so similar detailed descriptions are omitted.

[0224] In some embodiments, the timing diagram 800 enables the memory circuit 700 to achieve one or more of the benefits described herein.

[0225] Other configurations of the timing diagram 800 are within the scope of the present disclosure.

[0226] Figure 9 is a timing diagram 900 of waveforms of a memory circuit (e.g., the memory circuit 400 in Figure 4 , the memory circuit 600 in Figure 6 or the memory circuit 700 in Figure 7 ) according to some embodiments.

[0227] In some embodiments, one or more read operations or write operations are applied to Figure 2 the memory cell 202 of Figure 1 or at least one memory cell in a single column of the memory cell array 110AR of Figure 2 and the timing diagram 900 corresponds to the waveforms during one or more read operations or write operations of the memory cell 202 of Figure 1 or at least one memory cell in a single column of the memory cell array 110AR of .

[0228] In some embodiments, at least Figure 1 one or more read operations or write operations of the memory banks in the memory circuit 100 are applied to at least one of the memory partitions 102A, 102B, 102C, or 102D, and the timing diagram 900 corresponds to the waveforms during the read operations or write operations of at least one of the memory partitions 102A, 102B, 102C, or 102D.

[0229] The timing diagram 900 includes a signal S1 and a signal S2.

[0230] In some embodiments, when the size S1 is equal to the first size S1a, the signal S1 represents the word line signal WL', and when the size S1 is equal to the second size S2a and the second size S2a is greater than the first size S1a, the signal S2 represents the word line signal WL'.

[0231] In some embodiments, when the size S1 is equal to the first size S1a, the signal S1 represents the tracking word line signal TRKWL', and when the size S1 is equal to the second size S2a and the second size S2a is greater than the first size S1a, the signal S2 represents the tracking word line signal TRKWL'.

[0232] As Figure 9 shown, the signal SL2 is delayed by a delay DEL2 with respect to the signal SL1. In some embodiments, the amount of the delay DEL2 can be adjusted by the level shifter 406 or 606.

[0233] In some embodiments, although the timing diagram 900 is described with respect to the sizes S1a and S2a, the timing diagram 900 also applies in a similar manner to one or more of the sizes S2, S3, or S4, and is not described herein for the sake of brevity.

[0234] In some embodiments, although the timing diagram 900 is described with respect to the sizes S1a and S2a, the timing diagram 900 also applies in a similar manner to different power supply voltages of the power supply voltage VDDM, and is not described herein for the sake of brevity.

[0235] In some embodiments, although the timing diagram 900 is with respect to Figure 4 , Figure 6 or Figure 7 described, the timing diagram 900 also applies in a similar manner to one or more of the memory banks 110L or 110R, and is not described herein for the sake of brevity.

[0236] Other configurations of the timing diagram 900 are within the scope of the present disclosure.

[0237] Figure 10 is a flowchart of a method 1000 for operating an operational circuit according to some embodiments.

[0238] In some embodiments, Figure 10 is for operating Figure 1 the memory circuit 100 of Figure 2 the memory circuit 200 of Figure 3 the memory circuit 300 of Figure 4 the memory circuit 400 of Figure 6 the memory circuit 600 of Figure 7 or the memory circuit 700 of

[0239] In some embodiments, Figure 10 is for operating Figure 1 the memory circuit 100 of Figure 2memory circuit 200, Figure 3 memory circuit 300, Figure 4 memory circuit 400, Figure 6 memory circuit 600, or Figure 7 at least one of memory circuit 700. Flowchart of method 1000. In some embodiments, Figure 10 is a flowchart of method 1000 for operating a memory circuit, and method 1000 includes Figure 5 timing diagram 500, Figure 8 timing diagram 800, or Figure 9 at least one of the features of timing diagram 900, and similar detailed descriptions are omitted for the sake of brevity.

[0240] It should be understood that additional operations may be performed before, during, and / or after method 1000 depicted in Figure 10 and some other operations may be described only briefly herein. It should be understood that method 1000 utilizes Figure 1 memory circuit 100, Figure 2 memory circuit 200, Figure 3 memory circuit 300, Figure 4 memory circuit 400, Figure 6 memory circuit 600, or Figure 7 one or more features of at least one of memory circuit 700, and similar detailed descriptions are omitted for the sake of brevity.

[0241] In some embodiments, other operation orders of method 1000 are within the scope of the present disclosure. Method 1000 includes exemplary operations, but these operations are not necessarily performed in the order shown. Operations may be appropriately added, replaced, reordered, and / or eliminated according to the spirit and scope of the disclosed embodiments. In some embodiments, one or more operations of method 1000 are not performed.

[0242] In operation 1002 of method 1000, a first input signal is generated in response to a first decoder signal.

[0243] In some embodiments, operation 1002 is performed by a first post-decoder circuit. In some embodiments, the first post-decoder circuit of method 1000 includes post-decoder circuit 302.

[0244] In some embodiments, the first input signal of method 1000 includes at least one of input signals LS_IN or TRKLS_IN.

[0245] In some embodiments, the first decoder signal of method 1000 includes decoder signal DEC_X.

[0246] In operation 1004 of method 1000, an inverted first input signal is generated in response to a first input signal. In some embodiments, the first input signal and the inverted first input signal are in opposite phases.

[0247] In some embodiments, operation 1004 is performed by an inverter. In some embodiments, the inverter of method 1000 includes inverter 403.

[0248] In some embodiments, the inverted first input signal of method 1000 includes at least one of input signals LS_INB or TRKLS_INB.

[0249] In operation 1006 of method 1000, a first signal and a second signal are generated in response to at least the first input signal or the second input signal.

[0250] In some embodiments, operations 1006 and 1008 are performed by a level shifter. In some embodiments, the level shifter of method 1000 includes at least one of level shifters 404 or 604.

[0251] In some embodiments, the first signal of method 1000 includes at least signal OUTB. In some embodiments, the second signal of method 1000 includes at least signal FB.

[0252] In operation 1008 of method 1000, the leading edge of the word line signal is delayed in response to at least the first signal or the second signal. In some embodiments, the leading edge of the word line signal includes a rising edge or a falling edge.

[0253] In some embodiments, the word line signal of method 1000 includes at least word line signal WL'.

[0254] In some embodiments, the amount of delay of the leading edge of the word line signal is based on the voltage difference between a first power supply voltage and a second power supply voltage. In some embodiments, the first power supply voltage has a first swing. In some embodiments, the second power supply voltage has a second swing.

[0255] In some embodiments, the amount of delay of the leading edge of the word line signal includes delay DEL2. In some embodiments, the first power supply voltage includes power supply voltage VDD. In some embodiments, the second power supply voltage includes power supply voltage VDDM.

[0256] In operation 1010 of method 1000, a word line signal is generated in response to the first signal. In some embodiments, the word line signal and the first signal are in opposite phases.

[0257] In some embodiments, operation 1010 is performed by an inverter. In some embodiments, the inverter of method 1000 includes inverter 406.

[0258] By operating method 1000, Figure 1 memory circuit 100 of Figure 2 memory circuit 200 of Figure 3 memory circuit 300 of Figure 4 memory circuit 400 of Figure 6 memory circuit 600 of Figure 7 or at least one of memory circuit 700 of is operated to achieve the benefits discussed herein.

[0259] In some embodiments, one or more operations of method 1000 are not performed. Additionally, Figure 2 , Figure 4 and Figures 6 to 7 the various PMOS or NMOS transistors shown in with a particular dopant type (e.g., N-type or P-type) are for illustrative purposes. Embodiments of the present disclosure are not limited to a particular transistor type, and Figure 2 , Figure 4 and Figures 6 to 7 one or more of the PMOS or NMOS transistors shown in the PMOS or NMOS transistors may be replaced with corresponding transistors of different transistor / dopant types. Similarly, the low or high logic values of the various signals used in the above description are also for illustrative purposes. When activating and / or deactivating signals, embodiments of the present disclosure are not limited to particular logic values. Selecting different logic values is within the scope of the various embodiments. In Figure 2 , Figure 4 and Figures 6 to 7 selecting different numbers of inverters is within the scope of the various embodiments. In Figure 2 , Figure 4 and Figures 6 to 7 selecting different numbers of transistors is within the scope of the various embodiments.

[0260] One of ordinary skill in the art will readily see that one or more of the embodiments of the present disclosure achieve one or more of the above advantages. After reading the above specification, one of ordinary skill in the art will be able to implement the various changes, equivalents, and various other embodiments as broadly disclosed herein. Therefore, the protection granted herein is defined only by the definitions contained in the appended claims and their equivalents.

[0261] One aspect of this specification relates to a memory circuit. In some embodiments, the memory circuit includes a first inverter coupled to a first voltage source and configured to generate a first input signal in response to a second input signal, the first input signal being inverted with respect to the second input signal. In some embodiments, the memory circuit further includes a level shifter circuit coupled to at least the first inverter and a second voltage source different from the first voltage source and configured to receive at least the first input signal or the second input signal and generate a first signal and a second signal in response to at least the first input signal or the second input signal. In some embodiments, the memory circuit further includes a second inverter configured to generate a word line signal in response to the first signal. In some embodiments, the level shifter circuit is configured to delay a leading edge of the word line signal in response to at least the first signal or the second signal, the amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage having a first swing and a second power supply voltage having a second swing.

[0262] Another aspect of this specification relates to a memory circuit. The memory circuit includes a memory cell array and a word line driver coupled to the memory cell array. In some embodiments, the word line driver includes a first inverter coupled to a first voltage source and configured to generate a first input signal in response to a second input signal, the first input signal being inverted with respect to the second input signal. In some embodiments, the word line driver further includes a level shifter circuit coupled to at least the first inverter and a second voltage source different from the first voltage source and configured to receive at least the first input signal or the second input signal and generate a first signal and a second signal in response to at least the first input signal or the second input signal. In some embodiments, the word line driver further includes a second inverter configured to generate a word line signal in response to the first signal. In some embodiments, the level shifter circuit is configured to delay a leading edge of the word line signal in response to at least the first signal or the second signal, the amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage having a first swing and a second power supply voltage having a second swing.

[0263] Another aspect of the present specification relates to a method of operating a memory circuit. In some embodiments, the method includes: generating, by a first inverter, an inverted first input signal in response to a first input signal, the first input signal being inverted with respect to the inverted first input signal. In some embodiments, the method further includes: generating, by a voltage shifter circuit, a first signal and a second signal in response to at least the first input signal or a second input signal. In some embodiments, the method further includes: delaying, by the voltage shifter circuit, a leading edge of a word line signal in response to at least the first signal or the second signal, the amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage and a second power supply voltage, the first power supply voltage having a first swing and the second power supply voltage having a second swing. In some embodiments, the method further includes: generating, by a second inverter, a word line signal in response to the first signal, the word line signal being inverted with respect to the first signal.

[0264] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and architectures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

[0265] Example 1. A memory circuit, comprising:

[0266] A first inverter, coupled to a first voltage source and configured to generate a first input signal in response to a second input signal, the first input signal being inverted with respect to the second input signal;

[0267] A voltage shifter circuit, coupled to at least the first inverter or a second voltage source different from the first voltage source and configured to receive at least the first input signal or the second input signal and generate a first signal and a second signal in response to at least the first input signal or the second input signal; and

[0268] A second inverter, configured to generate a word line signal in response to the first signal;

[0269] wherein the voltage shifter circuit is configured to delay a leading edge of the word line signal in response to at least the first signal or the second signal, the amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage and a second power supply voltage, the first power supply voltage having a first swing and the second power supply voltage having a second swing.

[0270] Example 2. The memory circuit according to Example 1 further includes:

[0271] A post-decoder circuit, coupled to the first voltage source and the first inverter, and configured to generate the second input signal in response to a first decoder signal.

[0272] Example 3. The memory circuit according to Example 2, wherein the post-decoder circuit includes:

[0273] A first p-type transistor, including a first end configured to receive the first decoder signal, a second end of the first p-type transistor is coupled to the first voltage source, and a third end of the first p-type transistor is coupled to a first output node; and

[0274] A first n-type transistor, including a first end configured to receive the first decoder signal, a second end of the first n-type transistor is coupled to a reference voltage source, and a third end of the first n-type transistor is coupled to the first output node and the third end of the first p-type transistor.

[0275] Example 4. The memory circuit according to Example 1, wherein the level shifter circuit includes:

[0276] A first p-type transistor, including a first end configured to receive the second input signal, a second end of the first p-type transistor is coupled to the second voltage source, and a third end of the first p-type transistor is coupled to at least a first node;

[0277] A second p-type transistor, including a first end coupled to at least a second node and configured to receive the second signal, a second end of the second p-type transistor is coupled to the third end of the first p-type transistor and the first node, and a third end of the second p-type transistor is coupled to at least a third node; and

[0278] A first n-type transistor, including a first end coupled to the first end of the first P-type transistor and configured to receive the second input signal, a second end of the first n-type transistor is coupled to a reference voltage source, and a third end of the first n-type transistor is coupled to the third node and the third end of the second p-type transistor.

[0279] Example 5. The memory circuit according to Example 4, wherein the level shifter circuit further includes:

[0280] A third p-type transistor, including a first end coupled to the third node, a third end of the first n-type transistor, and a third end of the second p-type transistor and configured to receive the first signal, a second end of the third p-type transistor is coupled to the second voltage source, and a third end of the third p-type transistor is coupled to at least a fourth node;

[0281] A fourth p-type transistor, including a first end coupled to an output end of the first inverter and configured to receive the first input signal, a second end of the fourth p-type transistor is coupled to the fourth node and a third end of the third p-type transistor, and a third end of the fourth p-type transistor is coupled to the second node and a first end of the first p-type transistor; and

[0282] A second n-type transistor, including a first end coupled to an output end of the first inverter and a first end of the fourth p-type transistor and configured to receive the first input signal, a second end of the second n-type transistor is coupled to the reference voltage source, and a third end of the second n-type transistor is coupled to a third end of the fourth p-type transistor, the second node, and a first end of the first p-type transistor.

[0283] Example 6. The memory circuit according to Example 5, wherein the level shifter circuit further includes:

[0284] A fifth p-type transistor, including a first end coupled to a first end of the first P-type transistor and a first end of the first N-type transistor and configured to receive the second input signal, a second end of the fifth p-type transistor is coupled to the second voltage source and a second end of the first p-type transistor, and a third end of the fifth p-type transistor is coupled to the first node, a third end of the first p-type transistor, and a second end of the second p-type transistor.

[0285] Example 7. The memory circuit according to Example 4, wherein

[0286] The first p-type transistor further includes a first size,

[0287] The second p-type transistor further includes a second size,

[0288] The first n-type transistor further includes a third size, and

[0289] The first size is greater than the third size.

[0290] Example 8. The memory circuit according to Example 7, wherein the second size is greater than the third size.

[0291] Example 9. The memory circuit according to Example 8, wherein the first dimension is equal to the second dimension.

[0292] Example 10. The memory circuit according to Example 8, wherein the first dimension is different from the second dimension.

[0293] Example 11. The memory circuit according to Example 1, wherein the first inverter includes:

[0294] A first p-type transistor including a first terminal configured to receive the first input signal, a second terminal of the first p-type transistor being coupled to the first voltage source, and a third terminal of the first p-type transistor being coupled to a first output node; and

[0295] A first n-type transistor including a first terminal configured to receive the first input signal, a second terminal of the first n-type transistor being coupled to a reference voltage source, and a third terminal of the first n-type transistor being coupled to the first output node and the third terminal of the first p-type transistor.

[0296] Example 12. The memory circuit according to Example 1, wherein the second inverter includes:

[0297] A first p-type transistor including a first terminal configured to receive the first signal, a second terminal of the first p-type transistor being coupled to the second voltage source, and a third terminal of the first p-type transistor being coupled to a first output node; and

[0298] A first n-type transistor including a first terminal configured to receive the first signal, a second terminal of the first n-type transistor being coupled to a reference voltage source, and a third terminal of the first n-type transistor being coupled to the first output node and the third terminal of the first p-type transistor.

[0299] Example 13. A memory circuit, comprising:

[0300] A memory cell array; and

[0301] A word line driver coupled to the memory cell array, the word line driver including:

[0302] A first inverter coupled to a first voltage source and configured to generate a first input signal in response to a second input signal, the first input signal being inverted with respect to the second input signal;

[0303] A voltage shifter circuit, coupled to at least the first inverter or a second voltage source different from the first voltage source, and configured to receive at least the first input signal or the second input signal, and generate a first signal and a second signal in response to at least the first input signal or the second input signal; and

[0304] A second inverter, configured to generate a word line signal in response to the first signal;

[0305] Wherein, the voltage shifter circuit is configured to delay a leading edge of the word line signal in response to at least the first signal or the second signal, and an amount of delay of the leading edge of the word line signal is based on a voltage difference between a first power supply voltage and the second power supply voltage, the first power supply voltage has a first swing, and the second power supply voltage has a second swing.

[0306] Example 14. The memory circuit according to Example 13, wherein the voltage shifter circuit includes:

[0307] A first p-type transistor, including a first end configured to receive the second input signal, a second end of the first p-type transistor is coupled to the second voltage source, and a third end of the first p-type transistor is coupled to at least a first node;

[0308] A second p-type transistor, including a first end coupled to at least a second node and configured to receive the second signal, a second end of the second p-type transistor is coupled to the third end of the first p-type transistor and the first node, and a third end of the second p-type transistor is coupled to at least a third node; and

[0309] A first n-type transistor, including a first end coupled to the first end of the first P-type transistor and configured to receive the second input signal, a second end of the first n-type transistor is coupled to a reference voltage source, and a third end of the first n-type transistor is coupled to the third node and the third end of the second p-type transistor.

[0310] Example 15. The memory circuit according to Example 14, wherein the voltage shifter circuit further includes:

[0311] A third p-type transistor, including a first end coupled to the third node, the third end of the first n-type transistor and the third end of the second p-type transistor and configured to receive the first signal, a second end of the third p-type transistor is coupled to the second voltage source, and a third end of the third p-type transistor is coupled to at least a fourth node;

[0312] A fourth p-type transistor, including a first end coupled to the output end of the first inverter and configured to receive the first input signal, a second end of the fourth p-type transistor is coupled to the fourth node and a third end of the third p-type transistor, and a third end of the fourth p-type transistor is coupled to the second node and a first end of the first p-type transistor; and

[0313] A second n-type transistor, including a first end coupled to the output end of the first inverter and a first end of the fourth p-type transistor and configured to receive the first input signal, a second end of the second n-type transistor is coupled to the reference voltage source, and a third end of the second n-type transistor is coupled to a third end of the fourth p-type transistor, the second node and a first end of the first p-type transistor.

[0314] Example 16. The memory circuit according to Example 15, wherein the level shifter circuit further includes:

[0315] A fifth p-type transistor, including a first end coupled to a first end of the first P-type transistor and a first end of the first N-type transistor and configured to receive the second input signal, a second end of the fifth p-type transistor is coupled to the second voltage source and a second end of the first p-type transistor, and a third end of the fifth p-type transistor is coupled to the first node, a third end of the first p-type transistor and a second end of the second p-type transistor.

[0316] Example 17. The memory circuit according to Example 13, wherein the word line driver further includes:

[0317] A post decoder circuit, coupled to the first voltage source and the first inverter, and configured to generate the second input signal in response to a first decoder signal.

[0318] Example 18. The memory circuit according to Example 17, wherein the post decoder circuit includes:

[0319] A first p-type transistor, including a first end configured to receive the first decoder signal, a second end of the first p-type transistor is coupled to the first voltage source, and a third end of the first p-type transistor is coupled to a first output node; and

[0320] A first n-type transistor, including a first end configured to receive the first decoder signal, a second end of the first n-type transistor is coupled to the reference voltage source, and a third end of the first n-type transistor is coupled to the first output node and a third end of the first p-type transistor.

[0321] Example 19. A method of operating a memory circuit, the method comprising:

[0322] generating, by a first inverter, an inverted first input signal in response to a first input signal, the first input signal being inverted with respect to the inverted first input signal;

[0323] generating, by a voltage level shifter circuit, a first signal and a second signal in response to at least the first input signal or a second input signal;

[0324] delaying, by the voltage level shifter circuit, a leading edge of a word line signal in response to at least the first signal or the second signal, an amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage and a second power supply voltage, the first power supply voltage having a first swing, and the second power supply voltage having a second swing; and

[0325] generating, by a second inverter, the word line signal in response to the first signal, the word line signal being inverted with respect to the first signal.

[0326] Example 20. The method according to Example 19, further comprising:

[0327] generating, by a first post - decoder circuit, the first input signal in response to a first decoder signal.

Claims

1. A memory circuit, comprising: A first inverter, coupled to a first voltage source and configured to generate a first input signal in response to a second input signal, the first input signal being inverted with respect to the second input signal; A level shifter circuit, coupled to at least the first inverter or a second voltage source different from the first voltage source, and configured to receive at least the first input signal or the second input signal and generate a first signal and a second signal in response to at least the first input signal or the second input signal; And A second inverter, configured to generate a word line signal in response to the first signal; Wherein, the level shifter circuit is configured to delay a leading edge of the word line signal in response to at least the first signal or the second signal, and an amount of delay of the leading edge of the word line signal is based on a voltage difference between a first power supply voltage and a second power supply voltage, the first power supply voltage having a first swing, and the second power supply voltage having a second swing.

2. The memory circuit according to claim 1, further comprising: A post decoder circuit, coupled to the first voltage source and the first inverter and configured to generate the second input signal in response to a first decoder signal.

3. The memory circuit according to claim 2, wherein, The post decoder circuit includes: A first p-type transistor, including a first end configured to receive the first decoder signal, a second end of the first p-type transistor being coupled to the first voltage source, and a third end of the first p-type transistor being coupled to a first output node; and A first n-type transistor, including a first end configured to receive the first decoder signal, a second end of the first n-type transistor being coupled to a reference voltage source, and a third end of the first n-type transistor being coupled to the first output node and the third end of the first p-type transistor.

4. The memory circuit according to claim 1, wherein, The level shifter circuit includes: A first p-type transistor, including a first end configured to receive the second input signal, a second end of the first p-type transistor being coupled to the second voltage source, and a third end of the first p-type transistor being coupled to at least a first node; A second p-type transistor, including a first end coupled to at least a second node and configured to receive the second signal, a second end of the second p-type transistor being coupled to the third end of the first p-type transistor and the first node, and a third end of the second p-type transistor being coupled to at least a third node; and A first n-type transistor, including a first end coupled to the first end of the first P-type transistor and configured to receive the second input signal, a second end of the first n-type transistor being coupled to a reference voltage source, and a third end of the first n-type transistor being coupled to the third node and the third end of the second p-type transistor.

5. The memory circuit according to claim 4, wherein, The level shifter circuit further includes: A third p-type transistor, including a first end coupled to the third node, a third end of the first n-type transistor, and a third end of the second p-type transistor and configured to receive the first signal, a second end of the third p-type transistor is coupled to the second voltage source, and a third end of the third p-type transistor is coupled to at least a fourth node; A fourth p-type transistor, including a first end coupled to the output end of the first inverter and configured to receive the first input signal, a second end of the fourth p-type transistor is coupled to the fourth node and a third end of the third p-type transistor, and a third end of the fourth p-type transistor is coupled to the second node and a first end of the first p-type transistor; and A second n-type transistor, including a first end coupled to the output end of the first inverter and a first end of the fourth p-type transistor and configured to receive the first input signal, a second end of the second n-type transistor is coupled to the reference voltage source, and a third end of the second n-type transistor is coupled to a third end of the fourth p-type transistor, the second node, and a first end of the first p-type transistor.

6. The memory circuit according to claim 5, wherein, The level shifter circuit further includes: A fifth p-type transistor, including a first end coupled to a first end of the first P-type transistor and a first end of the first N-type transistor and configured to receive the second input signal, a second end of the fifth p-type transistor is coupled to the second voltage source and a second end of the first p-type transistor, and a third end of the fifth p-type transistor is coupled to the first node, a third end of the first p-type transistor, and a second end of the second p-type transistor.

7. The memory circuit according to claim 4, wherein The first p-type transistor further includes a first size, The second p-type transistor further includes a second size, The first n-type transistor further includes a third size, and The first size is greater than the third size.

8. The memory circuit according to claim 7, wherein, The second size is greater than the third size.

9. A memory circuit, including: A memory cell array; And A word line driver, coupled to the memory cell array, the word line driver includes: A first inverter, coupled to a first voltage source and configured to generate a first input signal in response to a second input signal, the first input signal being inverted with respect to the second input signal; A level shifter circuit, coupled to at least the first inverter or a second voltage source different from the first voltage source and configured to receive at least the first input signal or the second input signal and generate a first signal and a second signal in response to at least the first input signal or the second input signal; and A second inverter, configured to generate a word line signal in response to the first signal; Wherein, the level shifter circuit is configured to delay a leading edge of the word line signal in response to at least the first signal or the second signal, an amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage having a first swing and a second power supply voltage having a second swing.

10. A method of operating a memory circuit, the method comprising: generating, by a first inverter, an inverted first input signal in response to a first input signal, the first input signal being inverted with respect to the inverted first input signal; generating, by a level shifter circuit, a first signal and a second signal in response to at least the first input signal or a second input signal; delaying, by the level shifter circuit, a leading edge of a word line signal in response to at least the first signal or the second signal, an amount of delay of the leading edge of the word line signal being based on a voltage difference between a first power supply voltage and a second power supply voltage, the first power supply voltage having a first swing and the second power supply voltage having a second swing; and generating, by a second inverter, the word line signal in response to the first signal, the word line signal being inverted with respect to the first signal.

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