Etching method of semiconductor stack structure, method of manufacturing device, and apparatus

Abstract

The application provides an etching method of a semiconductor laminated structure, a manufacturing method of a device and equipment. The etching method comprises the following steps: using a first process gas to selectively etch a side wall of a first semiconductor layer in a semiconductor laminated structure, so that the side wall of the first semiconductor layer is recessed relative to a second semiconductor layer in a second direction, and the second direction is perpendicular to a first direction; wherein the first process gas comprises a first etching gas, the first etching gas comprises a first fluorine-containing gas and a second fluorine-containing gas; the etching selectivity ratio of the first fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer is higher than the etching selectivity ratio of the second fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer; and the etching rate of the second fluorine-containing gas to the first semiconductor layer is higher than the etching rate of the first fluorine-containing gas to the first semiconductor layer.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to an etching method for a semiconductor stacked structure, a manufacturing method for a semiconductor device, and semiconductor process equipment. Background Art

[0002] With the continuous advancement of Moore's Law and the development of semiconductor technology to the 3nm node, gate-all-around (GAA) transistors are considered to be an effective replacement for fin field-effect transistors (FinFETs).

[0003] The semiconductor stack structure of GAA FET is as follows Figure 1 and Figure 2 As shown, it is formed on the substrate 100, and the semiconductor stacked structure 200 can be multiple, and the multiple semiconductor stacked structures 200 are parallel to Figure 1 The semiconductor stacked structure 200 is arranged in the direction of the X1 axis, and includes a first semiconductor layer 201 and a second semiconductor layer 202 alternately stacked. The first semiconductor layer 201 includes, for example, Ge, and the second semiconductor layer 202 includes, for example, Si. In the GAA manufacturing process, it is necessary to Figure 1 On both sides of the X2 axis in the semiconductor stack structure 200, the sidewalls of the first semiconductor layer 201 or the second semiconductor layer 202 are selectively etched. Taking the etching of the first semiconductor layer 201 as an example, the morphology after etching is as follows: Figure 2 shown.

[0004] To reduce the subsequent negative impact on the device, it is necessary to have a very high selectivity between the first semiconductor layer 201 and the second semiconductor layer 202 relative to the other during the etching process to avoid or reduce damage to the channel. Currently, how to control the etching selectivity and etching rate of the first semiconductor layer / second semiconductor layer is an urgent problem to be solved. Summary of the Invention

[0005] The present invention aims to solve at least one of the technical problems existing in the prior art, and proposes an etching method for a semiconductor stacked structure, a manufacturing method for a semiconductor device, and a semiconductor process equipment, which can control the etching selectivity ratio and etching rate of the first semiconductor layer / second semiconductor layer.

[0006] To achieve the object of the present invention, a method for etching a semiconductor stacked structure is provided. The semiconductor stacked structure includes a first semiconductor layer and a second semiconductor layer alternately stacked in a first direction, the first semiconductor layer contains Ge, and the first semiconductor layer and the second semiconductor layer are made of different materials. The method includes:

[0007] Selectively etching the sidewalls of the first semiconductor layer in the semiconductor stacked structure using a first process gas so that the sidewalls of the first semiconductor layer are recessed relative to the second semiconductor layer in a second direction, where the second direction is perpendicular to the first direction;

[0008] Wherein, the first process gas includes a first etching gas, and the first etching gas includes a first fluorine-containing gas and a second fluorine-containing gas;

[0009] The etching selectivity of the first fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer is higher than the etching selectivity of the second fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer; and

[0010] An etching rate of the first semiconductor layer by the second fluorine-containing gas is higher than an etching rate of the first fluorine-containing gas on the first semiconductor layer.

[0011] In some embodiments, the first semiconductor layer is Si x Ge y , where 0.05≤y≤0.3, and x+y=1; and / or

[0012] The second semiconductor layer is one of Si, SiN, SiO, SiON, and SiCON.

[0013] In some embodiments, the first fluorine-containing gas includes F2 and / or ClF3, and the second fluorine-containing gas includes a fluorine-containing gas having a bond energy smaller than that of F2 or ClF3.

[0014] In some embodiments, the second fluorine-containing gas includes at least one of XeF2, XeF4, XeF6, KrF2, and BrF3.

[0015] In some embodiments, the first etching process includes a plurality of etching sub-steps, and the flow ratio of the first fluorine-containing gas to the second fluorine-containing gas in two adjacent etching sub-steps is different.

[0016] In some embodiments, the first process gas further includes a first auxiliary gas, and the first auxiliary gas contains at least one of hydrogen, oxygen, and nitrogen.

[0017] In some embodiments, the first auxiliary gas includes at least one of HF, O 2 , H 2 , and N 2 .

[0018] In some embodiments, the selective etching is a purely chemical etching.

[0019] In some embodiments, selectively etching the sidewall of the first semiconductor layer in the semiconductor stacked structure using a first process gas includes:

[0020] a pretreatment step of pretreating the sidewalls of the semiconductor stacked structure using the first auxiliary gas;

[0021] an etching step, etching the sidewall of the first semiconductor layer using the first etching gas;

[0022] Purge step, to purge the process chamber;

[0023] Repeat the pretreatment step, the etching step, and the purge step at least once.

[0024] In some embodiments, in the step of selectively etching the sidewall of the first semiconductor layer in the semiconductor stacked structure using a first process gas,

[0025] The temperature range of the wafer carrier is 0°C-80°C; and / or,

[0026] The flow rate of the first fluorine-containing gas is greater than 0 sccm and less than or equal to 1000 sccm; and / or,

[0027] The pressure of the process chamber is greater than or equal to 0.1 Torr and less than or equal to 10 Torr.

[0028] In some embodiments, the method further includes: performing plasma cleaning on the process chamber before or after performing the selective etching.

[0029] In some embodiments, before selectively etching the sidewall of the first semiconductor layer in the semiconductor stacked structure using the first process gas, the method further includes:

[0030] Pure chemical etching is used to remove the natural oxide layer on the sidewall surface of the semiconductor stacked structure.

[0031] In some embodiments, removing the natural oxide layer on the sidewall surface of the semiconductor stacked structure by pure chemical etching includes:

[0032] The natural oxide layer is etched using a second process gas, where the second process gas includes a second etching gas containing HF-pyridine.

[0033] In some embodiments, the second process gas further includes a second auxiliary gas, and the second auxiliary gas includes at least one of N2, Ar, He, and H2.

[0034] In some embodiments, in the step of removing the natural oxide layer on the sidewall surface of the semiconductor stacked structure:

[0035] The temperature range of the wafer carrier is 0°C-80°C; and / or,

[0036] The pressure of the process chamber is greater than or equal to 10 Torr and less than or equal to 40 Torr.

[0037] As another technical solution, the present invention further provides a method for manufacturing a semiconductor device, comprising:

[0038] forming a semiconductor stacked structure on a substrate, the semiconductor stacked structure comprising a first semiconductor layer and a second semiconductor layer alternately stacked in a first direction, the first semiconductor layer containing Ge, and the first semiconductor layer and the second semiconductor layer being made of different materials;

[0039] Etching the semiconductor stacked structure using the etching method provided by the present invention;

[0040] Filling a recessed space of the first semiconductor layer relative to the second semiconductor layer with an isolation layer;

[0041] forming a source region and a drain region on both sides of the semiconductor stacked structure along the second direction;

[0042] removing the first semiconductor layer;

[0043] A gate structure is formed around the second semiconductor layer.

[0044] In some embodiments, the process gas used in the step of removing the first semiconductor layer includes the first fluorine-containing gas and the second fluorine-containing gas.

[0045] As another technical solution, the present invention also provides a semiconductor process equipment, including: a front-end module, a load lock chamber, a transfer chamber and at least one first process module, the first process module is connected to the transfer chamber, the first process module is used to selectively etch a first semiconductor layer, and it includes a first controller, the first controller includes a processor and a memory, the memory stores a computer program, and when the computer program is executed by the processor, the above-mentioned etching method provided by the present invention is implemented.

[0046] In some embodiments, further comprising:

[0047] At least one second process module, the second process module is connected to the transfer chamber, the second process module includes a second controller, the second controller includes a processor and a memory, the memory stores a computer program, and when the computer program is executed by the processor, the above-mentioned etching method provided by the present invention is implemented.

[0048] The present invention has the following beneficial effects:

[0049] In the technical solutions of the semiconductor stack structure etching method, semiconductor device manufacturing method, and semiconductor process equipment provided by the present invention, a first process gas is used to selectively etch the sidewalls of a first semiconductor layer in the semiconductor stack structure, so that the sidewalls of the first semiconductor layer are recessed relative to the second semiconductor layer in a second direction. The first process gas includes a first etching gas, which includes a first fluorine-containing gas and a second fluorine-containing gas. The first fluorine-containing gas has a higher etching selectivity for the first semiconductor layer relative to the second semiconductor layer than the second fluorine-containing gas. Moreover, the second fluorine-containing gas has a higher etching rate for the first semiconductor layer than the first fluorine-containing gas. Thus, by using the first fluorine-containing gas and the second fluorine-containing gas in combination, not only can the etching selectivity of the first semiconductor layer / second semiconductor layer be improved to achieve selective etching of the sidewalls of the first semiconductor layer, but the etching rate of the first semiconductor layer can also be controlled to achieve a balance between the etching selectivity of the first semiconductor layer / second semiconductor layer and the etching rate of the first semiconductor layer, so that the profile of the recessed space formed after the selective etching of the sidewalls of the first semiconductor layer can meet requirements. In addition, by using the second fluorine-containing gas, high-speed etching of the first semiconductor layer can be achieved without using plasma or catalyst during the selective etching of the sidewall of the first semiconductor layer, thereby causing less damage to the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] Figure 1 is a vertical cross-sectional view of a semiconductor stacked structure of a GAA FET according to an embodiment of the present invention along a direction parallel to the X1 axis;

[0051] Figure 2 is a vertical cross-sectional view of a semiconductor stacked structure of a GAA FET according to an embodiment of the present invention, taken along a direction parallel to the X2 axis;

[0052] Figure 3 A three-dimensional diagram of a semiconductor stacked structure of a GAA FET according to an embodiment of the present invention;

[0053] Figure 4 A flowchart of step S200 of the method for etching a semiconductor stacked structure provided by an embodiment of the present invention;

[0054] Figure 5 This is a structural diagram of a first process module used to perform step S200 in an embodiment of the present invention;

[0055] Figure 6 A structural diagram of a related gas path connected to the first gas mixing chamber used in an embodiment of the present invention;

[0056] Figure 7This is a specific flow chart of step S200 in an embodiment of the present invention;

[0057] Figure 8 Detailed flowchart of step S100 and step S200 in an embodiment of the present invention;

[0058] Figure 9 Schematic diagram of the morphology of the semiconductor stack structure before removing the native oxide layer;

[0059] Figure 10 A flowchart of a method for manufacturing a semiconductor device provided by an embodiment of the present invention;

[0060] Figure 11 is a schematic diagram of the morphology of a semiconductor stacked structure after filling an isolation layer;

[0061] Figure 12 is a schematic diagram of the morphology of the semiconductor stacked structure after the source region and the drain region are formed;

[0062] Figure 13 is a schematic diagram of the morphology of the semiconductor stacked structure after the first semiconductor layer is removed;

[0063] Figure 14 is a schematic diagram of the morphology of the semiconductor stack structure after the gate structure is formed;

[0064] Figure 15 This is a structural diagram of a second process module used to perform step S100 in an embodiment of the present invention;

[0065] Figure 16 A structural diagram of a semiconductor process equipment provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0066] To make the purpose, technical solutions, and advantages of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0067] It should be understood by those skilled in the art that the embodiments of the present application are merely illustrations of the structures and methods for which the present application may be implemented in various forms. In addition, each example provided in conjunction with the various embodiments is intended to be illustrative, not restrictive. In addition, the drawings are not necessarily drawn to scale, and some features may be exaggerated to show the details of specific components. Therefore, the specific structural and functional details in the embodiments of the present application should not be interpreted as restrictive, but merely as a representative basis for teaching those skilled in the art to adopt the methods and structures of the embodiments of the present application in different ways. It should also be noted that identical and corresponding elements are represented by the same reference numerals.

[0068] In the following description, many specific details are set forth, such as specific structures, components, materials, dimensions, processing steps and techniques, in order to provide an understanding of the various embodiments of the present application. However, it should be understood by those skilled in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, well-known structures or processing steps are not described in detail to avoid obscuring the present application.

[0069] For the purposes of the following description, the terms "upper," "right," "left," "vertical," "horizontal," "top," "bottom," and their derivatives shall relate to the orientation of the structures and methods disclosed in the drawings of the specification. It will be understood that when an element as a layer, region, or substrate is referred to as being "on" another element, the element can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements between the two. It will also be understood that when an element is referred to as being "under" another element, the element can be directly under the other element or intervening elements may be present. Conversely, when an element is referred to as being "directly under" another element, there are no intervening elements between the two.

[0070] Figure 1 FIG. 4 is a vertical cross-sectional view of a semiconductor stacked structure of a GAA FET according to an embodiment of the present invention, taken along a direction parallel to the X1 axis. Figure 2 FIG. 1 is a vertical cross-sectional view of the semiconductor stacked structure of the GAA FET according to an embodiment of the present invention along a direction parallel to the X2 axis. Figure 1 and Figure 2 As shown, a semiconductor stacked structure is formed on a substrate 100. There may be multiple semiconductor stacked structures 200, and the multiple semiconductor stacked structures 200 are arranged parallel to the substrate 100. Figure 1 The semiconductor stack structures 200 are arranged in the direction of the X1 axis, and an isolation trench is formed in the substrate 100 between each two adjacent semiconductor stack structures 200 to form a shallow trench isolation (STI) structure 101. The STI structure 101 is used to electrically isolate adjacent GAA-FETs. Figure 3 shown. Figures 1 to 3 Only one of the semiconductor stacked structures 200 is shown.

[0071] In some embodiments, as Figures 1 to 3 As shown, after the preparation steps of the STI structure 101 are completed, it is necessary to further prepare the semiconductor stacked structure 200 along a direction parallel to the Figure 1 The protective layer 203 is formed on both sides and the top surface of the semiconductor stacked structure 200 and the STI structure 101 in the direction of the X1 axis. The protective layer 203 specifically covers the top surface of the semiconductor stacked structure 200 and the direction parallel to the X1 axis. Figure 1 The protective layer 203 protects the side surfaces of the semiconductor stacked structure 200 from being laterally etched during the etching of the substrate 100 in subsequent steps.

[0072] The semiconductor stacked structure 200 includes a first semiconductor layer 201 and a second semiconductor layer 202 alternately stacked. The first semiconductor layer 201 contains Ge, and the materials of the first semiconductor layer 201 and the second semiconductor layer 202 are different. In some embodiments, the first semiconductor layer 201 is removed in a subsequent step. The area where the second semiconductor layer 202 is located serves as the channel region of the GAA FET (e.g., Figure 14 The channel region 220 shown in FIG is used to realize the function of the semiconductor structure, the gate structure (such as Figure 14 The gate structure 600 shown in FIG is formed around each channel region 220 in a subsequent step. Those skilled in the art will appreciate that the present application is not limited thereto, and the second semiconductor layer 202 may also perform other functions in different application scenarios. The second semiconductor layer 202 and the first semiconductor layer 201 may be formed on the substrate surface by epitaxial growth.

[0073] For example, the material of the first semiconductor layer 201 may be Si. x Ge y , wherein 0.05≤y≤0.3, and x+y=1; the material of the second semiconductor layer 202 can be one of Si, SiN, SiO, SiON, and SiCON.

[0074] The substrate 100 includes a single crystal semiconductor layer on at least a portion of its surface. The material of the single crystal semiconductor layer includes, but is not limited to, Si, Ge, SiGe, GaAs, InSb, GaP, GaN, GaSb, InAlAs, InGaAs, GaSbP, GaAsSb, and InP. In some embodiments, the substrate 100 may be made of crystalline Si. Other layers may be present between the substrate 100 and the semiconductor stacked structure 200. The materials of the substrate 100 and the first semiconductor layer 201 or the second semiconductor layer 202 may be the same or different. When the materials of the substrate 100 and the first semiconductor layer 201 or the second semiconductor layer 202 are different, a buffer layer may be present between the substrate 100 and the semiconductor stacked structure 200. The buffer layer may be used to gradually shift the lattice constant from that of the substrate 100 to that of the first semiconductor layer 201 or the second semiconductor layer 202.

[0075] See also Figure 4 , and combined with Figures 1 to 3 , an embodiment of the present invention provides a method for etching a semiconductor stacked structure, comprising:

[0076] S200 , selectively etching the sidewalls of the first semiconductor layer 201 in the semiconductor stacked structure 200 using a first process gas, so that the first semiconductor layer 201 is recessed relative to the second semiconductor layer 202 in a second direction.

[0077] The second direction is perpendicular to the first direction. The first direction is the stacking direction of the first semiconductor layer 201 and the second semiconductor layer 202, for example Figures 1 to 3 The vertical direction in the vertical direction is the direction parallel to the Z axis, and the second direction is, for example, Figure 2 and Figure 3 The second direction is parallel to the X2 axis, for example, the arrangement direction of the plurality of semiconductor stacked structures 200 (ie, Figure 1 parallel to Figure 1 and Figure 3 The directions of the X1-axis and the Z-axis are perpendicular to each other.

[0078] Before performing step S200, the width of the first semiconductor layer 201 in the second direction is equal to the width of the second semiconductor layer 202 in the second direction; after completing step S200, as shown in FIG. Figure 2 and Figure 3As shown, the sidewalls of the first semiconductor layer 201 are recessed relative to the second semiconductor layer 202 in the second direction. That is, step S200 is used to selectively etch the sidewalls of the first semiconductor layer 201 in the second direction on both sides of the semiconductor stacked structure 200 along the second direction, thereby forming recessed spaces 206 between each adjacent second semiconductor layer 202. These recessed spaces 206 are used to fill and form isolation layers in subsequent steps. The depth of the recessed spaces 206 in the second direction is approximately 3 nm to 10 nm, more preferably approximately 5 nm.

[0079] In step S200, the first process gas includes a first etching gas, which includes a first fluorine-containing gas and a second fluorine-containing gas. The first fluorine-containing gas is used to increase the etching selectivity of the first semiconductor layer 201 relative to the second semiconductor layer 202, and the second fluorine-containing gas is used to increase the etching rate of the first semiconductor layer 201, thereby controlling the profile of the recessed space 206. Specifically, the etching selectivity of the first fluorine-containing gas for the first semiconductor layer 201 relative to the second semiconductor layer 202 is higher than the etching selectivity of the second fluorine-containing gas for the first semiconductor layer 201 relative to the second semiconductor layer 202; and the etching rate of the second fluorine-containing gas for the first semiconductor layer 201 is higher than the etching rate of the first fluorine-containing gas for the first semiconductor layer 202.

[0080] In addition, the first fluorine-containing gas is also used to improve the etching selectivity of the first semiconductor layer 201 relative to the protective layer 203. In some embodiments, the protective layer 203 may include a silicon nitride-based material formed by CVD (including LPCVD and PECVD), PVD, ALD or other suitable processes, such as silicon nitride, SiON, SiOCN or SiCN, and combinations thereof.

[0081] By using a first fluorine-containing gas and a second fluorine-containing gas in combination, the embodiment of the present invention can not only improve the etching selectivity of the first semiconductor layer / second semiconductor layer to achieve selective etching of the sidewalls of the first semiconductor layer, but also control the etching rate of the first semiconductor layer to achieve a balance between the etching selectivity of the first semiconductor layer / second semiconductor layer and the etching rate of the first semiconductor layer 201, thereby ensuring that the profile of the recessed space 206 formed after selectively etching the sidewalls of the first semiconductor layer 201 meets the requirements. In addition, in step S200, by using the second fluorine-containing gas, high-speed etching of the first semiconductor layer can be achieved without the use of plasma or catalyst during the selective etching of the sidewalls of the first semiconductor layer, thereby reducing damage to the device.

[0082] The first semiconductor layer 201 is Si x Ge y, the second semiconductor layer 202 is Si, by using a first fluorine-containing gas (for example, F2), the etching rate of Si x Ge y is 40 nm / min, and the selectivity is as high as 100:1. It can be considered that in the process of etching Si x Ge y , Si is basically not etched, so that the selective etching of the sidewall of the first semiconductor layer can be realized.

[0083] It should be noted that, taking the first semiconductor layer 201 as Si x Ge y and the second semiconductor layer 202 as Si as an example, at present, in the prior art, only in the case that the proportion of Ge element contained in Si x Ge y is large, a high etching selectivity of Si x Ge y / Si can be obtained, and by cooperating the use of the first fluorine-containing gas and the second fluorine-containing gas, a high etching selectivity of Si x Ge y / Si can also be obtained when the proportion of Ge element contained in Si x Ge y is small (for example, 0.05≤y≤0.3, and x+y=1), so that a high etching selectivity of SiGe / Si can be obtained in a wider range that the proportion of Ge element contained in SiGe is greater than or equal to 5% and less than or equal to 30%.

[0084] Further, in some embodiments, the second fluorine-containing gas can adopt a kind with a bond energy smaller than that of the first fluorine-containing gas, so that the second fluorine-containing gas is more easily dissociated, so that it can react with the first semiconductor layer 201 more quickly, so that the first semiconductor layer material in the recess can be etched better, and the intersection between the sidewall of the first semiconductor layer 201 constituting the recess space 206 and the surface of the adjacent second semiconductor layer 202 is closer to a right angle.

[0085] In some embodiments, the first fluorine-containing gas is F2 and / or ClF3. In this case, the second fluorine-containing gas may, for example, adopt a fluorine-containing gas with a bond energy smaller than that of F2 or ClF3.

[0086] In some embodiments, the second fluorine-containing gas is at least one of XeF2, XeF4, XeF6, KrF2, and BrF3.

[0087] In some embodiments, the first process gas may further include a carrier gas. For example, the carrier gas may be an inert gas, such as Ar and / or He. The percentage of the second fluorine-containing gas in the total flow of the carrier gas and the second fluorine-containing gas is greater than or equal to 0.01% and less than 10%. This allows the percentage within the range to satisfy the following corresponding relationship: the greater the percentage within the range, the greater the etching selectivity of the first semiconductor layer / the second semiconductor layer, and the lower the etching rate of the first semiconductor layer 201. Based on this corresponding relationship, the etching selectivity of the first semiconductor layer / the second semiconductor layer can be balanced with the etching rate of the first semiconductor layer 201 by selecting a suitable percentage within the above range, so that the profile of the recessed space 206 formed after selectively etching the sidewalls of the first semiconductor layer 201 can meet the requirements, such as the cross-section of the recessed space 206 in the vertical direction (for example Figure 2 The projected shape on the cross section of the recessed space 206 is a square with a specified width.

[0088] As mentioned above, the first semiconductor layer is Si x Ge y , taking Si as an example for the second semiconductor layer, currently, in the existing technology, a high SiGe / Si etching selectivity can only be obtained when the proportion of Ge elements in the first semiconductor layer is relatively large. However, the present application uses a second fluorine-containing gas and a carrier gas in combination, and controls the flow rate and ratio of the two, so that a high SiGe / Si etching selectivity can be obtained in a wide range where the proportion of Ge elements in SiGe is greater than or equal to 5% and less than or equal to 30%. That is, during the etching process of SiGe, Si is basically not etched. In addition, the present application can obtain a high Si for materials such as SiN, SiO, SiON, and SiCON. x Ge y Compared with the etching selectivity of these materials, that is, in etching Si x Ge y During the process, SiN, SiO, SiON, and SiCON were basically not etched.

[0089] Furthermore, in some embodiments, the percentage of the second fluorine-containing gas in the total flow of the carrier gas and the second fluorine-containing gas is between 1% and 5%. By selecting a suitable percentage within this range, the profile of the recessed space 206 formed after selectively etching the sidewalls of the first semiconductor layer 201 can be made to meet requirements.

[0090] In some embodiments, the carrier gas includes at least one of He, Ar, and N2.

[0091] In step S200, the first fluorine-containing gas can affect the etching selectivity of the first semiconductor layer / the second semiconductor layer. That is, the greater the flow rate of the first fluorine-containing gas, the higher the etching selectivity of the first semiconductor layer / the second semiconductor layer. The second fluorine-containing gas can affect the profile of the recessed space 206. That is, the greater the flow rate of the second fluorine-containing gas, the closer the profile of the recessed space 206 is to the target profile.

[0092] Furthermore, in some embodiments, the flow ratio of the first fluorine-containing gas to the second fluorine-containing gas is changed during step S200. In other words, the flow ratio can be adjusted during the process to more accurately control the etching selectivity of the first semiconductor layer / the second semiconductor layer and the profile of the recessed space 206.

[0093] Specifically, step S200 may include multiple etching sub-steps, and the flow ratio of the first fluorine-containing gas to the second fluorine-containing gas in two adjacent etching sub-steps is different; that is, the flow rates of the first fluorine-containing gas and the second fluorine-containing gas are switched multiple times through multiple etching sub-steps, so that the above-mentioned etching selectivity and the profile of the recessed space 206 can be more accurately controlled.

[0094] In some embodiments, in step S200 , the flow rate of the first fluorine-containing gas is greater than 0 sccm and less than or equal to 1000 sccm.

[0095] The inventors of the present invention have also discovered that, in the technical solution for selectively etching the first semiconductor layer 201, the pressure of the process chamber also affects the etching rate and the morphology of the semiconductor stack structure 200 after etching. Increasing the process chamber pressure can increase the etching rate, but excessive process chamber pressure can deteriorate the morphology of the semiconductor stack structure 200 after etching. In some optional implementations of the embodiments of the present invention, the pressure of the process chamber is greater than or equal to 0.1 Torr and less than or equal to 10 Torr. This can further control the etching rate of the first semiconductor layer 201.

[0096] In some embodiments, in step S200 , the temperature range of the wafer carrier is 0° C.-80° C. This temperature range is lower than that of the prior art. By adopting a lower temperature range, the selectivity of the second fluorine-containing gas (eg, XeF 2 gas) etching can be significantly improved.

[0097] In some embodiments, in step S200 , the etching equipment does not apply a bias voltage to generate plasma. That is, the sidewalls of the first semiconductor layer 201 in the semiconductor stacked structure 200 are chemically etched using the first process gas, and no plasma is generated during the process, thereby preventing damage.

[0098] Specifically, please see Figure 5 and Figure 6, the process chamber used to perform the above step S200 includes a first process module, which includes a first chamber body 300, a first gas inlet assembly and a first carrier 301, wherein the first carrier 301 is arranged in the first chamber body 300 for carrying wafers. The first gas inlet assembly includes a first spray cover 302 arranged on the top of the first chamber body 300, which is used to uniformly transport the process gas (and / or the plasma provided by the first remote plasma source (RPS) 313) into the first chamber body 300. On this basis, the first gas inlet assembly also includes a first gas mixing chamber 303, a first liquid or solid source 304 and a first gas cabinet 305, wherein the gas outlet end of the first gas path 309 for transporting the carrier gas is connected to the gas inlet end of the first gas mixing chamber 303; the first gas path 309 is provided with a third on-off valve 321 and a fourth on-off valve 322 and a mass flow controller 323 ( Figure 5 Not shown). The inlet end of the second gas path 311 for conveying other gases (for example, including but not limited to auxiliary gas, purge gas, etc.) is connected to the first gas cabinet 305, and the outlet end of the second gas path 311 is connected in parallel with the first gas path 309 to communicate with the inlet end of the first gas mixing chamber 303; the inlet end of the third gas path 310 for conveying the main etching gas (including the first fluorine-containing gas) is connected to the first gas cabinet 305, and the outlet end of the third gas path 310 is connected to the inlet end of the gas mixing path 312, and the outlet end of the first gas mixing chamber 303 is connected to the inlet end of the gas mixing path 312 through the connecting gas path 315, and the outlet end of the gas mixing path 312 is connected to the first spray cover 302, and the mixed first process gas is introduced into the first chamber body 300. It should be noted that, Figure 6 Not shown Figure 5 The mixed gas path 312, the connecting gas path 315, the third gas path 310, the second gas path 311 and the first gas cabinet 305.

[0099] In some embodiments, as Figure 6 As shown, a fifth gas path 320 is provided between the gas outlet of the first gas mixing chamber 303 and the connecting gas path 315 , and a first on-off valve 319 , a pressure switch 318 and a mass flow controller 317 are provided on the fifth gas path 320 . Figure 5 The fifth gas path 320 and the above-mentioned components thereon are not shown.

[0100] like Figure 5 and Figure 6As shown, the first mixing chamber 303 is communicated with a liquid or solid source 304 for generating the second fluorine-containing gas through a fourth gas path 316. A second on-off valve 325 is arranged on the fourth gas path 316. In addition, the first mixing chamber 303 is also communicated with the vacuum pump 307 through a bypass 314. A fifth on-off valve 324 is arranged on the bypass 314. The first chamber body 300 is also provided with an exhaust path and an exhaust valve 306 arranged on the exhaust path for controlling the pressure of the first chamber body 300, and an exhaust end of the exhaust path is communicated with the first vacuum pump 307. The first mixing chamber 303 and the first chamber body 300 can also be provided with a pressure sensor 307 and an OES (Optical Emission Spectrometer) 308.

[0101] Before the above step S200 is performed, first, the fifth on-off valve 324 is opened to extract the gas in the first mixing chamber 303 through the vacuum pump 307; then, according to the pressure of the first mixing chamber 303 detected by the pressure sensor 307, it is determined whether the current pressure of the first mixing chamber 303 is equal to a preset bottom pressure (a pressure required for forming a vacuum environment), if not, the gas extraction continues; if yes, the fifth on-off valve 324 is closed, the first on-off valve 319 is opened, and after a preset time (for example, 10s) elapses, the first on-off valve 319 is closed; then, the second on-off valve 325 is opened to introduce the second fluorine-containing gas into the first mixing chamber 303; according to the pressure of the first mixing chamber 303 detected by the pressure sensor 307, it is determined whether the current pressure of the first mixing chamber 303 is equal to a first preset pressure (for example, 1 Torr), if not, the introduction of the second fluorine-containing gas continues; if yes, the second on-off valve 325 is closed; after that, the third on-off valve 321 and the fourth on-off valve 322 are opened to introduce the carrier gas into the first mixing chamber 303, and the flow rate of the carrier gas in the first gas path 309 is controlled through the mass flow controller 323; according to the pressure of the first mixing chamber 303 detected by the pressure sensor 307, it is determined whether the current pressure of the first mixing chamber 303 is equal to a second preset pressure, which is greater than the first preset pressure, for example, the second preset pressure is 4 Torr, if not, the introduction of the carrier gas continues; if yes, the third on-off valve 312 and the fourth on-off valve 314 are closed, and the above step S200 is started to be performed.

[0102] By performing the above process before starting the above step S200, it can be ensured that the carrier gas and the second fluorine-containing gas are continuously introduced into the first chamber body 300 during the performance of the above step S200. Moreover, the percentage of the second fluorine-containing gas in the total flow rate of the carrier gas and the second fluorine-containing gas can be controlled through the pressure of the first mixing chamber 303 detected by the pressure sensor 307 and the flow rate detected by the mass flow controller 313.

[0103] When the above step S200 is started, the first on-off valve 319 is opened to connect the fifth gas path 320; at the same time, the second gas path 311, the third gas path 310, the connecting gas path 315 and the gas mixing gas path 312 are connected. At this time, the mixed gas containing the carrier gas and the second fluorine-containing gas in the first gas mixing chamber 303 enters the gas mixing gas path 312 through the fifth gas path 320 and the connecting gas path 315 in sequence. In the case of auxiliary gas, the auxiliary gas is introduced into the first gas mixing chamber 303 through the second gas path 311. When the carrier gas and the auxiliary gas are introduced at the same time, the carrier gas can be mixed with the auxiliary gas and then introduced into the first gas mixing chamber 303, and then mixed with the second fluorine-containing gas, and then introduced into the gas mixing gas path 312 through the fifth gas path 320 and the connecting gas path 315 in sequence. At the same time, the first fluorine-containing gas provided by the first gas cabinet 305 enters the mixing gas path 312 through the third gas path 310. The first fluorine-containing gas, the second fluorine-containing gas, the carrier gas and the auxiliary gas are mixed in the mixing gas path 312 and then enter the first chamber body 300 through the first spray cover 302.

[0104] The above step S200 is used to perform pure chemical etching on the sidewalls of the first semiconductor layer 201 (this process is a dry chemical etching process, and during the etching process, there is no plasma in the first chamber body 300).

[0105] In some embodiments, the first process module further includes a first remote plasma source (RPS) 313, which is used to perform plasma cleaning on the first chamber body 300 during process intervals to maintain stability during mass production. Specifically, the first remote plasma source (RPS) 313 is disposed above the first spray cover 302, and the outlet of the channel for conveying process gas and / or plasma in the first remote plasma source (RPS) 313 is connected to the air inlet of the first spray cover 302, and the outlet end of the mixed gas path 312 is connected to the inlet of the channel for conveying process gas and / or plasma in the first remote plasma source (RPS) 313. During the chamber cleaning process, gases such as H2, O2, and halogen can be ionized by the excitation of the first remote plasma source 313 to generate plasma, and the plasma enters the first chamber body 300 through the first spray cover 302, thereby removing deposits generated during the process on the remaining parts of the first chamber body 300 except the substrate surface.

[0106] In some embodiments, the first process gas further includes a first auxiliary gas for adjusting the etching selectivity of the first semiconductor layer / the second semiconductor layer. Furthermore, in some embodiments, the first auxiliary gas contains at least one of hydrogen, oxygen, and nitrogen. Furthermore, the first auxiliary gas, for example, includes at least one of HF, O2, H2, and N2. The addition of these auxiliary gases can further help improve the etching selectivity of the first semiconductor layer / the second semiconductor layer.

[0107] In some embodiments, referring to Figure 7 The step S200 can specifically include:

[0108] The pre-treatment step S2001 is to pre-treat the sidewall of the semiconductor stack structure 200 by using the first auxiliary gas;

[0109] The etching step S2002 is to etch the sidewall of the first semiconductor layer 201 by using the first etching gas;

[0110] The purging step S2003 is to purge the process chamber;

[0111] The pre-treatment step S2001, the etching step S2002 and the purging step S2003 are repeated at least once.

[0112] The pre-treatment step S2001 is to pre-treat the sidewall of the semiconductor stack structure 200 to remove the by-products on the sidewall of the semiconductor stack structure 200; in the pre-treatment step S2001, the first auxiliary gas is ionized to form plasma by the first remote plasma source (RPS) 313 and is delivered into the first chamber body 300 to etch the by-products on the sidewall of the semiconductor stack structure 200; the purging step S2003 is to purge the process chamber and the pipeline to further remove the by-products.

[0113] Specifically, in the purging step S2003, the purge gas enters the channel for delivering the process gas and / or plasma in the first remote plasma source (RPS) 313 through the second gas path 311, the first mixed gas chamber 303, the connecting gas path 315 and the mixed gas path 312 in sequence, the first auxiliary gas is ionized to form plasma by the first remote plasma source (RPS) 313 and is delivered into the first chamber body 300.

[0114] In some embodiments, referring to Figure 8 The pre-treatment step S2001, the etching step S2002 and the purging step S2003 are repeated at least once. By controlling the number of cycles of the pre-treatment step S2001, the etching step S2002 and the purging step S2003, the etching morphology can be better controlled.

[0115] In some embodiments, referring to Figure 8 Before the step S200, the etching method further includes:

[0116] S100, removing the natural oxide layer on the sidewall surface of the semiconductor stack structure 200 by using pure chemical etching;

[0117] Specifically, Figure 9The figure shows the morphology of the natural oxide layer 205 before being removed on the semiconductor stacked structure 200. The above-mentioned pure chemical etching is, for example, a dry chemical etching process.

[0118] In some embodiments, the above step S100 specifically includes:

[0119] The native oxide layer is etched using a second process gas.

[0120] In some embodiments, the second process gas includes a second etching gas containing HF-pyridine.

[0121] In some embodiments, the second process gas further includes a second auxiliary gas, wherein the second auxiliary gas includes at least one of N2, Ar, He, and H2.

[0122] In some embodiments, in the above step S100 , the temperature range of the wafer carrier is 0° C.-80° C.

[0123] In some embodiments, in step S100 , the pressure of the process chamber is greater than or equal to 10 Torr and less than or equal to 40 Torr.

[0124] In some embodiments, in step S100 , the etching equipment does not apply a bias voltage for generating plasma, that is, the native oxide layer is purely chemically etched using the second process gas, and no plasma is generated during the process, thereby causing no damage.

[0125] As another technical solution, an embodiment of the present invention further provides a method for manufacturing a semiconductor device, such as Figure 10 Shown, including:

[0126] S301, forming a semiconductor stacked structure 200 on a substrate, wherein the semiconductor stacked structure 200 includes a first direction (ie, parallel to Figure 1 First semiconductor layers 201 and second semiconductor layers 202 alternately stacked in the direction of the Z axis in FIG;

[0127] The first semiconductor layer 201 contains Ge, and the first semiconductor layer 201 and the second semiconductor layer 202 are made of different materials.

[0128] In some embodiments, the above step S301 may specifically include: first, using a patterned hard mask layer, etching the first semiconductor layer 201, the second semiconductor layer 202 and the substrate 100 to obtain a semiconductor stacked structure 200, and forming isolation trenches in the substrate 100 on both sides of the semiconductor stacked structure 200; then, forming shallow trench isolation structures 101 in the isolation trenches on both sides of the semiconductor stacked structure 200; and then, forming a plurality of trenches in the semiconductor stacked structure 200 along a line parallel to the substrate 100. Figure 1 and Figure 3The two sides in the direction of the X1 axis and the top surface of the semiconductor layer structure 200 form a protective layer 203 covering the semiconductor layer structure 200 and the substrate 100.

[0129] S302, using the above-mentioned etching method provided by the embodiment of the present application, etching the semiconductor layer structure 200.

[0130] As shown in Figure 2 and Figure 3 , the above-mentioned step S302 is used to selectively etch the sidewall of the first semiconductor layer 201 in the semiconductor layer structure 200 in the second direction (i.e., parallel to the direction of the X2 axis in the Y-Z plane) so that the first semiconductor layer 201 is recessed in the second direction relative to the second semiconductor layer 202. Figure 2

[0131] S303, as shown in Figure 11 , the isolation layer 204 is used to fill the space recessed by the first semiconductor layer 201 relative to the second semiconductor layer 202, i.e., the recessed space 206 shown in Figure 2 and Figure 3 .

[0132] S304, as shown in Figure 12 , the source region and the drain region 500 are formed on both sides of the semiconductor layer structure 200 in the above-mentioned second direction.

[0133] S305, as shown in Figure 13 , the first semiconductor layer 201 is removed.

[0134] S306, as shown in Figure 14 , the gate structure 600 is formed around the second semiconductor layer 202.

[0135] In some embodiments, as shown in Figure 14 , the second semiconductor layer 202 constitutes the channel region 220 of the GAA FET, and the gate structure 600 includes a gate dielectric layer 602 arranged around the second semiconductor layer 202 and a gate electrode layer 601 arranged around the gate dielectric layer 602.

[0136] As another technical solution, the embodiment of the present application also provides another semiconductor process equipment, please refer to Figure 15 , the above-mentioned step S100 is carried out in the second process module shown in Figure 15 . As an example, it includes a second cavity body 400, a second gas inlet assembly and a second bearing device 401, wherein the second bearing device 401 is arranged in the second cavity body 400 and is used to bear the wafer.

[0137] ​The second gas inlet assembly includes a second shower cover 402 disposed on the top of the second chamber body 400 for uniformly delivering process gas and / or plasma provided by a second remote plasma source (RPS) 415 into the second chamber body 400 .

[0138] In some embodiments, the second air inlet assembly includes a first pipeline for direct communication with the source 403 and / or the steam generator 404. For example, in some specific embodiments, the first pipeline serves as an edge air inlet and includes a seventh air line 412 and an eighth air line 413, each of which is connected to the source 403 and the steam generator 404 at one end, respectively, and to the edge air inlet of the second spray cover 402 at the other end. In some embodiments, the source 403 may also be an HF-pyridine source or other fluorine-based source. The steam generator 404 is configured to provide one of H2O and CH3OH vapor.

[0139] In some embodiments, the second gas inlet assembly further includes a second pipeline, which is connected to the central gas inlet of the second spray cover 402. In some specific embodiments, the second pipeline serves as a central gas inlet pipeline and includes a fifth gas line 410 and a sixth gas line 411. One end of the fifth gas line 410 and the sixth gas line 411 are connected to the second gas cabinet 405, and the other end is connected to the central gas inlet of the second spray cover 402. In some embodiments, the fifth gas line 410 is used to transport HF gas, while the sixth gas line 411 is used to transport other gases (including auxiliary gas, purge gas, etc.).

[0140] In some embodiments, the second chamber body 400 is further provided with an exhaust line and an exhaust valve 406 disposed on the exhaust line for controlling the chamber pressure. The outlet end of the exhaust line is connected to a second vacuum pump 407. In addition, the source 403 is also connected to the second vacuum pump 407 via a second bypass 414.

[0141] In some embodiments, the second process module further includes a second remote plasma source (RPS) 415 for performing plasma cleaning on the second chamber body 400 during process intervals to maintain stability during mass production. Specifically, the second remote plasma source (RPS) 415 is disposed above the second spray cover 402, and the outlet of the channel for conveying process gas and / or plasma in the second remote plasma source (RPS) 415 is connected to the central gas inlet of the second spray cover 402. The other ends of the fifth gas path 410 and the sixth gas path 411 are connected to the inlet of the channel for conveying process gas and / or plasma in the second remote plasma source (RPS) 415. During the chamber cleaning process, gases such as H2, O2, and halogen can be ionized by the excitation of the remote plasma source 415 to generate plasma. The plasma enters the second chamber body 400 through the second spray cover 402, thereby removing deposits generated during the process on the remaining parts of the second chamber body 400 except for the substrate surface.

[0142] As another technical solution, Figure 16 As shown, an embodiment of the present invention further provides a semiconductor process equipment, which includes a front-end module 70, a load lock chamber 60, a transfer chamber 50 and at least one process module; the process module is used to perform the above-mentioned at least one process flow.

[0143] like Figure 16 As shown, in some embodiments, multiple process modules are provided, for example: including a first process module 10, a second process module 20, a third process module 30 and a fourth process module 40; the second process module 20 and the first process module 10 are respectively used to execute step S100 and step S200 in the above embodiments, and the first process module 10 can also be used to execute the etching process in the above step 305; the third process module 30 and the fourth process module 40 can be selected according to process requirements, for example, they can be process modules that are the same as the first process module 10 or the second process module 20, or they can be other process modules, which are not limited here.

[0144] In the prior art, the removal of the natural oxide layer on the sidewall surface of the semiconductor stack structure is generally carried out using a wet etching process. After the process is completed, the wafer is placed in an etching chamber for etching. However, in the process of transferring the wafer with the natural oxide layer removed to the etching chamber, due to the long transfer time, a new natural oxide layer is often re-formed on the surface of the semiconductor stack structure, thereby affecting the performance of subsequent devices. To solve this problem, the embodiment of the present invention uses a second process module 20 to perform the above-mentioned step S100, that is, in the second process module 20, pure chemical etching is used to remove the natural oxide layer on the sidewall surface of the semiconductor stack structure 200. In this way, the wafer with the natural oxide layer removed in the second process module 20 can be transferred by a vacuum robot (not shown in the figure) in the transfer chamber 50 to the first process module 10 to perform step S200. This process is carried out in a vacuum environment, thereby avoiding the wafer with the natural oxide layer removed from being exposed to the atmospheric environment. At the same time, the transfer path and transfer time can be shortened, thereby improving process efficiency.

[0145] The semiconductor process equipment provided by an embodiment of the present invention can integrate different process modules into the same equipment. The first process module 10, the second process module 20, the third process module 30 and the fourth process module 40 are respectively coupled with the transfer chamber 50, and can transfer the wafer in one of the process modules to another process module through the vacuum robot in the transfer chamber 50. During the transfer process between the two process modules, since the wafer only passes through the transfer chamber in a vacuum state, there is no need for a vacuum-atmospheric environment conversion, thereby greatly improving work efficiency and process consistency.

[0146] In some specific embodiments, the transfer chamber 50 is a hexagonal structure, the two load lock chambers 60 are located at two adjacent sides of the transfer chamber 50, the first process module 10 and the third process module 30 are respectively arranged opposite to the two load lock chambers 60, and the first process module 10 is located between the second process module 20 and the third process module 30.

[0147] In some specific embodiments, the first process module 10 can be, for example, Figure 5 In other specific embodiments, the second process module 20 can be, for example, Figure 15 The structure shown.

[0148] The first process module 10 further includes a first controller, which includes at least one processor and at least one memory. The memory stores a computer program, and when the computer program is executed by the processor, step S200 in the etching method of the semiconductor stacked structure is implemented.

[0149] The second process module 20 further includes a second controller, which includes at least one processor and at least one memory. The memory stores a computer program, and when the computer program is executed by the processor, step S100 in the above-mentioned method for manufacturing a semiconductor device is implemented.

[0150] Exemplarily, both the first controller and the second controller may be a host computer or a slave computer.

[0151] The semiconductor process equipment integrating multiple process modules in the above embodiment can greatly improve the manufacturing efficiency of devices.

[0152] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A method for etching a semiconductor stacked structure, characterized in that: The semiconductor stacked structure includes a first semiconductor layer and a second semiconductor layer alternately stacked in a first direction, the first semiconductor layer contains Ge, and the first semiconductor layer and the second semiconductor layer are made of different materials. The method includes: Selectively etching the sidewalls of the first semiconductor layer in the semiconductor stacked structure using a first process gas so that the sidewalls of the first semiconductor layer are recessed relative to the second semiconductor layer in a second direction, where the second direction is perpendicular to the first direction; Wherein, the first process gas includes a first etching gas, and the first etching gas includes a first fluorine-containing gas and a second fluorine-containing gas; The etching selectivity of the first fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer is higher than the etching selectivity of the second fluorine-containing gas to the first semiconductor layer relative to the second semiconductor layer; and An etching rate of the first semiconductor layer by the second fluorine-containing gas is higher than an etching rate of the first fluorine-containing gas on the first semiconductor layer.

2. The etching method according to claim 1, wherein: The first semiconductor layer is Si x Ge y , where 0.05≤y≤0.3, and x+y=1; and / or The second semiconductor layer is one of Si, SiN, SiO, SiON, and SiCON.

3. The etching method according to claim 1, wherein: The first fluorine-containing gas includes F2 and / or ClF3, and the second fluorine-containing gas includes a fluorine-containing gas having a bond energy smaller than that of F2 or ClF3.

4. The etching method according to claim 3, wherein: The second fluorine-containing gas includes XeF2, XeF4, XeF 6、 At least one of KrF2, BrF3.

5. The etching method according to claim 1, wherein: The first etching process includes a plurality of etching sub-steps, and the flow ratio of the first fluorine-containing gas to the second fluorine-containing gas in two adjacent etching sub-steps is different.

6. The etching method according to claim 1, wherein: The first process gas further includes a first auxiliary gas, and the first auxiliary gas contains at least one of hydrogen, oxygen, and nitrogen.

7. The etching method according to claim 6, characterized in that: The first auxiliary gas includes at least one of HF, O2, H2, and N2.

8. The etching method according to claim 1, wherein: The selective etching is pure chemical etching.

9. The etching method according to claim 6, wherein: Selectively etching the sidewall of the first semiconductor layer in the semiconductor stacked structure using a first process gas includes: a pretreatment step of pretreating the sidewalls of the semiconductor stacked structure using the first auxiliary gas; an etching step, etching the sidewall of the first semiconductor layer using the first etching gas; Purge step, to purge the process chamber; Repeat the pretreatment step, the etching step, and the purge step at least once.

10. The etching method according to claim 1, wherein: In the step of selectively etching the sidewall of the first semiconductor layer in the semiconductor stacked structure using a first process gas, The temperature range of the wafer carrier is 0°C-80°C; and / or, The flow rate of the first fluorine-containing gas is greater than 0 sccm and less than or equal to 1000 sccm; and / or, The pressure of the process chamber is greater than or equal to 0.1 Torr and less than or equal to 10 Torr.

11. The etching method according to claim 1, wherein: Also includes: Before or after performing the selective etching, the process chamber is plasma cleaned.

12. The etching method according to any one of claims 1 to 11, characterized in that: Before selectively etching the sidewall of the first semiconductor layer in the semiconductor stacked structure using the first process gas, the method further includes: Pure chemical etching is used to remove the natural oxide layer on the sidewall surface of the semiconductor stacked structure.

13. The etching method according to claim 12, wherein: The step of removing the natural oxide layer on the sidewall surface of the semiconductor stacked structure by pure chemical etching comprises: The natural oxide layer is etched using a second process gas, where the second process gas includes a second etching gas containing HF-pyridine.

14. The etching method according to claim 13, characterized in that: The second process gas further includes a second auxiliary gas, and the second auxiliary gas includes at least one of N2, Ar, He, and H2.

15. The etching method according to claim 12, wherein: In the step of removing the natural oxide layer on the sidewall surface of the semiconductor stacked structure: The temperature range of the wafer carrier is 0°C-80°C; and / or, The pressure of the process chamber is greater than or equal to 10 Torr and less than or equal to 40 Torr.

16. A method for manufacturing a semiconductor device, characterized in that: include: forming a semiconductor stacked structure on a substrate, the semiconductor stacked structure comprising a first semiconductor layer and a second semiconductor layer alternately stacked in a first direction, the first semiconductor layer containing Ge, and the first semiconductor layer and the second semiconductor layer being made of different materials; Etching the semiconductor stacked structure using the etching method according to any one of claims 1 to 15; Filling a recessed space of the first semiconductor layer relative to the second semiconductor layer with an isolation layer; forming a source region and a drain region on both sides of the semiconductor stacked structure along the second direction; removing the first semiconductor layer; A gate structure is formed around the second semiconductor layer.

17. The manufacturing method according to claim 16, characterized in that: The process gas used in the step of removing the first semiconductor layer includes the first fluorine-containing gas and the second fluorine-containing gas.

18. A semiconductor process equipment, characterized in that: include: A front-end module, a load lock chamber, a transfer chamber and at least one first process module, wherein the first process module is connected to the transfer chamber, and the first process module is used to selectively etch a first semiconductor layer, and includes a first controller, the first controller includes a processor and a memory, the memory stores a computer program, and when the computer program is executed by the processor, it implements the etching method described in any one of claims 1 to 11.

19. The semiconductor process equipment according to claim 18, wherein: Also includes: At least one second process module, the second process module is connected to the transfer chamber, the second process module includes a second controller, the second controller includes a processor and a memory, the memory stores a computer program, and when the computer program is executed by the processor, it implements the etching method described in any one of claims 12-15.

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