Ultrathin DFN or QFN packaging structure and manufacturing method thereof

Abstract

The invention discloses an ultrathin DFN or QFN packaging structure and a manufacturing method thereof. The manufacturing method of the ultrathin DFN or QFN packaging structure comprises the following steps: pasting a mask on the surface of a carrier plate; exposing a required pattern on the upper surface of the carrier plate through exposure and development; forming a plurality of pins on the carrier plate after exposure and development; the mask is removed; grinding the wafer to obtain a chip with a limiting structure; mounting a chip on the upper surface of the carrier plate; welding the two ends of the lead with the chip and the pin respectively; a plastic package body wrapping the chip, the pins, the limiting structures and the leads is formed above the carrier plate through plastic package by using a plastic package material; the carrier plate is separated from the plastic package body, so that the lower surfaces of the pins and the chip are exposed out of the plastic package body; and cutting the plastic package body after the carrier plate is removed to obtain a plurality of independent DFN or QFN package products, the packaging mode of removing the base islands is adopted, so that the overall thickness of the products is thinner, and the market demand of the ultrathin DFN or QFN package structure is met.

Description

Technical Field

[0001] The present invention relates to the technical field of chip integrated circuit packaging, and particularly relates to an ultra-thin DFN or QFN packaging structure and a manufacturing method thereof. Background Art

[0002] Conventional DFN or QFN packaging structures mainly consist of a lead frame, a chip, leads, and a plastic package. The lead frame has pins and a base island, the chip is bonded to the base island, and the chip is electrically connected to the pins through the leads. However, in traditional packaging methods, usually, the lead frame, the chip, the pins, and the leads are coated with a plastic package. The overall thickness of the product is affected by the base island and the chip, resulting in a large thickness of the current DFN or QFN packaging structure, which is difficult to meet the market demand for ultra-thin DFN or QFN packaging structures. In addition, due to the limitation of the base island, the heat dissipation performance and electrical conductivity of the chip are affected, and the product performance is poor. Summary of the Invention

[0003] Aiming at the deficiencies existing in the prior art, the present invention provides an ultra-thin DFN or QFN packaging structure and a manufacturing method thereof, which adopt a packaging method of removing the base island, making the overall thickness of the product thinner and meeting the market demand for ultra-thin DFN or QFN packaging structures.

[0004] To achieve the above object, the present invention adopts the following technical solutions:

[0005] An ultra-thin DFN or QFN manufacturing method includes the following steps:

[0006] Step 1: Mask pasting, pasting a mask on the surface of a carrier board;

[0007] Step 2: Exposure and development, exposing the required pattern on the upper surface of the carrier board through exposure and development;

[0008] Step 3: Pin forming, forming a plurality of pins on the carrier board after exposure and development;

[0009] Step 4: Mask removal, removing the mask still attached to the carrier board;

[0010] Step 5: Wafer grinding and scribing, performing grinding and scribing on the wafer to obtain a chip with a limiting structure;

[0011] Step 6: Chip installation, placing the chip in a receiving groove surrounded by the carrier board and a plurality of pins, and mounting the chip on the upper surface of the carrier board;

[0012] Step 7: Lead soldering, soldering both ends of the lead to the chip and the pins respectively;

[0013] Step 8: Plastic encapsulation, plastic encapsulating above the carrier board with a plastic encapsulation material to form a plastic package covering the chip, the pins, the limiting structure, and the leads;

[0014] Step Nine: Carrier removal, separating the carrier from the plastic package body to expose the lower surfaces of the pins and the chip outside the plastic package body;

[0015] Step Ten: Cutting and separating, cutting the plastic package body after removing the carrier to obtain a number of independent DFN or QFN package products.

[0016] By successively adopting steps such as mask pasting, exposure and development, pin forming, mask removal, wafer scribing, chip mounting, wire bonding, plastic encapsulation, carrier removal, cutting and separating, etc., a DFN or QFN package structure without a base island is obtained, so that the overall thickness of the product is thinner, meeting the market demand for ultra-thin DFN or QFN package structures; in addition, the chip is exposed, so that the heat of the chip and the electricity at the bottom of the chip do not need to be conducted to the outside through the base island, and the chip can obtain better heat dissipation performance and electrical conductivity, and the product performance is better.

[0017] In one implementation manner, in Step One, the mask is pasted on the upper surface of the carrier.

[0018] In one implementation manner, in Step Two, the exposed pattern is a pin pattern.

[0019] In one implementation manner, in Step Three, the pins protruding from the upper surface of the carrier are formed by electroplating at the pin pattern.

[0020] In one implementation manner, the upper surface of the pin is not higher than the upper surface of the chip.

[0021] In one implementation manner, in Step Nine, the carrier is separated from the plastic package body by a peeling method.

[0022] In one implementation manner, in Step Ten, the pins are exposed on the side surface of the plastic package body.

[0023] In one implementation manner, the height h of the plastic package body is 0.15 mm to 0.3 mm.

[0024] An ultra-thin DFN or QFN package structure is prepared by using the above ultra-thin DFN or QFN manufacturing method. The ultra-thin DFN or QFN package structure includes a chip, pins and a plastic package body. The chip is electrically connected to the pins through wires. The plastic package body covers the chip, pins and wires. The lower surface of the chip is exposed outside the plastic package body, and the lower surface and / or side surface of the pins are exposed outside the plastic package body.

[0025] Compared with the prior art, the present invention has obvious advantages and beneficial effects. Specifically, by successively adopting steps such as mask pasting, exposure and development, lead forming, mask removal, wafer scribing, chip mounting, wire bonding, plastic encapsulation, carrier removal, and cutting and separation, a DFN or QFN package structure without a base island is obtained, thereby making the overall thickness of the product thinner and meeting the market demand for ultra-thin DFN or QFN package structures; in addition, the chip is exposed, so that the heat of the chip and the electrical properties at the bottom of the chip do not need to be conducted to the outside through the base island, and the chip can obtain better heat dissipation performance and electrical conductivity, and the product performance is better.

[0026] To more clearly elaborate on the structural features, technical means, and specific purposes and functions achieved by the present invention, the following further details the present invention in conjunction with the drawings and specific embodiments: BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 is a flowchart of the method of the present invention;

[0028] Figure 2 is a schematic diagram of mask pasting in the first embodiment of the present invention;

[0029] Figure 3 is a schematic diagram of exposure and development in the first embodiment of the present invention;

[0030] Figure 4 is a schematic diagram of lead forming in the first embodiment of the present invention;

[0031] Figure 5 is a schematic diagram of mask removal in the first embodiment of the present invention;

[0032] Figure 6 is a schematic diagram of the chip structure in the first embodiment of the present invention;

[0033] Figure 7 is a schematic diagram of chip mounting in the first embodiment of the present invention;

[0034] Figure 8 is a schematic diagram of wire bonding in the first embodiment of the present invention;

[0035] Figure 9 is a schematic diagram of plastic encapsulation in the first embodiment of the present invention;

[0036] Figure 10 is a schematic diagram of carrier removal in the first embodiment of the present invention;

[0037] Figure 11 is a schematic diagram of cutting and separation in the second embodiment of the present invention;

[0038] Figure 12 is a schematic diagram of mask pasting in the second embodiment of the present invention;

[0039] Figure 13 It is a schematic diagram of exposure and development of the second embodiment of the present invention;

[0040] Figure 14 It is a schematic diagram of pin forming of the second embodiment of the present invention;

[0041] Figure 15 It is a schematic diagram of mask removal of the second embodiment of the present invention;

[0042] Figure 16 It is a schematic diagram of the chip structure of the second embodiment of the present invention;

[0043] Figure 17 It is a schematic diagram of chip installation of the second embodiment of the present invention;

[0044] Figure 18 It is a schematic diagram of lead soldering of the second embodiment of the present invention;

[0045] Figure 19 It is a schematic diagram of plastic encapsulation of the second embodiment of the present invention;

[0046] Figure 20 It is a schematic diagram of carrier removal of the second embodiment of the present invention;

[0047] Figure 21 It is a schematic diagram of cutting and separation of the second embodiment of the present invention.

[0048] Explanation of the reference numerals in the drawings:

[0049] 10 - Carrier, 11 - Mask, 111 - First mask, 112 - Second mask, 12 - Pattern, 121 - Pin pattern, 122 - Non - pin pattern, 13 - Pin, 14 - Chip, 141 - Limiting structure, 142 - Step, 15 - Accommodating groove, 16 - Adhesive material, 17 - Lead, 18 - Plastic package, 19 - Encapsulated product. Detailed implementation manners

[0050] In the description of the present invention, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the invention and simplifying the description, rather than indicating or implying that the indicated position or element must have a specific orientation, be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation to the present invention.

[0051] In the description of the present invention, it should be noted that, unless otherwise clearly specified and defined, the terms "installation", "connection", and "coupling" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, and it can be the communication inside two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0052] As Figure 1-11 shown, the present invention discloses a method for manufacturing an ultra-thin DFN or QFN. In the first embodiment, the method for manufacturing the ultra-thin DFN or QFN includes the following steps:

[0053] Step 1: Mask 11 pasting, paste mask 11 on the surface of carrier 10;

[0054] Step 2: Exposure and development, expose the required pattern 12 on the upper surface of carrier 10 through exposure and development;

[0055] Step 3: Pin 13 forming, form a plurality of pins 13 on the carrier 10 after exposure and development. Among them, a plurality of pins 13 are formed on both the left and right sides of the carrier 10;

[0056] Step 4: Mask 11 removing, remove the mask 11 still attached to the carrier 10;

[0057] Step 5: Wafer grinding and scribing, perform grinding and scribing on the wafer to obtain a chip 14 with a limiting structure 141;

[0058] Step 6: Chip 14 installation, place the chip 14 in the accommodation groove 15 surrounded by the carrier 10 and a plurality of pins 13, and attach the chip 14 to the upper surface of the carrier 10 through an adhesive material 16;

[0059] Step 7: Lead 17 soldering, solder both ends of the lead 17 to the chip 14 and the pin 13 respectively to electrically connect the chip 14 and the pin 13;

[0060] Step 8: Plastic encapsulation, use a plastic encapsulation material to form a plastic encapsulation body 18 covering the chip 14, the pins 13, the limiting structure 141, and the lead 17 above the carrier 10;

[0061] Step 9: Carrier 10 removing, separate the carrier 10 from the plastic encapsulation body 18 to expose the lower surfaces of the pins 13 and the chip 14 outside the plastic encapsulation body 18;

[0062] Step 10: Cutting and separation, perform cutting on the plastic encapsulation body 18 after removing the carrier 10 to obtain a number of independent DFN or QFN package products 19.

[0063] Specifically, the carrier board 10 is a metal carrier board, and the metal carrier board can be a copper board or a stainless steel board.

[0064] In step one, the mask 11 is pasted on the upper surface of the carrier board 10.

[0065] In step two, the exposed pattern 12 is the pin pattern 121.

[0066] In step three, the pins 13 protruding from the upper surface of the carrier board 10 are electroplated and formed at the pin pattern 121 by electroplating.

[0067] In step three, the upper surface of the pins 13 is not higher than the upper surface of the chip 14; by setting the upper surface of the pins 13 not higher than the upper surface of the chip 14, the maximum height between the pins 13 and the chip 14 is the height of the chip 14. During plastic encapsulation, it helps to reduce the height of the plastic package 18, thereby reducing the thickness of the DFN or QFN package product 19.

[0068] In step five, the limiting structure 141 is a limiting bump respectively protruding from the outer side walls on the left and right sides of the chip 14, and a step 142 located below the limiting bump is formed between the limiting bump and the chip 14;

[0069] In step eight, the limiting bump is embedded in the plastic package 18; by setting the limiting bump on the chip 14, during plastic encapsulation, the limiting bump is embedded in the plastic package 18, and the cooperation between the step 142 and the plastic package 18 is used to enhance the bonding force between the chip 14 and the plastic package 18. When the carrier board 10 and the plastic package 18 are separated subsequently, the chip 14 and the plastic package 18 can be prevented from delaminating, enhancing the overall reliability of the product.

[0070] It should be noted that the limiting structure 141 can also be a limiting groove. In step eight, filling the plastic encapsulation material into the limiting groove can also enhance the bonding force between the chip 14 and the plastic package 18.

[0071] In step nine, the carrier board 10 is separated from the plastic package 18 by peeling, and the bonding material 16 is removed.

[0072] Before step three, a coating is applied on the upper surface of the carrier board 10. Specifically, the coating can be applied to the entire upper surface of the carrier board 10, or the coating can be applied to the upper surface of the carrier board 10 at the pin pattern 121. In step three, the pins 13 are electroplated on the coating; by applying the coating on the upper surface of the carrier board 10, the coating is used to isolate the pins 13 from the carrier board 10, reducing the peeling force of the carrier board 10 and making the carrier board 10 easy to peel.

[0073] In step ten, the pins 13 are exposed on the side surface of the plastic package 18.

[0074] The height h of the plastic package 18 is 0.15 mm to 0.3 mm.

[0075] As Figure 12-21 shown, in the second embodiment of the present invention, the difference from the first embodiment is that in step one, the carrier board 10 is a frame substrate, a first mask 12 is pasted on the upper surface of the frame substrate, and a second mask 112 is pasted on the lower surface of the frame substrate.

[0076] In step two, the exposed pattern 12 is a non-pin pattern 122.

[0077] In step three, the frame substrate is etched at the non-pin pattern 122 by an etching method, so that the unetched part of the upper surface of the frame substrate forms pins 13.

[0078] In step nine, the frame substrate is separated from the plastic package 18 by grinding or etching.

[0079] As Figure 11 and Figure 21 shown, the present invention also discloses an ultra-thin DFN or QFN package structure, which is prepared by using the ultra-thin DFN or QFN manufacturing method. The ultra-thin DFN or QFN package structure includes a chip 14, pins 13 and a plastic package 18. The chip 14 is electrically connected to the pins 13 through leads 17. The plastic package 18 covers the chip 14, the pins 13 and the leads 17. The lower surface of the chip 14 is exposed outside the plastic package 18, and the lower surface and / or side surface of the pins 13 are exposed outside the plastic package 18.

[0080] In summary, the present invention obtains a DFN or QFN package structure without a base island by successively adopting steps such as mask 11 pasting, exposure and development, pin 13 forming, mask 11 removing, wafer grinding, chip 14 mounting, lead 17 soldering, plastic packaging, carrier board 10 removing, cutting and separating, etc., so that the overall thickness of the product is thinner, meeting the market demand for ultra-thin DFN or QFN package structures; in addition, the chip 14 is exposed, so that the heat of the chip 14 and the electricity at the bottom of the chip 14 do not need to be conducted to the outside through the base island, and the chip 14 can obtain better heat dissipation performance and electrical conductivity, and the product performance is better.

[0081] The above is only a preferred embodiment of the present invention and is not intended to limit the present invention. Therefore, any modifications, equivalent replacements, improvements, etc. made to the above embodiments according to the technical reality of the present invention still fall within the scope of the technical solution of the present invention.

Claims

1. A manufacturing method for an ultra-thin DFN or QFN, characterized in that, It includes the following steps: Step 1: Mask pasting, pasting a mask on the surface of the carrier board; Step 2: Exposure and development, exposing the required pattern on the upper surface of the carrier board through exposure and development; Step 3: Pin forming, forming a plurality of pins on the carrier board after exposure and development; Step 4: Mask removal, removing the mask still attached to the carrier board; Step 5: Wafer grinding and scribing, performing grinding and scribing on the wafer to obtain a chip with a limiting structure; Step 6: Chip installation, placing the chip in the accommodation groove surrounded by the carrier board and a plurality of pins, and mounting the chip on the upper surface of the carrier board; Step 7: Lead soldering, soldering the two ends of the lead to the chip and the pin respectively; Step 8: Plastic encapsulation, using a plastic encapsulation material to form a plastic encapsulation body covering the chip, pins, limiting structure, and leads above the carrier board; Step 9: Carrier board removal, separating the carrier board from the plastic encapsulation body, so that the lower surfaces of the pins and the chip are both exposed outside the plastic encapsulation body; Step 10: Cutting and separation, performing cutting on the plastic encapsulation body after removing the carrier board to obtain a number of independent DFN or QFN packaged products.

2. The manufacturing method of the ultra-thin DFN or QFN according to claim 1, wherein In Step 1, the mask is pasted on the upper surface of the carrier board.

3. The manufacturing method of the ultra-thin DFN or QFN according to claim 1, characterized in that In Step 2, the exposed pattern is a pin pattern.

4. The manufacturing method of the ultra-thin DFN or QFN according to claim 3, characterized in that In Step 3, the pins protruding from the upper surface of the carrier board are formed by electroplating at the pin pattern.

5. The manufacturing method of the ultra-thin DFN or QFN according to claim 1, wherein The upper surface of the pin is not higher than the upper surface of the chip.

6. The manufacturing method of the ultra-thin DFN or QFN according to claim 1, characterized in that, In Step 9, the carrier board is separated from the plastic encapsulation body by a peeling method.

7. The manufacturing method of the ultra-thin DFN or QFN according to claim 1, wherein In Step 10, the pins are exposed on the side surface of the plastic encapsulation body.

8. The method for manufacturing an ultra-thin DFN or QFN according to claim 1, wherein The height h of the plastic encapsulation body is 0.15 mm to 0.3 mm.

9. An ultra-thin DFN or QFN package structure, characterized in that, Prepared by using the ultra-thin DFN or QFN manufacturing method described in any one of claims 1-8, the ultra-thin DFN or QFN packaging structure includes a chip, pins, and a plastic encapsulation body. The chip and the pins are electrically connected through leads. The plastic encapsulation body covers the chip, pins, and leads. The lower surface of the chip is exposed outside the plastic encapsulation body. The lower surface and / or side surface of the pins are exposed outside the plastic encapsulation body.

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