QFN (Quad Flat No-lead) lead frame, preparation method thereof and QFN packaging structure

Abstract

The invention discloses a QFN lead frame, a preparation method thereof and a QFN packaging structure, the QFN lead frame is manufactured by adopting a process of combining etching and stamping, and inner pins and base islands are stamped in a stamping mode to be lower than outer pins and in a step shape, so that a support frame is provided for the novel QFN packaging structure; not only is the production efficiency improved, but also the production cost is reduced, and the possibility is provided for large-scale production. The QFN packaging structure adopts the lead frame with an upper-layer pin structure and a lower-layer pin structure, the limitation that traditional packaging welding points are only in the same plane is broken through, the internal wiring space and the welding point distribution space of a chip are effectively increased, and the integration level of the packaging structure is improved. According to the structural design of the lead frame, the heat dissipation area of the chip is increased, particularly, a multi-layer heat dissipation network is formed through the arrangement of an upper-layer pin structure and a lower-layer pin structure, the heat dissipation efficiency is greatly improved, and the heat dissipation requirement of a large-size chip packaging structure is effectively met.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor packaging, and more particularly to a QFN lead frame, a preparation method thereof, and a QFN packaging structure. Background Art

[0002] As a chip carrier for integrated circuits, a lead frame is a key structural component that realizes the electrical connection between the internal circuit leads of a chip and the external leads by means of a bonding material, forming an electrical loop. It serves as a bridge for connecting to external wires and is also the main way for heat dissipation inside the chip. Most semiconductor integrated circuits require the use of lead frames.

[0003] Traditional QFN packaging structures use conventional lead frames as the main framework, and the pins are distributed around the edges of the product. This structural design limits the flexibility of the product in applications, and due to the limited spatial position and number of pin positions of the pins, the integration level is low. In addition, the lead frame in the traditional QFN packaging structure is a flat frame, and problems such as plastic encapsulation delamination and poor wire bonding are likely to occur during the plastic encapsulation and wire bonding processes; at the same time, the packaging structure will completely encapsulate the lead frame in the plastic package, and the heat dissipation channel is relatively single, mainly relying on the back surface of the base island located in the center of the bottom of the package for heat dissipation, and the heat dissipation speed is slow, which is difficult to meet the growing heat dissipation requirements and will also affect the service life of the product. In order to overcome these deficiencies, the industry has been seeking new QFN packaging design solutions.

[0004] Some improvement solutions have been proposed in the prior art, such as improving the heat dissipation performance and integration level of the package by changing the lead frame structure and optimizing the pin distribution. However, these solutions still have some limitations, such as insufficient heat dissipation effect and insufficient pin stability, and have not completely solved the technical problems in the traditional QFN packaging structure.

[0005] Therefore, there is an urgent need to provide a new lead frame structure. Summary of the Invention

[0006] To solve the above problems, the present invention provides a QFN lead frame and a preparation method thereof, and a lead frame with multi-turn pins in different planes is fabricated by a combination of etching and stamping. The QFN packaging structure after encapsulation increases the internal wiring space and solder joint distribution space of the chip, improves the integration level of the packaging structure, and also increases the heat dissipation area. In particular, by setting the pin structures in different planes, a multi-level heat dissipation network is formed, greatly improving the heat dissipation efficiency and effectively meeting the heat dissipation requirements of the large-size chip packaging structure.

[0007] In a first aspect, the present invention discloses a preparation method of a QFN lead frame, and the method includes the following steps: S1. Provide a high-strength metal substrate, and use chemical etching process to form base islands and multiple turns of pins on the front surface of the metal substrate. The multiple turns of pins are arranged around the periphery of the base island. The multiple turns of pins include one turn of inner pins and at least one turn of outer pins, and the inner pins are the closest to the base island. S2. Stamp the metal substrate to form an independent QFN lead frame. In the stamping process, stamp the base island and the inner pin area downward from the front surface to the back surface of the QFN lead frame, so that the QFN lead frame has a stepped structure. Wherein, the surfaces of the base island and the inner pins are in the same plane, the surfaces of the base island, the inner pins and the outer pins are not in the same plane, and the surface of the outer pins is higher than the surfaces of the base island and the inner pins.

[0008] Preferably, the stamping distance is 1-5 mm.

[0009] Preferably, one turn of outer pins is provided.

[0010] Preferably, the metal substrate is made of copper or copper alloy.

[0011] In the second aspect, the present invention discloses a QFN lead frame prepared according to the above method, which includes a metal substrate and base islands and multiple turns of inner and outer pins provided on the front surface of the metal substrate. The multiple turns of pins are arranged around the periphery of the base island. The multiple turns of pins include one turn of inner pins and at least one turn of outer pins, and the inner pins are the closest to the base island. The QFN lead frame has a stepped structure. The surfaces of the base island and the inner pins are in the same plane. The surfaces of the base island, the inner pins and the outer pins are not in the same plane, and the surface of the outer pins is higher than the surfaces of the base island and the inner pins.

[0012] In the third aspect, the present invention also discloses a QFN package structure, which includes the aforementioned QFN lead frame. Specifically, a semiconductor chip is mounted on the base island of the QFN lead frame. After electrically connecting the semiconductor chip to the inner pins and the outer pins through leads, the semiconductor chip and the leads are encapsulated to form an encapsulation part, thereby forming a QFN package structure with a stepped structure.

[0013] Preferably, the exposed pins in the QFN package structure are electroplated with tin or tin alloy.

[0014] Compared with the prior art, the beneficial effects of the present invention are: 1. The present invention uses a combination of etching and stamping processes to manufacture the QFN lead frame. By stamping the inner pins and the base island, they are made lower than the outer pins, showing a stepped shape, providing a support frame for a new type of QFN package structure. By changing the manufacturing process of the lead frame and adopting a combination of etching and stamping, not only the production efficiency is improved, but also the production cost is reduced, providing the possibility for large-scale production.

[0015] 2. The QFN package structure of the present invention uses a lead frame with an upper and lower double-layer pin structure, breaking the limitation that the traditional package welding points are only on the same plane, effectively increasing the internal wiring space and solder joint distribution space of the chip, improving the integration of the package structure, and providing the possibility for implementing more complex wiring designs.

[0016] 3. The structural design of the lead frame in the present invention increases the heat dissipation area of the chip. In particular, by setting the upper and lower double-layer pin structures, a multi-level heat dissipation network is formed, greatly improving the heat dissipation efficiency and effectively meeting the heat dissipation requirements of the large-size chip package structure.

[0017] 4. In the QFN package structure of the present invention, the pin distribution is more uniform, no longer limited to the periphery of the package structure, significantly improving the flexibility of the package structure in applications and providing more choices for the design of electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic structural diagram of the QFN lead frame in Embodiment 1 of the present invention; Figure 2 It is a schematic side structural diagram of the QFN lead frame in Embodiment 1 of the present invention; Figure 3 It is a schematic structural diagram of the QFN package structure in Embodiment 2 of the present invention; Figure 4 It is another schematic diagram of the QFN package structure; Figure 5 It is a process flow chart of the QFN package structure.

[0019] Reference numerals: QFN lead frame 1, metal substrate 101, base island 102, inner pins 103, inner pin surface 1031, outer pins 104, outer pin surface 1041, semiconductor chip 2, leads 3, plastic encapsulation part 4. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0020] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments.

[0021] Embodiment 1 This embodiment discloses a preparation method of a QFN lead frame, specifically using a process combining etching and stamping to manufacture the QFN lead frame 1.

[0022] In this embodiment, the method of forming the base island 102 and multiple turns of pins on the front surface of the metal substrate 101 by using the chemical etching process is a prior art and will be briefly described herein. The main production process of the lead frame forming process (taking the mechanical template electroplating process as an example): frame design, opening an etching die, pre-cleaning of raw materials, pressing dry film, exposure, development, etching, stripping film, pressing dry film, exposure, development, silver plating, stripping film, stamping and packaging. An additional stamping process is added to the production process of the etched lead frame, and a matching stamping tool is opened according to the design. After the lead frame is silver plated, the production is completed through stamping.

[0023] The manufacturing method of the QFN lead frame 1 disclosed in this embodiment includes the following steps: S1. Provide a high-strength metal substrate 101, and use the chemical etching process to form a base island 102 and multiple turns of pins on the front surface of the metal substrate 101. The multiple turns of pins are arranged around the periphery of the base island 102. The multiple turns of pins include one turn of inner pins 103 and at least one turn of outer pins 104, and the inner pins 103 are the closest to the base island 102.

[0024] S2. Stamp the metal substrate 101 to form an independent QFN lead frame 1; in the stamping process, stamp the areas of the base island 102 and the inner pins 103 downward from the front surface to the back surface of the QFN lead frame 1, so that the QFN lead frame 1 has a stepped structure.

[0025] Among them, the base island 102 and the surface 1031 of the inner pins are on the same plane, the base island 102, the surface 1031 of the inner pins and the surface 1041 of the outer pins are not on the same plane, and the surface 1041 of the outer pins is higher than the base island 102 and the surface 1031 of the inner pins.

[0026] The QFN lead frame 1 prepared according to the above method has a schematic diagram of its specific structure as Figure 1 shown, and a schematic diagram of the side structure as Figure 2 shown. In this embodiment, one turn of outer pins 104 is taken as an example.

[0027] The QFN lead frame 1 includes a metal substrate 101, a base island 102 and multiple inner and outer turns of pins provided on the front surface of the metal substrate 101. The multiple turns of pins are arranged around the periphery of the base island 102. The multiple turns of pins include one turn of inner pins 103 and at least one turn of outer pins 104, and the inner pins 103 are the closest to the base island 102. The QFN lead frame 1 has a stepped structure. The base island 102 and the surface 1031 of the inner pins are on the same plane, the base island 102, the surface 1031 of the inner pins and the surface 1041 of the outer pins are not on the same plane, and the surface 1041 of the outer pins is higher than the base island 102 and the surface 1031 of the inner pins.

[0028] The high-strength metal substrate 101 is made of copper or copper alloy material, such as C7025 alloy. The metal substrate 101 in the present invention is a copper strip with a thickness of 0.1 - 0.2 mm.

[0029] In this embodiment, first, the metal substrate 101 (taking the copper strip as an example) is chemically cleaned (pickling or alkaline washing), ultrasonically cleaned, and rinsed with deionized water to remove the grease, oxides, and impurities on the surface of the copper strip, ensuring a clean surface. Then, a photosensitive dry film (Photoresist Dry Film) is laminated on the surface of the copper strip as a mask for subsequent pattern transfer. The dry film is exposed using ultraviolet light through a mask plate (lithography plate), and the circuit pattern is transferred onto the dry film (the unexposed part can be dissolved). The unexposed dry film is dissolved with an alkaline solution to expose the copper area to be etched, forming a circuit pattern. An acidic etching solution is used to dissolve the exposed copper, and the circuit pattern protected by the dry film is retained. The remaining dry film is removed with an alkaline solution to obtain a preliminarily formed copper lead frame structure. The dry film is laminated again to prepare for subsequent selective silver plating. The exposure and development steps are repeated, and only the pad and pin areas to be silver-plated are exposed. Silver (Ag) is electroplated, with a thickness usually of 1 - 5 μm, to improve the solderability and conductivity of the pads of the base island 102 and the pin pads. The non-exposed areas are protected by the dry film. The dry film is removed to complete the selectively silver-plated lead frame, which includes a base island 102 and multiple turns of pins. In this embodiment, one turn of outer pins 104 is provided as an example. One turn of inner pins 103 and one turn of outer pins 104 surround the periphery of the base island 102, and the inner pins 103 are closest to the base island 102. A high-precision mold is used to stamp the copper strip to form an independent QFN lead frame 1, and positioning holes and an outer contour are punched out.

[0030] In this embodiment, the difference from the conventional lead frame stamping is that in the stamping process, the areas of the base island 102 and the inner pins 103 are stamped downward from the front to the back of the QFN lead frame 1, so that the inner pins 103 and the outer pins 104 of the QFN lead frame 1 form a stepped structure. Specifically, the stamping process stamps the areas of the base island 102 and the inner pins 103 of the lead frame downward by a certain distance, and the stamping distance is 1 - 5 mm.

[0031] In the QFN lead frame 1 of this embodiment, the structure and distribution of the inner pins 103 and the outer pins 104 make the pin distribution more uniform. Using this lead frame to prepare a QFN package structure, the pins are no longer limited to the edges of the package structure, which can improve the flexibility of the package structure in applications and provide more choices for the design of electronic devices.

[0032] In this embodiment, the QFN lead frame 1 is fabricated by a process combining etching and stamping. The inner pins 103 and the base island 102 are stamped in a stamping manner, making the areas of the inner pins 103 and the base island 102 lower than the area of the outer pins 104, presenting a stepped shape, and providing a support frame for the novel QFN package structure; by changing the manufacturing process of the lead frame and adopting a combination of etching and stamping, not only the production efficiency is improved, but also the production cost is reduced, providing the possibility for large-scale production.

[0033] Embodiment 2 This embodiment discloses a QFN package structure, and the schematic structural diagram is as shown in Figure 3 and Figure 4 shown. It includes the QFN lead frame 1 prepared in Embodiment 1. Specifically, a semiconductor chip 2 is mounted on the base island 102 of the QFN lead frame 1. After electrically connecting the semiconductor chip 2 to the inner pins 103 and the outer pins 104 through leads 3, the semiconductor chip 2 and the leads 3 are encapsulated to form an encapsulation part 4, forming a QFN package structure with a stepped structure.

[0034] Among them, the semiconductor chip 2 can be pasted onto the base island 102 of the lead frame through a conductive adhesive, or can be electrically connected to the pads of the base island 102 through the leads 3.

[0035] The encapsulation material can be an epoxy molding compound (EMC), which can effectively protect the circuit structure inside the package structure.

[0036] The exposed pins in the QFN package structure are electroplated with tin or a tin alloy to enhance the antioxidant property and soldering performance of the package structure.

[0037] The main manufacturing process flow of the QFN package structure: chip mounting, wire bonding, encapsulation mold film covering, encapsulation, film tearing, tin plating, cutting, packaging. The encapsulation process is generally the same as that in the industry. In this embodiment, it is selected to first cover the customized encapsulation mold with a film, and then place the encapsulated semi-finished product after wire bonding on the film-covered mold for encapsulation, solving the limitation that the traditional frame needs to cover the film parallel to the frame surface to prevent overflow of materials, and the film paper is separated from the lead frame after injection molding.

[0038] The QFN package structure in this embodiment adopts a lead frame with an upper and lower double-layer pin structure, breaking the limitation that the traditional package welding points are only on the same plane, making the pin distribution more uniform, no longer limited to the periphery of the package structure, effectively increasing the internal wiring space and solder joint distribution space of the chip, improving the integration degree of the package structure, significantly improving the flexibility of the package structure in applications, providing the possibility for realizing more complex wiring designs, and also providing more choices for the design of electronic devices.

[0039] The overall process flowcharts of Embodiment 1 and Embodiment 2 of the present invention are as shown inFigure 5 As shown in Figure 5 , the process flow of the QFN package structure includes: raw materials - pre - cleaning - laminating dry film - exposure - development - etching - stripping film - laminating dry film - exposure - development - silver plating - stripping film - stamping - die bonding - wire bonding - encapsulation - tin plating; finally, it is cut and packaged.

[0040] The QFN package structure in this embodiment has a stepped structure in terms of appearance. This structure increases the heat dissipation area of the chip. Through the upper and lower two - layer pin structures, a multi - level heat dissipation network is formed, greatly improving the heat dissipation efficiency and effectively meeting the heat dissipation requirements of the large - size chip package structure.

[0041] The above are only some embodiments of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the creative concept of the present invention, other deformations and improvements can be made, and these all belong to the protection scope of the present invention.

Claims

1. Preparation method of QFN lead frame, characterized in that, The method includes the following steps: S1. Provide a high-strength metal substrate, and form base islands and multiple turns of pins on the front surface of the metal substrate by means of chemical etching. The multiple turns of pins surround the base islands on the periphery. The multiple turns of pins include one turn of inner pins and at least one turn of outer pins, and the inner pins are the closest to the base islands. S2. Stamp the metal substrate to form an independent QFN lead frame. In the stamping process, stamp the base islands and the inner pin areas downward from the front surface to the back surface of the QFN lead frame, so that the QFN lead frame has a stepped structure. Among them, the surfaces of the base islands and the inner pins are in the same plane, the surfaces of the base islands, the inner pins and the outer pins are not in the same plane, and the surface of the outer pins is higher than the surfaces of the base islands and the inner pins.

2. The method according to claim 1, wherein The stamping distance is 1-5 mm.

3. The method according to claim 2, wherein One turn of outer pins is provided.

4. The method according to claim 3, wherein The metal substrate is made of copper or copper alloy.

5. A QFN lead frame, prepared and formed by the method according to any one of claims 1-4, characterized in that, It includes a metal substrate, and base islands and multiple turns of inner and outer pins provided on the front surface of the metal substrate. The multiple turns of pins surround the base islands on the periphery. The multiple turns of pins include one turn of inner pins and at least one turn of outer pins, and the inner pins are the closest to the base islands. The QFN lead frame has a stepped structure. The surfaces of the base islands and the inner pins are in the same plane, the surfaces of the base islands, the inner pins and the outer pins are not in the same plane, and the surface of the outer pins is higher than the surfaces of the base islands and the inner pins.

6. A QFN package structure, comprising the QFN lead frame according to claim 5, characterized in that, Mount a semiconductor chip on the base island of the QFN lead frame. After electrically connecting the semiconductor chip to the inner pins and the outer pins through leads, encapsulate the semiconductor chip and the leads to form an encapsulation part, so as to form a QFN package structure with a stepped structure.

7. The QFN package structure according to claim 6, characterized in that, Electroplate tin or tin alloy on the exposed pins in the QFN package structure.

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