Embedded multi-chip interconnection bridge and preparation method and application thereof

Abstract

The invention provides an embedded multi-chip interconnection bridge (EMIB) and a preparation method and application thereof, and belongs to the technical field of integrated circuit packaging. According to the invention, the substrate taking the ABF resin material as the insulating material replaces the traditional EMIB taking silicon as the insulating material. A core serves as a bearing plate, an ABF material is adopted for layer-by-layer lamination, a copper circuit layer is manufactured through an SAP technology, after a to-be-split plate is symmetrically split, lamination is carried out to meet the plate thickness, then cutting is carried out with a circuit center, two embedded multi-tube-core interconnection bridges which are completely symmetrical and take ABF as a medium can be obtained, the tangent plane of each embedded multi-tube-core interconnection bridge is a matrix type bonding pad, and the embedded multi-tube-core interconnection bridges can serve as an EMIB and chip packaging butt joint face. Due to the fact that the ABF resin is used, the dielectric material of the ABF resin is consistent with that of an IC packaging substrate to be embedded, and the risk of uneven stress of EMIB and cracking of a silicon bridge can be greatly reduced. And the EMIB made of the ABF has an obvious cost advantage due to the fact that the material cost and the processing cost of the ABF are far lower than those of a silicon-based material.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit packaging, and particularly to an embedded multi-chip interconnect bridge, a preparation method thereof, and an application thereof. Background Art

[0002] EMIB (Embedded Multi-die Interconnect Bridge) is an embedded multi-chip interconnect bridge technology. By embedding a small silicon bridge in a packaging substrate, this silicon bridge contains high-density interconnect channels to achieve high-bandwidth and low-latency interconnect between two chips. It is designed to achieve selective high-density electrical connections and provide high-speed communication between heterogeneous chips within the same package. More practically, EMIB technology allows heterogeneous chips and hybrid components to be placed within the same package to meet system / product performance requirements. Multiple silicon bridges can be embedded at different positions on the packaging substrate, thus greatly improving design flexibility. It is compatible with different silicon technology nodes and can achieve large-size chip splicing. The EMIB advanced packaging technology is currently widely used in Intel's FPGA, discrete GPU, artificial intelligence (AI), servers, and other data-centric high-performance computing (HPC) market segments.

[0003] When using EMIB, a silicon bridge with ultra-high wiring density needs to be embedded into the substrate. Specifically, it includes opening a window in the substrate and pasting the silicon bridge in the receiving groove of the substrate through DAF (die attach film, patch glue). However, conventional EMIB is made of silicon material, while the substrate is mainly aromatic dibenzaldehyde resin (ABF resin material). After embedding, the EMIB is prone to problems of inconsistent expansion and contraction with the substrate. When external pressure is too high or temperature changes too much, etc., it will cause uneven stress distribution of the silicon bridge, and then lead to the problem that the substrate mechanism has a risk of cracking. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide an embedded multi-chip interconnect bridge, a preparation method thereof, and an application thereof. The embedded multi-chip interconnect bridge prepared by the present invention uses ABF resin, and its dielectric material is the same as the IC packaging substrate to be embedded, which can greatly reduce the stress unevenness of EMIB and the risk of silicon bridge cracking.

[0005] In order to achieve the above-mentioned invention purpose, the present invention provides the following technical solutions: The present invention provides a preparation method for an embedded multi-chip interconnect bridge, including the following steps: Press ABF materials symmetrically on both sides of a carrier plate to obtain a pressed plate; Drill positioning holes at the four corners of the pressed plate, and then perform double-sided copper deposition to obtain a copper seed layer; On both side surfaces of the copper seed layer, laminating, exposure, and development are sequentially performed to obtain a dry film pattern board; On both side surfaces of the dry film pattern board, pattern electroplating is performed to form electroplated copper circuits, and then stripping, flash etching, and palladium removal are sequentially performed to form a copper circuit layer, thereby obtaining a copper circuit board; On both side surfaces of the copper circuit board, super roughening, lamination, and drilling are sequentially performed to obtain a board to be split; the lamination is to laminate an ABF resin on the surface after super roughening; On the board to be split, symmetric splitting and full board etching are sequentially performed to obtain a split board; only one layer of copper foil is retained on the board obtained after symmetric splitting; After laminating ABF resins on both side surfaces of the split board, drilling, symmetric forming, and immersion nickel and gold plating are sequentially performed to obtain the embedded multi-chip interconnect bridge, wherein the symmetric forming is cut along the circuit center of the copper circuit layer, and the circuit section of the symmetric forming is a matrix-shaped pad.

[0006] Preferably, the carrier board is a coreless board, and the thickness of the coreless board is 0.1 - 1 mm.

[0007] Preferably, the coreless board includes an intermediate dielectric layer and an outer copper foil layer, and the thickness of the outer copper foil layer is 2 - 18 μm.

[0008] Preferably, the thickness of the ABF material for symmetric lamination of the ABF material is 5 - 30 μm.

[0009] Preferably, the positioning hole is a through hole or a blind hole.

[0010] Preferably, the thickness of the copper seed layer is 0.5 - 1 μm.

[0011] Preferably, the thickness, line width, and line spacing of the copper circuit layer are independently 5 - 30 μm.

[0012] Preferably, the thickness of the board obtained after laminating the ABF resin is 0.2 - 2 mm.

[0013] The present invention also provides an embedded multi-chip interconnect bridge prepared by the preparation method described in the above technical solution.

[0014] The present invention also provides an application of the embedded multi-chip interconnect bridge described in the above technical solution in the field of integrated circuit packaging.

[0015] The present invention provides a method for fabricating an embedded multi-chip interconnect bridge, comprising the following steps: symmetrically laminating ABF materials on both sides of a carrier board to obtain a laminated board; drilling positioning holes at the four corners of the laminated board, and then performing double-sided electroless copper plating to obtain a copper seed layer; sequentially laminating a dry film, exposing, and developing on both surface sides of the copper seed layer to obtain a dry film pattern board; performing pattern electroplating on both surface sides of the dry film pattern board, and sequentially performing stripping, flash etching, and palladium removal after forming electroplated copper lines to form copper line layers, thereby obtaining a copper line board; sequentially performing super roughening, lamination, and target punching on both surface sides of the copper line board to obtain a board to be split; the lamination is to laminate ABF resin on the surface after super roughening; sequentially performing symmetric splitting and full-board etching on the board to be split to obtain a split board; only one layer of copper foil is retained on the board obtained after symmetric splitting; after laminating ABF resin on both surface sides of the split board, sequentially performing target punching, symmetric forming, and immersion nickel and gold plating to obtain the embedded multi-chip interconnect bridge, the symmetric forming is cut along the center of the lines of the copper line layer, and the cross-section of the lines of the symmetric forming is a matrix-shaped pad.

[0016] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention uses an ABF resin material as the substrate of the insulating material to replace the traditional embedded multi-die interconnect bridge with silicon as the insulating material. By laminating ABF materials layer by layer, an embedded multi-chip interconnect bridge can be obtained; the SAP process is used to fabricate the copper line layer. After the board to be split is symmetrically split, lamination is performed to meet the board thickness, and then cutting along the center of the lines can obtain two completely symmetric embedded multi-die interconnect bridges. The cross-section of its lines is a matrix-shaped pad, which can be used as the docking surface between the EMIB and the chip package. Since the ABF resin is used, its dielectric material is consistent with the IC package substrate to be embedded, which can greatly reduce the stress non-uniformity of the EMIB and the risk of silicon bridge cracking; moreover, for the EMIB fabricated with the ABF material, since the material cost and processing cost of the silicon bridge are much higher than the cost of the ABF material, therefore, the EMIB of the present invention has an obvious cost advantage, is suitable for mass production, and has high production efficiency.

[0017] The present invention also provides an embedded multi-chip interconnect bridge prepared by the preparation method described in the above technical solution. The EMIB insulating material in the related technology is silicon. In essence, the EMIB at this time is a chip with a relatively simple design. In the related technology, the chip is embedded in the substrate groove, and the chip and the groove are glued together with glue. When the stress at the joint becomes large due to temperature or external force, since the two materials are a silicon chip and a polymer respectively, there must be a large difference in physical properties such as expansion and contraction. When the deformation is large, there may be a risk of cracking. The substrate of the present invention uses an ABF resin material as the insulating material, and the ABF material is laminated. The EMIB manufactured in this way has the same physical properties as the substrate, and there is no physical difference such as expansion and contraction, avoiding the cracking risk of traditional silicon chips; and the EMIB of the present invention is essentially a substrate, and has better anti-collision and toughness properties compared with silicon chips; in addition, the material cost and processing cost of ABF are much lower than those of silicon-based materials, and the EMIB of the present invention also has an obvious cost advantage. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 It is a schematic structural diagram of the coreless board in the embodiment; Figure 2 It is a schematic structural diagram of the laminated board in the embodiment; Figure 3 It is a schematic structural diagram of single-sided drilling; Figure 4 It is a schematic structural diagram of single-sided electroless copper plating; Figure 5 It is a schematic structural diagram of the single-sided dry film pattern board; Figure 6 It is a top view of the single-sided electroplated copper circuit; Figure 7 It is a schematic cross-sectional structure diagram of the board obtained by single-sided electroplated copper circuit; Figure 8 It is a schematic structural diagram of the single-sided copper circuit board; Figure 9 It is a schematic structural diagram after single-sided target punching; Figure 10 It is a schematic structural diagram of the single-sided split board; Figure 11 It is a schematic cross-sectional view of the single-sided split board after 5 times of layer-by-layer lamination; Figure 12 It is a schematic cross-sectional view after the whole board is etched; Figure 13 It is a schematic structural diagram of the board after lamination; Figure 14 It is a top view when cutting along the center of the circuit; Figure 15 It is a schematic cross-sectional view after Y’ cutting; Figure 16It is the top view after forming; Figure 17 It is the top view of the EMIB. Specific embodiments

[0019] The present invention provides a method for preparing an embedded multi-chip interconnect bridge, comprising the following steps: Press ABF materials symmetrically on both sides of a carrier board to obtain a pressed board; Drill positioning holes at the four corners of the pressed board, and then perform double-sided copper deposition to obtain a copper seed layer; Perform film pasting, exposure, and development on both sides of the copper seed layer in sequence to obtain a dry film pattern board; Perform pattern electroplating on both sides of the dry film pattern board to form electroplated copper circuits, and then perform film stripping, flash etching, and palladium removal in sequence to form a copper circuit layer, obtaining a copper circuit board; Perform super roughening, pressing, and target punching on both sides of the copper circuit board in sequence to obtain a board to be split; the pressing is to press ABF resin on the surface after super roughening; Perform symmetrical splitting and whole-board etching on the board to be split in sequence to obtain a split board; only one layer of copper foil is retained on the board obtained after symmetrical splitting; After pressing ABF resin on both sides of the split board, perform target punching, symmetrical forming, and immersion nickel and gold plating in sequence to obtain the embedded multi-chip interconnect bridge, the symmetrical forming is cut along the circuit center of the copper circuit layer, and the circuit section plane of the symmetrical forming is a matrix-shaped pad.

[0020] In the present invention, unless otherwise specified, the raw materials used are commercially available products in the art.

[0021] In the present invention, ABF materials are symmetrically pressed on both sides of a carrier board to obtain a pressed board.

[0022] In the present invention, the carrier board is preferably a coreless board, and the thickness of the coreless board is preferably 0.1 - 1 mm, specifically it can be 0.14, 0.19, or 0.24 mm.

[0023] In the present invention, the coreless board preferably includes an intermediate dielectric layer and an outer copper foil layer. The thickness of the outer copper foil layer is preferably 2 - 18 μm, specifically it can be 2, 3, 5, 12, or 18 μm. The thickness of the intermediate dielectric layer is preferably 0.1 - 0.5 mm, specifically it can be 0.1, 0.15, or 0.2 mm. In a specific embodiment of the present invention, the structure of the coreless board is preferably 3 μm copper foil, 18 μm copper foil, intermediate dielectric layer, 18 μm copper foil, and 3 μm copper foil.

[0024] In the present invention, the thickness of the ABF material for symmetrically pressing the ABF material is preferably 5 - 30 μm, and specifically can be 5, 10, 15, 20, 25 or 30 μm.

[0025] The present invention has no special limitation on the specific method for symmetrically pressing the ABF material, and any method well-known to those skilled in the art can be adopted.

[0026] After obtaining the pressed board, the present invention drills positioning holes at the four corners of the pressed board, and then performs double-sided electroless copper plating to obtain a copper seed layer.

[0027] In the present invention, the positioning holes are preferably through holes or blind holes.

[0028] After drilling the positioning holes, the present invention preferably removes the smear in the holes to ensure the smooth progress of the subsequent electroless copper plating process.

[0029] In the present invention, the thickness of the copper seed layer is preferably 0.5 - 1 μm, and specifically can be 0.5, 0.6, 0.8 or 1 μm.

[0030] In the present invention, the double-sided electroless copper plating preferably includes being carried out in the positioning holes, that is, the copper seed layer is also formed in the positioning holes. If it is necessary to remove the copper seed layer in the positioning holes, it is preferably etched off through subsequent steps. The subsequent steps refer to when exposing and developing, the dry film in the positioning holes remains. In this way, when performing pattern electroplating, copper will not be plated in the holes. After flash etching, the copper seed layer inside the pattern electroplating can be removed.

[0031] After obtaining the copper seed layer, the present invention sequentially performs film laminating, exposure and development on both side surfaces of the copper seed layer to form a dry film and obtain a dry film pattern board.

[0032] The present invention has no special limitation on the specific methods of film laminating, exposure and development, and any method well-known to those skilled in the art can be adopted.

[0033] After obtaining the dry film pattern board, the present invention performs pattern electroplating on both side surfaces of the dry film pattern board to form electroplated copper circuits, and then sequentially performs film stripping, flash etching and palladium removal to form a copper circuit layer and obtain a copper circuit board.

[0034] In the present invention, the thickness, line width and pitch of the copper circuit layer are independently preferably 5 - 30 μm, and specifically can be 5, 10, 15, 20, 25 or 30 μm. The copper circuit layer is a multi-turn fine circuit, and the pattern is based on the customer's design and corresponds to the welding points of the two chips connected in the package.

[0035] In the present invention, the function of the stripping is to remove the dry film and expose the copper seed layer below the dry film; the thickness of the flash etching is preferably 0.5 - 1.5 mm to remove the exposed copper seed layer; the function of the de-palladium is to remove the trace palladium element left during the electroless copper plating to obtain the copper circuit layer.

[0036] After obtaining the copper circuit board, the two side surfaces of the copper circuit board are sequentially subjected to super roughening, lamination and target punching in the present invention to obtain the board to be split; the lamination is to laminate the ABF resin on the surface after the super roughening.

[0037] In the present invention, the function of the super roughening is to increase the bonding force between the laminated copper surface and the ABF. The super roughening is preferably micro etching, and the micro etching amount of the micro etching is preferably 0.8 - 1.0 μm.

[0038] In the present invention, the thickness of the ABF resin for laminating the ABF resin is preferably 5 - 30 μm, specifically it can be 5, 10, 15, 20, 25 or 30 μm.

[0039] After the target punching is completed, the present invention preferably repeats the steps of double-sided electroless copper plating, forming a dry film, pattern electroplating, forming a copper circuit layer, super roughening and lamination to obtain a multilayer circuit board.

[0040] After obtaining the board to be split, the present invention sequentially performs symmetric splitting and whole board etching on the board to be split to obtain the split board; only one layer of copper foil is retained on the board obtained after the symmetric splitting.

[0041] In the present invention, the vertical structure of the board to be split is ABF material / electroplated copper circuit / coreless board / electroplated copper circuit / ABF material. Taking the structure of the coreless board as 3 μm copper foil, 18 μm copper foil, intermediate dielectric layer, 18 μm copper foil and 3 μm copper foil as an example, the symmetric splitting is described. The symmetric splitting is to split from between the two 3 μm copper foil / 18 μm copper foil of the coreless board to obtain 3 structures: the first laminated core board (i.e., the split board), the middle 18 μm copper foil / intermediate dielectric layer / 18 μm copper foil and the second laminated core board (also the split board). The middle 18 μm copper foil / intermediate dielectric layer / 18 μm copper foil is discarded, that is, two split boards are obtained by the symmetric splitting, and the vertical structure of the split board is ABF material / electroplated copper circuit / 3 μm copper foil.

[0042] In the present invention, the function of the whole board etching is to remove the copper foil left by the symmetric splitting.

[0043] After obtaining the splitting board, the present invention presses ABF resin on both side surfaces of the splitting board respectively, and then performs target punching, symmetric forming and immersion nickel and gold in sequence to obtain the embedded multi-chip interconnect bridge. The symmetric forming is cut along the center line of the copper circuit layer, and the cut surface of the symmetric forming is a matrix-shaped pad.

[0044] In the present invention, the thickness of the board obtained after pressing ABF resin is preferably 0.2-2 mm, and specifically can be 0.2, 1, 1.25, 1.5 or 2 mm.

[0045] In the present invention, the function of the target punching is positioning; the cut surface of the circuit can be used as the docking surface between the EMIB and the chip package.

[0046] In the present invention, the symmetric forming preferably obtains small-particle EMIBs. The line width and pitch of the small-particle EMIBs are both preferably 5 μm, and the size of the structure obtained by the symmetric forming is preferably 2×2×0.9 mm.

[0047] In the present invention, the immersion nickel and gold is preferably carried out on the surface of the pads. For the small-particle EMIBs, the immersion nickel and gold is preferably barrel plating.

[0048] The present invention also provides an embedded multi-chip interconnect bridge prepared by the preparation method described in the above technical solution.

[0049] The present invention also provides an application of the embedded multi-chip interconnect bridge described in the above technical solution in the field of integrated circuit packaging. The present invention has no special limitation on the specific manner of the application, and the manner well-known to those skilled in the art can be adopted.

[0050] Next, the technical solutions in the present invention will be clearly and completely described in conjunction with the embodiments in the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without creative work shall fall within the protection scope of the present invention.

[0051] Example 1 A preparation method for an embedded multi-chip interconnect bridge includes the following steps: Step 1: Blanking: Select a coreless board with a thickness of 0.19 mm as the carrier board. The structure of the coreless board is 3-μm copper foil, 18-μm copper foil, 150-μm intermediate dielectric layer, 18-μm copper foil and 3-μm copper foil. The structure is shown in Figure 1 .

[0052] Step 2: Pressing: Symmetrically press 5-μm-thick ABF materials on both sides of the coreless board to obtain a pressed board. The structure is shown in Figure 2。

[0053] Step 3: Drilling: Drill positioning holes at the four corners of the laminated board and through holes inside the board. Figure 3 It is a schematic structural diagram of single-sided drilling.

[0054] Step 4: Desmearing and copper deposition: Desmear the above-mentioned board to remove the glue residue in the holes and the glue remaining on the surface of the ABF; deposit copper 0.5μm on both sides of the board respectively as the copper seed layer for subsequent copper plating. Figure 4 It is a schematic structural diagram of single-sided copper deposition. Actually, copper is deposited on both sides of the board. Since both sides are symmetrical, only one side is shown for illustration.

[0055] Step 5: Circuit fabrication: Directly apply a film, expose, and develop on the copper seed layer to form a dry film and obtain a dry film pattern board. Figure 5 It is a schematic structural diagram of a single-sided dry film pattern board.

[0056] Step 6: Pattern electroplating: Electroplate the above-mentioned board with 5μm of copper to obtain electroplated copper circuits, which are multi-turn rectangular fine circuits. Figure 6 It is a top view of single-sided electroplated copper circuits. Figure 7 It is a schematic cross-sectional structure diagram of the board obtained from single-sided electroplated copper circuits.

[0057] Step 7: Stripping, flash etching, and palladium removal: Strip the film to remove the dry film and expose the copper deposition layer (copper seed layer) under the dry film; flash etch 0.5mm to remove the exposed copper deposition layer; perform palladium removal operation to remove the trace palladium element left by copper deposition, form copper circuits, and obtain a copper circuit board (with a line width and pitch of 5μm). Figure 8 It is a schematic structural diagram of a single-sided copper circuit board.

[0058] Step 8: Ultra-roughening, lamination, and punching: Ultra-roughen the above-mentioned board (with a micro-etching amount of 0.8μm), then laminate 5μm thick ABF materials on the upper and lower surfaces respectively, and then perform punching. Figure 9 It is a schematic structural diagram after single-sided punching.

[0059] Step 9: Repeat steps 4 to 8 (the number of times depends on the design) 4 times to obtain a multi-layer circuit board after 5 times of layer-by-layer lamination.

[0060] Step 10: Symmetrically split the above-mentioned board to obtain split boards. The vertical structure of the board to be split is ABF material / electroplated copper circuit / 3μm copper foil / 18μm copper foil / intermediate dielectric layer / 18μm copper foil / 3μm copper foil / electroplated copper circuit / ABF material. The symmetric split is carried out by splitting between the two 3μm copper foils / 18μm copper foils, resulting in 3 structures: the first laminated core board (i.e., the split board), the middle 18μm copper foil / intermediate dielectric layer / 18μm copper foil, and the second laminated core board (also the split board). Discard the middle 18μm copper foil / intermediate dielectric layer / 18μm copper foil. That is, the symmetric split obtains two split boards, and the vertical structure of the split board is ABF material / electroplated copper circuit / 3μm copper foil. Figure 10 It is a schematic structural diagram of a single-sided split board. Figure 11 It is a schematic cross-sectional diagram of a single-sided split board after 5 times of layer-by-layer lamination.

[0061] Step 11: Whole-board etching: Remove the remaining copper foil (3μm) after the symmetric split. Figure 12 It is a schematic cross-sectional diagram after whole-board etching.

[0062] Step 12: Lamination: Press ABF resin on both sides respectively to obtain the required board thickness. Figure 13 It is a schematic structural diagram of the board after lamination.

[0063] Step 13: Drilling and forming: Drilling is used for positioning; cutting along the center of the circuit can obtain two completely symmetric substrates, and the circuit cross-section is a matrix-shaped pad, serving as the docking surface for EMIB and chip packaging. What is completed is a small-particle EMIB. (The completed EMIB has a line width and pitch of 5μm, and the size after cutting is 2×2×0.9mm). Figure 14 It is a top view when cutting along the center of the circuit. Figure 15 It is a schematic cross-sectional diagram after Y' cutting. Figure 15 Dock two chips on the left and right respectively in it, so that the EMIB connects the two chips. Figure 16 It is a top view after forming.

[0064] Step 14: Immersion nickel and gold: Adopt the barrel plating method to carry out immersion nickel and gold surface treatment on the exposed pads to obtain the EMIB. Figure 17 It is a top view of the EMIB.

[0065] The substrate of the present invention uses ABF resin material as the insulating material to replace the traditional embedded multi-die interconnect bridge with silicon as the insulating material. By laminating the ABF material layer by layer, an embedded multi-chip interconnect bridge can be obtained. The copper circuit layer is fabricated using the SAP process. After the carrier board is symmetrically split and laminated to meet the board thickness, and then cut along the circuit center, two completely symmetrical embedded multi-die interconnect bridges can be obtained. Their cross-sections are matrix-shaped pads, which can be used as the docking surface between EMIB and chip packaging. Since ABF resin is used, its dielectric material is consistent with the IC packaging substrate to be embedded, which can greatly reduce the stress non-uniformity of EMIB and the risk of silicon bridge cracking. Moreover, for the EMIB fabricated using ABF material, since the material cost and processing cost of the silicon bridge are much higher than those of the ABF material, the EMIB of the present invention has obvious cost advantages, is suitable for mass production, and has high production efficiency.

[0066] The above are only the preferred embodiments of the present invention and do not impose any form of limitation on the present invention. It should be noted that for those of ordinary skill in the art of this technology, without departing from the principle of the present invention, several improvements and refinements can be made, and these improvements and refinements should also be regarded as the protection scope of the present invention.

Claims

1. A preparation method of an embedded multi-chip interconnection bridge, characterized in that The method includes the following steps: Symmetrically press-fit ABF materials on both sides of a carrier board to obtain a press-fitted board; Drill positioning holes at the four corners of the press-fitted board, and then perform double-sided electroless copper plating to obtain a copper seed layer; Apply a dry film, expose, and develop on the two side surfaces of the copper seed layer in sequence to obtain a dry film pattern board; Perform pattern electroplating on the two side surfaces of the dry film pattern board to form electroplated copper circuits, and then perform film stripping, flash etching, and palladium removal in sequence to form a copper circuit layer, thereby obtaining a copper circuit board; Perform super roughening, press-fitting, and punching on the two side surfaces of the copper circuit board in sequence to obtain a board to be split; the press-fitting is to press-fit ABF resin on the surface after super roughening; Perform symmetrical splitting and full-board etching on the board to be split in sequence to obtain a split board; only one layer of copper foil is retained on the board obtained after symmetrical splitting; After pressing ABF resin on the two side surfaces of the split board, perform punching, symmetrical shaping, and immersion nickel and gold plating in sequence to obtain the embedded multi-chip interconnect bridge, the symmetrical shaping is cut along the circuit center of the copper circuit layer, and the circuit section of the symmetrical shaping is a matrix-shaped pad.

2. The preparation method according to claim 1, characterized in that, The carrier board is a coreless board, and the thickness of the coreless board is 0.1 - 1 mm.

3. The preparation method according to claim 2, characterized in that, The coreless board includes an intermediate dielectric layer and an outer copper foil layer, and the thickness of the outer copper foil layer is 2 - 18 μm.

4. The preparation method according to claim 1, characterized in that, The thickness of the ABF material for symmetrically press-fitting ABF material is 5 - 30 μm.

5. The preparation method according to claim 1, characterized in that, The positioning holes are through holes or blind holes.

6. The preparation method according to claim 1, characterized in that, The thickness of the copper seed layer is 0.5 - 1 μm.

7. The preparation method according to claim 1, characterized in that, The thickness, line width, and pitch of the copper circuit layer are independently 5 - 30 μm.

8. The preparation method according to claim 1, wherein, The thickness of the board obtained after pressing ABF resin is 0.2 - 2 mm.

9. An embedded multi-chip interconnect bridge, characterized in that, Prepared by the preparation method according to any one of claims 1 - 8.

10. Application of an embedded multi-chip interconnect bridge, characterized in that, Apply the embedded multi-chip interconnect bridge according to claim 9 to the field of integrated circuit packaging.

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