Wafer testing method, system, equipment and medium

Abstract

The invention provides a wafer testing method, system and device and a medium, and the method comprises the steps: carrying out the appearance scanning of the back surface of a to-be-tested wafer based on a plurality of preset positioning identifiers on the to-be-tested wafer, so as to generate a position map for representing the position information of each crystal grain on the to-be-tested wafer; storing the position map and the wafer number corresponding to the position map to a cloud server; loading a position map stored in the cloud server into a test machine according to the wafer number; and putting the to-be-tested wafer into the test machine table to execute a test based on the loaded position map. According to the invention, the wafer testing efficiency can be effectively improved, and the productivity can be improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor production applications, and particularly to a wafer testing method, system, device, and medium. Background Art

[0002] Currently, when manufacturing semiconductor products, a wafer is cut and split into multiple die, that is, a wafer contains multiple die. To ensure the yield of the products, it is often necessary to perform multiple processes of inspection on the wafer. And each time the wafer is inspected, it is usually necessary to scan the wafer. Currently, the mainstream testing machines on the market take more than 7 minutes to scan the wafer to ensure accurate testing of the positions of the corresponding die on the wafer, and each test goes through a scan of the entire wafer, which will result in a longer in-process time of the product, and the production efficiency and output of the product will be greatly restricted. Summary of the Invention

[0003] In view of the above problems existing in the prior art, the present invention proposes a wafer testing method, system, device, and medium, mainly solving the problem that the long time-consuming of the existing wafer testing affects the production efficiency and production capacity.

[0004] To achieve the above object and other objects, the technical solutions adopted by the present invention are as follows.

[0005] The present application provides a wafer testing method, including: performing an appearance scan on the back surface of the to-be-tested wafer based on a plurality of preset positioning marks on the to-be-tested wafer to generate a position map for characterizing the position information of each die on the to-be-tested wafer; saving the position map and the wafer number corresponding to the position map to a cloud server; loading the position map saved in the cloud server into a testing machine according to the wafer number; and placing the to-be-tested wafer into the testing machine to perform a test based on the loaded position map.

[0006] In an embodiment of the present application, the step of performing an appearance scan on the back surface of the to-be-tested wafer based on a plurality of preset positioning marks on the to-be-tested wafer includes: taking any positioning mark as the origin mark; taking a die adjacent to the origin mark as the scan origin to establish a wafer coordinate system; and scanning the remaining to-be-scanned die located under the wafer coordinate system to generate the position map.

[0007] In an embodiment of the present application, the step of scanning the remaining to-be-scanned die located under the wafer coordinate system includes: generating virtual coordinates of the remaining to-be-scanned die in the wafer coordinate system according to the position information of the remaining to-be-scanned die relative to the scan origin; determining the mechanical coordinates of the remaining to-be-scanned die through the virtual coordinates of the remaining to-be-scanned die and the size information of the remaining to-be-scanned die; and associating the virtual coordinates with the mechanical coordinates to obtain the position map.

[0008] In an embodiment of the present application, before saving the position map and the corresponding wafer number to the cloud server, the following steps are further included: sorting each die in the to-be-tested wafer according to the virtual coordinates of each die in the wafer coordinate system; generating a pre-scan document for storing the position map based on the sorting result, and uploading the pre-scan document to the cloud server for storage.

[0009] In an embodiment of the present application, the step of performing a test based on the loaded position map includes: when performing a wafer test, positioning the wafer according to the positioning identifier, and obtaining the test origin of the to-be-tested wafer; aligning the test origin with the scan origin in the loaded position map, and performing a test according to the position information of each die in the position map starting from the test origin.

[0010] In an embodiment of the present application, after placing the to-be-tested wafer into the test machine, the following steps are further included: retrieving positioning identifiers from multiple preset regions of the to-be-tested wafer; determining the test origin of the to-be-tested wafer according to the retrieved positioning identifiers.

[0011] In an embodiment of the present application, the step of positioning the wafer according to the positioning identifier includes: obtaining the pattern information in each positioning identifier; determining that the wafer is positioned after the alignment of each positioning identifier according to the position and angle of the pattern information, and obtaining the corresponding test origin.

[0012] The present application further provides a wafer test system, including: a back inspection module, configured to perform an appearance scan on the back of the to-be-tested wafer based on multiple preset positioning identifiers on the to-be-tested wafer to generate a position map for characterizing the position information of each die on the to-be-tested wafer; a data uploading module, configured to save the position map and the corresponding wafer number to the cloud server; a data loading module, configured to load the position map saved in the cloud server into the test machine according to the wafer number; a wafer test module, configured to place the to-be-tested wafer into the test machine to perform a test based on the loaded position map.

[0013] The present application further provides a computer device, including: a memory, a processor, and a computer program stored on the memory and executable on the processor, where when the processor executes the computer program, the steps of the wafer test method are implemented.

[0014] The present application further provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the wafer test method are implemented.

[0015] As described above, a wafer test method, system, device, and medium proposed by the present application have the following beneficial effects.

[0016] Generating a position map by performing an appearance scan on the back side of the wafer to be tested can be used for subsequent various tests on the wafer to be tested, reducing the time spent on wafer scanning during testing, greatly improving the testing efficiency, and being beneficial to improving the product production efficiency. Description of the Drawings

[0017] Figure 1 It is a schematic flowchart of a wafer testing method in an embodiment of the present application.

[0018] Figure 2 It is a schematic diagram of a wafer provided with positioning marks in an embodiment of the present application.

[0019] Figure 3 It is a schematic diagram of the positioning marks in an embodiment of the present application.

[0020] Figure 4 It is a schematic diagram of the data in the scanned document in an embodiment of the present application.

[0021] Figure 5 It is a schematic diagram of the retrieval area of the positioning marks in the wafer to be tested in an embodiment of the present application.

[0022] Figure 6 It is a module diagram of a wafer testing system in an embodiment of the present application.

[0023] Figure 7 It is a schematic diagram of the architecture of a computer device in an embodiment of the present application.

[0024] Description of the Reference Numerals in the Drawings:

[0025] 1 - Wafer; 2 - Central positioning mark; 3 - Upper positioning mark; 4 - Left positioning mark; 5 - Right positioning mark; 6 - Lower positioning mark; 7 - LED chip; 8 - First column of data; 9 - Second column of data; 10 - Third column of data; 11 - Fourth column of data; 12 - Fifth column of data; 13 - Third retrieval area; 14 - Fourth retrieval area; 15 - First retrieval area; 16 - Second retrieval area; 17 - Fifth retrieval area; 60 - Back inspection module; 61 - Data upload module; 62 - Data loading module; 63 - Wafer testing module; 71 - Memory; 711 - Internal memory; 72 - Processor; 73 - Non-volatile storage medium; 74 - Display screen; 75 - Network interface. Detailed Embodiment

[0026] The following specific examples illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0027] It should be noted that the diagrams provided in the following embodiments only schematically illustrate the basic concept of the present invention. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0028] Term Explanation: AOI (Automated Optical Inspection) is a device that detects common defects encountered in welding production based on optical principles. AOI is a newly emerging new testing technology, but it has developed rapidly, and many manufacturers have launched AOI testing equipment. When automatically detecting, the machine automatically scans the object to be tested through a camera, collects images, compares the tested solder joints with the qualified parameters in the database, and after image processing, checks for defects on the object to be tested and displays / marks the defects through a display or an automatic marker for maintenance personnel to repair.

[0029] Please refer to Figure 1 , Figure 1 , which is a schematic flowchart of a wafer testing method in an embodiment of the present application. The wafer testing method includes the following steps:

[0030] Step S100: Perform an appearance scan on the back surface of the wafer to be tested based on multiple preset positioning marks on the wafer to be tested, so as to generate a position map for characterizing the position information of each die on the wafer to be tested.

[0031] Please refer to Figure 2 , Figure 2 , which is a schematic diagram of a wafer provided with positioning marks in an embodiment of the present application. Multiple positioning marks can be set on the wafer 1 to be tested. Exemplarily, 5 positioning marks can be set on each wafer 1 to be tested, which are respectively denoted as the left positioning mark 4, the right positioning mark 5, the upper positioning mark 3, the lower positioning mark 6, and the center positioning mark 2. The positioning marks can be made of materials such as a developing coating or a developing solution, and the patterns of the corresponding positioning marks can be displayed when illuminated. The positioning marks can be set as regular polygon patterns, such as rectangles or crosses, etc. The specific patterns and sizes of the positioning marks can be set and adjusted according to actual application requirements, and are not limited here.

[0032] In one embodiment, before performing various tests on the wafer to be tested, the back surface of the wafer to be tested can be subjected to an appearance scan (i.e., AOI back inspection) to generate a pre-scanned document. The document can store a position map corresponding to the wafer to be tested, and the position map is used to characterize the position information of each die in the wafer relative to the scan origin of the wafer.

[0033] In one embodiment, the step of performing an appearance scan on the back surface of the wafer to be tested based on a plurality of preset positioning marks on the wafer to be tested includes: taking any positioning mark as the origin mark; taking a die adjacent to the origin mark as the scan origin to establish a wafer coordinate system; and scanning the remaining dies to be scanned located in the wafer coordinate system to generate the position map.

[0034] Please refer to Figure 3 , Figure 3 which is a schematic diagram of the positioning marks in an embodiment of the present application. A corresponding pattern can also be set at the center of each positioning mark. The pattern can be a cross, a polygon, etc. The specific pattern can be set according to actual application requirements and is not limited here. Precise positioning is performed through the internal patterns of a plurality of positioning marks on the wafer to be tested. Specifically, after the positioning marks are made on the wafer, the first die in the upper left corner of the center positioning mark 2 can be designated as the scan origin. Taking the positioning mark with a cross pattern as an example, the straight line passing through the center cross horizontal line of the left positioning mark 4, the center positioning mark 2, and the right positioning mark 5 is denoted as the first straight line, and the straight line connecting the center cross vertical line of the upper positioning mark 3 and the lower positioning mark 6 is denoted as the second straight line. Then, the straight line passing through the scan origin and parallel to the first straight line is used as the horizontal axis, and the straight line passing through the scan origin and parallel to the second straight line is used as the vertical axis to construct the wafer coordinate system. The wafer coordinate system is based on dies as units to obtain the virtual coordinates of the dies. Based on the virtual coordinates of the dies and the size information of the dies, the mechanical coordinates of the corresponding dies can be calculated. The die can be an LED chip 7 or other chips that meet the actual production requirements and is not limited here.

[0035] In one embodiment, the step of scanning the remaining dies to be scanned in the wafer coordinate system includes: generating the virtual coordinates of the remaining dies to be scanned in the wafer coordinate system according to the position information of the remaining dies to be scanned relative to the scan origin; determining the mechanical coordinates of the die to be scanned through the virtual coordinates of the remaining dies to be scanned and the size information of the remaining dies to be scanned; and associating the virtual coordinates with the mechanical coordinates to obtain the position map. Among them, the remaining dies to be scanned refer to the dies other than the scan origin in the same wafer.

[0036] Specifically, the virtual coordinates of the scanning origin can be expressed as (0, 0). Then, the virtual coordinates of each die away from the coordinate origin in the positive direction of the horizontal axis of the wafer coordinate system can be expressed as (0, 1), (0, 2), ……, (0, n), and the virtual coordinates of each die away from the coordinate origin in the negative direction of the horizontal axis of the wafer coordinate system can be expressed as (-1, 0), (-2, 0), ……, (-n, 0), where n is a positive integer, and the virtual coordinates of the dice in each coordinate quadrant can be deduced by analogy. The corresponding mechanical coordinates can be calculated according to the virtual coordinates of each die. Exemplarily, assume that the virtual coordinates of the scanning origin (0, 0) can be expressed as (30, 18), the length of the die is 200μm, and the width is 100μm. Then, the mechanical coordinates of the die with virtual coordinates (2, 5) are (430, 518), where 430 = 2 * 200 + 30 and 518 = 5 * 100 + 18. The mechanical coordinates of other dice can be deduced by analogy. In this way, the mechanical coordinates of each die can be obtained, and subsequent die testing can be performed based on the mechanical coordinates of the die. Of course, the size of the die and the mechanical coordinates of the scanning origin can also be set and adjusted according to the differences in actual products and testing machines, which are not limited here. The mechanical coordinates are associated with the virtual coordinates of the die to obtain the position map of the wafer to be tested. The associated data is stored in the aforementioned pre-scanning document. The virtual coordinates in the position map are mainly used to determine the position of the die in the pre-scanning file, so that when the subsequent testing machine loads the position map, the mechanical coordinates of the die can be obtained from the corresponding position of the pre-scanning file, facilitating the positioning and testing of the die by the testing machine according to the mechanical coordinates.

[0037] In one embodiment, the virtual coordinates of each die in the wafer coordinate system can be sorted, and the sorted die information can be stored in the document generated by pre-scanning. The sorting method can be to save the scanning information of each die as a data sequence in the order of increasing horizontal axis first and then increasing vertical axis. An exemplary data sequence can be expressed as {(0, 1), (0, 2), ……, (0, n), (1, 1), (1, 2), ……, (1, m), ……, (-1, 0), (-2, 0), ……, (-m, 0), (-1, -1), (-2, -1), ……, (-m, -1), ……, (-1, 1), (-1, 2), ……, (-1, n)}, where both m and n are positive integers, and m is greater than n. A corresponding pre-scanning document can be generated based on the data sequence. Please refer to Figure 4 , Figure 4 FIG. for a schematic diagram of the data in the document obtained by scanning in an embodiment of the present application. The pre-scanning document can also be presented in the form of a data table. Figure 4In the first column of the data, 8 represents the grain serial number, in the second column, 9 represents the virtual abscissa of the corresponding grain, in the third column, 10 represents the virtual ordinate of the corresponding grain, in the fourth column, 11 represents the real abscissa of the corresponding grain, and in the fifth column, 12 represents the real ordinate of the corresponding grain. The specific sorting method and the form of the scanned document carrier can also be set and adjusted according to the actual application requirements, which are not limited here.

[0038] Step S110: Save the position map and the corresponding wafer number of the wafer to the cloud server.

[0039] In one embodiment, the pre-scanned document can be uploaded to the cloud server so that the pre-scanned document can be loaded from the cloud server to assist in completing the test during subsequent tests.

[0040] In one embodiment, after generating the position map of the wafer to be tested, the position map can be associated with the wafer number of the corresponding wafer to be tested and stored in the cloud server. Specifically, each wafer has a corresponding wafer number. The name of the pre-scanned document containing the position map is saved as the corresponding wafer number, thereby associating the wafer number with the position map. After the wafer to be tested completes the back inspection scan, the pre-scanned document can be uploaded to the cloud server for storage.

[0041] Step S120: Load the position map saved in the cloud server into the test machine according to the wafer number.

[0042] In one embodiment, when performing wafer testing, the position map corresponding to the wafer to be tested is obtained based on the wafer number. The corresponding pre-scanned document can be directly retrieved from the location where the pre-scanned document is stored according to the wafer number of the wafer to be tested to complete data loading. The specific association method between the position map and the wafer number can be adjusted according to the actual application requirements, which are not limited here.

[0043] Step S130: Place the wafer to be tested into the test machine to perform the test based on the loaded position map.

[0044] In one embodiment, after placing the wafer to be tested into the test machine, it further includes: retrieving the positioning marks from multiple preset areas of the wafer to be tested; determining the test origin of the wafer to be tested according to the retrieved positioning marks. Specifically, since the back appearance scan and the test of the same wafer to be tested are often not in the same process, when the wafer to be tested is transferred to the test machine after the appearance scan, the placement position of the wafer to be tested often changes, and the accurate position of the positioning mark cannot be directly obtained as in the back appearance scan. Therefore, it is necessary to retrieve the positions of the positioning marks in the wafer to determine the test origin of the wafer to be tested based on the positioning marks. Please refer to Figure 5 , Figure 5Schematic diagram of the retrieval area of the positioning mark in the wafer to be tested in an embodiment of the present application. Before wafer testing, the wafer to be tested can be placed at a specified position on the test machine table, and the test equipment will retrieve the positioning mark from multiple preset retrieval areas on the wafer to be tested. The size of the retrieval area can be set and adjusted according to actual application requirements, which is not limited here. Taking the five positioning marks preset in the above steps as an example, the retrieval area is also correspondingly set to five. If the positioning mark is not retrieved in any one of the retrieval areas, it is determined that the placement position of the wafer is deviated too much, and an alarm message is output to remind the operator to adjust the position of the wafer on the test machine table. If the corresponding positioning mark is retrieved in each retrieval area, the wafer is positioned based on the positioning mark. Specifically, it can be determined whether the patterns in each positioning mark are aligned. Taking the cross pattern as an example, it can be determined whether the horizontal lines of the crosses in the horizontal positioning marks are on a straight line, and whether the vertical lines of the crosses in the vertical positioning marks are on a straight line, so as to determine whether the retrieved positioning marks are aligned. At the same time, the test equipment is aligned based on the connection lines of the horizontal and vertical lines of the cross, the die at the upper left corner of the center positioning mark 2 is used as the test origin, and the test probe of the test equipment is moved to the test origin. Figure 5 In Figure 5 , the first retrieval area 15 is the retrieval area corresponding to the left positioning mark 4, the second retrieval area 16 is the target area corresponding to the right positioning mark 5, the third retrieval area 13 is the retrieval area corresponding to the center positioning mark 2, the fourth retrieval area 14 is the retrieval area corresponding to the upper positioning mark 3, and the fifth retrieval area 17 is the retrieval area corresponding to the lower positioning mark 6. When placing the wafer to be tested on the corresponding test machine table of the test equipment, the pre-scanned document stored in the cloud can be retrieved according to the wafer number of the wafer to be tested, and then the position map in the pre-scanned document can be obtained. The specific size of the retrieval area range can be set and adjusted according to actual application requirements, which is not limited here. The test equipment only needs to retrieve within the retrieval area range to obtain the current position of the positioning mark. Taking the positioning mark as a rectangle as an example, the current position of the positioning mark includes the coordinates of each vertex angle of the positioning mark, the coordinates of the center point of the positioning mark, etc.

[0045] In an embodiment, when wafer positioning is performed, it can be determined whether the corresponding positioning marks are aligned according to the patterns in two horizontal or vertical positioning marks. If the positioning marks are aligned, the COT test equipment can perform automatic alignment according to the connection line of the patterns in the positioning marks to ensure that the wafer coordinate system during back inspection is consistent with the wafer coordinate system during testing. Automatic alignment is a conventional function setting of the test equipment, and the specific alignment process will not be elaborated here.

[0046] In one embodiment, the steps of performing tests based on the test origin and the position information of each die in the called position map include: aligning the test origin with the scan origin in the called position map, starting from the test origin, and performing die positioning and completing the tests according to the virtual coordinates and mechanical coordinates of each die. Specifically, after determining the test origin within the wafer to be tested, the position map loaded from the cloud server is imported into the test machine so that the scan origin in the position map coincides with the test origin of the wafer to be tested. The test machine can then move and perform tests according to the virtual coordinates and mechanical coordinates of each die in the position map, and there is no need to scan each die, thereby shortening the test time. The test equipment performs COT tests mainly by bringing the test probe into contact with the front side of the die to test the electrical performance of the die, and if the test is unqualified, the corresponding die is marked. After wafer testing, wafer AOI front inspection is performed to determine whether there is any damage to the wafer by the probe during the test process. After completing the front inspection, sorting is performed to obtain qualified dice. The specific wafer test method and test content can be set and adjusted according to actual application requirements and are not limited here.

[0047] Based on the above technical solution of the present application, the wafer scan origin can be determined based on a preset positioning identifier before wafer testing, and a pre-scan document can be obtained by scanning based on the scan origin. The position of the die can be directly determined by calling the pre-scan document in subsequent stages of wafer testing, reducing the scan time for each test and improving the test efficiency and production capacity.

[0048] In one embodiment, as Figure 6 shown, a wafer test system is provided, which includes: a back inspection module 60 for performing an appearance scan on the back of the wafer to be tested based on a plurality of preset positioning identifiers on the wafer to be tested to generate a position map for characterizing the positions of the dice on the wafer to be tested; a data upload module 61 for saving the position map and the wafer lot number corresponding to the position map to the cloud server; a data loading module 62 for loading the position map saved in the cloud server into the test machine according to the wafer lot number; and a wafer test module 63 for placing the wafer to be tested into the test machine to perform tests based on the loaded position map.

[0049] In one embodiment, the back inspection module 60 is further configured to perform the following steps: using any one of the positioning identifiers as the origin identifier; taking a die adjacent to the origin identifier as the scan origin to establish a wafer coordinate system; and scanning the remaining dice to be scanned under the wafer coordinate system to generate the position map.

[0050] In one embodiment, the back inspection module 60 is further configured to perform the following steps: generate virtual coordinates of the remaining wafers to be scanned in the wafer coordinate system according to the position information of the remaining wafers to be scanned relative to the scanning origin; determine the mechanical coordinates of the remaining wafers to be scanned through the virtual coordinates of the remaining wafers to be scanned and the size information of the remaining wafers to be scanned; associate the virtual coordinates with the mechanical coordinates to obtain the position map.

[0051] In one embodiment, the wafer testing module 63 is further configured to perform the following steps: when performing wafer testing, perform wafer positioning according to the positioning identifier and obtain the test origin of the wafer to be tested; align the test origin with the scanning origin in the loaded position map, and perform testing according to the position information of each die in the position map starting from the test origin.

[0052] In one embodiment, the data uploading module 61 is further configured to perform the following steps: sort each die in the wafer to be tested according to the virtual coordinates of each die in the wafer coordinate system; generate a pre-scan document for storing the position map based on the sorting result, and upload the pre-scan document to the cloud server for storage.

[0053] In one embodiment, the wafer testing module 63 is further configured to perform the following steps: when performing wafer testing, perform wafer positioning according to the positioning identifier and obtain the test origin of the wafer to be tested; align the test origin with the scanning origin in the loaded position map, and perform testing according to the position information of each die in the position map starting from the test origin.

[0054] In one embodiment, the wafer testing module 63 is further configured to perform the following steps: retrieve positioning identifiers from multiple preset regions of the wafer to be tested; determine the test origin of the wafer to be tested according to the retrieved positioning identifiers.

[0055] In one embodiment, the wafer testing module 63 is further configured to perform the following steps: obtain the pattern information in each positioning identifier; determine that the wafer is positioned after the positioning identifiers are aligned according to the position and angle of the pattern information, and obtain the corresponding test origin.

[0056] The above wafer testing system can be implemented in the form of a computer program, and the computer program can run on a computer device as shown in Figure 7 The computer device includes: a memory 71, a processor 72, and a computer program stored on the memory 71 and executable on the processor 72.

[0057] Each module in the above wafer testing system can be implemented in whole or in part by software, hardware, or a combination thereof. Each of the above modules can be embedded in or independent of the memory 71 of the terminal in the form of hardware, or stored in the memory 71 of the terminal in the form of software, so that the processor 72 can call and execute the operations corresponding to each of the above modules. The processor 72 can be a central processing unit (CPU), a microprocessor, a single-chip microcomputer, etc.

[0058] As Figure 7 shown, it is a schematic internal structure diagram of a computer device in an embodiment. A computer device is provided, including: a memory 71, a processor 72, and a computer program stored on the memory 71 and executable on the processor 72. When the processor 72 executes the computer program, the following steps are implemented: performing an appearance scan on the back surface of the wafer to be tested based on a plurality of preset positioning marks on the wafer to be tested, so as to generate a position map for characterizing the position information of each die on the wafer to be tested; saving the position map and the wafer serial number corresponding to the position map to a cloud server; loading the position map saved in the cloud server into a test machine according to the wafer serial number; and placing the wafer to be tested into the test machine to perform a test based on the loaded position map.

[0059] In one embodiment, when the above processor 72 executes, the step of performing an appearance scan on the back surface of the wafer to be tested based on a plurality of preset positioning marks on the wafer to be tested includes: taking any positioning mark as the origin mark; taking a die adjacent to the origin mark as the scan origin to establish a wafer coordinate system; and scanning the remaining dies to be scanned located in the wafer coordinate system to generate the position map.

[0060] In one embodiment, when the above processor 72 executes, the step of scanning the remaining dies to be scanned in the wafer coordinate system includes: generating virtual coordinates of the remaining dies to be scanned in the wafer coordinate system according to the position information of the remaining dies to be scanned relative to the scan origin; determining the mechanical coordinates of the remaining dies to be scanned through the virtual coordinates of the remaining dies to be scanned and the size information of the remaining dies to be scanned; and associating the virtual coordinates with the mechanical coordinates to obtain the position map.

[0061] In one embodiment, before saving the position map and the wafer serial number corresponding to the position map to the cloud server when the above processor 72 executes, the following steps are further included: sorting each die according to the virtual coordinates of each die in the wafer coordinate system in the wafer to be tested; generating a pre-scan document for storing the position map based on the sorting result, and uploading the pre-scan document to the cloud server for storage.

[0062] In one embodiment, when the above-mentioned processor 72 executes, the steps of performing tests based on the loaded position map include: during wafer testing, positioning the wafer according to the positioning identifier and obtaining the test origin of the wafer to be tested; aligning the test origin with the scan origin in the loaded position map, and starting from the test origin, performing tests according to the position information of each die in the position map.

[0063] In one embodiment, after the above-mentioned processor 72 executes and the wafer to be tested is placed in the test machine, it further includes: retrieving positioning identifiers from multiple preset regions of the wafer to be tested; determining the test origin of the wafer to be tested according to the retrieved positioning identifiers.

[0064] In one embodiment, when the above-mentioned processor 72 executes, the steps of positioning the wafer according to the positioning identifier include: obtaining the pattern information in each positioning identifier; determining that wafer positioning is completed after the alignment of each positioning identifier according to the position and angle of the pattern information, and obtaining the corresponding test origin.

[0065] In one embodiment, the above computer device can be used as a server, including but not limited to an independent physical server, or a server cluster composed of multiple physical servers. The computer device can also be used as a terminal, including but not limited to mobile phones, tablets, personal digital assistants, or smart devices, etc. As Figure 7 shown, the computer device includes a processor 72, a non-volatile storage medium 73, an internal memory 711, a display screen 74, and a network interface 75 connected through a system bus.

[0066] Among them, the processor of the computer device is used to provide computing and control capabilities to support the operation of the entire computer device. The non-volatile storage medium 73 of the computer device stores an operating system and computer programs. The computer programs can be executed by the processor 72 to implement a wafer testing method provided by each of the above embodiments. The internal memory 711 in the computer device provides a high-speed cache operating environment for the operating system and computer programs in the non-volatile storage medium 73. The display interface can display data through the display screen 74. The display screen 74 can be a touch screen, such as a capacitive screen or an electronic screen, and can generate corresponding instructions by receiving click operations on the controls displayed on the touch screen.

[0067] Those skilled in the art can understand that Figure 7 the structure of the computer device shown in

[0068] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor 72, the following steps are implemented: performing an appearance scan on the back surface of the wafer to be tested based on a plurality of preset positioning marks on the wafer to be tested, so as to generate a position map for characterizing the position information of each die on the wafer to be tested; saving the position map and the wafer lot number corresponding to the position map to a cloud server; loading the position map saved in the cloud server into a test machine according to the wafer lot number; and placing the wafer to be tested into the test machine to perform a test based on the loaded position map.

[0069] In one embodiment, when the computer program is executed by the processor 72, the step of performing an appearance scan on the back surface of the wafer to be tested based on a plurality of preset positioning marks on the wafer to be tested includes: taking any one of the positioning marks as an origin mark; taking a die adjacent to the origin mark as a scan origin to establish a wafer coordinate system; and scanning the remaining dies to be scanned located in the wafer coordinate system to generate the position map.

[0070] In one embodiment, when the computer program is executed by the processor 72, the step of scanning the remaining dies to be scanned located in the wafer coordinate system includes: generating virtual coordinates of the remaining dies to be scanned in the wafer coordinate system according to the position information of the remaining dies to be scanned relative to the scan origin; determining the mechanical coordinates of the remaining dies to be scanned through the virtual coordinates of the remaining dies to be scanned and the size information of the remaining dies to be scanned; and associating the virtual coordinates with the mechanical coordinates to obtain the position map.

[0071] In one embodiment, before saving the position map and the wafer lot number corresponding to the position map to the cloud server when the computer program is executed by the processor 72, the following steps are further included: sorting each die according to the virtual coordinates of each die in the wafer coordinate system in the wafer to be tested; generating a pre-scan document for storing the position map based on the sorting result, and uploading the pre-scan document to the cloud server for storage.

[0072] In one embodiment, when the computer program is executed by the processor 72, the step of performing a test based on the loaded position map includes: during wafer testing, positioning the wafer according to the positioning mark and obtaining the test origin of the wafer to be tested; aligning the test origin with the scan origin in the loaded position map, and starting from the test origin, performing a test according to the position information of each die in the position map.

[0073] In one embodiment, after the computer program is executed by the processor 72 and the to-be-tested wafer is placed into the testing machine, the following steps are further included: retrieving positioning identifiers from multiple preset regions of the to-be-tested wafer; and determining the test origin of the to-be-tested wafer according to the retrieved positioning identifiers.

[0074] In one embodiment, the step of wafer positioning according to the positioning identifiers when the computer program is executed by the processor 72 includes: obtaining the pattern information in each of the positioning identifiers; and determining that wafer positioning is completed after the positioning identifiers are aligned according to the position and angle of the pattern information, and obtaining the corresponding test origin.

[0075] In one embodiment, the above computer device can be used as a server, including but not limited to an independent physical server or a server cluster composed of multiple physical servers. The computer device can also be used as a terminal, including but not limited to mobile phones, tablet computers, personal digital assistants, or smart devices, etc. As Figure 7 shown, the computer device includes a processor 72, a non-volatile storage medium 73, an internal memory 711, a display screen 74, and a network interface 75 connected through a system bus.

[0076] Among them, the processor of the computer device is used to provide computing and control capabilities to support the operation of the entire computer device. The non-volatile storage medium 73 of the computer device stores an operating system and a computer program. The computer program can be executed by the processor 72 to implement a wafer testing method provided in each of the above embodiments. The internal memory 711 in the computer device provides a high-speed cache operating environment for the operating system and the computer program in the non-volatile storage medium 73. The display interface can display data through the display screen 74. The display screen 74 can be a touch screen, such as a capacitive screen or an electronic screen, and can generate corresponding instructions by receiving click operations on the controls displayed on the touch screen.

[0077] Those of ordinary skill in the art can understand that all or part of the processes in the methods of the above embodiments can be completed by instructing relevant hardware through a computer program. The program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above methods. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only memory (ROM), etc.

[0078] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A wafer testing method, characterized in that, Including: Performing an appearance scan on the back of the wafer under test based on a plurality of preset positioning marks on the wafer under test to generate a position map for characterizing the position information of each die on the wafer under test; Saving the position map and the corresponding wafer lot number to a cloud server; Loading the position map saved in the cloud server into a test machine according to the wafer lot number; And Placing the wafer under test into the test machine to perform a test based on the loaded position map.

2. The wafer testing method according to claim 1, wherein The step of performing an appearance scan on the back of the wafer under test based on a plurality of preset positioning marks on the wafer under test includes: Taking any one of the positioning marks as the origin mark; Taking a die adjacent to the origin mark as the scan origin to establish a wafer coordinate system; Scanning the remaining dies to be scanned under the wafer coordinate system to generate the position map.

3. The wafer testing method according to claim 2, wherein The step of scanning the remaining dies to be scanned under the wafer coordinate system includes: Generating virtual coordinates of the remaining dies to be scanned under the wafer coordinate system according to the position information of the remaining dies to be scanned relative to the scan origin; Determining the mechanical coordinates of the remaining dies to be scanned through the virtual coordinates of the remaining dies to be scanned and the size information of the remaining dies to be scanned; Associating the virtual coordinates with the mechanical coordinates to obtain the position map.

4. The wafer testing method according to claim 3, characterized in that, Before saving the position map and the corresponding wafer lot number to the cloud server, the following steps are further included: Sorting each die in the wafer under test according to the virtual coordinates of each die under the wafer coordinate system; Generating a pre-scan document for storing the position map based on the sorting result, and uploading the pre-scan document to the cloud server for storage.

5. The wafer testing method according to claim 1, wherein The step of performing a test based on the loaded position map includes: Performing wafer positioning according to the positioning mark and obtaining the test origin of the wafer under test; Aligning the test origin with the scan origin in the loaded position map, and starting from the test origin, performing a test according to the position information of each die in the position map.

6. The wafer testing method according to claim 5, wherein After placing the wafer under test into the test machine, the following is further included: Retrieving positioning marks from a plurality of preset regions of the wafer under test; Determining the test origin of the wafer under test according to the retrieved positioning marks.

7. The wafer testing method according to claim 5, characterized in that, The step of performing wafer positioning according to the positioning mark includes: Obtaining the pattern information of each positioning mark; Determining that wafer positioning is completed after alignment of each positioning mark according to the position and angle of the pattern information, and obtaining the corresponding test origin.

8. A wafer testing system, characterized in that, Including: A back inspection module for performing an appearance scan on the back of the wafer under test based on a plurality of preset positioning marks on the wafer under test to generate a position map for characterizing the position information of each die on the wafer under test; A data upload module for saving the position map and the corresponding wafer lot number to a cloud server; A data loading module for loading the position map saved in the cloud server into a test machine according to the wafer lot number; A wafer test module for placing the wafer under test into the test machine to perform a test based on the loaded position map.

9. A computer device, comprising: A memory, a processor, and a computer program stored on the memory and executable on the processor, wherein the processor implements the steps of the wafer testing method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that, The computer program implements the steps of the wafer testing method according to any one of claims 1 to 7 when executed by the processor.

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