Packaging substrate and preparation method thereof

Abstract

The invention provides a packaging substrate and a preparation method thereof. The surface of a core board layer is provided with a core board circuit layer and core board through holes for filling the core board layer; a buffer layer is arranged between the core board circuit layers, a substrate adding layer is arranged on the core board circuit layers and the buffer layer, the communication groove penetrates through the substrate adding layer, and an interconnection lead layer is arranged between the side wall of the communication groove and the side wall of the silicon-based middle layer for electrical connection. The electrical connection points of the silicon-based middle layer are arranged on the side walls of the communication grooves, so that poor electrical connection contact caused by inaccurate alignment in the horizontal direction is avoided, the circuit interconnection accuracy is improved, and the interconnection circuit distance is shortened; meanwhile, the buffer layer is arranged in front of the silicon-based middle layer, so that the core plate layer exposed at the bottom of the communication groove is prevented from being damaged by laser drilling, and the structural flatness of the packaging substrate is ensured; in addition, the interconnection lead layer in the communication groove is prepared through a 3D printing method, and the preparation precision and the alignment precision of an interconnection lead layer circuit are improved; and finally, insulating glue is arranged for shielding crosstalk for a magnetic material, so that the signal integrity of the silicon-based intermediate layer is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor integrated circuit manufacturing, and particularly relates to a packaging substrate and a preparation method thereof. Background Art

[0002] With the rapid development of semiconductor industry technology, the number of I / O (input / output) pins on chips has increased. As a connection bridge between chips and printed circuit boards, more stringent requirements are put forward for the preparation of packaging substrates. The requirements for line fineness are getting higher and higher, and the requirements for controlling the shrinkage and warping of packaging substrates are even higher. Traditional packaging substrates can no longer meet the needs, and the development of advanced packaging technology has become the mainstream of the current era. Among them, heterogeneous integration applications are becoming more and more extensive. Multiple chips are embedded on the packaging substrate at the same time to form 2.5D or 3D multi-chip packaging. This technology is also called silicon interposer technology. Its advantage is that high-speed signals can be transmitted through the chips, greatly improving the transmission speed and greatly reducing signal loss. This solution greatly improves the transmission performance of the packaging substrate.

[0003] For silicon interposer technology, its technical solution is to bury silicon-based chips in the packaging substrate. There are still many technical difficulties in this technology, such as the position accuracy of burying silicon-based chips and the electrical interconnection accuracy after burying silicon-based chips. As a result, the electrical connection yield of silicon interposer packaging substrates is insufficient, making this technology unable to be widely applied in the industry.

[0004] Therefore, there is an urgent need for a preparation method that can improve the burying accuracy and electrical interconnection accuracy of silicon interposers in the substrate.

[0005] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely explaining the technical solutions of the present application and facilitating the understanding of those skilled in the art. It cannot be considered that the above technical solutions are well-known to those skilled in the art just because these solutions are described in the background art part of the present application. Summary of the Invention

[0006] In view of the above-mentioned disadvantages of the prior art, the purpose of the present invention is to provide a packaging substrate and a preparation method thereof, which are used to solve the problems of poor burying accuracy and electrical interconnection accuracy of silicon interposers buried in the substrate in the prior art.

[0007] To achieve the above purpose, the present invention provides a preparation method of a packaging substrate, and the preparation method includes:

[0008] Providing a core board layer, the core board layer includes a first surface and a second surface arranged opposite to each other;

[0009] Providing a core board through hole penetrating from the first surface to the second surface on the core board layer;

[0010] A patterned core board circuit layer is disposed on the surface of the core board layer. The core board circuit layer fills the core board through holes, and a buffer groove is included between the patterned core board circuit layers.

[0011] A buffer layer is disposed in the buffer groove, and the surface of the buffer layer is flush with the surface of the core board circuit layer.

[0012] An interposer dielectric layer including interposer through holes is disposed on the core board circuit layer. The interposer dielectric layer fills the gaps between the patterned core board circuit layers and between the buffer groove and the core board circuit layer and covers the surfaces of the core board circuit layer and the buffer layer. The interposer through holes penetrate the interposer dielectric layer and expose a part of the core board circuit layer.

[0013] A patterned interposer circuit layer is disposed on the interposer dielectric layer. The interposer circuit layer forms an effective electrical connection with the core board circuit layer through the interposer through holes. The interposer dielectric layer and the interposer circuit layer constitute an interposer build-up layer.

[0014] A groove is disposed in the interposer build-up layer, and the groove penetrates the interposer build-up layer to a preset depth. The groove corresponds and communicates with the buffer groove in a direction perpendicular to the core board layer, so that the bottom of the groove exposes the buffer layer.

[0015] The buffer layer is removed. The groove and the buffer groove together constitute a communication groove. The bottom of the communication groove exposes a part of the surface of the core board layer, and the side wall of the communication groove exposes preset substrate interconnection contacts of the core board circuit layer and / or the interposer circuit layer.

[0016] A silicon-based intermediate layer is disposed in the communication groove. The silicon-based intermediate layer is located on the part of the surface of the core board layer exposed at the bottom of the communication groove, and silicon-based intermediate layer interconnection contacts are disposed on the side wall of the silicon-based intermediate layer.

[0017] An interconnection lead layer is disposed in the gap between the side wall of the communication groove and the side wall of the silicon-based intermediate layer. The interconnection lead layer forms a preset effective electrical connection between the silicon-based intermediate layer interconnection contacts and the substrate interconnection contacts exposed on the side wall of the communication groove.

[0018] Optionally, the buffer layer is a release material or electroplated copper, and / or the interconnection lead layer is fabricated by a 3D printing method.

[0019] Optionally, an insulating adhesive is filled in the gap between the side wall of the communication groove and the side wall of the silicon-based intermediate layer where the interconnection lead layer is not disposed. The insulating adhesive also covers the surface of the silicon-based intermediate layer, so that the parts of the interconnection lead layer and the silicon-based intermediate layer that are not electrically interconnected are insulated.

[0020] Optionally, the insulating glue is a magnetic material.

[0021] Optionally, the method for setting the core board circuit layer includes:

[0022] A first seed layer is provided on the surface of the core board layer, and the first seed layer wraps all the exposed surfaces of the core board layer;

[0023] A first conductive layer is provided on the first seed layer, and the first conductive layer fills the core board through holes;

[0024] A patterned first photosensitive layer is provided on the first conductive layer to expose a part of the first conductive layer;

[0025] The first conductive layer exposed by the first photosensitive layer is etched, and the first seed layer exposed under the etched first conductive layer is removed;

[0026] The first photosensitive layer is removed to obtain a patterned core board circuit layer composed of the patterned first conductive layer and the first seed layer.

[0027] Optionally, before setting the core board through holes, core board conductive layers are respectively provided on the first surface and the second surface of the core board layer, and the core board through holes penetrate the core board conductive layers and the core board layer; after removing the first seed layer exposed under the etched first conductive layer, the exposed core board conductive layer is further removed downward to expose a part of the surface of the core board layer, and the buffer groove is included in the gap between the corresponding patterned core board conductive layer and the core board circuit layer; the build-up dielectric layer fills the gap between the patterned core board conductive layers.

[0028] Optionally, after setting the buffer layer, multiple substrate build-ups composed of build-up circuit layers and build-up dielectric layers are provided.

[0029] Optionally, after setting the silicon-based intermediate layer, a preset number of substrate build-ups are further provided on the silicon-based intermediate layer, and the further provided substrate build-ups also cover the surface of the substrate build-up located on the same horizontal plane as the silicon-based intermediate layer.

[0030] Optionally, a solder mask layer is filled in the gaps between the build-up circuit layers exposed on the surface of the packaging substrate, and / or a surface treatment layer is provided on the build-up circuit layers exposed on the surface of the packaging substrate.

[0031] The present invention also provides a packaging substrate, which is obtained by using any one of the above preparation methods, and the packaging substrate includes: a core board layer, a core board conductive layer, a core board circuit layer, multiple substrate build-ups, a silicon-based intermediate layer, an interconnection lead layer, a solder mask layer, and a surface treatment layer;

[0032] The core board layer includes a first surface and a second surface which are oppositely arranged. There is a layer of patterned core board conductive layer on each of the first surface and the second surface of the core board layer; the patterned core board circuit layer is located on the core board conductive layer, and the pattern on the core board circuit layer coincides with the projection of the pattern on the core board conductive layer on the core board layer. The gap between the patterned core board circuit layer and the core board conductive layer includes a buffer groove;

[0033] The substrate build-up layer includes a patterned build-up circuit layer and a build-up dielectric layer. The patterned build-up dielectric layer is filled in the gap of the underlying core board circuit layer or the build-up circuit layer and exposes a part of the underlying core board circuit layer or the build-up circuit layer. The build-up circuit layer is effectively electrically connected to the underlying exposed core board circuit layer or the build-up circuit layer through the patterned build-up dielectric layer;

[0034] A groove is provided in the substrate build-up layer. The groove corresponds and communicates with the buffer groove in the direction perpendicular to the core board layer. The groove and the buffer groove form a communication groove; the side wall of the communication groove exposes a part of the preset substrate interconnection contacts of the build-up circuit layer and / or the core board circuit layer. The silicon-based intermediate layer is located on a part of the surface of the core board layer exposed at the inner bottom of the communication groove. The side wall of the silicon-based intermediate layer is provided with silicon-based intermediate layer interconnection contacts. An interconnection lead layer is provided between the side wall of the communication groove and the side wall of the silicon-based intermediate layer. The interconnection lead layer effectively electrically connects the substrate interconnection contacts and the silicon-based intermediate layer interconnection contacts;

[0035] The solder mask layer is filled in the gap between the circuit layers of the substrate build-up layer exposed on the surface of the package substrate, and the surface treatment layer is located on the surface of the circuit layers of the substrate build-up layer exposed on the surface of the package substrate.

[0036] As above, the package substrate and its preparation method of the present invention have the following beneficial effects:

[0037] In the present invention, by arranging the electrical connection points of the silicon-based intermediate layer on the side wall of the communication groove for connection, it is avoided that the electrical connection is poor due to misalignment in the horizontal direction, the accuracy of line interconnection is improved, and the distance of the interconnection line is also shortened;

[0038] In the present invention, by providing a buffer layer before setting the silicon-based intermediate layer, it is avoided that the core board layer exposed at the bottom of the communication groove is damaged by laser drilling, and the structural flatness of the package substrate is ensured;

[0039] In the present invention, the interconnection lead layer in the communication groove is prepared by 3D printing, which improves the preparation accuracy of the lines of the interconnection lead layer and further improves the alignment accuracy;

[0040] The present invention improves the signal integrity of the silicon-based intermediate layer by using an insulating glue as a magnetic material to shield crosstalk. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 It shows a schematic structural diagram of the core board layer provided in Step 1 of the first embodiment of the present invention.

[0042] Figure 2 It shows a schematic structural diagram of the core board through holes provided in Step 2 of the first embodiment of the present invention.

[0043] Figure 3 It shows a schematic structural diagram of the first seed layer provided in an alternative example of Step 3 of the first embodiment of the present invention.

[0044] Figure 4 It shows a schematic structural diagram of the first conductive layer provided in an alternative example of Step 3 of the first embodiment of the present invention.

[0045] Figure 5 It shows a schematic structural diagram of the first photosensitive layer provided in an alternative example of Step 3 of the first embodiment of the present invention.

[0046] Figure 6 It shows a schematic structural diagram of the etching of the first conductive layer provided in an alternative example of Step 3 of the first embodiment of the present invention.

[0047] Figure 7 It shows a schematic structural diagram of the removal of the first photosensitive layer provided in an alternative example of Step 3 of the first embodiment of the present invention.

[0048] Figure 8 It shows a schematic structural diagram of the buffer layer provided in Step 4 of the first embodiment of the present invention.

[0049] Figure 9 It shows a schematic structural diagram of the build-up dielectric layer provided in Step 5 of the first embodiment of the present invention.

[0050] Figure 10 It shows a schematic structural diagram of the second seed layer provided in an alternative example of Step 6 of the first embodiment of the present invention.

[0051] Figure 11 It shows a schematic structural diagram of the second photosensitive layer provided in an alternative example of Step 6 of the first embodiment of the present invention.

[0052] Figure 12 It shows a schematic structural diagram of the second conductive layer provided in an alternative example of Step 6 of the first embodiment of the present invention.

[0053] Figure 13It shows a schematic structural diagram of removing the second photosensitive layer in an optional example of step 6 in the embodiment of the present invention.

[0054] Figure 14 It shows a schematic structural diagram of setting up a multi-layer substrate build-up in an optional example of step 6 in the embodiment of the present invention.

[0055] Figure 15 It shows a schematic structural diagram of setting up a groove in step 7 of the embodiment of the present invention.

[0056] Figure 16 It shows a schematic structural diagram of removing the buffer layer in step 8 of the embodiment of the present invention.

[0057] Figure 17 It shows a schematic structural diagram of setting up a silicon-based intermediate layer in step 9 of the embodiment of the present invention.

[0058] Figure 18 It shows a schematic structural diagram of setting up an interconnect lead layer in step 10 of the embodiment of the present invention.

[0059] Figure 19 It shows a schematic top view of a partial structure of connecting the silicon-based intermediate layer and the interconnect lead layer in the through hole in step 10 of the embodiment of the present invention.

[0060] Figure 20 It shows a schematic structural diagram of setting up an insulating adhesive in an optional example of step 10 in the embodiment of the present invention.

[0061] Figure 21 It shows a schematic structural diagram of setting up a build-up dielectric layer in the substrate build-up in an optional example of step 10 in the embodiment of the present invention.

[0062] Figure 22 It shows a schematic structural diagram of setting up a second seed layer in the substrate build-up in an optional example of step 10 in the embodiment of the present invention.

[0063] Figure 23 It shows a schematic structural diagram of setting up a second photosensitive layer in the substrate build-up in an optional example of step 10 in the embodiment of the present invention.

[0064] Figure 24 It shows a schematic structural diagram of setting up a second conductive layer in the substrate build-up in an optional example of step 10 in the embodiment of the present invention.

[0065] Figure 25 It shows a schematic structural diagram of removing the second photosensitive layer and the second seed layer in the substrate build-up in an optional example of step 10 in the embodiment of the present invention.

[0066] Figure 26It shows a schematic structural diagram presented by setting a solder mask layer and a surface treatment layer in an optional example of Step 10 of an embodiment of the present invention.

[0067] Figure 27 It shows a schematic structural diagram of a packaging substrate according to Embodiment 3 of the present invention.

[0068] Element number description

[0069] 10. Core board layer; 11. Core board conductive layer; 12. Core board through hole;

[0070] 20. Core board circuit layer; 21. First seed layer; 22. First conductive layer; 23. First photosensitive layer; 24. Buffer groove; 25. Buffer layer;

[0071] 31. Build-up dielectric layer; 311. Build-up through hole; 32. Build-up circuit layer; 321. Second seed layer; 322. Second photosensitive layer; 323. Second conductive layer; 33. Groove; 34. Interconnect lead layer; 341. Silicon-based intermediate layer interconnect contact; 342. Substrate interconnect contact; 35. Silicon-based intermediate layer; 36. Insulating adhesive; 37. Solder mask layer; 38. Surface treatment layer; 39. Communication groove. Detailed implementation manners

[0072] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0073] When detailing the embodiments of the present invention, for the convenience of description, the schematic diagrams showing the device structure will be enlarged locally not in accordance with the general scale, and the schematic diagrams are only examples, which should not limit the protection scope of the present invention here. In addition, in actual production, three-dimensional spatial dimensions including length, width and depth should be included.

[0074] For the convenience of description, spatial relationship terms such as "under", "below", "lower than", "beneath", "above", "on" etc. may be used here to describe the relationship between one element or feature shown in the drawings and other elements or features. It will be understood that these spatial relationship terms are intended to include other directions of the device in use or operation besides the directions depicted in the drawings.

[0075] In the context of the present application, the structure where the first feature is "above" the second feature may include an embodiment where the first and second features are in direct contact, and may also include an embodiment where additional features are formed between the first and second features, such that the first and second features may not be in direct contact.

[0076] It should be noted that the drawings provided in this embodiment only illustrate the basic concept of the present invention schematically. Therefore, only the components related to the present invention are shown in the drawings, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and ratios of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0077] Embodiment 1:

[0078] The present invention provides a method for preparing a packaging substrate, and the preparation method includes:

[0079] Step 1: Provide a core board layer, and the core board layer includes a first surface and a second surface arranged opposite to each other;

[0080] Step 2: Provide a core board through-hole penetrating from the first surface to the second surface on the core board layer;

[0081] Step 3: Provide a patterned core board circuit layer on the surface of the core board layer, the core board circuit layer fills the core board through-hole, and a buffer groove is included between the patterned core board circuit layers;

[0082] Step 4: Provide a buffer layer in the buffer groove, and the surface of the buffer layer is flush with the surface of the core board circuit layer;

[0083] Step 5: Provide a build-up dielectric layer including build-up vias on the core board circuit layer, the build-up dielectric layer fills the gaps between the patterned core board circuit layers and between the buffer groove and the core board circuit layer and covers the surfaces of the core board circuit layer and the buffer layer, and the build-up vias penetrate the build-up dielectric layer and expose part of the core board circuit layer;

[0084] Step 6: Provide a patterned build-up circuit layer on the build-up dielectric layer, the build-up circuit layer forms an effective electrical connection with the core board circuit layer through the build-up vias, and the build-up dielectric layer and the build-up circuit layer constitute a layer of substrate build-up;

[0085] Step 7: Provide a groove on the substrate build-up, the groove penetrates through a preset depth of the substrate build-up, and the groove and the buffer groove are correspondingly connected in a direction perpendicular to the core board layer, so that the bottom of the groove exposes the buffer layer;

[0086] Step 8: Remove the buffer layer, the groove and the buffer groove together constitute a communication groove, the bottom of the communication groove exposes a part of the surface of the core board layer, and the side wall of the communication groove exposes the preset substrate interconnection contacts of the core board circuit layer and / or the build-up circuit layer;

[0087] Step 9: A silicon-based intermediate layer is disposed in the communication groove. The silicon-based intermediate layer is located on a partial surface of the core board layer exposed at the bottom of the communication groove, and silicon-based intermediate layer interconnection contacts are disposed on the sidewalls of the silicon-based intermediate layer.

[0088] Step 10: An interconnection lead layer is disposed in the gap between the sidewall of the communication groove and the sidewall of the silicon-based intermediate layer. The interconnection lead layer enables the silicon-based intermediate layer interconnection contacts to form a preset effective electrical connection with the substrate interconnection contacts exposed on the sidewall of the communication groove.

[0089] The preparation method of the packaging substrate of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that the above sequence does not strictly represent the sequence of the preparation method of the packaging substrate protected by the present invention, and those skilled in the art can make changes according to the actual preparation steps.

[0090] First, as Figure 1 shown, step 1 is performed to provide a core board layer 10, and the core board layer 10 includes a first surface and a second surface disposed opposite to each other.

[0091] Then, as Figure 2 shown, step 2 is performed to form a core board through hole 12 penetrating from the first surface to the second surface in the core board layer 10.

[0092] Next, step 3 is performed to dispose a patterned core board circuit layer 20 on the surface of the core board layer 10. The core board circuit layer 20 fills the core board through hole 12, and a buffer groove 24 is included between the patterned core board circuit layers 20.

[0093] In one embodiment, the method for disposing the core board circuit layer 20 includes:

[0094] As Figure 3 shown, a first seed layer 21 is disposed on the surface of the core board layer 10, and the first seed layer 21 wraps all the surfaces of the core board layer 10 that are exposed.

[0095] As Figure 4 shown, a first conductive layer 22 is disposed on the first seed layer 21, and the first conductive layer 22 fills the core board through hole 12.

[0096] As Figure 5 shown, a patterned first photosensitive layer 23 is disposed on the first conductive layer 22, exposing a part of the first conductive layer 22.

[0097] As Figure 6 shown, the exposed first conductive layer 22 of the first photosensitive layer 23 is etched, and the first seed layer 21 exposed under the etched first conductive layer 22 is removed.

[0098] As Figure 7 shown, the first photosensitive layer 23 is removed to obtain a patterned core board circuit layer 20 composed of the patterned first conductive layer 22 and the first seed layer 21.

[0099] In one embodiment, the core board conductive layer 11 is a copper layer.

[0100] In one embodiment, before the core board through-hole 12 is provided, the core board conductive layer 11 is thinned to improve the drilling efficiency.

[0101] In one embodiment, the thickness of each layer of the core board conductive layer 11 is 10 μm - 15 μm, and the material is copper; after thinning, the thickness of each layer of the core board conductive layer 11 is 3 μm ± 0.5 μm.

[0102] In one embodiment, the core board through-hole 12 is obtained by mechanical drilling.

[0103] In one embodiment, the first seed layer 21 is provided by electroless copper plating.

[0104] In one embodiment, the first conductive layer 22 is provided by electroplating.

[0105] In one embodiment, the first photosensitive layer 23 is patterned by exposure and development.

[0106] Next, as Figure 8 shown, step 4 is performed to provide a buffer layer 25 in the buffer groove 24, and the surface of the buffer layer 25 is flush with the surface of the core board circuit layer 20.

[0107] In one embodiment, the buffer layer 25 is a release material or electroplated copper.

[0108] In the present invention, by providing the buffer layer 25 in the buffer groove 24, when the communication groove 39 is formed by laser drilling subsequently, the core board layer 10 exposed at the bottom of the communication groove 39 will not be damaged, so that it is possible to avoid damage to the core board layer 10 exposed at the bottom of the communication groove 39, and the subsequently provided silicon-based intermediate layer 35 can be smoothly provided in the communication groove 39 to obtain a packaging substrate with a flat surface, improving the circuit connection performance in the packaging substrate.

[0109] Then, as Figure 9As shown, perform Step 5 to provide a build-up dielectric layer 31 including build-up vias 311 on the core board circuit layer 20. The build-up dielectric layer 31 fills the gaps between the patterned core board circuit layers 20 and between the buffer grooves 24 and the core board circuit layer 20 and covers the surfaces of the core board circuit layer 20 and the buffer layer 25. The build-up vias 311 penetrate through the build-up dielectric layer 31 and expose a part of the core board circuit layer 20.

[0110] In one embodiment, as Figures 1 - 9 shown, before providing the core board vias 12, provide core board conductive layers 11 on the first and second surfaces of the core board layer 10 respectively. The core board vias 12 penetrate through the core board conductive layers 11 and the core board layer 10. After removing the first seed layer 21 exposed under the etched first conductive layer 22, continue to remove the exposed core board conductive layer 11 below to expose a part of the surface of the core board layer 10. The buffer grooves 24 are included in the gaps between the corresponding patterned core board conductive layers 11 and the core board circuit layer 20. The build-up dielectric layer 31 fills the gaps between the patterned core board conductive layers 11.

[0111] In one embodiment, the build-up vias 311 are provided by laser drilling.

[0112] In one embodiment, the material of the build-up dielectric layer 31 in the substrate build-up is ABF (Ajinomoto Build-up Film).

[0113] Next, perform Step 6 to provide a patterned build-up circuit layer 32 on the build-up dielectric layer 31. The build-up circuit layer 32 forms an effective electrical connection with the core board circuit layer 20 through the build-up vias 311. The build-up dielectric layer 31 and the build-up circuit layer 32 constitute one layer of substrate build-up.

[0114] In one embodiment, the method for providing the build-up circuit layer 32 includes:

[0115] As Figure 10 shown, provide a second seed layer 321 on the build-up dielectric layer 31. The second seed layer 321 covers the exposed surface of the build-up dielectric layer 31 and the part of the surface of the core board circuit layer 20 that is exposed.

[0116] As Figure 11 shown, provide a patterned second photosensitive layer 322 on the first seed layer 21.

[0117] As Figure 12 shown, fill the gaps between the patterned second photosensitive layers 322 with a second conductive layer 323.

[0118] As Figure 13As shown, by removing the second photosensitive layer 322 and the second seed layer 321 under the second photosensitive layer 322, a patterned seed layer 321 and a patterned build-up circuit layer 32 composed of the second conductive layer 323 are obtained.

[0119] In one embodiment, after the buffer layer 25 is provided, a plurality of substrate build-ups composed of the build-up circuit layer 32 and the build-up dielectric layer 31 are provided. Specifically, as Figure 14 shown, after the buffer layer 25 is provided, two substrate build-ups are provided.

[0120] In one embodiment, the second seed layer 321 is provided by electroless copper plating.

[0121] In one embodiment, the second conductive layer 323 is provided by electroplating.

[0122] In one embodiment, the second photosensitive layer 322 is patterned by exposure and development.

[0123] In one embodiment, the second seed layer 321 is removed by flash etching.

[0124] Then, as Figure 15 shown, step 7 is performed to provide a groove 33 in the substrate build-up. The groove 33 penetrates through a preset depth of the substrate build-up. The groove 33 corresponds and communicates with the buffer groove 24 in a direction perpendicular to the core board layer 10, so that the bottom of the groove 33 exposes the buffer layer 25.

[0125] Next, as Figure 16 shown, step 8 is performed to remove the buffer layer 25. The groove 33 and the buffer groove 24 together form a communication groove 39. The bottom of the communication groove 39 exposes a partial surface of the core board layer 10, and the side wall of the communication groove 39 exposes a preset substrate interconnection contact 342 of the core board circuit layer 20 and / or the build-up circuit layer 32.

[0126] Specifically, as Figures 16 - 27 shown in the build-up circuit layer 32, for the sake of simplicity and clarity of the drawing, only a part of the second conductive layer 323 is drawn out as a schematic of the build-up circuit layer 32. However, in the structure referred to in the present invention, the build-up circuit layer 32 includes the second conductive layer 323 and the second seed layer 321.

[0127] Specifically, as Figure 16Among them, only the substrate interconnection contacts 342 on the build-up wiring layer 32 are exposed on the side wall of the communication groove 39, or only the substrate interconnection contacts 342 on the core board wiring layer 20 can be exposed, or the substrate interconnection contacts 342 on the core board wiring layer 20 and / or the build-up wiring layer 32 are exposed at the same time, which can be adjusted according to specific circuit requirements.

[0128] Then, as Figure 17 shown, step 9 is carried out, and a silicon-based intermediate layer 35 is arranged in the communication groove 39. The silicon-based intermediate layer 35 is located on a partial surface of the core board layer 10 exposed at the bottom of the communication groove 39, and silicon-based intermediate layer interconnection contacts 341 are arranged on the side wall of the silicon-based intermediate layer 35.

[0129] Finally, as Figure 18 shown, step 10 is carried out, and an interconnection lead layer 34 is arranged in the gap between the side wall of the communication groove 39 and the side wall of the silicon-based intermediate layer 35. The interconnection lead layer 34 enables the silicon-based intermediate layer interconnection contacts 341 to form an effective electrical connection with the substrate interconnection contacts 342 exposed on the side wall of the communication groove 39.

[0130] In one embodiment, the interconnection lead layer 34 is fabricated by 3D printing.

[0131] By setting the interconnection lead layer 34 by 3D printing, the present invention can further improve the line accuracy achievable by the interconnection lead layer 34. Combining with the high-precision position alignment achieved on the side wall, it further improves the line alignment accuracy achievable by the silicon-based intermediate layer 35, which is beneficial to the application of the silicon-based intermediate layer 35 in higher-density packaging substrates.

[0132] In one embodiment, as Figure 19 shown is a top view of the silicon-based intermediate layer 35 and the interconnection lead layer 34 arranged in the communication groove 39. The interconnection lead layer 34 penetrates the gap between the side wall of the silicon-based intermediate layer 35 and the side wall of the communication groove 39 in a direction perpendicular to the silicon-based intermediate layer 35. The interconnection lead layer 34 is arranged at intervals in a patterned manner in a direction parallel to the silicon-based intermediate layer 35. The interconnection lead layer 34 is a plurality of columnar connection lines perpendicular to the silicon-based intermediate layer 35. The specific distribution of the interconnection lead layer 34 is set according to the distribution of the silicon-based intermediate layer interconnection contacts 341 that need to be electrically connected to the substrate interconnection contacts 342; this setting only shows the side cross-section of the filled interconnection lead layer 34 in the side view of Figure 18 but as Figure 19As shown, the interconnecting lead layer 34 may not completely fill the gap between the sidewall of the silicon-based intermediate layer 35 and the sidewall of the communication groove 39; an effective electrical connection is formed between the inner side of the interconnecting lead layer 34 and the silicon-based intermediate layer interconnecting contact 341, and an effective electrical connection is formed between the outer side of the interconnecting lead layer 34 and the substrate interconnecting contact 342 exposed on the sidewall of the communication groove 39, so as to realize an effective electrical connection between the silicon-based intermediate layer 35 and the circuit layer in the packaging substrate.

[0133] In the present invention, the electrical connection between the silicon-based intermediate layer 35 and the substrate is realized through the interconnecting lead layer 34 which is filled in a patterned manner according to a preset pattern between the sidewall of the communication groove 39 and the sidewall of the silicon-based intermediate layer 35, thereby avoiding a large alignment deviation that is likely to occur in the horizontal direction. As long as the silicon-based intermediate layer 35 is placed in the communication groove 39, an accurate electrical connection with the substrate can be realized through the filled interconnecting lead layer 34, improving the reliability of the electrical connection that can be achieved between the silicon-based intermediate layer 35 and the substrate, being beneficial to the preparation yield of the silicon-based intermediate layer 35 in the substrate, and being beneficial to the large-scale use of the silicon-based intermediate layer 35.

[0134] In one embodiment, a void-filling insulating adhesive 36 for the interconnecting lead layer 34 is not provided in the gap between the sidewall of the communication groove 39 and the sidewall of the silicon-based intermediate layer 35. As Figure 20 shown, the insulating adhesive 36 also covers the surface of the silicon-based intermediate layer 35, so that insulating isolation is formed for the parts of the interconnecting lead layer 34 and the silicon-based intermediate layer 35 that are not electrically interconnected.

[0135] Specifically, since Figure 20 only shows a cross-sectional view of the cross-section where the interconnecting lead layer 34 is filled, the insulating adhesive 36 filled in the gap of the interconnecting lead layer 34 is not shown, and only the insulating adhesive 36 covering the surface of the silicon-based intermediate layer is shown. However, in fact, the insulating adhesive 36 can be filled between the interconnecting lead layers.

[0136] In the present invention, by not providing the void-filling insulating adhesive 36 for the interconnecting lead layer 34 in the gap between the sidewall of the communication groove 39 and the sidewall of the silicon-based intermediate layer 35 and covering the insulating adhesive 36 on the surface of the silicon-based intermediate layer 35, the parts of the silicon-based intermediate layer 35 and the interconnecting lead layer 34 that do not need to be electrically connected can be insulated from the outside to ensure the reliability of the electrical connection.

[0137] In one embodiment, after the silicon-based intermediate layer 35 is provided, a preset number of substrate build-up layers are further provided on the silicon-based intermediate layer 35, and the further provided substrate build-up layers also cover the surface of the substrate build-up layer located on the same horizontal plane as the silicon-based intermediate layer 35. Specifically, as Figures 21 - 25 shown, one substrate build-up layer is further provided on the silicon-based intermediate layer 35: asFigure 21 As shown, a patterned build-up dielectric layer 31 is provided on the silicon-based intermediate layer 35, and a part of the second conductive layer 323 of the underlying substrate build-up is exposed between the patterned build-up dielectric layers 31; as Figure 22 shown, a second seed layer 321 is covered on the patterned build-up dielectric layer 31, and the second seed layer 321 covers the surface of the second conductive layer 323 exposed between the patterned build-up dielectric layers 31 and the exposed surface of the build-up dielectric layer 31; as Figure 23 shown, a patterned second photosensitive layer 322 is provided on the second seed layer 321; as Figure 24 shown, a second conductive layer 323 is provided between the patterned second photosensitive layers 322, and the second conductive layer 323 fills the gaps between the patterned second photosensitive layers 322; as Figure 25 shown, the second photosensitive layer 322 is removed, and the second seed layer 321 covered under the second photosensitive layer is removed, obtaining a layer of substrate build-up composed of the patterned second seed layer 321 and the patterned second conductive layer 323.

[0138] In one embodiment, when covering the insulating adhesive 36, a preset number of layers of substrate build-up are further provided on the insulating adhesive 36, and the substrate build-up also covers the substrate build-up on the same horizontal plane as the insulating adhesive 36.

[0139] In one embodiment, as Figure 26 shown, a solder mask layer 37 is filled in the gaps between the build-up circuit layers 32 exposed on the surface of the packaging substrate.

[0140] In one embodiment, the solder mask layer 37 is formed by exposing and developing after applying a dry film type solder mask ink.

[0141] In one embodiment, as Figure 26 shown, a surface treatment layer 38 is provided on the build-up circuit layers 32 exposed on the surface of the packaging substrate.

[0142] The present invention protects the parts that do not need to be electrically connected to the outside by providing the solder mask layer 37, and at the same time protects the exposed build-up circuit layers 32 from oxidation by providing the surface treatment layer 38, improving the reliability of the electrical connection of the packaging substrate.

[0143] Embodiment 2:

[0144] The present embodiment provides a method for manufacturing a packaging substrate. The method for manufacturing the packaging substrate in the present embodiment is basically the same as the method for manufacturing the packaging substrate in Embodiment 1, and the difference lies in:

[0145] The insulating glue 36 for filling the void of the interconnecting lead layer 34 and the insulating glue 36 covering the surface of the silicon-based intermediate layer 35 are not provided in the void between the side wall of the connecting groove 39 and the side wall of the silicon-based intermediate layer 35, and the material thereof is a magnetic material.

[0146] By setting the material of the insulating glue 36 as a magnetic material, the present invention has good insulating performance, and at the same time can shield external signal crosstalk, which is beneficial to maintaining the integrity of the signals of the silicon-based intermediate layer 35.

[0147] Embodiment Three:

[0148] As Figure 27 shown, this embodiment provides a packaging substrate obtained by using any one of the preparation methods in Embodiment One above. The packaging substrate includes: a core board layer 10, a core board conductive layer 11, a core board circuit layer 20, a multi-layer substrate build-up layer, a silicon-based intermediate layer 35, an interconnecting lead layer 34, a solder mask layer 37, and a surface treatment layer 38;

[0149] The core board layer 10 includes a first surface and a second surface which are oppositely arranged. There is a layer of patterned core board conductive layer 11 on each of the first surface and the second surface of the core board layer 10; the patterned core board circuit layer 20 is located on the core board conductive layer 11, and the pattern on the core board circuit layer 20 coincides with the pattern on the core board conductive layer 11 in the projection on the core board layer 10. The void between the patterned core board circuit layer 20 and the core board conductive layer 11 includes a buffer groove 24;

[0150] The substrate build-up layer includes a patterned build-up circuit layer 32 and a build-up dielectric layer 31. The patterned build-up dielectric layer 31 is filled in the void of the underlying core board circuit layer 20 or the build-up circuit layer 32 and exposes a part of the underlying core board circuit layer 20 or the build-up circuit layer 32. The build-up circuit layer 32 is effectively electrically connected to the underlying exposed core board circuit layer 20 or the build-up circuit layer 32 through the patterned build-up dielectric layer 31;

[0151] A groove 33 is provided in the substrate build-up layer. The groove 33 communicates with the buffer groove 24 correspondingly in a direction perpendicular to the core board layer 10. The groove 33 and the buffer groove 24 form a communication groove 39. The side wall of the communication groove 39 exposes some of the preset substrate interconnection contacts 342 of the build-up circuit layer 32 and / or the core board circuit layer 20. The silicon-based intermediate layer 35 is located on a part of the surface of the core board layer 10 exposed at the inner bottom of the communication groove 39. The side wall of the silicon-based intermediate layer 35 is provided with silicon-based intermediate layer interconnection contacts 341. An interconnection lead layer 34 is provided between the side wall of the communication groove 39 and the side wall of the silicon-based intermediate layer 35. The interconnection lead layer 34 enables effective electrical connection between the substrate interconnection contacts 342 and the silicon-based intermediate layer interconnection contacts 341.

[0152] The solder mask layer 37 fills the gaps between the circuit layers of the substrate build-up layer exposed on the surface of the packaged substrate. The surface treatment layer 38 is located on the surface of the circuit layers of the substrate build-up layer exposed on the surface of the packaged substrate.

[0153] In one embodiment, the top of the communication groove 39 is wrapped by the substrate build-up layer.

[0154] In summary, for the packaged substrate and its manufacturing method of the present invention, the electrical connection points of the silicon-based intermediate layer can be connected by setting them on the side wall of the communication groove, avoiding poor electrical connection contact caused by misalignment in the horizontal direction, improving the accuracy of line interconnection, and shortening the distance of the interconnection line. At the same time, by setting a buffer layer before setting the silicon-based intermediate layer, laser drilling is prevented from damaging the core board layer exposed at the bottom of the communication groove, ensuring the structural flatness of the packaged substrate. In addition, the interconnection lead layer in the communication groove is prepared by 3D printing, improving the preparation accuracy of the interconnection lead layer circuit and further improving the alignment accuracy. Finally, by setting the insulating glue as a magnetic material to shield crosstalk, the signal integrity of the silicon-based intermediate layer is improved.

[0155] Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial utilization value.

[0156] The above embodiments are only illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A method for preparing a packaging substrate, characterized in that, The preparation method includes: providing a core board layer, the core board layer including a first surface and a second surface disposed opposite to each other; forming a core board through-hole penetrating from the first surface to the second surface in the core board layer; forming a patterned core board circuit layer on the surface of the core board layer, the core board circuit layer filling the core board through-hole, and a buffer groove being included between the patterned core board circuit layers; disposing a buffer layer in the buffer groove, the surface of the buffer layer being flush with the surface of the core board circuit layer; disposing an interlayer dielectric layer including an interlayer via on the core board circuit layer, the interlayer dielectric layer filling the gaps between the patterned core board circuit layers and between the buffer groove and the core board circuit layer and covering the surfaces of the core board circuit layer and the buffer layer, the interlayer via penetrating the interlayer dielectric layer and exposing a part of the core board circuit layer; forming a patterned interlayer circuit layer on the interlayer dielectric layer, the interlayer circuit layer forming an effective electrical connection with the core board circuit layer through the interlayer via, and the interlayer dielectric layer and the interlayer circuit layer constituting a layer of substrate interlayer; forming a groove in the substrate interlayer, the groove penetrating through a preset depth of the substrate interlayer, the groove corresponding and communicating with the buffer groove in a direction perpendicular to the core board layer, so that the bottom of the groove exposes the buffer layer; removing the buffer layer, the groove and the buffer groove jointly constituting a communication groove, the bottom of the communication groove exposing a part of the surface of the core board layer, and the side wall of the communication groove exposing preset substrate interconnection contacts of the core board circuit layer and / or the interlayer circuit layer; disposing a silicon-based intermediate layer in the communication groove, the silicon-based intermediate layer being located on a part of the surface of the core board layer exposed at the bottom of the communication groove, and silicon-based intermediate layer interconnection contacts being disposed on the side wall of the silicon-based intermediate layer; disposing an interconnection lead layer in the gap between the side wall of the communication groove and the side wall of the silicon-based intermediate layer, the interconnection lead layer forming a preset effective electrical connection between the silicon-based intermediate layer interconnection contacts and the substrate interconnection contacts exposed on the side wall of the communication groove.

2. The method for preparing an encapsulated substrate according to claim 1, wherein The buffer layer is a release material or electroplated copper, and / or the interconnection lead layer is made by a 3D printing method.

3. The manufacturing method of the encapsulation substrate according to claim 1, wherein, filling the gap where the interconnection lead layer is not disposed between the side wall of the communication groove and the side wall of the silicon-based intermediate layer with an insulating adhesive, the insulating adhesive also covering the surface of the silicon-based intermediate layer, so that the parts of the interconnection lead layer and the silicon-based intermediate layer that are not electrically interconnected are insulated.

4. The manufacturing method of the packaging substrate according to claim 3, characterized in that, The insulating adhesive is a magnetic material.

5. The method for preparing a packaged substrate according to claim 1, wherein The method for forming the core board circuit layer includes: forming a first seed layer on the surface of the core board layer, the first seed layer covering all the exposed surfaces of the core board layer; forming a first conductive layer on the first seed layer, the first conductive layer filling the core board through-hole; forming a patterned first photosensitive layer on the first conductive layer, exposing a part of the first conductive layer; etching the first conductive layer exposed by the first photosensitive layer, and removing the first seed layer exposed under the etched first conductive layer; Remove the first photosensitive layer to obtain a patterned core board circuit layer composed of the patterned first conductive layer and the first seed layer.

6. The manufacturing method of the encapsulation substrate according to claim 5, characterized in that, Before setting the core board vias, core board conductive layers are respectively provided on the first surface and the second surface of the core board layer, and the core board vias penetrate through the core board conductive layers and the core board layer; after removing the first seed layer exposed under the etched first conductive layer, continue to remove the exposed core board conductive layer downward to expose a partial surface of the core board layer, and a buffer groove is included in the gap between the corresponding patterned core board conductive layer and the core board circuit layer; the build-up dielectric layer fills the gap between the patterned core board conductive layers.

7. The manufacturing method of the encapsulation substrate according to any one of claims 1-6, characterized in that, After setting the buffer layer, a plurality of substrate build-ups composed of build-up circuit layers and build-up dielectric layers are provided.

8. The method for preparing a packaged substrate according to any one of claims 7, characterized in that, After setting the silicon-based intermediate layer, a preset number of substrate build-ups are further provided on the silicon-based intermediate layer, and the further provided substrate build-ups also cover the surface of the substrate build-up located on the same horizontal plane as the silicon-based intermediate layer.

9. The manufacturing method of the encapsulation substrate according to any one of claims 1-6, characterized in that, Fill a solder mask in the gap between the build-up circuit layers exposed on the surface of the packaging substrate, and / or provide a surface treatment layer on the build-up circuit layers exposed on the surface of the packaging substrate.

10. An encapsulation substrate, characterized in that, The packaging substrate is obtained by using the preparation method described in any one of claims 1-9, and the packaging substrate includes: a core board layer, core board conductive layers, a core board circuit layer, a plurality of substrate build-ups, a silicon-based intermediate layer, an interconnecting lead layer, a solder mask, and a surface treatment layer; The core board layer includes a first surface and a second surface disposed opposite to each other, and there is a layer of patterned core board conductive layer on each of the first surface and the second surface of the core board layer; the patterned core board circuit layer is located on the core board conductive layer, and the pattern on the core board circuit layer coincides with the projection of the pattern on the core board conductive layer on the core board layer, and the gap between the patterned core board circuit layer and the core board conductive layer includes a buffer groove; The substrate build-up includes a patterned build-up circuit layer and a build-up dielectric layer, the patterned build-up dielectric layer fills the gap inside the underlying core board circuit layer or build-up circuit layer and exposes a part of the underlying core board circuit layer or build-up circuit layer, and the build-up circuit layer is effectively electrically connected to the underlying exposed core board circuit layer or build-up circuit layer through the patterned build-up dielectric layer; A groove is provided inside the substrate build-up, and the groove corresponds to and communicates with the buffer groove in a direction perpendicular to the core board layer, and the groove and the buffer groove form a communication groove; the side wall of the communication groove exposes partial preset substrate interconnecting contacts of the build-up circuit layer and / or the core board circuit layer, the silicon-based intermediate layer is located on a partial surface of the core board layer exposed at the inner bottom of the communication groove, silicon-based intermediate layer interconnecting contacts are provided on the side wall of the silicon-based intermediate layer, and an interconnecting lead layer is provided between the side wall of the communication groove and the side wall of the silicon-based intermediate layer, and the interconnecting lead layer effectively electrically connects the substrate interconnecting contacts and the silicon-based intermediate layer interconnecting contacts; The solder mask layer fills the gaps between the circuit layers of the substrate build-up layer exposed on the surface of the packaging substrate, and the surface treatment layer is located on the surface of the circuit layers of the substrate build-up layer exposed on the surface of the packaging substrate.

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