Ceramic patch type packaging shell for high-side and low-side gate drivers

Abstract

The invention discloses a high-side and low-side gate driver ceramic patch type packaging shell structure, and belongs to the field of microelectronic device packaging. The high-low-edge gate driver comprises a multi-layer ceramic substrate structure, a groove is formed in the center of a ceramic substrate (13), a molybdenum-copper alloy electrode plate (11) is arranged in the groove, a high-low-edge gate driver chip is connected to the electrode plate (11) in the groove in a lead-tin-silver soldering lug sintering mode, and the chip is connected with an external pin through a metallization layer; the ten pins are located at the bottom of the package and comprise two power supply pins VCC, a power supply ground pin COM, a logic ground pin VSS, a high-side logic signal input pin HIN, a low-side logic signal input pin LIN, a low-side driving input pin LO, a high-end suspension ground end pin VS, a high-end suspension power supply pin VB and a high-side driving output pin HO. The device is good in heat dissipation, high in reliability and suitable for wide application and popularization.

Description

Technical Field

[0001] The present invention relates to the packaging of microelectronic devices, and specifically to a ceramic surface-mount package housing for high and low side gate drivers. Background Art

[0002] The original package of the existing high and low side gate drivers uses a plastic packaging process. The chip is directly sintered on the copper sheet with a solder chip. Copper has a relatively high coefficient of thermal expansion, which does not match the semiconductor material. It is easy to generate stress during thermal cycling, resulting in reliability problems and certain hidden dangers in high-reliability scenarios. Plastic has low mechanical strength and is easily damaged by external forces, affecting the packaging reliability. Plastic has poor high-temperature resistance and is easily softened and decomposed at high temperatures, restricting the operating temperature range. The original package design has 14 pins, including five empty pins, with redundant pins, which is not conducive to the installation and design of subsequent circuits. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a ceramic surface-mount package housing structure for high and low side gate drivers to improve the packaging reliability in view of the problems existing in the prior art.

[0004] The technical solution of the present inventor: A ceramic surface-mount package housing structure for high and low side gate drivers, including a multi-layer ceramic substrate structure. A groove is provided at the central position of the ceramic substrate. The high and low side gate driver chips are placed in the central groove and connected to the external pins through a metallization layer; there are 10 pins at the bottom of the package, with a pin pitch of 1.27 mm, including two power pins VCC, a power ground pin COM, a logic ground pin VSS, a high side logic signal input pin HIN, a low side logic signal input pin LIN, a low side drive input pin LO, a high side floating ground pin VS, a high side floating power pin VB, and a high side drive output pin HO.

[0005] Preferably, the ceramic substrate is made of a material of more than 95% Al2O3 ceramic (aluminum oxide) / AlN ceramic (aluminum nitride).

[0006] Preferably, the ceramic substrate is prepared by a tape casting process and formed into a multi-layer structure through high-temperature sintering.

[0007] Preferably, the metallization layer is made of pure material, with a thickness of 1.3 um - 5.7 um, and is prepared by a printing process. The connection between the chip and the electrode piece uses a lead-tin-silver solder chip with a diameter of 1 mm, and is sintered using a vacuum sintering furnace. The highest sintering temperature is 355°C.

[0008] Preferably, the metallization layer uses a screen printing process to print pure gold paste on the surface of the ceramic substrate, and a conductive layer is formed through drying and sintering.

[0009] Preferably, chip soldering adopts the solder tab soldering process. The high-side and low-side gate driver chips are placed in the soldering area of the substrate and fixed by the melting and solidification of the solder tabs.

[0010] Preferably, package sealing adopts the parallel seam welding process to achieve high airtightness packaging through resistance heating and local melting.

[0011] Preferably, the high-side and low-side gate driver chips are connected to the chip signal terminals and external pins through metallization wiring and gold wire bonding processes. Thermal vias are provided inside the package to conduct the heat generated by the chip to the heat sink at the bottom of the package. The power pin VCC and the power ground pin COM are connected through a wide metallization layer to reduce resistance and thermal resistance.

[0012] Advantages of the present invention: ① Structural design: Multilayer ceramic substrates (such as LTCC or HTCC) are used to achieve complex electrical wiring and high-density integration. The heat dissipation efficiency is improved by optimizing the layout and heat dissipation path (such as thermal vias, heat sinks). The size and shape are designed according to application requirements to ensure compatibility and installation convenience.

[0013] ② Electrical performance optimization: The wiring is optimized to reduce parasitic inductance and capacitance and improve high-frequency performance. Electromagnetic interference (EMI) is reduced through reasonable grounding and shielding designs. The high insulation of the ceramic material is ensured to avoid air breaks.

[0014] ③ Thermal management design and coefficient of thermal expansion matching: In the present invention, a molybdenum-copper alloy (containing 70% molybdenum and 30% copper) electrode sheet is designed under the chip to improve the heat dissipation capacity of the device. The coefficient of thermal expansion (CTE) of Mo70Cu30 is closer to that of semiconductor materials (such as silicon, silicon carbide, gallium nitride, etc.), which can reduce thermal stress, avoid interface cracking or failure caused by temperature changes, and reduce reliability problems caused by stress generated during thermal cycling.

[0015] The chip soldering area adopts a sunken design (also known as a groove design or an embedded design), which has multiple advantages in ceramic chip packaging, especially in terms of thermal management, mechanical stability, and electrical performance. The sunken design brings the chip closer to the ceramic substrate, shortening the heat conduction path and improving the heat dissipation efficiency. The contact area between the chip and the substrate increases, reducing the thermal resistance and helping to quickly transfer heat from the chip to the outside. The sunken design can distribute heat more evenly on the substrate, avoiding local overheating. The sunken design can better match the coefficient of thermal expansion (CTE) of the chip and the substrate, reducing thermal stress caused by temperature changes. The chip is embedded in the substrate, reducing the risk of detachment or damage caused by mechanical vibration or shock. The sunken design makes the overall structure of the package more compact, enhancing the mechanical strength. The sunken design can reduce the lead length between the chip and the external connection, reducing parasitic inductance and capacitance and improving high-frequency performance. The shorter electrical path helps to reduce signal delay and noise, enhancing the electrical performance. It can make the solder joints more stable, reducing connection failures caused by vibration or thermal cycling. It effectively utilizes space, reducing the overall size of the package and meeting the requirements of high-density integration and miniaturization. The chip is embedded in the substrate, reducing the overall height of the package and being suitable for applications with strict thickness requirements (such as mobile devices). It reduces the interfacial stress between the chip and the substrate, reducing the risk of cracking or delamination. It makes the package more stable and can better adapt to harsh environments such as high temperature and high humidity. In addition, the chip groove design, combined with the added electrode plates, forms channels at the edges of the grooves. After sintering the solder pads or solder, it can effectively prevent problems such as solder climbing onto the chip surface to form short circuits.

[0016] The ceramic chip pins are designed with a pitch of 1.27 mm (i.e., 50 mil), which is a common standard pitch in electronic packaging and is widely used in various packaging types (such as SOP, DIP, PLCC, etc.). It is convenient for design and use. Many soldering devices (such as reflow soldering, wave soldering) and testing devices support a 1.27 mm pitch, reducing the complexity of manufacturing and testing. The 1.27 mm pitch provides sufficient space, reducing the risk of bridging (short circuit) between pins during the soldering process. The larger pitch makes the soldering process easier to control, improving the production yield. It can disperse mechanical stress and reduce the risk of pin breakage or de-soldering caused by vibration or shock. The 1.27 mm pitch makes the package more stable when mounted on the PCB, suitable for high-reliability applications. This pin pitch design provides sufficient space for PCB wiring, facilitating the design of multi-layer boards and complex circuits. The larger pitch helps with heat dissipation design, allowing heat dissipation vias or heat dissipation paths to be arranged between the pins. The reasonable pitch makes it easier for test probes to contact the pins, improving the test efficiency and accuracy. The larger pitch is convenient for manual soldering and repair, reducing the repair difficulty and cost. It can also reduce electromagnetic interference (EMI) and signal crosstalk between pins, improving electrical performance and helping to reduce parasitic inductance and capacitance, suitable for high-frequency applications. The 1.27 mm pitch is suitable for high-reliability fields such as aerospace and automotive electronics, capable of meeting stringent environmental requirements. In industrial control and consumer electronics products, the 1.27 mm pitch provides a good balance between performance and cost. Brief Description of the Drawings

[0017] Figure 1 is a schematic diagram of the pins of the prior art package; Figure 2 is a cross-sectional view of the present invention; Figure 3 is a schematic diagram of the inner cavity of the present invention; Figure 4 is a schematic diagram of the bottom of the present invention.

[0018] In the figures: 1 - first pad; 2 - second pad; 3 - third pad; 4 - fourth pad; 5 - fifth pad; 6 - sixth pad; 7 - seventh pad; 8 - eighth pad; 9 - ninth pad; 10 - tenth pad; 11 - electrode piece; 12 - sealing frame; 13 - ceramic substrate; 14 - lead. Detailed Description of the Invention

[0019] This embodiment provides a ceramic surface mount package for a high and low side gate driver, with a package size of 6mm×6.5mm×2.8mm, adopting a multi-layer ceramic substrate structure. The high and low side gate driver chip is placed in a central groove and connected to external pins through a metallization layer. There are 10 pins at the bottom of the package, with a pin pitch of 1.27mm, including two power pins VCC, a power ground pin COM, a logic ground pin VSS, a high side logic signal input pin HIN, a low side logic signal input pin LIN, a low side drive input pin LO, a high side floating ground pin VS, a high side floating power pin VB, and a high side drive output pin HO.

[0020] In this embodiment, the ceramic substrate uses a material of more than 95% Al2O3 ceramic (aluminum oxide) / AlN ceramic (aluminum nitride), with a bottom thickness of 1.2mm and a kovar thickness of 0.5mm, having excellent thermal conductivity and insulation. The metallization layer uses pure materials, with a thickness of 1.3um - 5.7um, and is prepared by a printing process. The connection between the chip and the electrode piece uses a lead-tin-silver solder piece with a diameter of 1mm, and is welded using a vacuum sintering furnace, with the highest welding temperature being 355°C.

[0021] The ceramic substrate is prepared by a tape casting process and forms a multi-layer structure after high-temperature sintering. The metallization layer uses a screen printing process to print pure gold paste on the surface of the ceramic substrate, and forms a conductive layer after drying and sintering. Chip soldering uses a solder piece soldering process, placing the high and low side gate driver chip in the welding area of the substrate and fixing it by melting and solidifying the solder piece. Package sealing uses a parallel seam welding process to achieve high airtightness packaging through resistance heating and local melting.

[0022] The high and low side gate driver chip realizes the connection between the chip signal end and external pins through metallization wiring and gold wire bonding process. There are thermal vias inside the package to conduct the heat generated by the chip to the heat sink at the bottom of the package. The power pin VCC and the power ground pin COM are connected through a wide metallization layer to reduce resistance and thermal resistance.

[0023] The high and low side gate driver ceramic surface mount package in this embodiment is applicable to application scenarios such as motor drive and power modules. The operating temperature range of the package is from -50°C to 150°C, the peak sink current capacity is 3.5A, and the peak source current capacity is 2.5A. In actual applications, the package exhibits excellent heat dissipation and electrical reliability.

[0024] The key raw materials for each part of the package shell are as follows: Electrode piece: Mo70Cu30 Sealing frame: 4J29 Ceramic part: alumina black porcelain Lead wire: 4J42 The corresponding relationship between the interior of the component of the present invention and the pins is as follows: The first pad 1 -- HIN (high-side logic signal input) The second pad 2 -- LIN (low-side logic signal input) The third pad 3 -- VSS (logic ground) The fourth pad 4 -- COM (power ground) The fifth pad 5 -- VCC (positive power supply) The sixth pad 6 -- VCC (positive power supply) The seventh pad 7 -- LO (low-side drive output) The eighth pad 8 -- VS (high-side floating ground terminal) The ninth pad 9 -- VB (high-side floating power supply) The tenth pad 10 -- HO (high-side drive output) The package size is 6mm × 6.5mm × 2.8mm, and the thickness of the ceramic substrate is 1.4mm, which is convenient for the processing and manufacturing of component manufacturers. The reasonable thickness of the ceramic substrate can improve the heat dissipation performance and enhance the mechanical strength.

[0025] Considering the convenience of subsequent circuit connection, the bonding lead-out point of the HO terminal of the chip is designed as an island structure, that is, the tenth pad 10 in the figure, and is led out through the internal wiring of the ceramic component and connected to the HO pin. There are nine effective signal terminals of the chip, and there is one VCC pin for the power supply on each of the left and right pins of the ceramic component, which can not only make full use of the pins but also facilitate the subsequent circuit connection.

[0026] The embedded design of the chip reduces the subsequent chip soldering and positioning problems, and the reasonable distribution of the metallization layer avoids risks such as bonding wire crossing and overpass. The minimum distance between the metallization layers is 0.3mm, providing sufficient insulation distance to avoid electrical short circuits in high-voltage applications.

Claims

1. A ceramic surface mount package housing structure for a high and low side gate driver, characterized in that: It includes a multi-layer ceramic substrate structure. A groove is provided at the central position of the ceramic substrate (13), and a molybdenum-copper alloy electrode sheet (11) is provided in the groove. The high and low side gate driver chips are connected to the electrode sheet (11) in the groove by means of sintering with a lead-tin-silver solder sheet, and the chips are connected to the external pins through a metallization layer; there are 10 pins in total, located at the bottom of the package, including two power supply pins VCC, a power supply ground pin COM, a logic ground pin VSS, a high side logic signal input pin (HIN), a low side logic signal input pin LIN, a low side drive input pin LO, a high side floating ground pin VS, a high side floating power supply pin VB, and a high side drive output pin HO.

2. The ceramic chip package housing structure of the high and low side gate drivers according to claim 1, wherein: The ceramic substrate adopts a ceramic material of more than 95% Al2O3 or AlN ceramic; the ceramic substrate is prepared by a tape casting process and forms a multi-layer structure after high-temperature sintering.

3. The high and low side gate driver ceramic chip-type package housing structure according to claim 1, characterized in that: The bonding lead-out point of the HO end of the chip is designed as an island structure, namely the tenth pad (10), and is led out through the internal wiring of the ceramic part and connected to the high side drive output pin.

4. The ceramic chip package housing structure of the high- and low-side gate driver according to claim 1, characterized in that: The metallization layer adopts a pure material with a thickness of 1.3um - 5.7um, and is prepared by a screen printing process. The pure gold paste is printed on the surface of the ceramic substrate and forms a conductive layer after drying and sintering.

5. The high and low side gate driver ceramic chip-type package housing structure according to claim 1, characterized in that: The connection between the chip and the electrode sheet uses a lead-tin-silver solder sheet with a diameter of 1mm, and is sintered using a vacuum sintering furnace, and the highest sintering temperature is 355°C.

6. The high and low side gate driver ceramic chip-type package housing structure according to claim 1, characterized in that: Chip soldering adopts a solder sheet soldering process. The high and low side gate driver chips are placed in the welding area of the substrate and fixed by the melting and solidification of the solder sheet.

7. The high and low side gate driver ceramic chip-type package housing structure according to claim 1, characterized in that: Package sealing adopts a parallel seam welding process to achieve high airtightness packaging through resistance heating and local melting.

8. The ceramic chip package housing structure of the high- and low-side gate driver according to claim 1, characterized in that: The high and low side gate driver chips are connected to the chip signal terminals and the external pins through metallization wiring and gold wire bonding processes.

9. The ceramic chip package housing structure of the high and low side gate drivers according to claim 1, characterized in that: There is a thermal via inside the package to conduct the heat generated by the chip to the heat sink at the bottom of the package.

10. The ceramic chip package housing structure of the high and low side gate drivers according to claim 1, wherein: The power supply pin VCC and the power supply ground pin COM are connected through a wide metallization layer to reduce resistance and thermal resistance.

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