Semiconductor package with sidewall connections

Abstract

The embodiment of the invention relates to a semiconductor package with sidewall connections. A fan-out wafer level package is provided that includes a semiconductor die having a redistribution layer on a sidewall thereof. A redistribution layer over the die includes an extension portion extending along the sidewalls. The semiconductor die is encapsulated in a molding compound layer. The molding compound layer is between the extended portion of the redistribution layer and the sidewall of the semiconductor die. Solder contacts for electrically connecting the semiconductor device to the electronic circuit board are on the redistribution layer. The solder contacts and sidewalls of the redistribution layer may provide electrical contacts in two different locations. Thus, the package may be used to improve interconnectivity by providing vertical and horizontal connections.

Description

[0001] This application is a divisional application of the invention patent application with the application number 201911371464.2 and the title "Semiconductor Package with Sidewall Connection", which was filed on December 26, 2019. Technical Field

[0002] The present disclosure relates to a wafer-level package having an extended redistribution layer formed on a sidewall of a semiconductor die for providing additional input / output terminals in the package. Background Art

[0003] Typical semiconductor packages include input / output connections for connecting the semiconductor package to various other external circuits on the top surface. These various external circuits can include other semiconductor packages or printed circuit boards or any kind of external circuit.

[0004] In a conventional wafer-level chip scale package (WLCSP), which is a technology for packaging integrated circuits (ICs) at the wafer level, the WLCSP typically provides I / O connections only on the top side of the package through solder balls mounted on the semiconductor die. Such a WLCSP package limits the number of I / O connections in the package and, since the I / O connections are provided only on the top side of the package, limits the ways in which the packages can be stacked.

[0005] Due to this limited application in the conventional WLCSP structure, the size of the package cannot meet the industry's growing demand for providing packages with minimized size. Summary of the Invention

[0006] The present disclosure relates to a semiconductor package that utilizes the sidewall region of a WLCSP package to provide additional I / O connections and reduce the package size. Accordingly, a semiconductor package and a method of manufacturing such a semiconductor package are provided, the semiconductor package having additional I / O connections and minimizing the overall size of the semiconductor package. That is, by increasing the number of I / O connections in the package, the semiconductor package can be horizontally and vertically stacked with other semiconductor packages or circuits using the proposed sidewall I / O connections.

[0007] Another aspect of the present disclosure is to provide a semiconductor package capable of providing improved interconnectivity between semiconductor packages.

[0008] Yet another aspect of the present disclosure is to provide a semiconductor package capable of being vertically and horizontally stacked to increase connectivity in all directions.

[0009] A further aspect of the present disclosure is to provide a semiconductor package that can be stacked in a 3D structure that occupies the least amount of space and thus reduces the overall size of the semiconductor device.

[0010] Another aspect of the present disclosure is to provide a method of manufacturing a semiconductor package with additional I / O connections by using a conventional wafer-level chip-scale packaging bump formation process without adding additional manufacturing stages. This helps to maintain the cost of the entire manufacturing process. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] To better understand the embodiments, reference is now made to the drawings by way of example only. In the drawings, like reference numerals identify similar elements or acts. The dimensions and relative positions of the elements in the drawings need not be drawn to scale. For example, the shapes and angles of the various elements need not be drawn to scale, and some of these elements may be enlarged and positioned to improve the readability of the drawings. Further, the particular shapes of the elements depicted are not necessarily intended to convey any information regarding the actual shape of the particular elements and may have been selected merely for ease of identification in the drawings.

[0012] Figure 1 is a cross-sectional view of an exemplary embodiment of a semiconductor structure according to the present disclosure, the semiconductor structure having an extended redistribution layer on a sidewall of a semiconductor die;

[0013] Figure 2 is according to an exemplary embodiment of the present disclosure Figure 1 top view of a semiconductor structure;

[0014] Figure 3A and Figure 3B illustrates an example of providing a mold protection layer according to an embodiment of the present disclosure;

[0015] Figure 4 illustrates a cross-sectional view of two semiconductor structures having connections using solder balls according to an embodiment of the present disclosure;

[0016] Figure 5 illustrates a cross-sectional view of two semiconductor structures having connections using wire bonding according to another embodiment of the present disclosure;

[0017] Figures 6A to 6I is a cross-sectional view showing an exemplary method of fabricating an extended redistribution layer according to an exemplary embodiment of the present disclosure;

[0018] Figure 7 illustrates a cross-sectional view of scribing adjacent semiconductor structures according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In the following description, specific details are set forth in order to provide a thorough understanding of the various disclosed embodiments. However, those skilled in the relevant art will recognize that the embodiments may be practiced without one or more of these specific details or with other methods, components, materials, etc. In other instances, well-known structures associated with chip packaging or wafer-level chip scale packaging (WLCSP) have not been shown or described in detail so as not to unnecessarily obscure the description of the embodiments.

[0020] Unless the context otherwise requires, throughout the following specification and claims, the word "comprise" and variations thereof (such as "comprises" and "comprising") shall be interpreted in an open, inclusive sense, i.e., as "including but not limited to". Further, unless the context clearly indicates otherwise, the terms "first", "second" and similar sequential indicators shall be interpreted as interchangeable.

[0021] Throughout the specification, references to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the phrases "in one embodiment" or "in an embodiment" that appear throughout the specification are not necessarily all referring to the same embodiment. Furthermore, the particular features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0022] Unless the content clearly dictates otherwise, the singular forms "a", "an", and "the" used in this specification and the appended claims include plural referents. It should also be noted that, unless the content clearly dictates otherwise, the term "or" is generally employed in its broadest sense, i.e., "and / or".

[0023] Dashed lines in the figures are used to indicate the presence of additional elements that are omitted for simplicity.

[0024] Figure 1FIG. 0 is a cross-sectional view of a portion of a semiconductor structure 100 in accordance with an exemplary embodiment of the present disclosure. In this embodiment, the semiconductor structure 100 includes a semiconductor die 110 having a semiconductor substrate that includes various active and passive circuits such as transistors, resistors, capacitors, logic, etc. The semiconductor structure 100 also includes contact pads 120, a passivation layer 130, a first dielectric layer 140, a redistribution layer 150, a second dielectric layer 160, and a conductive structure 171 that includes a metallization layer 170. The conductive structure 171 can be any suitable structure capable of conducting an electrical signal and can be, but is not limited to, an under-bump metal structure (UBM) as the metallization layer 170, and solder bumps or solder balls 180. These conductive structures form the basis for providing electrical contacts, which will be described in detail below. However, other embodiments may include fewer or more elements of the semiconductor structure depending on specific design requirements.

[0025] The semiconductor die 110 is disposed on a carrier substrate of a wafer (not shown). The semiconductor die 110 can have a first surface 111, a second surface 113, and a third surface 115. In one embodiment, the first surface 111 can refer to the top surface of the semiconductor die 110 as arranged in Figure 1 FIG. 5. The first surface can be, for example, a planar surface. The contact pads 120 can be disposed on the top surface of the semiconductor die 110. The semiconductor die 110 includes a second surface 113, which can refer to the side surface of the semiconductor die 110. In one embodiment, the first surface 111 and the second surface 113 are lateral to each other. In another embodiment, the first surface 111 and the second surface 113 are perpendicular to each other. The semiconductor die 110 further includes a third surface 115, which can refer to the bottom surface of the semiconductor die 110. The third surface 115 of the semiconductor die 110 can contact the carrier substrate of the wafer. The first surface 111 and the third surface 115 are opposite to each other and can be parallel to each other. The semiconductor die 110 can be made of a material including, but not limited to, silicon (Si) or gallium arsenide (GaAs).

[0026] The contact pad 120 is located on the first surface 111 of the semiconductor die 110. In one embodiment, the contact pad 120 is disposed on the top surface of the semiconductor die 110. In this embodiment, the contact pad 120 may overlay an area of the semiconductor die 110 and does not necessarily have a surface coplanar with the first surface 111 of the semiconductor die 110. However, in some embodiments, to minimize the overall height and thickness of the semiconductor structure 100, the contact pad 120 may be embedded or recessed in the semiconductor die 110 and may have a top surface coplanar with the first surface 111 of the semiconductor die 110. Embedding the contact pad 120 in the semiconductor die 110 may include: etching the semiconductor die 110 and depositing the contact pad 120 on the etched portion of the die 110. This contact may be part of the processing steps for forming active and passive circuits in the die. Thus, the contact pad 120 may be deposited on the semiconductor die 110 to a position below the first surface 111 of the semiconductor die 110. In one embodiment, the contact pad 120 is a metal pad and may be made of a conductive material including but not limited to metals such as copper (Cu), aluminum (Al), etc.

[0027] The passivation layer 130 is located on the semiconductor die 110. In one embodiment, the passivation layer 130 is disposed on the semiconductor die 110 and on a first portion 117 of the contact pad 120. For example, the passivation layer 130 overlaps and contacts two edge portions of the contact pad 120. The passivation layer 130 may be made of an inorganic dielectric material. For example, the passivation layer 130 may be made using silicon nitride (SiN), silicon dioxide (SiO2), other dielectrics, or any compound utilizing a combination of Si and N or Si and O. The passivation layer 130 is used to protect the semiconductor die 110. Depending on the design, the passivation layer 130 may be omitted.

[0028] The first dielectric layer 140 is located on the passivation layer 130. In one embodiment, the first dielectric layer 140 is disposed on the passivation layer 130 and on a second portion 119 of the contact pad 120. For example, the first dielectric layer 140 overlaps and contacts the second portion 119 of the contact pad 120. In one embodiment, the first dielectric layer 140 is made of an insulating material including but not limited to polybenzoxazole (PBO) or polyimide (PI).

[0029] The redistribution layer 150 is located on the first dielectric layer 140. In one embodiment, the redistribution layer 150 is disposed on the first dielectric layer 140 and the contact pad 120. For example, the redistribution layer 150 contacts the third portion 121 of the contact pad 120 and overlaps the passivation layer 130 and the first dielectric layer 140. In one embodiment, the redistribution layer 150 includes an extension portion 152. For example, the extension portion 152 extends to the side of the semiconductor die 110 to cover the sides of the passivation layer 130 and the first dielectric layer 140. The semiconductor die 110 may include a plurality of redistribution layers 150 formed around the perimeter of the die and associated with other solder balls 180 located around the semiconductor die 110. In different applications, the redistribution layer 150 extends along each side of the semiconductor die 110 to provide electrical contact on some of the sidewalls.

[0030] For a more detailed illustration, the extension portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110. In one embodiment, the redistribution layer 150 extends to the second surface 113 of the semiconductor die 110 (e.g., the sidewall of the semiconductor die 110) and covers the sides of the passivation layer 130 and the first dielectric layer 140, such that the passivation layer 130 and the first dielectric layer 140 are prevented from being directly exposed.

[0031] In one embodiment, the extension portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 to expose the lip portion 112 of the semiconductor die 110. For example, the redistribution layer 150 does not extend all the way down along the second surface 113 (e.g., the sidewall) and may cover the sides of the passivation layer 130 and the first dielectric layer 140 while exposing the top surface and the side surfaces of the lip portion 112 of the semiconductor die 110. In another embodiment, as Figure 1 shown, the outer surface of the extended redistribution layer 150 may be coplanar with the outer surface of the lip portion 112 of the semiconductor die 110.

[0032] In another embodiment, the extension portion 152 of the redistribution layer 150 extends all the way down along the second surface 113 of the semiconductor die 110. For example, the redistribution layer 150 extends all the way down along the sidewall and may cover the sides of the passivation layer 130, the first dielectric layer 140, and the side of the semiconductor die 110. In this embodiment, the extended redistribution layer 150 may cover over the lip portion 112 of the semiconductor die 110 to provide the entire surface as an electrical contact. Although not shown, if the extended redistribution layer 150 covers over the lip portion 112 of the semiconductor die 110, the extended redistribution layer 150 will form a stepped shape in the side of the semiconductor die 110 due to the lip portion 112.

[0033] In yet another embodiment, the semiconductor die 110 may not have the lip portion 112, and the extension portion 152 of the redistribution layer 150 may extend downward along the second surface 113 of the semiconductor die 110 all the way to reach the third surface 115 of the semiconductor die 110. Refer to Figure 3B . For example, the side surfaces of the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140 may be coplanar, and the redistribution layer 150 may extend along the sidewalls to completely cover the side surfaces of the passivation layer 130, the first dielectric layer 140, and the semiconductor die 110. In this embodiment, the extended redistribution layer 150 may extend until it reaches the third surface 115 (e.g., the bottom surface of the semiconductor die 110) to provide electrical contacts including the entire second surface 113.

[0034] The second dielectric layer 160 is located on the redistribution layer 150. In one embodiment, the second dielectric layer 160 overlaps with the contact pads 120, the passivation layer 130, the first dielectric layer 140, and the redistribution layer 150. In one embodiment, the second dielectric layer 160 may only contact a certain area of the redistribution layer 150. The second dielectric layer 160 may be made of the same material as the first dielectric layer 140, and the material includes but is not limited to PBO or PI.

[0035] The under bump metallurgy (UBM) 170 is located on the second dielectric layer 160. The UBM 170 is included as one of the conductive structures 171 for conducting electrical signals. In one embodiment, the UBM 170 is in direct contact with the redistribution layer 150 at a position spaced apart from the contact pads 120. The redistribution layer 150 can be electrically and physically connected to the contact pads 120. This connection enables the conductive structure 171 to provide electrical signals to other input / output terminals, such as a printed circuit board (PCB) or other circuits (not shown). In this embodiment, the UBM 170 is located on the second dielectric layer 160 that does not overlap with the contact pads 120. However, in another embodiment, the position of the UBM 170 may overlap with the contact pads 120, or may be located at different positions according to any design requirements. The UBM 170 may be made of a metal, and the metal includes but is not limited to nickel (Ni), Al, Cu, chromium (Cr), titanium (Ti), or any combination thereof.

[0036] The solder balls 180 are located on the UBM 170. The solder balls 180 are also included in the conductive structure 171 for conducting electrical signals. The solder balls 180 may be collectively referred to as solder balls, solder bumps, solder joints, etc. Any structure capable of conducting electrical signals will satisfy, and is not limited to solder balls.

[0037] In an integrated circuit package, solder balls provide electrical contacts between the chip package and the PCB, and the PCB provides an electrical contact via the solder balls. However, according to the present disclosure, the redistribution layer 150 on the first dielectric layer 140 extends along the side of the semiconductor die 110 to provide a second electrical contact on the sidewall of the semiconductor die 110. With this configuration, chip packages can be stacked vertically and horizontally. This design will improve the interconnectivity between chip modules and save area consumption.

[0038] Additionally, due to this configuration, another electrical contact is provided on the side of the semiconductor die 110, which avoids the use of through-silicon vias (TSVs) or through-chip vias as vertical electrical connections through the silicon die. Although TSVs also provide interconnectivity in 3D packaging and 3D integrated circuits, the manufacturing process involved in forming TSVs in the silicon die is complex, difficult, and expensive. Therefore, the extended redistribution layer 150 can provide a configuration that consumes less area, involves less cost, consumes less power, and maintains a high interconnect speed due to the shortening of the connection length. A more detailed description of the vertical connection is provided in Figure 4 and Figure 5 .

[0039] In another embodiment, the electrical signals output to the solder balls 180 and the extended portion 152 of the redistribution layer 150 can be different. The semiconductor structure can be configured to provide two significantly different electrical signals. For example, the semiconductor structure 100 provides at least two output terminals, and each of the signals output through the solder balls 180 and the extended portion 152 of the redistribution layer 150 can be different according to the design requirements.

[0040] Alternatively, in some embodiments, the electrical signals output from the solder balls 180 and the extended portion 152 will be the same.

[0041] Figure 2 is a top view of the semiconductor structure 100 according to an exemplary embodiment of the present disclosure. Figure 1 of

[0042] Referring to Figure 2 , the semiconductor structure 100 according to an embodiment of the present disclosure can have an extended portion of the redistribution layer 150. Referring to Figure 1 , a cross-sectional view of the semiconductor structure 100 along the dotted line has been explained. The top view of the semiconductor structure 100 shows only one ball, however, the package will include multiple balls, and some or all of these balls can have an extended portion of the redistribution layer 150.

[0043] In Figure 2In this case, solder balls 180 and redistribution layer 150 are formed on semiconductor die 110. Redistribution layer 150 extends to the side of semiconductor die 110 to cover a portion of the sidewall of die 110. Although the sidewall region overlapping with the extended redistribution layer 150 is completely covered on the side, the extended redistribution layer 150 may not cover the remaining side region of semiconductor die 110.

[0044] In one embodiment, the sidewall region covered by the extended redistribution layer 150 may be narrow, thus providing a small-sized contact area. However, in another embodiment, the sidewall region covered by the extended redistribution layer 150 may be wide, thus providing a large-sized contact area. Therefore, contact areas of different sizes can be provided based on design requirements.

[0045] In other embodiments not shown, the extended redistribution layer 150 can be re-wired to provide contacts at different parts of semiconductor die 110. By stretching the extended redistribution layer 150 to different positions in semiconductor die 110, the second contact provided by the extended redistribution layer 150 does not necessarily have to be located on the side as shown with respect to Figure 1 and Figure 2 shown on the side.

[0046] Figure 3A and Figure 3B shows an example of providing a mold protection layer in combination with semiconductor die 110 and an extended portion 152 of redistribution layer 150 according to an embodiment of the present disclosure.

[0047] In Figure 3A a mold protection layer 190 is provided to cover the side of semiconductor die 110, the side of passivation layer 130, and the side of first dielectric layer 140. Mold protection layer 190 is located between the extended portion 152 of redistribution layer 150 and semiconductor die 110, passivation layer 130, and first dielectric layer 140.

[0048] Referring to Figure 3A semiconductor die 110 has a lip portion 112 on a carrier substrate of a wafer (not shown). Semiconductor die 110 may have a first surface 111 and a second surface 113. The lip may extend through the second surface 113.

[0049] In one embodiment, the first surface 111 may refer to the top surface of the semiconductor die 110, and the contact pad 120 may be deposited on the first surface 111 of the semiconductor die 110. The semiconductor die 110 includes a second surface 113, which may refer to the side surface of the semiconductor die 110. In one embodiment, the first surface 111 and the second surface 113 may be lateral to each other. For example, the first surface 111 and the second surface 113 do not need to be perpendicular to each other. Thus, the first surface 111 and the second surface 113 may form an inclined angle with each other. However, in another embodiment, the first surface 111 and the second surface 113 may be perpendicular to each other. The semiconductor die 110 may be made of materials including but not limited to Si or GaAs.

[0050] The contact pad 120 is deposited on the first surface 111 of the semiconductor die 110. In one embodiment, the contact pad 120 is located on the top surface of the semiconductor die 110. In this embodiment, the contact pad 120 may be positioned such that the surface of the contact pad 120 is coplanar with the first surface 111 of the semiconductor die 110. However, in different embodiments, the surface of the contact pad 120 and the semiconductor die 110 do not necessarily have to be coplanar. In some embodiments, in order to minimize the overall height and thickness of the semiconductor structure 300, the contact pad 120 may be embedded in the semiconductor die 110 and may have a top surface coplanar with the semiconductor die 110. For example, the contact pad 120 may be a metal pad and may be made of conductive materials including but not limited to Cu, Al, etc.

[0051] The passivation layer 130 is deposited on the semiconductor die 110. In one embodiment, the passivation layer 130 is located on the semiconductor die 110 and overlaps with a first portion 117 of the contact pad 120. For example, the passivation layer 130 covers two edge portions of the contact pad 120 and contacts the contact pad 120. In this embodiment, the passivation layer 130 is deposited on the semiconductor die 110 but does not extend to the lip portion 112 of the semiconductor die 110. The passivation layer 130 may be made of inorganic or organic dielectric materials. For example, the passivation layer 130 may be made using SiN, SiO2, other dielectrics, or any compound utilizing a combination of Si and N or Si and O. The passivation layer 130 is used to protect the semiconductor die 110. According to the design, the passivation layer 130 may be omitted.

[0052] The first dielectric layer 140 is deposited on the passivation layer 130. In one embodiment, the first dielectric layer 140 is located on the passivation layer 130 and overlaps with the second portion 119 of the contact pad 120. For example, the first dielectric layer 140 overlays the second portion 119 of the contact pad 120 and contacts both the contact pad 120 and the passivation layer 130. In this embodiment, the first dielectric layer 140 is deposited on the passivation layer 130, but does not extend to the lip portion 112 of the semiconductor die 110. The first dielectric layer 140 can be made of, for example, but not limited to, PBO or PI.

[0053] The redistribution layer 150 is deposited on the first dielectric layer 140. In one embodiment, the redistribution layer 150 is located on the contact pad 120, the first dielectric layer 140, and the die protection layer 190. For example, the redistribution layer 150 contacts the third portion 121 of the contact pad 120 and overlaps with the passivation layer 130, the first dielectric layer 140, and the die protection layer 190. In one embodiment, the redistribution layer 150 includes an extension portion 152 that extends along the sidewall or the second surface 113 of the semiconductor die 110. In another embodiment, the other end of the redistribution layer 150 does not have to extend to the other side surface of the semiconductor die 110. That is, according to the circuit design requirements, the redistribution layer 150 can be formed only on one side of the semiconductor die 110. However, in different applications, the redistribution layer 150 can extend along both sides of the semiconductor die 110 to provide electrical contacts on both sidewalls of the semiconductor die 110.

[0054] The extension portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 including the lip portion 112. In one embodiment, the redistribution layer 150 extends to the second surface 113 of the semiconductor die 110 (e.g., the sidewall of the semiconductor die 110) and covers the top surface of the first dielectric layer 140 as well as the top surface and the side surface of the die protection layer 190, so as to prevent the passivation layer 130, the first dielectric layer 140, and the die protection layer 190 from being directly exposed.

[0055] In one embodiment, the extension portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110, but does not cover the lip portion 112 of the semiconductor die 110. For example, the redistribution layer 150 may not extend all the way down along the second surface 113 (e.g., the sidewall of the semiconductor die 110), and may cover the die protection layer 190 until it reaches the top surface of the lip portion 112 of the semiconductor die 110.

[0056] In another embodiment, an extension portion 152 of the redistribution layer 150 extends along a second surface 113 of the semiconductor die 110 to expose a lip portion 112 of the semiconductor die 110. For example, the extension portion 152 of the redistribution layer 150 may be coplanar with the lip portion 112 of the semiconductor die 110. That is, a side surface of the lip portion 112 of the semiconductor die 110 may be coplanar with the extension portion 152 of the redistribution layer 150 that extends along the second surface 113 (e.g., sidewall) of the semiconductor die 110.

[0057] A mold protection layer 190 is provided to cover side surfaces of the semiconductor die 110, side surfaces of the passivation layer 130, and side surfaces of the first dielectric layer 140. The mold protection layer 190 may provide additional protection on top of the extended redistribution layer 150. The mold protection layer 190 is located between the extension portion 152 of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140. The mold protection layer 190 is disposed adjacent to an outer periphery of the semiconductor die. In one embodiment, the mold protection layer 190 surrounds the semiconductor die 110 to provide protection on sidewalls of the semiconductor structure 300.

[0058] A compression molding process may be used to form the mold protection layer 190 to encapsulate the die with a molding compound. However, other methods may be used and are not limited to this molding process. The mold protection layer 190 may provide additional protection on top of the extended redistribution layer 150. The mold protection layer 190 is located between side surfaces of the semiconductor die 110, side surfaces of the passivation layer 130, side surfaces of the first dielectric layer 140, and the extension portion of the redistribution layer 150 such that an electrical contact area on sidewalls of the semiconductor die 110 is not reduced.

[0059] In another embodiment, the mold protection layer 190 may be positioned to cover a portion of the extension portion 152 of the redistribution layer 150. With this configuration, the electrical contact area provided on sidewalls of the semiconductor die 110 using the extension portion 152 of the redistribution layer 150 may be reduced. For example, the mold protection layer 190 may be formed between the lip portion 112 of the semiconductor die 110 and the extension portion 152 of the redistribution layer 150 to partially cover a lower extension portion of the redistribution layer 150. However, in different embodiments, the mold protection layer 190 may be provided to cover an upper extension portion or a middle extension portion of the redistribution layer 150 according to design requirements.

[0060] The second dielectric layer 160 is deposited on the redistribution layer 150. In one embodiment, the second dielectric layer 160 overlaps with the contact pads 120, the passivation layer 130, the first dielectric layer 140, and the redistribution layer 150. For example, the second dielectric layer 160 is positioned such that the layer contacts a portion of the first dielectric layer 140 and a portion of the redistribution layer 150. The second dielectric layer 160 may be made of the same material as the first dielectric layer 140, which includes but is not limited to PBO or PI.

[0061] The UBM 170 is deposited on the second dielectric layer 160. The conductive structure 171 according to the present disclosure particularly further includes the UBM 170, the solder ball 180, etc., which are capable of conducting electrical signals. In one embodiment, the UBM 170 directly contacts the redistribution layer 150 at a position not overlapping with the contact pads 120. The redistribution layer 150 may be electrically or physically connected to the contact pads 120, and this connection enables the conductive structure 171 to provide electrical signals to other input / output terminals, such as a PCB or other external circuits (not shown). In this embodiment, the UBM 170 is located on the second dielectric layer 160 at a position not overlapping with the contact pads 120. However, in another embodiment, the position of the UBM 170 may overlap with the contact pads 120 or be located at different positions according to any design requirements. The UBM 170 may be made of a metal including but not limited to, for example, Ni, Al, Cu, Cr, Ti, or any combination thereof.

[0062] The solder ball 180 is mounted on the UBM 170. The solder ball 180 is also included in the conductive structure 171 for conducting electrical signals. The solder ball 180 may be collectively referred to as a solder ball, a solder bump, a solder joint, etc. Any structure capable of conducting electrical signals will satisfy and is not limited to a solder ball.

[0063] According to the current circuit package, the solder ball may provide a first electrical contact to the chip package or the PCB, but the extended redistribution layer 150 may also provide a second electrical contact on the sidewall of the semiconductor die 110. With this configuration, the chip packages can be vertically and horizontally stacked. This design will improve the interconnectivity between chip modules and save area occupancy.

[0064] In addition, this configuration enhances the interconnectivity in 3D packaging and 3D integrated circuits and reduces the complexity involved in the manufacturing process, because forming the extended redistribution layer 150 can be used in the conventional bump formation process without adding additional manufacturing stages. For example, the extended redistribution layer 150 can be easily formed using the conventional WLCSP bump process. Therefore, the complexity involved in forming the extended redistribution layer 150 is reduced and the cost is lower. Further, due to the shortening of the connection length between chip packages or to the PCB, the extended redistribution layer 150 can provide a configuration that occupies less area, consumes less power and still maintains a high interconnect speed. In Figure 4 and Figure 5 the vertical connection will be explained in more detail.

[0065] In another embodiment, the electrical signals output to the solder balls 180 and the electrical signals output to the extended portion 152 of the redistribution layer 150 can be different. The semiconductor structure can be configured to provide two significantly different electrical signals. For example, the semiconductor structure 100 provides at least two output terminals, and each of the signals output through the solder balls 180 and the extended portion of the redistribution layer 150 can be different according to the design requirements.

[0066] In Figure 3B a mold protective layer 190 is provided to cover the sides of the semiconductor die 110, the sides of the passivation layer 130, and the sides of the first dielectric layer 140. The mold protective layer 190 is located between the extended portion of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140.

[0067] Referring to Figure 3B , the semiconductor die 110 has no lip portion. The semiconductor die 110 without a lip portion is disposed on a carrier substrate of a wafer (not shown). For the purpose of clarity and so as not to obscure the subject matter of the present disclosure, repetitive descriptions that can be easily found in connection with Figure 1 and Figure 3A are omitted.

[0068] A mold protective layer 190 is provided to cover the sides of the semiconductor die 110, the sides of the passivation layer 130, and the sides of the first dielectric layer 140. The mold protective layer 190 can provide additional protection on top of the extended redistribution layer 150 for the semiconductor die 110. The mold protective layer 190 is located between the extended portion of the redistribution layer 150 and the semiconductor die 110, the passivation layer 130, and the first dielectric layer 140. The mold protective layer 190 is disposed adjacent to the outer perimeter of the semiconductor die. In one embodiment, the mold protective layer 190 surrounds the semiconductor die 110 to provide protection on the sidewalls of the semiconductor structure 320.

[0069] Only the features related to the mold protection layer 190 are described in detail. A compression molding process can be used to encapsulate the die with molding compound to form the mold protection layer 190. However, as mentioned, another suitable molding process can be used. The mold protection layer 190 is located between the side surface 113 of the semiconductor die 110, the side surface of the passivation layer 130, the side surface of the first dielectric layer 140, and the extension portion 152 of the redistribution layer 150, such that the electrical contact area on the sidewall of the semiconductor die 110 is not reduced. Since Figure 3B the semiconductor die 110 in

[0070] has no lip portion, the mold protection layer 190 can be formed to cover all the way down until it reaches the third surface 115 of the semiconductor die 110. For example, the mold protection layer 190 can be formed to cover the entire second surface 113 of the semiconductor die 110.

[0071] The extension portion 152 of the redistribution layer 150 extends along the second surface 113 of the semiconductor die 110 and covers the mold protection layer 190. In one embodiment, the redistribution layer 150 extends on top of the mold protection layer 190 to the sidewall of the semiconductor die 110, such that the mold protection layer 190 is not directly exposed. This configuration allows the mold protection layer 190 to protect the semiconductor die 110 and the outer boundary of the extended redistribution layer 150 to have a wide contact surface on the sidewall of the semiconductor die 110.

[0072] Figure 4 A cross-sectional view of two semiconductor structures according to an embodiment of the present disclosure is shown, the two semiconductor structures being stacked and connected and having solder balls on the lateral surfaces.

[0073] In Figure 4Among them, a part of the package 400 includes a first semiconductor die 110 and a second semiconductor die 410 attached together via an adhesive layer 498. The adhesive layer 498 can be any suitable material for attaching silicon dies together. For example, an adhesive including but not limited to polyimide or epoxy resin can be used to bond two silicon dies. The first semiconductor die 110 includes a first contact pad 120, a first passivation layer 130, a first dielectric layer 140, a first redistribution layer 150, a second dielectric layer 160, a first conductive structure 171 including a first UBM 170, and a first solder ball 180. The second semiconductor die 410 includes a second contact pad 420, a second passivation layer 430, a third dielectric layer 440, a second redistribution layer 450, a fourth dielectric layer 460, a second conductive structure 471 including a second UBM 470, and a second solder ball 480. However, according to specific design requirements, other embodiments may include fewer or more elements of the semiconductor structure.

[0074] The first semiconductor die 110 and other elements of the first semiconductor die 110 are formed in a manner similar to that Figure 1 or Figure 3A described. Therefore, the repeated description of the same elements is omitted.

[0075] The first semiconductor die 110 having the first solder ball 180 can be connected to a printed circuit board (PCB) 494 using a conductive layer 492. The conductive layer 492 can provide an electrical connection between the first solder ball 180 and the PCB 494. The conductive layer 492 can be made of any metal capable of conducting signals, including but not limited to Cu, Al, etc.

[0076] The second semiconductor die 410 can have a fourth surface 411, a fifth surface 413, and a sixth surface 415. In one embodiment, the fourth surface 411 can refer to the bottom surface, the fifth surface 413 can refer to the side surface, and the sixth surface 415 can refer to the top surface of the second semiconductor die 410, which faces in the downward direction in the figure.

[0077] The second contact pad 420 can be disposed on the top surface of the second semiconductor die 410. In one embodiment, the fifth surface 413 and the sixth surface 415 can be lateral to each other. In another embodiment, the fifth surface 413 and the sixth surface 415 can be perpendicular to each other.

[0078] The second semiconductor die 410 further includes a sixth surface 415, which may correspond to the top surface of the second semiconductor die 410. In one embodiment, the fourth surface 411 and the sixth surface 415 may face each other. For example, the fourth surface 411 and the sixth surface 415 may be located on opposite sides facing each other. In another embodiment, the fourth surface 411 and the sixth surface 415 may be parallel to each other. The second semiconductor die 410 may be made of materials including but not limited to Si or GaAs.

[0079] In this embodiment, the third surface 115 (e.g., the bottom surface of the first semiconductor die 110) of the first semiconductor die 110 and the fourth surface 411 (e.g., the bottom surface of the second semiconductor die 410) of the second semiconductor die 410 may face each other. For example, the third surface 115 of the first semiconductor die 110 and the fourth surface 411 of the second semiconductor die 410 may be located on opposite sides and may be glued to each other using an adhesive layer 498. In other embodiments, the adhesive layer 498 may be omitted.

[0080] The second contact pad 420 is located on the sixth surface 415 of the second semiconductor die 410. In one embodiment, the second contact pad 420 is disposed on the top surface of the second semiconductor die 410. In this embodiment, the second contact pad 420 may overlap an area of the second semiconductor die 410, and does not necessarily have a surface coplanar with the sixth surface 415 of the second semiconductor die 410. However, in some embodiments, to minimize the overall height and thickness of the semiconductor structure 400, the second contact pad 420 may be embedded in the second semiconductor die 410 and may have a top surface coplanar with the second semiconductor die 410. Embedding the second contact pad 420 in the second semiconductor die 410 may include: etching the second semiconductor die 410 and depositing the second contact pad 420 on the second semiconductor die 410. Thus, the second contact pad 420 may be deposited on the second semiconductor die 410 at a position lower than the top surface of the second semiconductor die 410. In one embodiment, the second contact pad 420 is a metal pad and is made of a conductive material including but not limited to Cu, Al, etc.

[0081] The second passivation layer 430 is located on the second semiconductor die 410. In one embodiment, the second passivation layer 430 is disposed on the second semiconductor die 410 and on a first portion 417 of the second contact pad 420. For example, the second passivation layer 430 overlaps and contacts two edge portions of the second contact pad 420. The second passivation layer 430 can be made of SiN, SiO2, other dielectrics, or any compound using a combination of Si and N or Si and O. The second passivation layer 430 is used to protect the second semiconductor die 410. Depending on the design, the second passivation layer 430 can be omitted.

[0082] The third dielectric layer 440 is located on the second passivation layer 430. In one embodiment, the third dielectric layer 440 is disposed on the second passivation layer 430 and on a second portion 419 of the second contact pad 420. For example, the third dielectric layer 440 overlaps and contacts the second portion 419 of the second contact pad 420. In one embodiment, the third dielectric layer 440 is made of, but not limited to, PBO or PI.

[0083] The second redistribution layer 450 is located on the third dielectric layer 440. In one embodiment, the second redistribution layer 450 is disposed on the third dielectric layer 440 and on the second contact pad 420. For example, the second redistribution layer 450 contacts a third portion 421 of the second contact pad 420 and overlaps the second passivation layer 430 and the third dielectric layer 440. In one embodiment, the second redistribution layer 450 includes an extension portion 452. In another embodiment, the other end of the second redistribution layer 450 does not have to extend to the other side surface of the second semiconductor die 410. That is, the second redistribution layer 450 can be formed only on one side surface of the second semiconductor die 410. However, in different applications, the second redistribution layer 450 can extend along two side surfaces of the second semiconductor die 410 to provide electrical contacts on two sidewalls.

[0084] The extension portion 452 of the second redistribution layer 450 extends along a fifth surface 413 (e.g., a side surface) of the second semiconductor die 410. In one embodiment, the second redistribution layer 450 extends to the fifth surface 413 (e.g., the sidewall of the second semiconductor die 410) of the second semiconductor die 410 and covers the side surfaces of the second passivation layer 430 and the third dielectric layer 440, so as to prevent the second passivation layer 430 and the third dielectric layer 440 from being directly exposed.

[0085] In one embodiment, an extension portion 452 of the second redistribution layer 450 extends along a fifth surface 413 of the second semiconductor die 410 to expose a lip portion 412 of the semiconductor die 410. For example, the second redistribution layer 450 does not extend all the way down along the fifth surface 413 and can cover the sides of the second passivation layer 430 and the third dielectric layer 440, but leaves the lip portion 412 of the second semiconductor die 410 open.

[0086] In another embodiment, in a semiconductor die without a lip portion 412 (e.g., both the first semiconductor die 110 and the second semiconductor die 410 are similar to the die structure 320 seen Figure 3B and do not have a lip portion), the surfaces of the extended second redistribution layer 450 and the extended first redistribution layer 150 can be coplanar. However, due to the adhesive layer 498 between the two semiconductor dies, the extended second redistribution layer 450 and the extended first redistribution layer 150 can be electrically insulated from each other.

[0087] In an additional embodiment, the extension portion 452 of the second redistribution layer 450 extends all the way down along the fifth surface 413 of the second semiconductor die 410. For example, the second redistribution layer 450 extends all the way down along the sidewalls and can cover the sides of the second passivation layer 430, the third dielectric layer 440, and the second semiconductor die 410. In this embodiment, the extended second redistribution layer 450 can cover the lip portion 412 of the second semiconductor die 410 to provide an entire surface as an electrical contact. Although not shown, if the extended second redistribution layer 450 covers the lip portion 412 of the second semiconductor die 410, it will form a stepped shape in the side of the second semiconductor die 410 due to the lip portion 412. Due to the adhesive layer 498 between the two semiconductor dies, the extended second redistribution layer 450 and the extended first redistribution layer 150 can still be electrically insulated from each other.

[0088] A fourth dielectric layer 460 is located on the second redistribution layer 450. In one embodiment, the fourth dielectric layer 460 overlaps with the second contact pad 420, the second passivation layer 430, the third dielectric layer 440, and the second redistribution layer 450. In one embodiment, the fourth dielectric layer 460 can contact only a certain area of the second redistribution layer 450. The fourth dielectric layer 460 can be made of, but not limited to, the same material as the third dielectric layer 140 (e.g., PBO or PI).

[0089] The second UBM 470 is located on the fourth dielectric layer 460. The second UBM 470 is included as one of the conductive structures 471 for conducting electrical signals. In one embodiment, the second UBM 470 is in direct contact with the second redistribution layer 450 at a position spaced apart from the second contact pad 420. The second redistribution layer 450 can be electrically and physically connected to the second contact pad 420. In this embodiment, the second UBM 470 is located on the fourth dielectric layer 460 that does not overlap with the second contact pad 420. However, in another embodiment, the position of the second UBM 470 can overlap with the second contact pad 420 or be located at different positions according to any design requirements. The second UBM 470 can be made of, but not limited to, Ni, Al, Cu, Cr, Ti, or any combination thereof.

[0090] The second solder ball 480 is located on the second UBM 470. The second solder ball 480 is also included in the conductive structure 471 for conducting electrical signals. The second solder ball 480 can be collectively referred to as a solder ball, a solder bump, a solder joint, etc. Any structure capable of conducting electrical signals will satisfy and is not limited to a solder ball. A conductive structure such as the second solder ball 480 can provide electrical signals to other input / output terminals such as a PCB or other circuits. Although not shown in Figure 4 the first solder ball 180 mounted on the first semiconductor die 110 is connected to the PCB 494 to provide input / output terminals. According to design requirements, additional PCBs can be attached to the second solder ball 480 mounted on the second semiconductor die 410.

[0091] In a wafer-level package, solder balls can be used for electrical connection to a chip package or a PCB. However, according to the wafer-level package of the present disclosure, the first semiconductor die 110 and the second semiconductor die 410 are vertically stacked on top of each other, and additional electrical contacts are also provided on the second surface of the first semiconductor die 110 and the fifth surface 413 of the second semiconductor die 410. The first extended redistribution layer 150 and the second extended redistribution layer 450 can be connected by a conductive connection. The conductive connection can be any material capable of conducting electrical signals, such as a metal. In one embodiment, the conductive connection includes but is not limited to a solder joint, a solder bump, a solder ball 496, or a bonding wire 510 ( Figure 5 as shown), or any similar structure that provides electrical contacts on the sidewalls. With this configuration, due to the electrical contacts on the sidewalls, the chip packages can be vertically stacked and also horizontally connected. This design will improve the interconnectivity between chip modules and save floor space.

[0092] In Figure 4In [the figure], the conductive connection 496 connects both the first extended redistribution layer 150 and the second extended redistribution layer 450 to form a large single contact. However, in other embodiments, separate conductive connections 496 may be used for each of the extended redistribution layers 150, 450. For example, one solder ball may be separately mounted on the first extended redistribution layer 150 to form one electrical contact, and a second solder ball may be separately mounted on the second extended redistribution layer 450 to form another electrical contact. This configuration not only increases the number of electrical contacts on the side of the double-stacked semiconductor structure 400, but also provides a basis for retrieving two different signals from the first extended redistribution layer 150 and the second extended redistribution layer 450. In the previous embodiment where the solder ball 496 overlays both the first extended redistribution layer 150 and the second extended redistribution layer 450, since the solder ball 496 is connected to both the first extended redistribution layer 150 and the second extended redistribution layer 450, the electrical contact provided by the solder ball 496 may have only one identical signal. However, if separate solder balls are connected to each of the extended redistribution layers 150, 450 of the first extended redistribution layer 150 and the second extended redistribution layer 450, two separate electrical signals may exist that can be retrieved from each of the extended redistribution layers 150, 450 of the first extended redistribution layer 150 and the second extended redistribution layer 450.

[0093] In addition, this configuration enhances the interconnectivity in 3D packaging and 3D integrated circuits. The manufacturing process involved in forming the extended redistribution layer is not complex, difficult, or expensive because it utilizes the traditional WLCSP process. The additional processes involved are stacking two semiconductor dies together and providing solder joints 496 on the side of the stacked semiconductor dies. The solder joints 496 provide side connections for the two vertically stacked semiconductor dies 110, 410. The solder joints 496 can further be used to horizontally connect any semiconductor package or external circuit in the horizontal direction of the semiconductor structure 400. This allows for the formation of 3D packaging that occupies less area and also involves lower costs. In addition, this allows for the expansion of interconnectivity in the vertical and horizontal directions. Additionally, since the connection length is shortened, it consumes less power and maintains a high interconnect speed.

[0094] In another embodiment, the electrical signals output to the first solder ball 180 and the second solder ball 480 may be different from the electrical signals output through the solder joint 496. The semiconductor structure 400 may be configured to provide significantly different electrical signals according to different design requirements.

[0095] Figure 5 A cross-sectional view of a semiconductor package having connections using wire bonding according to an embodiment of the present disclosure is shown. In Figure 5 In [the figure], [it has been shown for] Figure 4The corresponding components are explained and will not be repeated.

[0096] Referring to Figure 5 , the first semiconductor die 110 and the second semiconductor die 410 in the vertically stacked semiconductor structure 500 can be connected together using wire bonding 510.

[0097] In vertically stacking two semiconductor dies (e.g., the first semiconductor die 110 and the second semiconductor die 410), the electrical connection between the top semiconductor die 110 and the bottom semiconductor die 410 can be accomplished using wire bonding 510. For example, the material for the wire bonding 510 can include, for example, any metal capable of conducting an electrical signal, such as Cu, Al, etc. Contrary to the solder joints 496 used in Figure 4 , the wire bonding 510 can electrically connect the extended first redistribution layer 150 of the top die 110 and the extended second redistribution layer 450 of the bottom die 410. In other embodiments, the wire bonding 510 can be used to connect the semiconductor die to other semiconductor packages or other external circuits (not shown).

[0098] The vertical stacking of the semiconductor structure 500 not only improves the interconnectivity in 3D packaging and 3D integrated circuits, but also saves space, which minimizes the total package size. The semiconductor structure 500 also improves the horizontal connectivity by providing additional electrical contacts on the second surface 113 of the first semiconductor die 110 and the fifth surface 413 of the second semiconductor die 410. The first extended redistribution layer 150 and the second extended redistribution layer 450 can be connected by wire bonding 510, and the wire can be used to connect to an external circuit or PCB according to industrial requirements. With this configuration, chip packages can be vertically stacked and horizontally connected. This design improves the interconnectivity between chip modules and saves floor space. It also allows the formation of such a 3D package that consumes less power due to the shortened connection length but maintains a high interconnect speed.

[0099] In another embodiment, the electrical signals output to the first solder ball 180 and the second solder ball 480 can be different from the electrical signals output through the wire bonding 510. The semiconductor structure 500 can be configured to provide significantly different electrical signals according to different design requirements.

[0100] Figures 6A to 6I is a cross-sectional view showing an exemplary method of fabricating an extended redistribution layer according to an embodiment of the present disclosure.

[0101] In this embodiment, in Figure 6AIn this case, the method begins with a carrier substrate 602. A semiconductor die 604 is placed on the carrier substrate 602. For example, the semiconductor die 604 is attached to the carrier substrate 602 such that it is affixed to the carrier substrate 602. The semiconductor die 604 includes a first surface 605, a second surface 607 transverse to the first surface 605, and a third surface 609 opposite the first surface 605. The first surface 605 may refer to the top surface of the semiconductor die 604. The second surface 607 may refer to the side surface of the semiconductor die 604. In another embodiment, the first surface 605 and the second surface 607 may be perpendicular to each other. In other embodiments, the angle formed by the first surface 605 and the second surface 607 may be an inclined angle. Additionally, in some embodiments, the first surface 605 and the third surface 609 may be located on opposite sides. For example, the first surface 605 and the third surface 609 may be parallel to each other, but they do not necessarily have to be parallel. Additionally, the third surface 609 and the second surface 607 may be transverse to each other. The semiconductor die 604 may be made of materials such as, but not limited to, Si or GaAs.

[0102] In Figure 6B this case, contact pads 606 are provided on the first surface 605 of the semiconductor die 604. In one embodiment, the contact pads 606 are disposed on the top surface of the semiconductor die 604. In this embodiment, the contact pads 606 may overlay an area of the semiconductor die 604 and do not necessarily have a surface coplanar with the first surface 605 of the semiconductor die 604. However, in some embodiments, to minimize the overall height and thickness of the semiconductor structure, the contact pads 606 may be embedded in the semiconductor die 604 and may have a top surface coplanar with the semiconductor die 604. Embedding the contact pads 606 in the semiconductor die 604 may include: etching the semiconductor die 604 and depositing the contact pads 606 on the die 604. Thus, in some embodiments, the contact pads 606 may be deposited on the semiconductor die 604 to a position below the top surface of the semiconductor die 604. In one embodiment, the contact pads 606 are metal pads and are made of conductive materials including, but not limited to, Cu, Al, etc.

[0103] In Figure 6C this case, a passivation layer 608 is provided on the semiconductor die 604 and the contact pads 606. The passivation layer 608 may be deposited on the semiconductor die 604 and the contact pads 606 using various deposition methods known in the art. For example, the passivation layer 608 is made of materials such as SiN, SiO2, other dielectrics, or any compound using a combination of Si and N or Si and O. The passivation layer 608 is used to protect the semiconductor die 604. Depending on the design, the passivation layer 608 may be omitted.

[0104] InFigure 6D In Figure 6D , a portion of the passivation layer 608 is removed to expose a portion of the contact pad 606. This partial removal of the passivation layer 608 creates an opening 610 and partially exposes the contact pad 606. Through this removal, the passivation layer 608 overlaps with a first portion 617 of the contact pad 606.

[0105] In Figure 6E In Figure 6E , a first dielectric layer 612 is provided on the passivation layer 608 and in the opening 610 created by the partial removal of the passivation layer 608. The first dielectric layer 612 can be deposited based on any known deposition method in the art. For example, the first dielectric layer 612 is disposed along the passivation layer 130 and the shape made by the opening 610. The first dielectric layer 612 is made of, but not limited to, PBO or PI.

[0106] In Figure 6F In Figure 6F , a redistribution layer 616 is provided on the first dielectric layer 612. Before depositing the redistribution layer 616 on the first dielectric layer 612, the first dielectric layer 612 is etched and removed to expose a portion of the contact pad 606. As a result of the removal, in one embodiment, the first dielectric layer 612 is disposed on the passivation layer 608 and on a second portion 619 of the contact pad 606. For example, the first dielectric layer 612 overlaps and contacts the second portion 619 of the contact pad 606.

[0107] In addition, after providing the first dielectric layer 612 and partially removing the first dielectric layer 612 to expose the contact pad 606, a die protection layer 614 can be provided on the second surface 607 of the semiconductor die 604. The die protection layer 614 is provided adjacent to the outer perimeter of the semiconductor die 604. In one embodiment, the die protection layer 614 surrounds the semiconductor die 604 to provide protection on the sidewalls of the semiconductor structure. For example, as shown, the die protection layer 614 is positioned to cover the second surface 607 of the semiconductor die 604, the sides of the passivation layer 608, and the sides of the first dielectric layer 612. The process of forming the die protection layer 614 can be performed using, for example, a compression molding process. This process is used to encapsulate the semiconductor die 604 with a molding compound while protecting the active surface of the die. For example, the molding compound can surround all exposed silicon die surfaces while ignoring certain surfaces of the die. In some embodiments, the process of forming the die protection layer 614 can be omitted based on industrial design requirements.

[0108] Returning to Figure 6F, a redistribution layer 616 is provided on a portion of the contact pad 606 and the first dielectric layer 612. In one embodiment, the redistribution layer 616 is disposed on the contact pad 606, the first dielectric layer 612, and the die protection layer 614. For example, the redistribution layer 616 contacts a third portion 621 of the contact pad 606 and overlaps the passivation layer 608, the first dielectric layer 612, and the die protection layer 614. A second portion 619 of the contact pad 606 is located between a first portion 617 and a third portion 621 of the pad 606. In one embodiment, the redistribution layer 616 includes an extension portion 626. In this embodiment, the redistribution layer 616 extends over the die protection layer 614, completely covering the die protection layer 614, and contacts the carrier substrate 602. The extension portion 626 of the redistribution layer 616 extends along a second surface 607 of the semiconductor die 604 such that the passivation layer 608, the first dielectric layer 612, and the die protection layer 614 are prevented from being directly exposed.

[0109] In one embodiment, the redistribution layer 616 may be formed on one side of the semiconductor die 604. However, in different embodiments, the other end of the redistribution layer 616 may extend to the other surface of the semiconductor die 604. That is, the redistribution layer 616 may extend along two sides of the semiconductor die 604 to provide electrical contacts on two sidewalls.

[0110] In Figure 6F , the extension portion 626 of the deposited redistribution layer 616 has been explained with respect to a semiconductor die 604 without a lip portion (not shown). However, the same process of forming a layer on the semiconductor die 604 can be applied to a die having a lip portion. In some embodiments, in the case where the semiconductor die has a lip portion, the redistribution layer 616 may extend along the second surface of the semiconductor die 604 and, for the sidewalls, extend right above the lip portion such that the lip portion of the semiconductor die 604 is exposed. For example, the redistribution layer 616 may not extend all the way down along the second surface 607 (e.g., the sidewall) to cover the lip portion of the semiconductor die 604. It may extend to cover the side surface of the die protection layer 614, the side surface of which covers the side surfaces of the passivation layer 608 and the first dielectric layer 612, but leave the lip portion of the semiconductor die 604 open.

[0111] In Figure 6GIn [the structure], a second dielectric layer 618 is provided on the redistribution layer 616. In one embodiment, the second dielectric layer 618 overlaps with the contact pad 606, the passivation layer 608, the first dielectric layer 612, and the redistribution layer 616. In one embodiment, the second dielectric layer 160 may only contact a partial region of the redistribution layer 616. The second dielectric layer 618 may be made of the same material as the first dielectric layer 612 and may be deposited using the same method. The second dielectric layer 618 may be made of, but is not limited to, materials such as PBO or PI.

[0112] In Figure 6H [the structure], a UBM 620 is provided on the second dielectric layer 618. In one embodiment, the UBM 620 is in direct contact with the redistribution layer 616 at a position spaced apart from the contact pad 606. For example, the redistribution layer 616 may be electrically and physically connected to the contact pad 606. This connection enables a conductive structure such as the UBM 620 to provide an electrical signal to other input / output terminals such as a PCB or other external circuit (not shown). In this embodiment, the UBM 620 is located on the second dielectric layer 618 that does not overlap with the contact pad 606. However, in another embodiment, the position of the UBM 620 may overlap with the contact pad 606 or be located at a different position according to any design requirements. For example, the UBM 620 may be made of a metal that includes, but is not limited to, for example, Ni, Al, Cu, Cr, Ti, or any combination thereof.

[0113] In Figure 6I [the structure], a solder ball 622 is provided on the UBM 620. The solder ball 622 may include any conductive material capable of conducting an electrical signal and may include, for example, solder bumps, solder joints, wire bonds, etc. Any structure capable of conducting an electrical signal will satisfy and is not limited to solder balls.

[0114] Figure 7 A cross-sectional view of scribing adjacent semiconductor structures according to an embodiment of the present disclosure is shown.

[0115] In Figure 7 [the structure], a semiconductor structure 700 having two silicon dies is shown, with the first semiconductor die 704 and the second semiconductor die 804 placed adjacent to each other. It will be apparent to those of ordinary skill in the art that multiple semiconductor dies are mounted on carrier substrates 702, 802 of a wafer. In this embodiment, as Figure 7As shown, two silicon dies are attached to a carrier substrate. The first semiconductor die 704 is attached to the first carrier substrate 702, and the second semiconductor die 804 is attached to the second carrier substrate 802. The first carrier substrate 702 and the second carrier substrate 802 can be the same and can form a large single carrier substrate. The carrier substrate can have multiple semiconductor dies placed on top of the carrier substrate.

[0116] The semiconductor structure formed on top of the carrier substrate 802 can be formed based on the same or similar processes used to form the semiconductor structure built on top of the carrier substrate 702. For example, contact pads (not shown), a passivation layer 808, a first dielectric layer 812, a die protection layer 814, a redistribution layer 816, a second dielectric layer 818, a UBM 820, and solder balls 822 can be formed in the same or similar manner as explained in the previous embodiments.

[0117] In other embodiments, the process of forming contact pads 706, a passivation layer 708, a first dielectric layer 712, a die protection layer 714, a redistribution layer 716, a second dielectric layer 718, a UBM 720, solder balls 722, etc. on the semiconductor die 704 can be in a single unified process for multiple semiconductor dies mounted on the carrier substrate. For example, the aforementioned elements and layers can be formed in a single process for each of the multiple semiconductor dies mounted on the carrier substrate. Thus, the same elements and layers formed on the semiconductor die 704 will be formed on the adjacent semiconductor die 804 and on any other multiple semiconductor dies mounted on the carrier substrates 702, 802. For example, the passivation layer 708 in the first semiconductor die 704 can be formed in the same process as the passivation layer 808 in the second semiconductor die 804. The passivation layers for all other semiconductor dies (not shown) on the carrier substrates 702, 802 can also be formed in the same single process.

[0118] An exemplary method of forming an extended redistribution layer on a semiconductor die is to form a redistribution layer on each of the multiple semiconductor dies in a reconstructed wafer. In the reconstructed wafer, multiple semiconductor dies are mounted on the reconstructed wafer and are spaced apart from each other. The process of forming various layers on top of the multiple semiconductor dies involved is as explained in conjunction with the previous embodiments. After forming various layers (such as contact pads, passivation layers, first dielectric layers, die protection layers, redistribution layers, second dielectric layers, UBMs, solder balls, etc.), the semiconductor die with the redistribution layer and the adjacent semiconductor die with the redistribution layer are picked up and removed from the carrier substrate (not shown).

[0119] In other embodiments, the semiconductor die may have lip portions 705, 805, and the lip portion 705 of one semiconductor die 704 may be connected to the lip portion 805 of an adjacent semiconductor die 804, as Figure 7 shown. For these semiconductor dies, another exemplary method of forming an extended redistribution layer on the semiconductor die may be used. The exemplary method includes: forming a redistribution layer on each of a plurality of semiconductor dies on a semi-cut wafer, and scribing the lip portions of each of the adjacent semiconductor dies.

[0120] For example, in Figure 7 , the first semiconductor die 704 is connected to the second semiconductor die 804 through their respective lip portions 705, 805. The process of forming various layers on the first semiconductor die 704 and the second semiconductor die 804 includes processes similar to those explained in the previous embodiments related to bonding. After forming various layers (such as contact pads, passivation layers, first dielectric layers, die protection layers, redistribution layers, second dielectric layers, UBMs, solder balls, etc.), the first semiconductor die 704 and the adjacent second semiconductor die 804 are cut along the scribe line 710. The scribe line 710 cuts between the lip portion 705 of the first semiconductor die 704 and the lip portion 805 of the second semiconductor die 804. After cutting on the semi-cut wafer along the scribe line 710, the first semiconductor die 704 and the adjacent second semiconductor die 804 are separated. Other semiconductor dies mounted on the carrier substrate are cut in a similar manner. After singulating each of the plurality of semiconductor dies into individual semiconductor dies, the individual dies are removed from the carrier substrates 702, 802. Each of the individual semiconductor dies includes an extended redistribution layer that allows for a large contact area to be achieved at the chip sidewalls.

[0121] The various embodiments described above may be combined to provide other embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the application data sheet are hereby incorporated by reference in their entirety. If concepts from various patents, applications, and publications are needed to provide other embodiments, aspects of the embodiments may be modified.

[0122] These and other changes may be made to the embodiments in light of the above detailed description. In general, in the following claims, the terms used should not be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be construed to include all possible embodiments and equivalents of the full scope of the claims to which the claims are entitled. Thus, the claims are not limited by the disclosure.

Claims

1. A device, comprising: A semiconductor die, comprising a first surface, a second surface opposite to the first surface, and a first sidewall surface transverse to the first surface and the second surface; A contact pad exposed from the first surface; A first dielectric layer on the contact pad and extending from the contact pad to the first sidewall surface, the first dielectric layer comprising a second sidewall surface coplanar with the first sidewall surface; A second dielectric layer on the contact pad and extending from the contact pad to the first sidewall surface and the second sidewall surface, the second dielectric layer having a third sidewall surface coplanar with the first sidewall surface and the second sidewall surface, the second dielectric layer having a surface facing away from the semiconductor die; A mold protective layer on the first sidewall surface, the second sidewall surface, and the third sidewall surface and covering the first sidewall surface, the second sidewall surface, and the third sidewall surface, the mold protective layer having an end surface facing away from the semiconductor die and a fourth sidewall surface transverse to the end surface of the mold protective layer; A redistribution layer on the contact pad and extending from the contact pad to the mold protective layer, the redistribution layer covering the surface of the dielectric layer, the end surface of the mold protective layer, and the sidewall surface of the mold protective layer; And A third dielectric layer on the redistribution layer and the second dielectric layer, the third dielectric layer overlapping with the contact pad and the first dielectric layer.

2. The device according to claim 1, further comprising a conductive layer extending into the third dielectric layer to reach the redistribution layer, the conductive layer being coupled to the redistribution layer.

3. The device according to claim 2, wherein the conductive layer is an under-bump metal structure.

4. The device according to claim 3, further comprising a solder ball coupled to the under-bump metal structure.

5. The device according to claim 4, further comprising a printed circuit board, the printed circuit board comprising a contact pad coupled to the solder ball.

6. The device according to claim 1, wherein the redistribution layer is spaced apart from the first sidewall surface, the second sidewall surface, and the third sidewall surface by the mold protective layer.

7. The device according to claim 1, further comprising a solder material coupled to a portion of the redistribution layer on the sidewall surface of the mold protective layer.

8. A device, comprising: A semiconductor die having a first surface, a second surface transverse to the first surface, and a third surface opposite to the first surface, the second surface being between the first surface and the third surface, the semiconductor die comprising a contact pad exposed from the first surface; A first dielectric layer on the first surface of the semiconductor die, the first dielectric layer extending from the contact pad to the second surface of the semiconductor die; A redistribution layer on the first surface and the second surface of the semiconductor die, the redistribution layer being on the first dielectric layer and the contact pad; A second dielectric layer on the first surface of the semiconductor die, the second dielectric layer being on the redistribution layer and the first dielectric layer; and A conductive structure on the first surface of the semiconductor die, the conductive structure extending through the second dielectric layer to the redistribution layer, and the conductive structure being on the redistribution layer and the second dielectric layer.

9. The device according to claim 8, wherein the conductive structure includes an under-bump metal structure extending into the second dielectric layer to the redistribution layer, and the under-bump metal structure is coupled to the redistribution layer.

10. The device according to claim 9, wherein the conductive structure further includes a solder structure coupled to the under-bump metal structure.

11. The device according to claim 10, wherein: The semiconductor die further includes a lip portion extending through the mold protection layer to the redistribution layer, the lip portion being transverse to the second surface; The mold protection layer has an end on the lip portion; and The redistribution layer has an end on the lip portion.

12. The device according to claim 11, further including a mold protection layer on the second surface between the redistribution layer and the second surface, the mold protection layer separating the redistribution layer from the second surface.

13. A device, comprising: A first semiconductor die structure, including: A first semiconductor die, including a first surface, a first sidewall transverse to the first surface, a second surface opposite the first surface, a first contact pad at the first surface, and a first lip portion extending outward from the first sidewall, the first lip portion being at the first sidewall, and the first sidewall extending from the first lip portion to the first surface; A first passivation layer on the first surface of the semiconductor die and on the first contact pad, the first passivation layer including a second sidewall coplanar with the first sidewall; A first dielectric layer on the first passivation layer and on the first contact pad, the first dielectric layer including a third sidewall coplanar with the first sidewall and the second sidewall; and A first redistribution layer, including: A first portion on the first contact pad, the first portion extending along the first dielectric layer in a first direction from the first contact pad to the first sidewall, the second sidewall, and the third sidewall, the first direction being transverse to the first sidewall, the second sidewall, and the third sidewall; and A second portion overlapping the first sidewall, the second sidewall, and the third sidewall and extending to the first lip portion, the second portion extending in a second direction transverse to the first direction, the first surface, and the second surface.

14. The device according to claim 13, wherein: The first lip portion includes an end surface transverse to the first surface and the second surface; and The second portion includes a contact surface transverse to the first surface and the second surface, and the contact surface is coplanar with an end surface of the first lip portion.

15. The device according to claim 13, further comprising a mold protective layer that physically contacts and covers the first sidewall, the second sidewall, and the third sidewall, and the mold protective layer is located between the second portion and the first sidewall, the second sidewall, and the third sidewall.

16. The device according to claim 15, wherein the mold protective layer extends along the first sidewall, the second sidewall, and the third sidewall to the first lip portion.

17. The device according to claim 13, wherein: The second portion includes a contact surface transverse to the first surface and the second surface; and The first lip portion includes an end surface transverse to the first surface and the second surface, the first lip portion extends past the contact surface of the second portion, and the end surface of the first lip portion is further away from the first sidewall, the second sidewall, and the third sidewall relative to the contact surface.

18. The device according to claim 13, wherein the mold protective layer extends along the first sidewall, the second sidewall, and the third sidewall to the first lip portion, and the mold protective layer is located between the second portion and the first sidewall, the second sidewall, and the third sidewall.

19. The device according to claim 18, wherein: The second portion includes a contact surface transverse to the first surface and the second surface; and The first lip portion includes an end surface transverse to the first surface and the second surface, the first lip portion extends past the contact surface of the second portion, and the end surface of the first lip portion is further away from the first sidewall, the second sidewall, and the third sidewall relative to the contact surface.

20. The device according to claim 13, further comprising: A second semiconductor die structure coupled to the first semiconductor die structure by an adhesive layer, the second semiconductor die structure comprising: A second semiconductor die including a third surface, a fourth sidewall transverse to the third surface, a fourth surface opposite the third surface, a second contact pad at the third surface, and a second lip portion extending outward from the fourth sidewall, the second lip portion being at the fourth sidewall, and the fourth sidewall extending from the second lip portion to the third surface; A second passivation layer on the third surface of the second semiconductor die and on the second contact pad, the second passivation layer including a fifth sidewall coplanar with the fourth sidewall; A second dielectric layer on the second passivation layer and on the second contact pad, the second dielectric layer including a sixth sidewall coplanar with the fourth sidewall and the fifth sidewall; and A second redistribution layer, comprising: Third part, on the second contact pad, the third part extends along the second dielectric layer in the first direction from the second contact pad to the fourth sidewall, the fifth sidewall, and the sixth sidewall, the first direction being transverse to the fourth sidewall, the fifth sidewall, and the sixth sidewall; and Fourth part, overlapping with the fourth sidewall, the fifth sidewall, and the sixth sidewall and extending to the second lip portion, the second part extending in a second direction transverse to the first direction, the third surface, and the fourth surface.

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