Semiconductor device and method of manufacturing the same

Abstract

Some embodiments of the present disclosure provide a semiconductor device and a method of manufacturing the same. The semiconductor device includes a conductive structure forming a portion of a copper redistribution layer. Forming the conductive structure includes forming the conductive structure in the shielding structure and performing a chemical / mechanical polishing process to planarize the conductive structure. Formation of the conductive structure in the shielding structure enables the conductive structure to have a rounded foot, and stress concentration in the semiconductor device may be reduced relative to another semiconductor device using an aluminum copper redistribution layer. In addition, the planarized conductive structure reduces the rounded surface of the conductive structure bonded to the interconnect structure to reduce the likelihood of bonding defects.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the same. Background Art

[0002] A semiconductor device (such as a processor, a memory element, or another type of semiconductor device, etc.) may include one or more redistribution layers. A redistribution layer (RDL) is a thin layer of conductive material including conductive traces and / or pads to redistribute the conductive structures (such as, bonding pads and / or interconnects) of the semiconductor device in different patterns, typically matching the pitch requirements of the wiring and / or external connection structures connected to the semiconductor device. Summary of the Invention

[0003] Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a conductive structure of a redistribution layer and an interconnect structure. The conductive structure of the redistribution layer includes vertical sidewalls, a circular foot protruding laterally from the vertical sidewalls at the base of the conductive structure, and a nearly flat horizontal surface. The nearly flat horizontal surface forms a sharp angle with the vertical sidewalls located at the top of the conductive structure, with the top of the conductive structure relative to the base. The interconnect structure is connected to the conductive structure along the nearly flat horizontal surface.

[0004] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including the following steps. Form a masking layer. Form a conductive structure in a plurality of openings of the masking layer, wherein the conductive structure has a portion extending above the top surface of the masking layer. Remove the portion extending above the top surface to form a nearly flat horizontal surface on the conductive structure. Remove the masking layer. Form a dielectric layer above the conductive structure. Form an interconnect structure that penetrates the dielectric layer and is connected to the nearly flat horizontal surface of the conductive structure.

[0005] Some embodiments of the present disclosure provide a method for manufacturing a semiconductor device, including the following steps. Form a plurality of conductive structures spanning a semiconductor die and redistribution layers having a plurality of different heights in a plurality of openings of a masking layer above the semiconductor die. Remove a portion of at least one of the conductive structures to reduce the variation in different heights spanning the semiconductor die. Remove the masking layer. Form a dielectric layer above the conductive structures. Form a plurality of interconnect structures that penetrate the dielectric layer and are connected to the conductive structures. Brief Description of the Drawings

[0006] Embodiments of the present disclosure can be better understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard practices in the art, the features are not drawn to scale. In fact, for the sake of clarity in discussion, the dimensions of various features can be arbitrarily increased or decreased.

[0007] Figure 1 A diagram of an exemplary environment configured to implement the systems and / or methods described in this disclosure;

[0008] Figure 2 A diagram that is part of an exemplary semiconductor device described in this disclosure;

[0009] Figures 3A to 3F A diagram of an exemplary embodiment of forming a structure of a semiconductor device using the exemplary chemical / mechanical planarization process described in this disclosure;

[0010] Figure 4 A diagram of an exemplary semiconductor die package described in this disclosure;

[0011] Figure 5 A diagram of an exemplary embodiment described in this disclosure;

[0012] Figures 6A to 6C A data diagram related to an exemplary embodiment of a conductive structure described in this disclosure;

[0013] Figure 7 A diagram of exemplary elements of one or more devices described in this disclosure; and

[0014] Figure 8 and Figure 9 A flowchart of an exemplary process related to forming a semiconductor device using the chemical / mechanical planarization process described in this disclosure.

[0015]

Symbol Description

[0016] 100: Environment

[0017] 102, 104, 106, 108, 110, 112, 114: Processing tools

[0018] 102: Deposition tool

[0019] 104: Exposure tool

[0020] 106: Development tool

[0021] 108: Etching tool

[0022] 110: Planarization tool

[0023] 112: Electroplating tool

[0024] 114: Ion implantation tool

[0025] 116: Wafer / die transfer tool

[0026] 200: Semiconductor device

[0027] 202, 408, 418: Device area

[0028] 204,410,420: Interconnection region

[0029] 206,216: Dielectric layer

[0030] 208: Integrated circuit

[0031] 210: Isolation structure

[0032] 212: Liner layer

[0033] 214,228,414,424,432: Interconnection structure

[0034] 218,218a,218b: Conductive structure

[0035] 220,220a,220b: Vertical sidewall

[0036] 222: Round foot

[0037] 224,224a,224b: Horizontal surface

[0038] 226,226a,226b: Sharp corner

[0039] 230,416,426: Bond pad structure

[0040] 300,500,600: Embodiment

[0041] 302: Masking layer

[0042] 304: Portion

[0043] 306,308: Cavity

[0044] 400: Semiconductor die package

[0045] 402,404: Semiconductor die

[0046] 406: Bonding interface region

[0047] 412,422: Redistribution layer structure

[0048] 428: Bump region

[0049] 430: Bump

[0050] 602,624: Height

[0051] 604: Width

[0052] 606,608,610,616,618,620,628,630: Data

[0053] 612: Variation

[0054] 614: Protrusion distance

[0055] 622: Threshold

[0056] 626: Lateral position

[0057] 700: Device

[0058] 710: Bus

[0059] 720: Processor

[0060] 730: Memory

[0061] 740: Input component

[0062] 750: Output component

[0063] 760: Communication component

[0064] 800,900: Process

[0065] 810,820,830,840,850,860,910,920,930,940,950: Steps

[0066] D1,D2,D4: Height

[0067] D3: Height difference

[0068] D5: Flatness

[0069] D7,D8: Width

[0070] D9: Distance

[0071] D10,D10a,D10b: Angle Detailed implementation manners

[0072] The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these specific examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature and the second feature may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and in itself does not indicate the relationship between the various embodiments and / or configurations discussed.

[0073] In addition, for ease of description, spatial relative terms (such as "below", "beneath", "lower", "above", "upper", and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the accompanying drawings. In addition to the orientation depicted in the drawings, the spatial relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatial relative descriptors used herein may be interpreted accordingly.

[0074] In some cases, a redistribution layer (RDL) includes a conductive structure formed of an aluminum-copper (AlCu) material. Forming the conductive structure may include using a sputtering process that forms an abruptly angled footer, and the abruptly angled footer combines with the coefficient of thermal expansion of the AlCu material, resulting in stress concentration, which in turn results in cracks and / or defects in the conductive structure. In other cases, the RDL includes a copper (Cu) material. Although using a Cu material allows the conductive structure to have a rounded footer that reduces such stress concentration, variations in the height of the conductive structure can result in variations in the etch profile. As a result, the top of the conductive structure is formed as a rounded surface. The rounded surface (e.g., a rounded pad) may cause bonding defects between the conductive structure and an interconnect structure connected to the conductive structure. The bonding defects reduce the quality and / or reliability of a semiconductor device formed by using an RDL including a Cu material.

[0075] Some embodiments described in this disclosure provide a semiconductor device including a conductive structure formed as part of a copper RDL. Forming the conductive structure includes forming the conductive structure in a masking structure and performing a chemical / mechanical polishing (CMP) process to planarize the conductive structure. The conductive structure is formed in the masking structure such that the conductive structure can have a rounded footer and reduce stress concentration in the semiconductor device (relative to another semiconductor device using an aluminum-copper RDL). In addition, the conductive structure is planarized to reduce the rounding of the surface of the conductive structure that forms a bond with the interconnect structure, thereby reducing the likelihood of bonding defects.

[0076] As a result, the quality and / or reliability of the semiconductor device is improved. By improving the quality and / or reliability of the semiconductor device, the amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) configured to support the market that consumes the semiconductor device is reduced.

[0077] Figure 1Figure of an exemplary environment 100 configured to implement the systems and / or methods described in this disclosure. The exemplary environment 100 includes semiconductor processing tools configurable to form semiconductor structures and devices (such as the conductive structures described in this disclosure).

[0078] As Figure 1 shown, the environment 100 may include multiple semiconductor processing tools 102 - 114 and a wafer / die transfer tool 116. The semiconductor processing tools 102 - 114 include a deposition tool 102, an exposure tool 104, a development tool 106, an etching tool 108, a planarization tool 110, an electroplating tool 112, an ion implantation tool 114, and / or another semiconductor processing tool. The tools included in the exemplary environment 100 may be included in a semiconductor cleanroom, a semiconductor fabrication plant, semiconductor processing and / or manufacturing equipment, or others.

[0079] The deposition tool 102 is a semiconductor processing tool and includes a semiconductor processing chamber and one or more devices capable of depositing various types of materials onto a substrate. In some embodiments, the deposition tool 102 includes a spin coating tool capable of depositing a photoresist layer onto a substrate (such as a wafer). In some embodiments, the deposition tool 102 may include a chemical vapor deposition (CVD) tool, such as a plasma-enhanced CVD (PECVD) tool, a high-concentration plasma CVD (HDP-CVD) tool, a sub-atmospheric CVD (SACVD) tool, an atomic layer deposition (ALD) tool, a plasma-enhanced atomic layer deposition (PEALD) tool, or other types of CVD tools. In some embodiments, the deposition tool 102 includes a physical vapor deposition (PVD) tool, such as a sputtering tool or other types of PVD tools. In some embodiments, the exemplary environment 100 includes multiple types of deposition tools 102.

[0080] The exposure tool 104 is a semiconductor processing tool capable of exposing a photoresist layer to a radiation source, such as an ultraviolet light (UV) source (e.g., a deep UV light source and / or an extreme UV light (EUV) source, etc.), an X-ray source, an electron beam (e-beam) source, and / or other types of exposure tools. The exposure tool 104 can expose the photoresist layer to the radiation source to transfer a pattern from a photomask to the photoresist layer. The pattern can include one or more semiconductor device layer patterns configured to form one or more semiconductor devices, can include a pattern of one or more structures configured to form semiconductor devices, and / or can include a pattern configured to etch various parts of the semiconductor device, etc. In some embodiments, the exposure tool 104 includes a scanner, a stepper, or a similar type of exposure tool.

[0081] The developing tool 106 is a semiconductor processing tool capable of developing a photoresist layer that has been exposed to a radiation source to develop the pattern transferred from the exposure tool 104 to the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the unexposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by removing the exposed portions of the photoresist layer. In some embodiments, the developing tool 106 develops the pattern by using a chemical developer to dissolve the exposed or unexposed portions of the photoresist layer.

[0082] The etching tool 108 is a semiconductor processing tool capable of etching various types of materials of a substrate, a wafer, or a semiconductor device. For example, the etching tool 108 can include a wet etching tool, a dry etching tool, and / or other types of etching tools. In some embodiments, the etching tool 108 includes a processing chamber filled with an etchant, and places the substrate in the processing chamber for a specific time to remove one or more portions of the substrate by a specific amount. In some embodiments, the etching tool 108 uses plasma etching or plasma-assisted etching to etch one or more portions of the substrate, such that the one or more portions can be etched anisotropically or directionally by using an ionized gas.

[0083] The planarization tool 110 is a semiconductor processing tool capable of polishing or planarizing the layers of a wafer or semiconductor device. For example, the planarization tool 110 may include a chemical mechanical planarization (CMP) tool and / or other types of planarization tools for polishing or planarizing layers or surfaces of deposited or electroplated materials. The planarization tool 110 can polish or planarize the surface of a semiconductor device by utilizing a combination of chemical and mechanical forces (e.g., chemical etching and free abrasive polishing). The planarization tool 110 can be used in combination with an abrasive pad and a retainer ring (e.g., typically having a diameter larger than that of the semiconductor device) using an abrasive and a corrosive chemical polishing fluid. The abrasive pad and the semiconductor device can be pressed together by a dynamic polishing head and held in position by the retainer ring. The dynamic polishing head can rotate about different axes of rotation to remove material and planarize any irregular topography of the semiconductor device, thereby planarizing or making the semiconductor device flat.

[0084] The electroplating tool 112 is a semiconductor processing tool capable of electroplating a substrate (e.g., a wafer, a semiconductor device, etc.) or a portion of the substrate with one or more metals. For example, the electroplating tool 112 may include a copper electroplating device, an aluminum electroplating device, a nickel electroplating device, a tin electroplating device, a compound material or alloy (e.g., tin-silver and / or tin-lead, etc.) electroplating device, and / or an electroplating device configured to electroplate one or more of other types of conductive materials and / or metals, etc.

[0085] The ion implantation tool 114 is a semiconductor processing tool capable of implanting ions into a substrate. The ion implantation tool 114 can generate ions from a source material (e.g., a gas or a solid) in an arc chamber. The source material can be provided into the arc chamber, and a discharge voltage is applied between a cathode and an electrode to generate a plasma containing ions of the source material. One or more extraction electrodes can be used to extract ions from the plasma in the arc chamber and accelerate the ions to form an ion beam. The ion beam can be directed towards the substrate such that the ions are implanted beneath the surface of the substrate.

[0086] The wafer / die transfer tool 116 includes a mobile robot, a robotic arm, a tram or a railcar, an overhead hoist transfer (OHT) vehicle, an automated material handling system (AMHS), and / or other types of tools configured to transfer wafers and / or dies between semiconductor processing tools 102 - 114 and / or to and from other locations (e.g., a wafer rack, a storage room, or other locations). In some embodiments, the wafer / die transfer tool 116 is a programmed tool to travel a specific path and / or can operate semi-autonomously or autonomously.

[0087] As combined withFigures 3A to 3F As shown, one or more of the semiconductor processing tools 102-114 can perform a series of semiconductor manufacturing steps. The series of semiconductor manufacturing steps includes forming a masking layer. The series of semiconductor manufacturing steps includes forming a conductive structure in an opening of the masking layer, the conductive structure having a portion that extends above the top surface of the masking layer. The series of semiconductor manufacturing steps includes removing the portion that extends above the top surface to form an approximately planar, horizontal surface on the conductive structure. The series of semiconductor manufacturing steps includes removing the masking layer. The series of semiconductor manufacturing steps includes forming a dielectric layer above the conductive structure. The series of semiconductor manufacturing steps includes forming an interconnect structure that penetrates the dielectric layer and connects to the approximately planar, horizontal surface of the conductive structure.

[0088] Additionally or alternatively, the series of semiconductor manufacturing steps includes forming a conductive structure in an opening of the masking layer above the semiconductor die that has a redistribution layer with different heights across the semiconductor die. The series of semiconductor manufacturing steps includes removing a portion of at least one conductive structure to reduce the variation in different heights of the semiconductor die. The series of semiconductor manufacturing steps includes removing the masking layer. The series of semiconductor manufacturing steps includes forming a dielectric layer above the conductive structure. The series of semiconductor manufacturing steps includes forming an interconnect structure that penetrates the dielectric layer and connects to the conductive structure.

[0089] Figure 1 The number and configuration of the tools shown are provided as one or more examples. In practice, there may be more tools, fewer tools, different tools, or tools with different configurations than those Figure 1 shown. Additionally, Figure 1 two or more of the tools shown can be implemented in a single tool, or Figure 1 a single tool shown can be implemented as multiple distributed tools. Additionally or alternatively, a set of tools (e.g., one or more tools) in environment 100 can perform one or more functions described as being performed by another set of tools in environment 100.

[0090] Figure 2A figure that is part of the exemplary semiconductor device described in this disclosure. The semiconductor device 200 may include a system on chip (SoC) device, a logic device (such as a central processing unit (CPU) or a graphics processing unit (GPU)), a memory device (such as a high bandwidth memory (HBM) device), and / or other types of semiconductor devices including one or more transistor structures.

[0091] As Figure 2 shown in the side view of, the semiconductor device 200 may include a device region 202 and an interconnect region 204 located above the device region 202. The device region 202 includes one or more dielectric layers 206. The dielectric layer 206 may be located above or on a substrate (such as a silicon substrate), and the dielectric layer 206 includes silicon nitride (SixN), an oxide (such as silicon oxide (SiOx) and / or another oxide material), and / or another type of dielectric material.

[0092] An integrated circuit 208 (such as an integrated circuit device) may be included in the dielectric layer 206 located in the device region 202. The integrated circuit 208 may include semiconductor devices such as transistors (such as planar transistors, fin field-effect transistors (finFETs), gate all around (GAA) transistors, pixel sensors, capacitors, resistors, inductors, photodetectors, transceivers, transmitters, receivers, optical circuits, other types of semiconductor devices, and / or metallization layers connecting semiconductor devices.

[0093] In some embodiments, the semiconductor device 200 includes one or more isolation structures 210. The isolation structure 210 may penetrate the dielectric layer 206 and include one or more liner layers 212. The liner layer 212 may include a dielectric material such as silicon nitride (SixN), an oxide (such as silicon oxide (SiOx) and / or another oxide material), and / or another type of dielectric material. The isolation structure 210 may electrically isolate one or more interconnect structures 214 extending into the dielectric layer 206 and / or connected to the integrated circuit 208.

[0094] The interconnect region 204 includes one or more dielectric layers 216 located above and / or on the device region 202. In some embodiments, the dielectric layer 216 includes an oxide (such as silicon oxide (SiOx) and / or another oxide material), borophosphosilicate glass (BPSG), and / or another type of dielectric material.

[0095] In the dielectric layer 216, a redistribution layer (RDL) including a conductive material is included, and the redistribution layer (RDL) can be configured to form one or more conductive structures 218. Each conductive structure 218 can include vertical sidewalls 220 in the vertical direction, and the vertical sidewalls 220 in the vertical direction have concave surfaces extending inwardly towards the center of the conductive structure 218. The conductive structure 218 (e.g., RDL) can include a conductive material, such as copper (Cu), etc. In some embodiments, one or more dielectric layers 216 surround the conductive structure 218.

[0096] As Figure 2 shown, circular feet 222 can project laterally from the vertical sidewalls 220 near the base of each conductive structure 218. The circular feet 222 can include a curvature to reduce stress concentration at the base of the conductive structure 218, thereby improving the quality and / or reliability of the semiconductor device 200. In addition, the dielectric layer 216 is conformal with the vertical sidewalls 220 (e.g., the concave surfaces of the vertical sidewalls 220) and / or the circular feet 222.

[0097] Further, as Figure 2 shown, each conductive structure 218 can include a nearly flat horizontal surface 224. The nearly flat horizontal surface 224 can intersect the vertical sidewalls 220 and form sharp corners 226. As described in more detail in connection with Figure 3C , Figure 4 and other parts of this disclosure, the sharp corners 226 can include acute angles or obtuse angles.

[0098] The semiconductor device 200 can also include one or more interconnect structures 228 (e.g., vertical interconnect access structures) connected to the conductive structures 218. The interconnect structures 228 include a conductive material, such as copper (Cu) or other conductive materials. The interconnect structures 228 can be connected (e.g., bonded or merged) to the conductive structures 218 along the corresponding nearly flat horizontal surfaces 224. As described in more detail in connection with Figure 3B and other parts of this disclosure, the nearly flat horizontal surfaces 224 can provide a more secure connection with the interconnect structures 228 to improve the quality and / or reliability of the semiconductor device 200.

[0099] One or more bonding pad structures 230 can be located above and / or on the interconnect structures 228. As described in more detail in connection with Figure 4 , the bonding pad structures 230 can be configured to bond the semiconductor device 200 to another semiconductor device.

[0100] As described in more detail in connection with Figure 2As shown, in some embodiments, a device (e.g., semiconductor device 200) includes a conductive structure of a redistribution layer (e.g., conductive structure 218). The conductive structure includes a vertical sidewall in a vertical direction (e.g., vertical sidewall 220), a circular foot that laterally protrudes from the vertical sidewall at a base of the conductive structure (e.g., circular foot 222), and a near-flat horizontal surface (e.g., near-flat horizontal surface 224), and the near-flat horizontal surface forms a sharp angle (e.g., sharp angle 226) with the vertical sidewall at a top of the conductive structure opposite to the base. The device includes an interconnect structure (e.g., interconnect structure 228) connected to the conductive structure along the near-flat horizontal surface.

[0101] As previously described, take Figure 2 as an example. Other examples may be different from Figure 2 that described.

[0102] Figures 3A to 3F FIG. is an exemplary embodiment 300 of a semiconductor device (e.g., semiconductor device 200) formed using the exemplary chemical / mechanical planarization process described in this disclosure. Embodiment 300 may include using one or more of the semiconductor processing tools 102 - 114 and / or the wafer / die transfer tool 116 described in Figure 1 connection.

[0103] As Figure 3A shown in the side view of, a masking layer 302 (e.g., masking structure) is formed above and / or on the device area 202. In some embodiments, the masking layer 302 includes a photoresist material. In this embodiment, the deposition tool 102 can be used to dispose the photoresist material above and / or on the device area 202. The exposure tool 104 can be configured to expose a pattern on the masking layer 302, and the development tool 106 can be configured to remove the exposed photoresist material to form an opening in the masking layer 302.

[0104] Alternatively, in some embodiments, the masking layer 302 includes a hard mask material. In this embodiment, the pattern in the photoresist layer is used to etch the hard mask material to form an opening in the masking layer 302. In these embodiments, the deposition tool 102 may be configured to form a photoresist layer on and / or above the device region 202. The exposure tool 104 may be configured to expose the photoresist layer to a radiation source to pattern the photoresist layer. The developing tool 106 may be configured to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 may be used to etch the masking layer 302 based on the pattern to form an opening in the masking layer 302. In some embodiments, the etching step includes a plasma etching step, a wet chemical etching step, and / or another type of etching step. In some embodiments, the photoresist removal tool may be configured to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, the hard mask layer is configured as an alternative technique to etch the masking layer 302 based on the pattern.

[0105] Further, as Figure 3A shown, the conductive structure 218 is formed in the opening of the masking layer 302. To form the conductive structure 218, the deposition tool 102 and / or the electroplating tool 112 as Figure 1 described may be used to deposit the conductive structure 218 by CVD technology, PVD technology, ALD technology, electroplating technology, or another suitable deposition technology. The conductive structure 218 may be deposited in one or more deposition steps. In some embodiments, a seed layer is first deposited, and the conductive structure 218 is deposited on the seed layer.

[0106] Further, as Figure 3A shown, based on the width of the opening in the masking layer 302, the height of the conductive structure 218 may vary. As an example, the conductive structure 218a may have a portion 304 extending above the top surface of the masking layer 302, such that one or more of the conductive structures 218 have a height D1 greater than the height D2. In some embodiments, there is a height difference D3 on the conductive structure 218 located in the region of the semiconductor device 200.

[0107] Please refer to Figure 3B , and a planarization process is performed to planarize the conductive structure 218 and reduce the height variation (e.g., reduce the height difference D3). To planarize the conductive structure 218, a chemical / mechanical planarization process may be performed using the planarization tool 110. As an example, in an embodiment where the conductive structure 218 includes a copper material, the planarization tool 110 may use a copper polishing slurry in combination with a polishing pad having a Shore hardness (Durometer) of approximately D<50 and a porosity greater than approximately 25%. However, other polishing slurries and / or polishing pad characteristics are also within the scope of this disclosure.

[0108] In some embodiments, the planarization process includes removing a portion of the masking layer 302 (e.g., the planarization process stops on or within the masking layer 302). Alternatively, in some embodiments, the planarization process does not include removing a portion of the masking layer (e.g., the planarization process stops above the masking layer 302).

[0109] After the planarization process, the conductive structure 218 may have a height D4 between about 2 micrometers (μm) and about 7 μm. Additionally or alternatively, the conductive structure 218 may have a flatness D5 of less than about 100 nanometers (nm) (e.g., height variations within the semiconductor die including the conductive structure 218). If the flatness D5 is greater than about 100 nm, the planarization process may not be complete, and there may be one or more circular surfaces of the conductive structure 218, thereby reducing the quality and / or reliability (e.g., robustness) of the interface (e.g., bonding region) formed subsequently between the conductive structure 218 and the interconnect structure (e.g., interconnect structure 228). However, other values and ranges of the height D4 and / or the flatness D5 are also within the scope of this disclosure.

[0110] Please refer to Figure 3C , by removing the masking layer 302, a cavity 306 is formed between the conductive structures 218. To remove the masking layer 302, a photoresist removal tool may be used to remove the masking layer 302 by chemical strippers, plasma ashing, and / or other techniques. Alternatively, the etching tool 108 may be configured to use plasma etching, wet chemical etching, and / or another type of etching technique to remove the masking layer 302.

[0111] As Figure 3C shown, the conductive structure 218 includes a circular base 222, a vertical sidewall 220, a nearly flat horizontal surface 224, and a sharp corner 226. For example, the width D7 at the top of one or more conductive structures 218 may include between about 1.5 μm and about 100 μm. However, other values and ranges of the width D7 are also within the scope of this disclosure.

[0112] Additionally or alternatively, the width D8 near the bottom of one or more conductive structures 218 may be greater than the width D7. If the width D8 is less than or equal to the width D7, the planarization process may not be complete, and there may be a circular surface at the top of the conductive structure 218, thereby reducing the reliability of the interface formed subsequently between the conductive structure 218 and the interconnect structure 228.

[0113] Additionally or alternatively, the circular base 222 may laterally protrude from the vertical sidewall 220 by a distance D9, and the distance D9 is between about 0.1 μm and about 100 μm. However, other values and ranges of the width D7 are also within the scope of this disclosure.

[0114] Please refer to Figure 3D , a dielectric layer 216 is formed above and / or on a conductive structure 218. The deposition tool 102 can deposit the dielectric layer 216 by using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, and / or another deposition technique and / or another suitable deposition technique as described Figure 1 . The dielectric layer 216 can be deposited in one or more deposition steps. In some embodiments, the planarization tool 110 can be configured to planarize the dielectric layer 216 after depositing the dielectric layer 216.

[0115] Please refer to Figure 3E , a cavity 308 is formed in the dielectric layer 216 to expose the conductive structure 218. In some embodiments, a pattern in a photoresist layer is configured to etch the dielectric layer 216 to form the cavity 308. In these embodiments, in some embodiments, the deposition tool 102 can be configured to form a photoresist layer on the dielectric layer 216. The exposure tool 104 can be configured to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 can be configured to develop and remove a portion of the photoresist layer to expose the pattern. The etching tool 108 can be configured to etch the dielectric layer 216 based on the pattern to form the cavity 308 in the dielectric layer 216. In some embodiments, the etching step includes a plasma etching step, a wet chemical etching step, and / or another type of etching step. In some embodiments, a photoresist removal tool can be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is configured as an alternative technique to etch the dielectric layer 216 based on the pattern.

[0116] Please refer to Figure 3F , an additional dielectric layer 216 is formed. The deposition tool 102 can deposit the dielectric layer 216 by using PVD techniques, ALD techniques, CVD techniques, oxidation techniques, and / or another deposition technique and / or another suitable deposition technique as described Figure 1 . The dielectric layer 216 can be deposited in one or more deposition steps. In some embodiments, the planarization tool 110 can be configured to planarize the dielectric layer 216 after depositing the dielectric layer 216.

[0117] In addition, a bonding pad structure 230 is formed above and / or on the interconnect structure 228. In some embodiments, the pattern in the photoresist layer is configured to etch the dielectric layer 216 to form a cavity exposing the interconnect structure 228. In these embodiments, the deposition tool 102 may be configured to form a photoresist layer on the dielectric layer 216. The exposure tool 104 may be configured to expose the photoresist layer to a radiation source to pattern the photoresist layer. The development tool 106 may be configured to develop and remove portions of the photoresist layer to expose the pattern. The etching tool 108 may be configured to etch the dielectric layer 216 based on the pattern to form the cavity and expose the interconnect structure 228. In some embodiments, the etching step includes a plasma etching step, a wet chemical etching step, and / or another type of etching step. In some embodiments, a photoresist removal tool may be used to remove the remaining portion of the photoresist layer (e.g., using a chemical stripper, plasma ashing, and / or another technique). The bonding pad structure 230 may be formed in the cavity. To form the bonding pad structure 230, the deposition tool 102 and / or the electroplating tool 112 deposit the bonding pad structure 230 by using CVD techniques, PVD techniques, ALD techniques, electroplating techniques, and / or other deposition techniques and / or another suitable deposition technique as described in Figure 1 The bonding pad structure 230 may be deposited in one or more deposition steps. In some embodiments, a seed layer is first deposited, and the bonding pad structure 230 is deposited on the seed layer. In some embodiments, the planarization tool 110 may be configured to planarize the bonding pad structure 230 after depositing the bonding pad structure 230.

[0118] As described above, taking Figures 3A to 3F as an example. Other examples may be different from Figures 3A to 3F that described.

[0119] Figure 4 FIG. is a diagram of an exemplary semiconductor die package 400 described in the present disclosure. The semiconductor die package 400 may correspond to a wafer-on-wafer (WoW) semiconductor die package and has two semiconductor dies bonded using the bonding pad structure (e.g., the bonding pad structure 230) described in the present disclosure.

[0120] As Figure 4As shown in the side view, semiconductor die 402 (e.g., an embodiment of semiconductor device 200) is bonded to semiconductor die 404 along bonding interface region 406. Semiconductor die 402 includes device region 408 (e.g., an embodiment of device region 202) and interconnect region 410 (e.g., an embodiment of interconnect region 204). In interconnect region 410, semiconductor die 402 includes redistribution layer structure 412 (e.g., an embodiment of conductive structure 218), interconnect structure 414 (e.g., an embodiment of interconnect structure 228), and bond pad structure 416 (e.g., an embodiment of bond pad structure 230).

[0121] Semiconductor die 404 (e.g., an embodiment of semiconductor device 200) includes device region 418 (e.g., an embodiment of device region 202) and interconnect region 420 (e.g., an embodiment of interconnect region 204). In interconnect region 420, semiconductor die 404 includes redistribution layer structure 422 (e.g., an embodiment of conductive structure 218), interconnect structure 424 (e.g., an embodiment of interconnect structure 228), and bond pad structure 426 (e.g., an embodiment of bond pad structure 230).

[0122] Bump region 428 may be on and / or above semiconductor die 404 and includes one or more bumps 430 (e.g., solder bumps and / or pillar structures) formed of a conductive material (such as copper (Cu), tin silver copper alloy (SAC), or tin copper nickel alloy (SN100C), etc.), and bumps 430 are suitable for soldering to an interface board and transmitting electrical signals. Such electrical signals may be sent between semiconductor die 402 and semiconductor die 404 using through-silicon via (TSV) interconnect structures 432 included in semiconductor die 402 and / or semiconductor die 404, and such electrical signals are sent to or from bumps 430.

[0123] As Figure 4 shown, a eutectic bonding process may be used to bond bond pad structure 416 and bond pad structure 426. Additionally, as shown in conjunction with Figures 3A to 3F shown, the interface between interconnect structures 414 / 424 and bond pad structures 416 / 426 may be a nearly horizontal flat interface, thereby improving the overall quality and / or reliability of semiconductor die package 400.

[0124] Figure 5It is a diagram of exemplary embodiment 500 described in this disclosure. The diagram of embodiment 500 shows a view of the conductive structure 218 and includes an angle D10 associated with the sharp corner 226.

[0125] As Figure 5 shown, the conductive structure 218a includes a vertical sidewall 220a and a nearly flat horizontal surface 224a. The vertical sidewall 220a has a concave surface that extends inwardly towards the center of the conductive structure 218a. The vertical sidewall 220a intersects with the nearly flat horizontal surface 224a to form a sharp corner 226a. Additionally, the sharp corner 226a includes an angle D10a, where the angle D10a is an acute angle (e.g., an angle less than about 90 degrees).

[0126] Furthermore, as Figure 5 shown, the conductive structure 218b includes a vertical sidewall 220b and a nearly flat horizontal surface 224b. The vertical sidewall 220b has a concave surface that extends inwardly towards the center of the conductive structure 218b. The vertical sidewall 220b intersects with the nearly flat horizontal surface 224b to form a sharp corner 226b. Additionally, the sharp corner 226b includes an angle D10b, where the angle D10b is an obtuse angle (e.g., an angle between about 90 degrees and about 180 degrees).

[0127] Therefore, in some embodiments, the angle D10 associated with the sharp corner 226 of the conductive structure 218 may include an angle between about 10 degrees and about 170 degrees. If the angle D10 is less than about 10 degrees, the thickness of the conductive structure 218 across and / or near the nearly flat horizontal surface 224 may decrease, and the conductive structure 218 may not have enough material to form a strong interface with another structure (e.g., the interconnect structure 228). If the angle D10 is between about 10 degrees and about 170 degrees, the conductive structure 218 can be properly formed and includes enough material across and / or near the nearly flat horizontal surface 224 to form a strong interface. Additionally, an angle D10 greater than about 170 degrees indicates that the conductive structure 218 is oversized (e.g., incorrectly formed), resulting in a risk of bridging and / or electrical short circuit within a device (e.g., the semiconductor device 200) including the conductive structure 218. However, other values and ranges of the angle D10 are also within the scope of this disclosure.

[0128] As previously mentioned, using Figure 5 as an example. Other examples may be different from Figure 5 that described.

[0129] Figures 6A to 6C It is a data diagram related to exemplary embodiment 600 of the conductive structure described in this disclosure. The conductive structure can correspond to one or more of the conductive structures 218 described in connection with Figures 2 to 5 that.

[0130] Figure 6A shows the relationship between the height 602 of the conductive structure 218 (e.g., corresponding to the height D4 as shown in Figure 3A ), the deposition thickness of the RDL material (e.g., corresponding to the height D1 as shown), and different combinations of semiconductor technology generations (e.g., semiconductor processing technologies related to specific semiconductor device structures and / or feature sizes), and the width 604 of the conductive structure 218 (e.g., corresponding to the width D7 as shown in Figure 3B ). Figure 3C ).

[0131] In Figure 6A , the data 606 may correspond to an embodiment of the first-generation technology using a non-copper RDL material with a first nominal deposition thickness, and the data 608 may correspond to an embodiment of the second-generation technology using a copper RDL material with a first deposition thickness, where the second-generation technology is more advanced than the first-generation technology (e.g., the semiconductor processing technology related to the second-generation technology can produce structures with reduced feature sizes). The data 610 may correspond to an embodiment of the second-generation technology using a copper RDL material with a second deposition thickness, where the second deposition thickness is greater than the first deposition thickness.

[0132] As Figure 6A shown, the change 612 in the height 602 related to the change in the width 604 is more significant for a relatively small range of widths. In other words, as the conductive structure 218 becomes "wider" in design or practice, the planarization process may become more predictable, stable, and / or repeatable. In addition, the embodiment using a copper RDL material with a first deposition thickness (e.g., as shown by the data 608) may be more stable and involve fewer variations than the embodiment using a copper RDL material with a second deposition thickness (e.g., as shown by the data 610).

[0133] Figure 6B shows an exemplary relationship between the protrusion distance 614 of the circular foot 222 (e.g., the distance D9 as shown in Figure 3C ) and the width 604 of the conductive structure 218 (e.g., the width D7 as shown in Figure 3C ).

[0134] In Figure 6BAmong them, data 616 may correspond to an embodiment of a first-generation technology using a non-copper RDL material with a first standard deposition thickness, and data 618 may correspond to an embodiment of a second-generation technology using a copper RDL material with a first deposition thickness, where the second-generation technology is more advanced than the first-generation technology (for example, semiconductor processing technologies associated with the second-generation technology can produce structures with reduced feature sizes). Data 620 may correspond to an embodiment of a second-generation technology using a copper RDL material with a second deposition thickness, where the second deposition thickness is greater than the first deposition thickness.

[0135] Figure 6B Exemplary threshold 622 corresponding to the radius and / or size of the circular foot 222 is shown. Meeting threshold 622 can reduce stress concentration in the conductive structure. As Figure 6B shown, for a smaller range of widths 604, the protrusion distance 614 associated with data 618 and 620 is significantly greater than the protrusion distance 614 associated with data 616. In other words, using a copper RDL material can increase the size and / or radius of the circular foot 222 relative to using a non-copper RDL material.

[0136] In addition, the protrusion distance 614 associated with data 618 and 620 meets threshold 622 for all widths 604, while the protrusion distance 614 associated with data 616 only meets threshold 622 for larger widths 604. In other words, using a copper RDL material can meet threshold 622 for all widths 604 to reduce stress concentration within the conductive structure 218.

[0137] Figure 6C A comparison plot of the height 624 of the conductive structure 218 with respect to the lateral position 626 of the conductive structure 218 on the semiconductor device 200 is shown. Data 628 may correspond to the conductive structure 218 formed in an embodiment without planarization, and data 630 may correspond to the conductive structure 218 formed using a planarization process as Figure 3B shown.

[0138] As Figure 6C shown, the variation in height 624 associated with data 630 is significantly less than the variation in height associated with data 628. In other words, using a planarization process as Figure 3B described to form the conductive structure 218 can achieve significant within-die (WiD) improvement.

[0139] As previously mentioned, take Figures 6A to 6C as an example. Other examples may be different from Figures 6A to 6C described.

[0140] Figure 7FIG. is a diagram of exemplary elements of one or more devices 700 described in this disclosure. Device 700 may correspond to one or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 described in connection with Figure 1 In some embodiments, one or more of the semiconductor processing tools 102-114 and / or the wafer / die transfer tool 116 may include one or more devices 700 and / or one or more components of device 700. As shown in Figure 7 , device 700 may include a bus 710, a processor 720, a memory 730, an input element 740, an output element 750, and / or a communication element 760.

[0141] Bus 710 may include one or more components that enable wired and / or wireless communication between the components of device 700. Bus 710 may couple Figure 7 two or more of the components together, such as via operative coupling, communication coupling, electrical coupling, and / or electro - magnetic coupling. For example, bus 710 may include electrical connections (e.g., wires, traces, and / or leads) and / or a wireless bus. Processor 720 may include a central processing unit, a graphics processing unit, a microprocessor, a controller, a microcontroller, a digital signal processor, a field programmable gate array, an application specific integrated circuit, and / or another type of processing component. Processor 720 may be implemented in hardware, firmware, or a combination of hardware and software. In some embodiments, processor 720 may include one or more processors that can be programmed to perform one or more of the steps or processes described elsewhere in this disclosure.

[0142] Memory 730 may include volatile and / or non - volatile memory. For example, memory 730 may include random access memory (RAM), read only memory (ROM), a hard disk, and / or other types of memory (e.g., flash memory, magnetic disks, and / or optical disks). Memory 730 may include internal memory (e.g., RAM, ROM, or a hard disk) and / or removable memory (e.g., removable via a universal serial bus connection). Memory 730 may be a non - transitory computer - readable medium. Memory 730 may store information related to the operation of device 700, one or more instructions, and / or software (e.g., one or more software applications). In some embodiments, memory 730 may include one or more memories that are coupled (e.g., communicatively coupled) to one or more processors (e.g., processor 720) via bus 710. The communication coupling between processor 720 and memory 730 may enable processor 720 to read and / or process information stored in memory 730 and / or store information in memory 730.

[0143] The input component 740 can enable the device 700 to receive inputs, such as user inputs and / or sensed inputs. For example, the input component 740 may include a touch screen, a keyboard, a keypad, a mouse, buttons, a microphone, switches, sensors, a global positioning system sensor, a global navigation satellite system sensor, an accelerometer, a gyroscope, and / or an actuator. The output component 750 can enable the device 700 to provide outputs, such as via a display, a speaker, and / or a light-emitting diode. The communication component 760 can enable the device 700 to communicate with other devices via a wired connection and / or a wireless connection. For example, the communication component 760 may include a receiver, a transmitter, a transceiver, a modem, a network interface card, and / or an antenna.

[0144] The device 700 can perform one or more operations or processes described in this disclosure. For example, a non-transitory computer-readable medium (e.g., the memory 730) can store a set of instructions (e.g., one or more instructions or codes) for execution by the processor 720. The processor 720 can execute a set of instructions to perform one or more operations or processes described in this disclosure. In some embodiments, the execution of the group of instructions by one or more processors 720 causes the one or more processors 720 and / or the device 700 to perform one or more operations or processes described in this disclosure. In some embodiments, hardwired circuitry can be used in place of or in combination with the instructions to perform one or more operations or processes described in this disclosure. Additionally or optionally, the processor 720 can be configured to perform one or more operations or processes described in this disclosure. Thus, implementing the embodiments described in this disclosure is not limited to any specific combination of hardware circuitry and software.

[0145] Figure 7 The number and arrangement of the provided components are presented as examples. The device 700 may include more components, fewer components, different components, or components arranged differently than Figure 7 those shown. Additionally or optionally, a group of components (e.g., one or more components) of the device 700 can perform one or more functions described as being performed by another group of components of the device 700.

[0146] Figure 8 is a flowchart of an exemplary process 800 related to forming a semiconductor device using the chemical / mechanical planarization process described in this disclosure. In some embodiments, one or more semiconductor processing tools (e.g., one or more of the semiconductor processing tools 102 - 114) are used to perform Figure 8 one or more steps. Additionally or optionally, Figure 8One or more steps of can be performed using one or more components of apparatus 700, such as processor 720, memory 730, input element 740, output element 750, and / or communication element 760.

[0147] As Figure 8 shown, process 800 can include forming a masking layer (step 810). For example, a masking layer (e.g., masking layer 302) can be formed by one or more of semiconductor processing tools 102 - 114, as described in this disclosure.

[0148] Further, as Figure 8 shown, process 800 can include forming a conductive structure in an opening of the masking layer, the conductive structure having a portion extending above a top surface of the masking layer (step 820). For example, a conductive structure (e.g., conductive structure 218) can be formed in the opening of the masking layer by one or more of semiconductor processing tools 102 - 114, and the conductive structure has a portion (e.g., portion 304) extending above the top surface of the masking layer, as described in this disclosure.

[0149] Further, as Figure 8 shown, process 800 can include removing the portion extending above the top surface to form a substantially flat horizontal surface on the conductive structure (step 830). For example, the portion extending above the top surface can be removed by one or more of semiconductor processing tools 102 - 114 to form a substantially flat horizontal surface (e.g., substantially flat horizontal surface 224) on the conductive structure, as described in this disclosure.

[0150] Further, as Figure 8 shown, process 800 can include removing the masking layer (step 840). For example, the masking layer can be removed by one or more of semiconductor processing tools 102 - 114, as described in this disclosure.

[0151] Further, as Figure 8 shown, process 800 can include forming a dielectric layer over the conductive structure (step 850). For example, a dielectric layer (e.g., dielectric layer 216) can be formed over the conductive structure by one or more of semiconductor processing tools 102 - 114, as described in this disclosure.

[0152] Further, as Figure 8 shown, process 800 can include forming an interconnect structure that penetrates the dielectric layer and is connected to the substantially flat horizontal surface of the conductive structure (step 860). For example, an interconnect structure (e.g., interconnect structure 228) that penetrates the dielectric layer and is connected to the substantially flat horizontal surface of the dielectric layer can be formed by one or more of semiconductor processing tools 102 - 114, as described in this disclosure.

[0153] Process 800 may include other embodiments, such as the steps described hereinafter and / or any single embodiment or any combination of embodiments that incorporate one or more other processes described elsewhere in this disclosure.

[0154] In a first embodiment, forming a masking layer includes depositing a photoresist layer on a conductive layer and forming an opening using a lithography process.

[0155] In a second embodiment, alone or in combination with the first embodiment, forming a masking layer includes depositing a hard mask layer on a conductive layer and forming an opening using an etching process.

[0156] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming a conductive structure having a portion extending above a top surface of the masking layer includes forming a rounded footer (e.g., rounded footer 222), and the rounded footer laterally protrudes from a vertical sidewall of the conductive structure at a base of the conductive structure.

[0157] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, removing the portion extending above the top surface to form a substantially flat horizontal surface includes using a chemical / mechanical planarization process to remove the portion.

[0158] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, removing the portion to form a substantially flat horizontal surface includes removing a portion of the masking layer.

[0159] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, removing the portion to form a substantially flat horizontal surface includes removing the portion to form a sharp corner (e.g., sharp corner 226) with a vertical sidewall of the conductive structure.

[0160] Although Figure 8 illustrative steps of process 800 are shown, in some embodiments, process 800 includes more steps, fewer steps, different steps, or steps in a different arrangement than Figure 8 shown.

[0161] Figure 9 is a flowchart of an illustrative process 900 related to forming a semiconductor device using the chemical / mechanical planarization process described in this disclosure. In some embodiments, one or more steps of Figure 9 are performed using one or more semiconductor processing tools (e.g., one or more of semiconductor processing tools 102 - 114). Additionally or alternatively, Figure 9 one or more steps of

[0162] As Figure 9 shown, process 900 may include forming a conductive structure of a redistribution layer having different heights across a semiconductor die in an opening of a masking layer over the semiconductor die (step 910). For example, a conductive structure (e.g., conductive structure 218) of a redistribution layer having different heights across a semiconductor die (e.g., semiconductor device 200) may be formed in an opening of a masking layer (e.g., masking layer 302) over the semiconductor die by one or more of semiconductor processing tools 102-114, as described in this disclosure.

[0163] Further, as Figure 9 shown, process 900 may include removing a portion of at least one conductive structure to reduce the variation in different heights across the semiconductor die (step 920). For example, a portion of at least one conductive structure may be removed by one or more of semiconductor processing tools 102-114 to reduce the variation in different heights (e.g., height difference D3) across the semiconductor die, as described in this disclosure.

[0164] Further, as Figure 9 shown, process 900 may include removing the masking layer (step 930). For example, the masking layer may be removed by one or more of semiconductor processing tools 102-114, as described in this disclosure.

[0165] Further, as Figure 9 shown, process 900 may include forming a dielectric layer over the conductive structure (step 940). For example, a dielectric layer (e.g., dielectric layer 216) may be formed over the conductive structure by one or more of semiconductor processing tools 102-114, as described in this disclosure.

[0166] Further, as Figure 9 shown, process 900 may include forming an interconnect structure that penetrates the dielectric layer and connects to the conductive structure (step 950). An interconnect structure (e.g., interconnect structure 228) that penetrates the dielectric layer and connects to the conductive structure may be formed by one or more of semiconductor processing tools 102-114, as described in this disclosure.

[0167] Process 900 may include other embodiments, such as the steps described hereinafter and / or any single embodiment or any combination of embodiments that incorporate one or more other processes described elsewhere in this disclosure.

[0168] In a first embodiment, a portion of at least one conductive structure is removed to reduce the variation in different heights to improve the flatness of the conductive structure in the semiconductor die to less than about 100 nanometers.

[0169] In a second embodiment, alone or in combination with the first embodiment, removing a portion of at least one of the conductive structures to form at least one conductive structure having a nearly flat horizontal surface (e.g., nearly flat horizontal surface 224) that intersects a vertical sidewall (e.g., vertical sidewall 220), wherein the intersection of the nearly flat horizontal surface and the vertical sidewall forms a sharp corner (e.g., sharp corner 226) having an acute angle.

[0170] In a third embodiment, alone or in combination with one or more of the first and second embodiments, removing a portion of at least one of the conductive structures to form at least one conductive structure having a nearly flat horizontal surface (e.g., nearly flat horizontal surface 224) that intersects a vertical sidewall (e.g., vertical sidewall 220), wherein the intersection of the nearly flat horizontal surface and the vertical sidewall is a sharp corner (e.g., sharp corner 226) having an acute angle.

[0171] In a fourth embodiment, alone or in combination with one or more of the first to third embodiments, removing a portion of at least one of the conductive structures to reduce variations in different heights includes using a chemical / mechanical planarization process to remove the portion, and the chemical / mechanical planarization process uses a copper polishing liquid supplied on a polishing pad.

[0172] In a fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, using a chemical / mechanical planarization process to remove the portion includes stopping the chemical / mechanical planarization process on or in a masking layer.

[0173] In a sixth embodiment, alone or in combination with one or more of the first to fifth embodiments, using a chemical / mechanical planarization process to remove the portion includes stopping the chemical / mechanical planarization process above a masking layer.

[0174] Although Figure 9 illustrative steps of process 900 are shown, in some embodiments, process 900 includes Figure 9 more steps, fewer steps, different steps, or steps with different settings than those shown.

[0175] Some embodiments described in this disclosure provide a semiconductor device including a conductive structure formed as part of a copper RDL. Forming the conductive structure includes forming the conductive structure in a masking structure and performing a chemical / mechanical polishing (CMP) process to planarize the conductive structure. Forming the conductive structure in the masking structure enables the conductive structure to have a circular foot, and, relative to another semiconductor device using an aluminum copper RDL, the embodiments of this disclosure can reduce stress concentration in the semiconductor device. Additionally, planarizing the conductive structure reduces the rounded corner surfaces of the conductive structure that are joined to the interconnect structure to reduce the likelihood of bonding defects.

[0176] In this way, the quality and / or reliability of the semiconductor device is improved. By improving the quality and / or reliability of the semiconductor device, the amount of resources (e.g., raw materials, semiconductor manufacturing tools, labor, and / or computing resources) used to support the market that consumes the semiconductor device is reduced.

[0177] As described in more detail previously, some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a conductive structure of a redistribution layer. The conductive structure includes vertical sidewalls, a circular footer that laterally protrudes from the vertical sidewalls of the base of the conductive structure, and a nearly flat horizontal surface that forms a sharp corner with the vertical sidewalls of the top of the conductive structure opposite the base. The semiconductor device includes an interconnect structure connected to the conductive structure along the nearly flat horizontal surface. In some embodiments, the circular footer includes a curvature configured to reduce stress concentration at the base of the conductive structure. In some embodiments, the sharp corner has an angle including between 10 degrees and 170 degrees. In some embodiments, the width of the base of the circular footer is greater than the width of the nearly flat horizontal surface. In some embodiments, the vertical sidewalls include concave surfaces that extend inwardly toward the center of the conductive structure. In some embodiments, the semiconductor device further includes a dielectric layer that surrounds the conductive structure and is conformal with the concave surfaces and conformal with the circular footer.

[0178] As described in more detail previously, some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes forming a masking layer. The method includes forming a conductive structure in a plurality of openings of the masking layer, and the conductive structure has a portion extending above the top surface of the masking layer. The method includes removing the portion extending above the top surface to form a nearly flat horizontal surface on the conductive structure. The method includes removing the masking layer. The method includes forming a dielectric layer over the conductive structure. The method includes forming an interconnect structure that penetrates the dielectric layer and is connected to the nearly flat horizontal surface of the conductive structure. In some embodiments, forming the masking layer includes depositing a photoresist layer on the conductive layer; and forming openings using a lithography process. In some embodiments, forming the masking layer includes depositing a hard mask layer on the conductive layer; and forming openings using an etching process. In some embodiments, forming the conductive structure having a portion extending above the top surface of the masking layer includes forming a circular footing at the base of the conductive structure that laterally protrudes from a vertical sidewall of the conductive structure. In some embodiments, removing the portion extending above the top surface to form a nearly flat horizontal surface includes using a chemical / mechanical planarization step to remove the portion. In some embodiments, removing the portion to form a nearly flat horizontal surface includes removing a portion of the masking layer. In some embodiments, removing the portion to form a sharp corner with a vertical sidewall of the conductive structure. In some embodiments, removing the portion to form a nearly flat horizontal surface includes removing the portion to form a sharp corner with a vertical sidewall of the conductive structure.

[0179] As described in more detail above, some embodiments of the present disclosure provide a method of manufacturing a semiconductor device. The method includes forming a plurality of conductive structures across a semiconductor die and a redistribution layer having a plurality of different heights in a plurality of openings of a masking layer over the semiconductor die. The method includes removing a portion of at least one of the conductive structures to reduce a variation in different heights across the semiconductor die. The method includes removing the masking layer. The method includes forming a dielectric layer over the conductive structures. The method includes forming a plurality of interconnect structures that penetrate the dielectric layer and are connected to the conductive structures. In some embodiments, removing the portion of at least one of the conductive structures to reduce the variation in different heights improves the planarity of the conductive structures in the semiconductor die to be less than 100 nanometers. In some embodiments, removing the portion of at least one of the conductive structures forms at least one conductive structure having a nearly flat horizontal surface that intersects a sidewall in a vertical direction, wherein an intersection of the nearly flat horizontal surface and the sidewall in the vertical direction forms a sharp corner having an acute angle. In some embodiments, removing the portion of at least one of the conductive structures forms at least one conductive structure having a nearly flat horizontal surface that intersects a sidewall in a vertical direction, wherein an intersection of the nearly flat horizontal surface and a sidewall in the vertical direction is a sharp corner having an acute angle. In some embodiments, removing the portion of at least one of the conductive structures to reduce the variation in different heights includes using a chemical / mechanical planarization process to remove the portion, and the chemical / mechanical planarization process uses a copper polishing liquid supplied on a polishing pad. In some embodiments, using the chemical / mechanical planarization process to remove the portion includes stopping the chemical / mechanical planarization process on or in the masking layer. In some embodiments, using the chemical / mechanical planarization process to remove the portion includes stopping the chemical / mechanical planarization process above the masking layer.

[0180] As used in the present disclosure, the term "and / or" when used in conjunction with a plurality of features is intended to individually cover each of the plurality of features and any and all combinations of the plurality of features. For example, "A and / or B" covers "A and B", "A and not B", and "B and not A".

[0181] As used in the present disclosure, depending on the context, "meeting a threshold" may refer to a value greater than a threshold, greater than or equal to a threshold, less than a threshold, or less than or equal to a threshold.

[0182] The features of several embodiments are outlined above, so that those of ordinary skill in the art can better understand the various embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can simply use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described in the present disclosure. Those of ordinary skill in the art should also understand that such equivalent structures do not depart from the spirit and scope of the present disclosure, and those of ordinary skill in the art can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that, Comprising: A conductive structure of a rewiring layer, comprising: A vertical sidewall; A circular foot protruding laterally from the vertical sidewall of a base of the conductive structure; and An approximately flat horizontal surface forming a sharp angle with the vertical sidewall at a top of the conductive structure, the top of the conductive structure being relative to the base; and An interconnect structure connected to the conductive structure along the approximately flat horizontal surface.

2. The semiconductor device according to claim 1, wherein The circular foot includes a curvature configured to reduce stress concentration at the base of the conductive structure.

3. The semiconductor device according to claim 1, characterized in that, The vertical sidewall includes a concave surface extending inwards towards the center of the conductive structure.

4. A method of manufacturing a semiconductor device, characterized in that, Comprising: Forming a shielding layer; Forming a conductive structure in a plurality of openings of the shielding layer, wherein the conductive structure has a portion extending above a top surface of the shielding layer; Removing the portion extending above the top surface to form an approximately flat horizontal surface on the conductive structure; Removing the shielding layer; Forming a dielectric layer above the conductive structure; And Forming an interconnect structure penetrating the dielectric layer and connected to the approximately flat horizontal surface of the conductive structure.

5. The method according to claim 4, wherein Forming the conductive structure having the portion extending above the top surface of the shielding layer includes: Forming a circular foot protruding laterally from a vertical sidewall of a base of the conductive structure at the base of the conductive structure.

6. The method according to claim 4, wherein Removing the portion to form the approximately flat horizontal surface includes: Removing the portion to form a sharp angle with a vertical sidewall of the conductive structure.

7. A method of manufacturing a semiconductor device, characterized in that, Comprising: Forming a plurality of conductive structures in a plurality of openings of a shielding layer above a semiconductor die, spanning the semiconductor die and a plurality of redistribution layers having a plurality of different heights; Removing a portion of at least one of the plurality of conductive structures to reduce a variation of the plurality of different heights spanning the semiconductor die; Removing the shielding layer; Forming a dielectric layer above the plurality of conductive structures; And Forming a plurality of interconnect structures penetrating the dielectric layer and connected to the plurality of conductive structures.

8. The method according to claim 7, wherein Removing the portion of at least one of the plurality of conductive structures to reduce the variation of the plurality of different heights, so as to improve a planarity of the plurality of conductive structures in the semiconductor die to be less than 100 nanometers.

9. The method according to claim 7, characterized in that, Removing the portion of at least one of the plurality of conductive structures to form at least one conductive structure having an approximately flat horizontal surface intersecting a vertical sidewall, wherein an intersection of the approximately flat horizontal surface and the vertical sidewall forms a sharp angle with an acute angle.

10. The method according to claim 7, characterized in that, Removing the portion of at least one of the plurality of conductive structures to reduce the variation of the plurality of different heights includes: Using a chemical / mechanical planarization process to remove the portion, and the chemical / mechanical planarization process uses a copper polishing liquid supplied on a polishing pad.

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