Integrated chip and electronic equipment

Abstract

The invention relates to the technical field of semiconductor devices, and discloses an integrated chip and electronic equipment. The integrated chip comprises a first packaging substrate, a first packaging layer and a shielding layer. Wherein the shielding layer is connected to a first grounding structure in the first packaging substrate through the current limiting layer, the current limiting layer comprises a first material, and the first material can be in a low-resistance state when the current is small and can be in a high-resistance state when the current is large. Thus, the current limiting layer is arranged between the shielding layer and the first grounding structure, so that the current limiting layer and the first chip in the first packaging layer are connected in series, surface charges of the shielding layer can pass through the current limiting layer and then pass through the first grounding structure to enter the chip, and when too much charges are accumulated on the surface of the shielding layer to form a large current, the current limiting layer is prevented from falling off. The current limiting layer can be in a high-resistance state under large current, so that the current discharging speed can be slowed down by the current limiting layer, and the amount of discharged electric charges in unit time is reduced, so that the peak value of current flowing through the chip is small, and the chip is not damaged.

Description

Technical Field

[0001] This application relates to the technical field of semiconductor devices, and particularly to an integrated chip and an electronic device. Background Art

[0002] An integrated chip refers to a chip obtained by integrating multiple functional modules through semiconductor technology according to application requirements. Currently, there are mainly two methods for integrating multiple functional modules into one chip. The first method: fabricate multiple functional modules on the same chip, and then package the chip to obtain an integrated chip. The second method: fabricate multiple functional modules on multiple chips. For example, fabricate different functional modules on different chips, then fix the multiple chips to the same substrate through soldering or bonding processes, and finally package the whole to obtain an integrated chip.

[0003] Generally, a shielding layer is further provided outside the packaging layer of the integrated chip. The shielding layer is made of a conductive material and is grounded with the internal chip, which can prevent the internal chip from being interfered by the external electromagnetic field and avoid the interference caused by the internal chip radiating electromagnetic fields to external devices. However, during the assembly and testing processes of the integrated chip, friction and contact between the shielding layer and the outside will cause the shielding layer to carry static electricity. Especially for the above-mentioned integrated chip containing multiple chips, its size is relatively large, and the shielding layer is prone to accumulate a large amount of static charges. This means that during the assembly and testing processes of the integrated chip, if the pin pads of the integrated chip come into contact with other conductors, the static charges accumulated in the shielding layer will transfer under the drive of the potential difference, forming a large current. The large current will flow through the internal chip and then be discharged through the pins, and the current-carrying capacity of the internal circuit and devices in the chip is limited, which may cause damage to the internal chip. Summary of the Invention

[0004] To avoid the problem of chip damage caused by the large current formed due to the charge accumulation in the shielding layer, embodiments of this application provide an integrated chip and an electronic device including the integrated chip.

[0005] In a first aspect, an embodiment of the present application provides an integrated chip, including: a first packaging substrate and a first packaging layer stacked on each other, and at least one first chip wrapped by the first packaging layer and disposed on the first packaging substrate, wherein the first packaging substrate includes a first grounding structure exposed on its surface, and at least one first chip is directly connected to the first grounding structure respectively, and a shielding layer disposed outside the first packaging layer for shielding electromagnetic interference, wherein the shielding layer is connected to the first grounding structure through a current limiting layer, the current limiting layer includes a first material, corresponding to a first current density of the current flowing through the current limiting layer, the first material exhibits a first impedance, and the product of the first impedance and the perimeter of the current limiting layer is a first value; corresponding to a second current density of the current flowing through the current limiting layer, the first material exhibits a second impedance, and the product of the second impedance and the perimeter of the current limiting layer is a second value; wherein the first current density is greater than the second current density, and the first value is greater than the second value.

[0006] In the above solution, a current limiting layer is disposed between the shielding layer and the first grounding structure, so that a series relationship is formed between the current limiting layer and the first chip, and the surface charge of the shielding layer can first pass through the current limiting layer and then enter the chip via the first grounding structure. Moreover, the current limiting layer is made of a first material, and the impedance of the first material is affected by the current. For example, when the current density flowing through the current limiting layer is the first current density, the first material can exhibit a first impedance, and the product of the first impedance and the perimeter of the current limiting layer is a first value. When the current density flowing through the current limiting layer is the second current density, the first material can exhibit a second impedance, and the product of the second impedance and the perimeter of the current limiting layer is a second value. Wherein, the first current density is greater than the second current density, and the first value is greater than the second value. That is to say, the first material can be in a low impedance state when the current is small and in a high impedance state when the current is large. In this way, when too much charge accumulates on the surface of the shielding layer to form a large current, since the current limiting layer can be in a high impedance state under a large current, the current limiting layer can slow down the current discharge speed and reduce the amount of charge discharged per unit time, so that the peak value of the current flowing through the chip is small enough not to damage the chip.

[0007] In some embodiments of the above first aspect, the first current density is greater than 1 A / cm, and the first value is greater than 10 Ω·cm.

[0008] In some embodiments of the above first aspect, the second current density is less than 0.1 A / cm, and the second value is less than 1 Ω·cm.

[0009] It can be understood that since the grounding structure is generally arranged along the edge or perimeter of the integrated chip, the current-limiting layer between the shielding layer and the grounding structure can also be arranged along the edge or perimeter of the integrated chip. Moreover, for integrated chips of different sizes, that is, integrated chips with different perimeters, the tolerance for the same magnitude of current is different. Therefore, when determining the magnitude of the current flowing through the current-limiting layer, it is necessary to consider the perimeter of the current-limiting layer or the perimeter of the integrated chip, that is, the current density can be used to measure the magnitude of the current, and the current density is the amount of current per unit length.

[0010] Here, specific values of the first current density, the first data, the second current density, and the second value are exemplarily given. In practical applications, the first current density, the first data, the second current density, and the second value can also be other values.

[0011] In some embodiments of the first aspect described above, the ratio of the first impedance to the second impedance is greater than 10.

[0012] It can be understood that the impedance of the first material can vary significantly under different currents to simultaneously adapt to large-current and small-current scenarios.

[0013] It can be understood that the impedance, resistance, and resistance value mentioned in this application are different expressions of the same physical quantity.

[0014] In some embodiments of the first aspect described above, the first material has a first volt-ampere characteristic curve, and the ratio of current to voltage in the first volt-ampere characteristic curve decreases as the current increases.

[0015] It can be understood that the first material needs to satisfy the condition of being in a low-resistance state when the current is small and in a high-resistance state when the current is large. Thus, the ratio of current to voltage in the first volt-ampere characteristic curve of the first material, that is, the reciprocal of the resistance, decreases as the current increases.

[0016] In some embodiments of the first aspect described above, along the width direction of the integrated chip, the width of the first encapsulation substrate is greater than the width of the first encapsulation layer; the first grounding structure is exposed along the edge of the upper surface of the first encapsulation substrate facing the first encapsulation layer.

[0017] In some embodiments of the first aspect described above, the current-limiting layer is formed on the surface of the first grounding structure; the shielding layer includes a first top portion and a first sidewall surrounding the edge of the first top portion, and the first sidewall extends along the thickness direction of the integrated chip relative to the first top portion to the upper surface of the first encapsulation substrate and contacts the current-limiting layer; the first grounding structure, the current-limiting layer, and the first sidewall are stacked in sequence along the thickness direction.

[0018] It can be understood that according to the different internal structures of the encapsulation substrate, the first grounding structure can extend from the inside of the encapsulation substrate to the upper surface of the encapsulation substrate, that is, the first grounding structure can be exposed on the upper surface, so that the current limiting layer can be arranged on the surface of the first grounding structure, and then a structure in which the first grounding structure, the current limiting layer and the first side wall of the shielding layer are stacked in sequence along the thickness direction is formed.

[0019] In some embodiments of the above first aspect, along the width direction of the integrated chip, the width of the first encapsulation substrate is equal to the width of the first encapsulation layer; the first grounding structure is exposed from the side of the first encapsulation substrate.

[0020] It can be understood that according to the different internal structures of the encapsulation substrate, the first grounding structure can also extend from the inside of the encapsulation substrate to the side of the encapsulation substrate.

[0021] In some embodiments of the above first aspect, the current limiting layer includes a second top and a second side wall surrounding the edge of the second top. The second side wall extends along the thickness direction of the integrated chip to the side of the first encapsulation substrate relative to the second top and is connected to the lower surface of the first encapsulation substrate facing away from the first encapsulation layer; the shielding layer is arranged outside the current limiting layer. The shielding layer includes a third top and a third side wall surrounding the edge of the third top. The third side wall extends along the thickness direction of the integrated chip relative to the third top and is flush with the bottom connected to the second side wall and the lower surface of the first encapsulation substrate; the first grounding structure, the second side wall and the third side wall are connected in sequence along the width direction of the integrated chip.

[0022] It can be understood that when the first grounding structure extends from the inside of the encapsulation substrate to the side of the encapsulation substrate, the current limiting layer needs to be provided with a second side wall to contact the first grounding structure through the second side wall. Moreover, the shielding layer and the current limiting layer adopt a similar structure to form a structure in which the first grounding structure, the second side wall and the third side wall are connected in sequence along the width direction of the integrated chip.

[0023] In some embodiments of the above first aspect, it further includes: a second encapsulation substrate and a second encapsulation layer stacked on each other, and at least one second chip wrapped by the second encapsulation layer and arranged on the second encapsulation substrate; wherein, the second encapsulation substrate, the second encapsulation layer and at least one second chip constitute a first encapsulation part, the first encapsulation substrate, the first encapsulation layer and at least one first chip constitute a second encapsulation part, and the first encapsulation part and the second encapsulation part are stacked up and down to form a double-layer encapsulation structure.

[0024] It can be understood that the integrated chip can be in the form of single-sided single-layer packaging, and the integrated chip includes a first packaging substrate and a first packaging layer. The integrated chip can also be in the form of single-sided double-layer packaging. In this case, in addition to the first packaging substrate and the first packaging layer, the integrated chip further includes a second packaging substrate and a second packaging layer. The first packaging substrate, the first packaging layer, and the first chip belong to the first packaging part, and the second packaging substrate, the second packaging layer, and the second chip belong to the second packaging part.

[0025] In some embodiments of the first aspect described above, a second grounding structure is provided inside the second packaging substrate. At least one second chip is directly connected to the second grounding structure respectively. The second grounding structure penetrates the second packaging substrate along the thickness direction of the integrated chip and is connected to the first grounding structure through the conductive material in the first packaging layer.

[0026] It can be understood that the connection manner between the second grounding structure and the second chip is the same as that between the first grounding structure and the first chip. Moreover, the second grounding structure also passes through the first packaging layer and is connected to the first grounding structure.

[0027] In some embodiments of the first aspect described above, it further includes: at least one third chip disposed on the first packaging substrate, and a second packaging layer that wraps the at least one third chip; wherein, the third chip and the first chip are respectively disposed on two opposite surfaces of the first packaging substrate along the thickness direction of the integrated chip, and the first packaging layer and the second packaging layer are respectively formed on both sides of the first packaging substrate along the thickness direction, forming a double-sided packaging structure.

[0028] It can be understood that the integrated chip can also be in the form of double-sided single-layer packaging. That is, chips are provided on both surfaces of the first packaging substrate along the opposite directions of the thickness direction of the integrated chip. Therefore, it is necessary to package the chips on both surfaces.

[0029] In some embodiments of the first aspect described above, at least one conductive member is provided inside the second packaging layer. The conductive member penetrates the second packaging layer along the thickness direction; the conductive member is used to connect the metal interconnection structure in the first packaging substrate to the pin pad at the bottom of the second packaging layer facing away from the first packaging layer.

[0030] Among them, the conductive member can be a copper ball or a copper column. In other embodiments, the conductive member can also be made of other metal materials (such as tin, copper) and have other shapes (such as a cubic column).

[0031] In the first aspect described above, the shielding layer is an integral part of the integrated chip. The manufacturing of the shielding layer is part of the preparation of the integrated chip. For the prepared integrated chip, the outermost layer is the shielding layer. That is, the shielding layer constitutes the appearance of the integrated chip.

[0032] It can be understood that the shielding layer can be a separate component. For example, a shielding device is separately prepared and formed, and then assembled with the packaged integrated chip, which can achieve a shielding effect after assembly.

[0033] In a second aspect, embodiments of the present application provide a shielding device for assembling with an integrated chip to shield electromagnetic interference generated or received by the integrated chip. The shielding device includes a shielding layer and a current-limiting layer provided on the inner wall of the shielding layer. The current-limiting layer includes a first material. Corresponding to a first current density of the current flowing through the current-limiting layer, the first material exhibits a first impedance, and the product of the first impedance and the perimeter of the current-limiting layer is a first value. Corresponding to a second current density of the current flowing through the current-limiting layer, the first material exhibits a second impedance, and the product of the second impedance and the perimeter of the current-limiting layer is a second value. Among them, the first current density is greater than the second current density, and the first value is greater than the second value.

[0034] It can be understood that a current-limiting layer is provided inside the shielding device, which can achieve the same effect as the first aspect after being assembled with the integrated chip, and will not be elaborated here.

[0035] In some embodiments of the first aspect above, the first current density is greater than 1 A / cm, and the first value is greater than 10 Ω·cm.

[0036] In some embodiments of the first aspect above, the second current density is less than 0.1 A / cm, and the second value is less than 1 Ω·cm.

[0037] In some embodiments of the first aspect above, the ratio of the first impedance to the second impedance is greater than 10.

[0038] In some embodiments of the first aspect above, the first material has a first volt-ampere characteristic curve, and the ratio of current to voltage in the first volt-ampere characteristic curve decreases as the current increases.

[0039] In a third aspect, embodiments of the present application provide a chip component, including the shielding device of the second aspect above and an integrated chip, and the shielding device covers the outside of the integrated chip.

[0040] In a fourth aspect, embodiments of the present application provide an electronic device, including the integrated chip of the first aspect above and a circuit board, and the integrated chip is disposed on the circuit board.

[0041] In a fifth aspect, embodiments of the present application provide an electronic device, including the chip component of the third aspect above and a circuit board, and the chip component is disposed on the circuit board. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 is a schematic diagram of a mobile phone 10 provided by an embodiment of the present application;

[0043] Figure 2A It is a schematic structural diagram of an integrated chip 30 provided by an embodiment of the present application;

[0044] Figure 2B It is a cross-sectional view of an integrated chip 30 along the A-A' direction provided by an embodiment of the present application;

[0045] Figure 2C It is a schematic diagram of an integrated chip 30 with static electricity provided by an embodiment of the present application;

[0046] Figure 2D It is a schematic diagram of a large current discharge path in an integrated chip 30 provided by an embodiment of the present application;

[0047] Figure 3 It is a schematic diagram of a typical CDM discharge scenario provided by an embodiment of the present application;

[0048] Figure 4 It is an equivalent circuit diagram when an integrated chip 30 undergoes CDM discharge provided by an embodiment of the present application;

[0049] Figure 5A It is a schematic diagram of an integrated chip 30' provided by an embodiment of the present application;

[0050] Figure 5B It is an equivalent circuit diagram when an integrated chip 30' undergoes CDM discharge provided by an embodiment of the present application;

[0051] Figure 6 It is a schematic diagram of an IV curve provided by an embodiment of the present application;

[0052] Figure 7A It is a cross-sectional view of an integrated chip 50 provided by an embodiment of the present application;

[0053] Figure 7B It is a top view of an integrated chip 50 provided by an embodiment of the present application;

[0054] Figure 7C It is an equivalent circuit diagram when an integrated chip 50 undergoes CDM discharge provided by an embodiment of the present application;

[0055] Figure 8 It is a comparison diagram of simulation waveforms of discharge currents provided by an embodiment of the present application;

[0056] Figure 9 It is a cross-sectional view of an integrated chip 50' provided by an embodiment of the present application;

[0057] Figure 10 It is a cross-sectional view of an integrated chip 50'' provided by an embodiment of the present application;

[0058] Figure 11It is a cross-sectional view of an integrated chip 50”’ in a bilateral single-layer packaging form provided by an embodiment of the present application. Detailed implementation manners

[0059] The following details the specific implementation manners of the present application in conjunction with the accompanying drawings.

[0060] First, the integrated chip of the embodiment of the present application may include one or more chips. The one or more chips can be used to implement at least one of the data processing function, image processing function, communication function, and display function of the electronic device including the integrated chip. It can be understood that the electronic device can be any electronic device including an integrated chip such as a mobile phone, a computer, a virtual reality (VR) device, a tablet computer, a wearable device, an augmented reality (AR) device, a laptop computer, and an automobile. The form of the electronic device is not specifically limited in the embodiment of the present application.

[0061] Taking the electronic device as a mobile phone as an example. Figure 1 It is a schematic diagram of a mobile phone 10 provided by an embodiment of the present application. As Figure 1 shown, the mobile phone 10 includes a circuit board 20, and an integrated chip 30 is assembled on the circuit board 20. The integrated chip 30 is used to implement at least one of the above-mentioned data processing function, image processing function, communication function, and display function in the mobile phone 10.

[0062] Exemplarily, the integrated chip 30 can be a radio frequency front-end chip for implementing the communication function of the mobile phone 10. Specifically, the radio frequency front-end chip can include a chip serving as at least one of the following functional devices: power amplifier (PA), low-noise amplifier (LNA), switch, filter, integrated passive device (IPD). Exemplarily, the integrated chip 30 can also be a system-on-chip (SoC) for implementing the data processing function of the mobile phone 10. Specifically, the SoC can include a chip serving as at least one of the following functional units: central processing unit (CPU), graphics processing unit (GPU), memory (RAM), flash memory, neural processing unit (NPU), baseband unit (BM).

[0063] As mentioned above, if the pin pads of the integrated chip come into contact with other conductors, the static charges accumulated on the shielding layer will transfer under the drive of the potential difference, thus forming a large current. The following combines Figures 2A - 2D to detail the formation process of the large current. It should be noted that in this article, each Figure X X direction represents the width direction of the integrated chip, the Y direction represents the length direction of the integrated chip, and the Z direction represents the thickness direction or height direction of the integrated chip.

[0064] Figure 2A FIG. 2 is a schematic structural diagram of an integrated chip 30 provided by an embodiment of the present application. Figure 2B FIG. 3 is a cross-sectional view of the integrated chip 30 along the A-A' direction. Figure 2C FIG. 4 is a schematic diagram of the integrated chip 30 with static electricity. Figure 2D FIG. 5 is a schematic diagram of a large current discharge path in the integrated chip 30.

[0065] For ease of subsequent description, before introducing the structure of the integrated chip 30, the package substrate and the assembly substrate are first defined. In the present application, the substrate inside the integrated chip 30 is referred to as the package substrate. The package substrate can support multiple chips and realize the interconnection between multiple chips. For example, Figure 2A and 2B as shown in FIGS. 5 and 6, the package substrate 5 is used to support chips 1 to 3. In the present application, the substrate outside the integrated chip 30 is referred to as the assembly substrate. For example, the assembly substrate can support multiple integrated chips and realize the interconnection between multiple integrated chips. As Figure 3 shown in FIG. 7, the assembly substrate 40 is used to support the integrated chip 30.

[0066] Combined with Figure 2A and Figure 2B , the integrated chip 30 includes chips 1, 2, 3, pin pads 4, and a package substrate 5. Among them, chips 1, 2, and 3 can be fixed on the upper surface of the package substrate 5 through soldering or bonding processes and are connected through the metal interconnect lines 6 inside the package substrate 5.

[0067] The pin pads 4 are arranged on the lower surface of the package substrate 5. That is to say, the pin pads 4 and chips 1 to 3 are respectively arranged on two opposite surfaces of the package substrate 5 along the Z direction. Among them, the number of pin pads 4 is usually multiple. Multiple pin pads 4 can be arranged along the edges around the integrated chip 30. For example, 8 pin pads 4 are arranged on each edge of the rectangular integrated chip 30. The pin pads 4 at different positions can be respectively connected to chips 1 to 3 through the metal interconnect lines 6. For example, Figure 2B the pin pad 4 in the lower left corner can be connected to chip 1 through the metal interconnect line 6. The pin pads 4 can be used for soldering with the assembly substrate and realizing electrical connection with other chips on the assembly substrate through the metal traces in the assembly substrate.

[0068] It can be understood that the encapsulated integrated chip 30 has a packaging layer 7. The packaging layer 7 is made of a plastic encapsulation material, which fills the gaps between chips 1 to 3 and isolates chips 1 to 3 from the outside. A shielding layer 8 is provided on the outer side of the packaging layer 7 (i.e., the side of the packaging layer 7 facing away from chips 1 to 3). The shielding layer 8 is made of a conductive material and is connected to a ground wire 6-1 arranged along the edge of the packaging substrate 5. This ground wire 6-1 is the common ground wire for chips 1 to 3. In this way, the shielding layer 8 and chips 1 to 3 are grounded. When an external electromagnetic field radiates onto the surface of the shielding layer 8, since the shielding layer 8 has conductivity, it can absorb or reflect the electromagnetic field, thereby preventing the external electromagnetic field from entering the packaging layer 7 and interfering with chips 1 to 3 inside the packaging layer 7. Similarly, the shielding layer 8 can also absorb the electromagnetic field radiated by chips 1 to 3 and prevent chips 1 to 3 from interfering with external circuits. It should be noted that Figure 2B the ground wire directly connected to chip 2 is not in Figure 2B the cross-section shown, so Figure 2B it is not shown in

[0069] However, during the assembly and testing of the integrated chip 30, as Figure 2C shown, the shielding layer 8, as the largest good conductor in chip 1, will store a relatively large amount of static charges. Also, a small amount of static charges will be stored on the metal interconnections 6 inside the integrated chip 30. If the pin pads 4 of the integrated chip 30 come into contact with other conductors, the static charges on the shielding layer 8 and the metal interconnections 6 will rapidly transfer driven by the potential difference and discharge through the pin pads in contact with other conductors.

[0070] For example Figure 2D as shown, when the pin pad 4 connected to chip 1 in the lower left corner comes into contact with other conductors, the surface charges of the shielding layer 8 will discharge to the other conductor in the direction indicated by the arrow. Specifically, the surface charges of the shielding layer 8 first flow from the top surface of the shielding layer 8 to the side surface of the shielding layer 8, then enter chip 1 through the ground wire 6-1 directly connected to chip 1, then flow to the pin pad 4 through the metal interconnection 6 between chip 1 and the pin pad 4, and finally discharge from the pin pad 4. Since the current-carrying capacity of the internal circuits and devices in chip 1 is limited, the current formed by the surface charges of the shielding layer 8 is very likely to cause damage to the chip.

[0071] The above discharge process of the surface charges of the shielding layer 8 can also be understood as the charged device model (CDM) in the standard electrostatic discharge (ESD) model. CDM is a model established based on the fact that when a charged device discharges to the ground through its pins, device failure occurs. As Figure 3 shown, Figure 3It is a typical CDM discharge scenario, taking the soldering of the integrated chip 30 and the assembly substrate 40 as an example. First, the robotic arm 01 sucks the integrated chip 30 through the nozzle 02, moves the integrated chip 30 above the assembly substrate 40, so that the positions of the respective pin pads 4 on the integrated chip 30 correspond one by one to the positions of the respective pads 401 on the assembly substrate 40. Then, the robotic arm 01 lowers the integrated chip 30 onto the assembly substrate 40. When the pin pads 4 contact the pads 401, the surface charges of the shielding layer 8 will transfer and be discharged to the assembly substrate 40 through the pin pads 4. Here, the pad 401 is an example of the above-mentioned other conductors.

[0072] Figure 4 It is the equivalent circuit diagram during the CDM discharge of the integrated chip 30 provided by this application. As Figure 4 shown, Cs represents the capacitance of the shielding layer 8, Cp represents other parasitic capacitances inside the integrated chip 30, M1 represents the equivalent circuit of chip 1, K1 represents the discharge switch, Ls represents the parasitic inductance in the discharge path, and Rs represents the parasitic resistance in the discharge path. When the pin pad 4 corresponding to chip 1 touches other conductors, a discharge path is formed between the shielding layer 8 and the ground, the discharge switch K1 closes, and the charges stored in the capacitor Cs and the capacitor Cp are discharged to the ground along the direction shown by the arrow via M1 and other conductors in the discharge path. It can be understood that when any pin pad 4 touches other conductors, the charges on the surface of the shielding layer 8 will pass through the chip connected to the pin pad 4. When only one pin pad 4 touches other conductors, all the charges on the surface of the shielding layer 8 will pass through the chip connected to the pin pad 4. Therefore, if the pin pad 4 corresponding to chip 2 also contacts other conductors, then Figure 4 M2 (shown in the dotted box) can also be connected in series between M1 and Ls in

[0073] It can be understood that the magnitude of the current formed by the charge transfer is related to the chip size and the magnitude of the potential difference. Generally, the maximum peak discharge current can reach several amperes (A) or even dozens of amperes, which is sufficient to cause damage to the chip.

[0074] In some embodiments, as Figure 5A shown, Figure 5A It is a schematic diagram of an integrated chip 30'. The difference between this integrated chip 30' and the integrated chip 30 is that an ESD device 9 is added on the package substrate 5. One end of the ESD device 9 is connected to the ground wire 6-1, and the other end is directly connected to the pin pad 4 through the added metal interconnection line 6-2. In this way, the ESD device 9 and chip 1 form a parallel relationship, so that most of the charges on the surface of the shielding layer 8 can be discharged to the pin pad 4 through the ESD device 9. As Figure 5AAs shown by the arrow in the figure, for the direction of charge flow, most of the charges on the surface of the shielding layer 8 flow directly to the pin pad 4 through the ground wire 6-1 and the ESD device 9, and a small part of the charges still flow to the pin pad 4 through the chip 1. Here, the ESD device 9 can be any one of components such as a transient voltage suppressor (TVS), a diode, a varistor, a capacitor, etc.

[0075] Figure 5B is the equivalent circuit diagram during the CDM discharge of the integrated chip 30', where M3 represents the ESD device 9, and M3 is connected in parallel with M1. As Figure 5B shown, when the CDM discharge occurs in the integrated chip 30', the ESD device 9 connected in parallel with the chip 1 can shunt most of the charges, thereby avoiding a large current from entering the chip 1 and causing damage. However, for the integrated chip 30', an ESD device 9 corresponding to each pin pad 4 needs to be set, which leads to an increase in the number of ESD devices 9, resulting in an increase in the overall package size and cost. Moreover, the parallel ESD devices 9 will inevitably introduce some parasitic effects (such as parasitic capacitance, leakage current, etc.), and these parasitic effects will affect the overall performance indicators of the integrated chip 30'.

[0076] To solve the above problems, an embodiment of the present application provides a chip. On the basis of the chip structure as Figure 2A shown, by setting a current limiting layer between the shielding layer and the ground wire, a series relationship is formed between the current limiting layer and the chip, so that the charges on the surface of the shielding layer can first pass through the current limiting layer and then enter the chip through the ground wire. Among them, the current limiting layer includes a first material. When the current density flowing through the current limiting layer is the first current density, the first material can exhibit a first impedance, and the product of the first impedance and the perimeter of the current limiting layer is a first value. When the current density flowing through the current limiting layer is the second current density, the first material can exhibit a second impedance, and the product of the second impedance and the perimeter of the current limiting layer is a second value. Among them, the first current density is greater than the second current density, and the first value is greater than the second value. That is to say, the first material can be in a low-resistance state when the current is small and in a high-resistance state when the current is large. In this way, even if a large current is formed by the charges on the surface of the shielding layer, since the current limiting layer can be in a high-resistance state under a large current, the current limiting layer can slow down the current discharge speed, reduce the amount of charge discharged per unit time, and make the peak value of the current flowing through the chip smaller so as not to damage the chip.

[0077] It can be understood that in some embodiments, the ratio of current to voltage in the volt-ampere characteristic curve (abbreviated as the IV curve) of the first material decreases as the current increases, or in other words, the resistance of the first material increases as the current increases. Exemplarily, Figure 6 is an example of an IV curve of the first material, where the horizontal axis represents voltage, the vertical axis represents current, and the slope of the curve is the reciprocal of the resistance.Figure 6 It can be seen that when the current (an example of the second current) at point A is small, the slope of the curve is large, that is, the resistance is low. At this time, the first material exhibits the second impedance, or a low-resistance state; when the current (an example of the first current) at point B is large, the slope of the curve is small, that is, the resistance is high. At this time, the first material exhibits the first impedance, or a high-resistance state.

[0078] It can be understood that compared with Figure 5A the method in which an ESD device 9 corresponding to each pin pad 4 needs to be provided inside the encapsulation layer 7, for the chip of the embodiment of the present application, only a thin current-limiting layer needs to be formed on the surface of the ground wire 6-1 exposed along the four peripheral edges of the encapsulation substrate 5 first, and then the shielding layer 8 is formed, so that the current-limiting layer can be arranged between the shielding layer and the ground wire. And, since each chip is connected to the ground wire 6-1, in this way, no matter which pin pad corresponding to the chip discharges the charge on the surface of the shielding layer, the current formed by the charge on the surface of the shielding layer will first pass through the current-limiting layer and then enter the corresponding chip through the ground wire, so that the peak value of the current entering the chip becomes smaller under the action of the current-limiting layer and will not damage the chip. In this way, there is no need to provide an ESD device for each pin pad to shunt, no parasitic effect will be introduced, and the overall encapsulation size will not be increased.

[0079] It can be understood that the current-limiting layer is in a low-resistance state when the current is small. In this way, the resistance between the shielding layer and the ground wire is low, and the original shielding effect of the shielding layer will not be affected.

[0080] It can be understood that the ground wire can extend from the inside of the encapsulation substrate to the surface of the encapsulation substrate. Among them, the surface can refer to the upper surface of the encapsulation substrate facing the encapsulation layer, or the side surface of the encapsulation substrate. The ground wire is exposed on the upper surface or the side surface of the encapsulation substrate to facilitate contact with the current-limiting layer.

[0081] Corresponding to the two ways in which the ground wire can be exposed on the upper surface or the side surface of the encapsulation substrate, the position and setting method of the current-limiting layer are different. Therefore, the chip including the current-limiting layer can also have various forms. Several specific embodiments of the chip including the current-limiting layer are introduced below.

[0082] Several specific embodiments of the chip including the current-limiting layer are introduced below. In the integrated chip 50 provided by the embodiment of the present application, the ground wire extends from the inside of the encapsulation substrate to the upper surface of the encapsulation substrate.

[0083] Figure 7A is a cross-sectional schematic diagram of the integrated chip 50 provided by the embodiment of the present application. The integrated chip 50 includes an encapsulation substrate 5 (an example of the first encapsulation substrate) and an encapsulation layer 7 (an example of the first encapsulation layer) stacked on each other, chips 1 (an example of the first chip), chip 2 (another example of the first chip), chip 3 (Figure 7A a shielding layer 8 disposed outside the encapsulation layer 7 (not shown);

[0084] Wherein, along the X direction, the width of the encapsulation layer 7 is smaller than the width of the encapsulation substrate 5. The encapsulation substrate 5 includes a ground wire 6-1 exposed on its upper surface.

[0085] As Figure 7B shown, Figure 7B is a top view of the integrated chip 50 before forming the encapsulation layer 7 and the shielding layer 8. The ground wire 6-1 (an example of the first grounding structure) is exposed along the edge of the upper surface of the encapsulation substrate 5. Near the chips 1 to 3, the ground wire 6-1 can extend from the edge of the encapsulation substrate 5 to the bottom of the chips 1 to 3 to achieve common grounding of the chips 1 to 3. For example, Figure 7A shown, near the chip 1, the ground wire 6-1 can extend from the edge of the encapsulation substrate 5 to the bottom of the chip 1. Similarly, from other cross-sections, the ground wire 6-1 extending from the bottom of the chip 2 or chip 3 to the edge of the encapsulation substrate 5 can also be seen.

[0086] As Figure 7A and Figure 7B shown, the integrated chip 50 includes a current-limiting layer 501, and the current-limiting layer 501 can be formed on the surface of the ground wire 6-1 exposed on the upper surface of the encapsulation substrate 5, and is located between the shielding layer 8 and the ground wire 6-1.

[0087] The shielding layer 8 includes a top 8-1 and side walls 8-2, and the side walls 8-2 surround the four peripheral edges of the top 8-1 and extend towards the encapsulation substrate 5 along the Z-axis direction relative to the top 8-1 to contact the current-limiting layer 501 formed on the surface of the ground wire 6-1.

[0088] In some embodiments, the first material of the current-limiting layer 501 includes but is not limited to organic materials such as doped polyaniline, and inorganic materials such as doped ceramic materials. Exemplarily, the first material of the current-limiting layer 501 can be polyaniline doped with H2SO4 or HClO4, or Bi2O3 ceramic material doped with SrO.

[0089] In the preparation process of the integrated chip 50, the current-limiting layer 501 can be formed by methods such as spraying, physical vapor deposition (PVD), or chemical vapor deposition (CVD). For example, when the first material for forming the current-limiting layer 501 is an organic colloid, it can be achieved by dispensing, spraying, spin-coating and then patterning. When the first material for forming the current-limiting layer 501 is in other forms, it can be achieved by PVD or CVD deposition and then patterning. After the current-limiting layer 501 is fabricated, the shielding layer 8 is then welded to the surface of the current-limiting layer 501.

[0090] As described above, in the IV curve of the first material of the current limiting layer 501, the ratio of current to voltage decreases as the current increases. That is, the first material has the characteristic that its resistance is lower when the current is smaller and higher when the current is larger. Generally, the IV curve of the material can be measured to determine whether the material satisfies the above characteristics. The IV curve of the material that satisfies the above characteristics will exhibit Figure 6 the trend shown, that is, the slope of the IV curve (the reciprocal of the resistance) decreases as the current or voltage increases. It can be understood that Figure 6 the specific values of the horizontal and vertical coordinates shown need to be measured according to the actual material, Figure 6 and it is only an exemplary illustration of a trend. The horizontal and vertical coordinate values of the IV curves of different materials can be different.

[0091] Referring to Figure 7A and 7B shown, the current limiting layer 501 can be arranged along the edge of the integrated chip 50. Thus, the perimeter of the current limiting layer 501 is basically the same as the perimeter of the integrated chip 50. It can be understood that the magnitude of the current flowing through the current limiting layer 501 needs to be judged in combination with the perimeter of the current limiting layer 501 or rather the perimeter of the integrated chip 50. In the embodiments of the present application, the current density is used to measure the magnitude of the current, and the current density is the amount of current per unit length.

[0092] In some embodiments, when the current density flowing through the current limiting layer 501 is greater than 1 A / cm, the product of the perimeter of the current limiting layer 501 and the resistance of the current limiting layer 501 should be greater than 10 Ω·cm. That is, the conductance of the current limiting layer 501 / the perimeter of the current limiting layer 501 should be greater than 1 S / cm; where the conductance is the reciprocal of the resistance. The current limiting layer 501 that satisfies the above requirements can be in a high-resistance state in a large-current scenario, playing a role in slowing down the current discharge speed and reducing the current peak value flowing through chips 1 to 3.

[0093] Correspondingly, in some embodiments, when the current density flowing through the current limiting layer 501 is less than 0.1 A / cm, the product of the perimeter of the current limiting layer 501 and the resistance of the current limiting layer 501 should be less than 1 Ω·cm. That is, the conductance of the current limiting layer 501 / the perimeter of the current limiting layer 501 should be greater than 1 S / cm. The current limiting layer 501 that satisfies this requirement can be in a low-resistance state at low currents. In this way, the resistance between the shielding layer 8 and the ground wire 6-1 is relatively low, and the external electromagnetic field absorbed by the shielding layer 8 or the electromagnetic field radiated outward by chips 1 to 3 can still be smoothly released through the ground wire 6-1, and the shielding effect of the shielding layer 8 is not affected.

[0094] In some embodiments, the ratio of the resistance of the current limiting layer 501 in the high resistance state to its resistance in the low resistance state is greater than 10. In this way, when electromagnetic fields need to be shielded, the current limiting layer 501 can ensure the shielding effect of the shielding layer 8 with a lower resistance; when facing CDM risks, the current limiting layer 501 can avoid chip damage with a higher resistance.

[0095] Figure 7C FIG. 4 is an equivalent circuit diagram of the integrated chip 50 during CDM discharge. Here, M4 represents the equivalent resistance of the current limiting layer 501, and M4 is connected in series with M1. When the integrated chip 50 undergoes CDM discharge, the charge stored in the capacitor Cs flows along the direction indicated by the arrow, first passing through M4, then through M1 and other conductors in the discharge path, and then discharging to the ground. Since the formation of large currents is mainly due to the shielding layer 8 storing excessive charges, ensuring that the capacitor Cs can release charges through the current limiting layer 501 can avoid damage to the chip 1.

[0096] Figure 8 FIG. 5 is a comparison diagram of the simulation waveforms of the discharge currents of an integrated chip 50 and an integrated chip 30 provided in an embodiment of the present application under the same CDM voltage level. Here, the same CDM voltage level can be understood as that the amount of charge stored on the surface of the shielding layer 8 in the integrated chip 50 is the same as the amount of charge stored on the surface of the shielding layer 8 in the integrated chip 30, and the integrated chip 50 and the integrated chip 30 discharge charges outward through the same pin pads (for example, Figure 2B and Figure 7A the pin pad 4 connected to the chip 1 at the lower left corner shown). As Figure 8 shown, the dashed line represents the discharge curve corresponding to the integrated chip 30, and the solid line represents the discharge curve of the integrated chip 50. When the integrated chip 30 undergoes CDM discharge, the charge is released at a relatively fast speed, and the peak value of the maximum discharge current exceeds 4A; when the integrated chip 50 undergoes CDM discharge, due to the increase in the current magnitude, the resistance of the current limiting layer 501 also increases, so as to achieve a slower release speed, and the peak value of the maximum discharge current does not exceed 2A. It can be seen that when the integrated chip 50 undergoes CDM, the charge discharge speed on the surface of the shielding layer 8 is slower, which can greatly reduce the peak current during CDM discharge, avoid the formation of a high peak current, and thus reduce the risk of CDM failure of the integrated chip 50.

[0097] For the integrated chip 50 in the embodiment of the present application, there is no need to add additional protection devices on the packaging substrate 5. By only setting the current limiting layer 501 between the shielding layer 8 and the ground wire 6-1, the CDM risk can be reduced, the cost and occupied area of the protection devices can be saved, the metal interconnections for connecting the protection devices can be reduced, the design difficulty of the packaging substrate 5 can be reduced, and the degradation of chip performance caused by the parasitics introduced by the protection devices can be avoided.

[0098] The following introduces an integrated chip 50' provided by an embodiment of the present application. In the integrated chip 50', the ground wire extends from the inside of the package substrate to the side of the package substrate.

[0099] Figure 9 It is a schematic cross-sectional view of the integrated chip 50' provided by an embodiment of the present application. The difference between the integrated chip 50' and the integrated chip 50 is that, along the X direction, the width of the encapsulation layer 7' is the same as the width of the package substrate 5'. And, the ground wire 6-1' is exposed from the side of the package substrate 5'.

[0100] Correspondingly, along the Z direction, the side wall 8-2' of the shielding layer 8' extends to the side of the package substrate 5' and is connected to the lower surface of the package substrate 5' to ensure that the shielding layer 8' can be connected to the ground wire 6-1' exposed on the side of the package substrate 5' to play a shielding role.

[0101] In the integrated chip 50', the current-limiting layer 501' is arranged inside the shielding layer 8'. The current-limiting layer 501' adopts a structure similar to that of the shielding layer 8', that is, the current-limiting layer 501' includes a top 501-1 and side walls 501-2. The side walls 501-2 surround the top 501-1 on all sides and extend along the Z-axis direction relative to the top wall 501-1 to the side of the package substrate 5' and are directly in contact with the ground wire 6-1' exposed on the side of the package substrate 5'. In this way, it is ensured that the shielding layer 8' can be connected to the ground wire 6-1' exposed on the side of the package substrate 5' through the current-limiting layer 501'.

[0102] In the preparation process of the integrated chip 50', the current-limiting layer 501' is first formed on the upper surface, side surface of the encapsulation layer 7' and the side surface of the package substrate 5' by means such as spraying, PVD, CVD, etc., and then the shielding layer 5' is formed on the upper surface and side surface of the current-limiting layer 501' by PVD.

[0103] In addition, for the first material, characteristics, and resistance value range of the current-limiting layer 501', reference can be made to the embodiments of the current-limiting layer 501, which will not be elaborated here.

[0104] In the integrated chip 50' of the embodiment of the present application, the current-limiting layer 501' is connected to the ground wire 6-1' exposed on the side of the package substrate 5', and the shielding layer 8' is then connected to the current-limiting layer 501', which can achieve the same effect as the integrated chip 50.

[0105] It can be understood that there are various chip packaging forms. The above integrated chips 50 and 50' are both single-sided single-layer packaging forms. The following will be combined with Figure 10 introduce an integrated chip 50" with a single-sided double-layer packaging form.

[0106] Such as Figure 10As shown, the integrated chip 50” is different from the integrated chip 50 in that the integrated chip 50” further includes a stacked packaging substrate 502 (an example of a second packaging substrate) and a packaging layer 503 (an example of a second packaging layer), and a chip 4 (an example of a second chip) located inside the packaging layer 503 and on the surface of the packaging substrate 502. Here, the packaging substrate 502, the packaging layer 503, and the chip 4 form a first packaging part, the packaging substrate 5”, the packaging layer 7”, and the chips 1 to 3 form a second packaging part, and the first packaging part and the second packaging part are stacked vertically to form a double-layer packaging structure.

[0107] Among them, a ground wire 504 (an example of a second grounding structure) is provided inside the packaging substrate 502, and the ground wire 504 penetrates the packaging substrate 502 in the Z direction, that is, the ground wire 504 extends from the bottom of the chip 4 to the surface of the packaging layer 7”. A through hole 701 is provided in the packaging layer 7”, and the through hole 701 can be filled with a conductive material to connect the ground wire 504 to the ground wire 6-1” inside the packaging substrate 5” to achieve a common ground for the chips 1-4.

[0108] In addition, the integrated chip 50” further includes a shielding layer 8” and a current-limiting layer 501”. Among them, the shielding layer 8” can refer to the embodiment of the above-mentioned shielding layer 8’. The current-limiting layer 501” can refer to the embodiment of the above-mentioned current-limiting layer 501’, and details are not described herein again.

[0109] For the integrated chip 50” of the embodiment of the present application, the current-limiting layer 501” is connected to the ground wire 6-1” exposed on the side surface of the packaging substrate 5”, and the shielding layer 8” is then connected to the current-limiting layer 501”, which can achieve the same effect as the integrated chip 50.

[0110] Next, in conjunction with Figure 11 An integrated chip 50”’ in a double-sided single-layer packaging form is introduced.

[0111] As Figure 11 shown, the integrated chip 50”’ is different from the integrated chip 50 in that the integrated chip 50”’ further includes a chip 5 (an example of a third chip) integrated on the lower surface of the packaging substrate 5”’, and a packaging layer 505 for protecting the chip 5. Here, the chip 5, the chips 1 to 3 are all integrated on the same packaging substrate 5”’, and the chip 5 and the chips 1 to 3 are respectively arranged on two opposite surfaces of the packaging substrate 5”’ along the Z direction.

[0112] Among them, the encapsulation layer 505, the encapsulation substrate 5”’, and the encapsulation layer 7”’ are stacked in sequence from bottom to top. The pin pad 4”’ is disposed at the bottom of the encapsulation layer 505 facing away from the chip 5. At least one conductive member 506 is further disposed inside the encapsulation layer 505. The conductive member 506 penetrates the encapsulation layer 505 along the Z direction. The conductive member 506 is used to connect the metal interconnect line 6”’ in the encapsulation substrate 5”’ to the pin pad 4”’. Here, the conductive member 506 can be a copper ball, a copper pillar, or other metal materials (such as tin, copper) and shapes (such as a cubic pillar).

[0113] It can be understood that the chip 5 may have a ground wire 6-1”’ extending to the side of the encapsulation substrate 5”’ in other cross-sections, and the chip 5 and the chip 1-2 are grounded together.

[0114] In addition, the integrated chip 50” further includes a shielding layer 8”’ and a current-limiting layer 501”’. Among them, the shielding layer 8”’ can refer to the embodiment of the shielding layer 8’. The current-limiting layer 501”’ can refer to the embodiment of the current-limiting layer 501’, and details are not described herein again.

[0115] In the integrated chip 50”’ of the embodiment of the present application, the current-limiting layer 501”’ is connected to the ground wire 6-1”’ exposed on the side of the encapsulation substrate 5”’, and the shielding layer 8”’ is further connected to the current-limiting layer 501”’, which can achieve the same effect as the integrated chip 50.

[0116] In the above embodiments, the shielding layer is a part of the integrated chip as a whole. The manufacturing of the shielding layer belongs to a part of the preparation of the integrated chip. For the prepared integrated chip, the outermost layer is the shielding layer, that is, the shielding layer constitutes the appearance of the integrated chip. It can be understood that the shielding layer can also be a separate component. For example, a shielding device is separately prepared and then assembled with the packaged integrated chip, and the shielding effect can be achieved after assembly.

[0117] Therefore, in some embodiments, the current-limiting layer can be directly formed on the shielding device. Specifically, the shielding device may include a shielding layer and a current-limiting layer, and the current-limiting layer is formed on the inner wall of the shielding layer.

[0118] Combined with Figure 9 As shown, the shielding device can be separately prepared with reference to the structures of the shielding layer 8’ and the current-limiting layer 501’, and then the shielding device can be directly covered outside the encapsulation substrate 5’ and the encapsulation layer 7’. In this way, since the current-limiting layer is provided on the inner wall of the shielding layer, when discharging charges, it still needs to pass through the current-limiting layer first and then enter the ground wire 6-1’ of the encapsulation substrate 5’, which can achieve the same effect as the integrated chip 50’.

[0119] In the above description of this embodiment, unless otherwise specified, " / " means "or". For example, A / B can denote A or B. The "and / or" in this document is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, B exists alone, and both A and B exist simultaneously.

[0120] It should be noted that in the examples and descriptions of this application, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "including one" does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

[0121] Although this application has been illustrated and described by referring to some preferred embodiments of this application, those of ordinary skill in the art should understand that various changes can be made to it in form and detail without departing from the scope of this application.

Claims

1. An integrated chip, characterized in that, Comprising: A first encapsulation substrate and a first encapsulation layer that are stacked on top of each other, At least one first chip that is wrapped by the first encapsulation layer and disposed on the first encapsulation substrate, wherein the first encapsulation substrate includes a first grounding structure exposed on its surface, and the at least one first chip is directly connected to the first grounding structure respectively, A shielding layer disposed outside the first encapsulation layer for shielding electromagnetic interference, wherein the shielding layer is connected to the first grounding structure through a current-limiting layer, the current-limiting layer includes a first material, corresponding to a first current density of the current flowing through the current-limiting layer, the first material exhibits a first impedance, and the product of the first impedance and the perimeter of the current-limiting layer is a first value; corresponding to a second current density of the current flowing through the current-limiting layer, the first material exhibits a second impedance, and the product of the second impedance and the perimeter of the current-limiting layer is a second value; wherein, the first current density is greater than the second current density, and the first value is greater than the second value.

2. The integrated chip according to claim 1, characterized in that, The first current density is greater than 1 A / cm, and the first value is greater than 10 Ω·cm.

3. The integrated chip according to claim 1, wherein The second current density is less than 0.1 A / cm, and the second value is less than 1 Ω·cm.

4. The integrated chip according to any one of claims 1 to 3, characterized in that, The ratio of the first impedance to the second impedance is greater than 10.

5. The integrated chip according to claim 1, characterized in that, The first material has a first voltage-current characteristic curve, and the ratio of current to voltage in the first voltage-current characteristic curve decreases as the current increases.

6. The integrated chip according to claim 1, characterized in that, Along the width direction of the integrated chip, the width of the first encapsulation substrate is greater than the width of the first encapsulation layer; The first grounding structure is exposed along the edge of the upper surface of the first encapsulation substrate facing the first encapsulation layer.

7. The integrated chip according to claim 6, wherein The current-limiting layer is formed on the surface of the first grounding structure; The shielding layer includes a first top and a first sidewall surrounding the edge of the first top, and the first sidewall extends along the thickness direction of the integrated chip relative to the first top to the upper surface of the first encapsulation substrate and contacts the current-limiting layer; The first grounding structure, the current-limiting layer and the first sidewall are stacked in sequence along the thickness direction.

8. The integrated chip according to claim 1, characterized in that, Along the width direction of the integrated chip, the width of the first encapsulation substrate is equal to the width of the first encapsulation layer; The first grounding structure is exposed from the side of the first encapsulation substrate.

9. The integrated chip according to claim 8, wherein The current-limiting layer includes a second top and a second sidewall surrounding the edge of the second top, and the second sidewall extends along the thickness direction of the integrated chip relative to the second top to the side of the first encapsulation substrate and is connected to the lower surface of the first encapsulation substrate facing away from the first encapsulation layer; The shielding layer is disposed outside the current-limiting layer, the shielding layer includes a third top and a third sidewall surrounding the edge of the third top, and the third sidewall extends along the thickness direction of the integrated chip relative to the third top and is flush with the bottom connected to the second sidewall and the lower surface of the first encapsulation substrate; The first grounding structure, the second sidewall and the third sidewall are connected in sequence along the width direction of the integrated chip.

10. The integrated chip according to claim 1, 8 or 9, characterized in that, Further comprising: A second encapsulation substrate and a second encapsulation layer stacked on top of each other, and at least one second chip wrapped by the second encapsulation layer and disposed on the second encapsulation substrate; wherein, The second encapsulation substrate, the second encapsulation layer, and the at least one second chip constitute a first encapsulation part, the first encapsulation substrate, the first encapsulation layer, and the at least one first chip constitute a second encapsulation part, and the first encapsulation part and the second encapsulation part are stacked on top of each other in a vertical direction to form a double-layer encapsulation structure.

11. The integrated chip according to claim 10, characterized in that, A second grounding structure is disposed inside the second encapsulation substrate, and the at least one second chip is directly connected to the second grounding structure respectively. The second grounding structure penetrates through the second encapsulation substrate along the thickness direction of the integrated chip, and is connected to the first grounding structure through a conductive material inside the first encapsulation layer.

12. The integrated chip according to claim 1, 8 or 9, characterized in that, It further includes: At least one third chip disposed on the first encapsulation substrate, and a second encapsulation layer that wraps the at least one third chip; wherein, The third chip and the first chip are respectively disposed on two opposite surfaces of the first encapsulation substrate along the thickness direction of the integrated chip, and the first encapsulation layer and the second encapsulation layer are respectively formed on two sides of the first encapsulation substrate along the thickness direction to form a double-sided encapsulation structure.

13. The integrated chip according to claim 12, characterized in that, At least one conductive member is disposed inside the second encapsulation layer, and the conductive member penetrates through the second encapsulation layer along the thickness direction. The conductive member is used to connect a metal interconnection structure inside the first encapsulation substrate to a pin pad at the bottom of the second encapsulation layer facing away from the first encapsulation layer.

14. A shielding device, characterized in that, For assembling with an integrated chip to shield electromagnetic interference generated or received by the integrated chip; wherein, The shielding device includes a shielding layer and a current-limiting layer disposed on the inner wall of the shielding layer. The current-limiting layer includes a first material. Corresponding to a first current density of the current flowing through the current-limiting layer, the first material exhibits a first impedance, and the product of the first impedance and the perimeter of the current-limiting layer is a first value; corresponding to a second current density of the current flowing through the current-limiting layer, the first material exhibits a second impedance, and the product of the second impedance and the perimeter of the current-limiting layer is a second value; wherein, the first current density is greater than the second current density, and the first value is greater than the second value.

15. The shielding device according to claim 14, wherein The first current density is greater than 1 A / cm, and the first value is greater than 10 Ω·cm.

16. The shielding device according to claim 14, wherein The second current density is less than 0.1 A / cm, and the second value is less than 1 Ω·cm.

17. The shielding device according to any one of claims 14 to 16, characterized in that, The ratio of the first impedance to the second impedance is greater than 10.

18. The shielding device according to claim 14, wherein The first material has a first volt-ampere characteristic curve, and the ratio of current to voltage in the first volt-ampere characteristic curve decreases as the current increases.

19. A chip component, characterized in that, It includes the shielding device according to any one of claims 14-18 and an integrated chip, and the shielding device covers the outside of the integrated chip.

20. An electronic device, characterized in that, It includes the integrated chip according to any one of claims 1-13 and a circuit board, and the integrated chip is disposed on the circuit board.

21. An electronic device, characterized in that, It includes the chip assembly according to claim 19 and a circuit board, and the chip assembly is disposed on the circuit board.

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