Package assembly and manufacturing method of package assembly
By setting up a balanced structure of materials such as copper, stainless steel or ceramics in the laminated packaging structure, the warping and deformation problem is solved, and the assembly yield of packaging components and the reliability of the terminal products are improved.
Patent Information
- Application Number
- CN202411295920.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-14
- Publication Date
- 2025-07-25
AI Technical Summary
The stacked packaging structure causes warping and deformation due to different thermal expansion coefficients of materials, resulting in poor welding between the chip and the substrate and between adjacent layers, affecting the assembly yield and the reliability of the terminal product.
A balanced structure is set up in the stacked packaging structure to balance warping deformation, and a balanced structure of materials such as copper, stainless steel or ceramics is used to surround the chip to enhance stiffness to reduce warping.
It reduces warpage of stacked packages, reduces air welding and short circuit phenomena, improves assembly yield and reliability of terminal products.
Smart Images
Figure CN120376554A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the technical field of semiconductor packaging, and particularly to a packaging component and a manufacturing method thereof. Background Art
[0002] The new growth point of today's semiconductor integrated circuits has shifted from traditional computer and communication industries to portable mobile devices such as smart phones, tablet computers and a new generation of wearable devices. Accordingly, new trends have emerged in semiconductor packaging technology to meet the special requirements of mobile device products, such as stacking different chips (package on package, PoP) such as logic chips and memory chips to achieve the purpose of ultra-thin, low power consumption and low signal loss.
[0003] However, various different materials are used in the stacked packaging structure, such as chips, substrates, plastic packages, etc. These materials have different coefficients of thermal expansion. When the entire package undergoes a temperature change, for example, from a high temperature during the packaging process to room temperature, due to the different coefficients of thermal expansion of various materials, the expansion and contraction are inconsistent, resulting in warping of the package, which will cause poor soldering phenomena such as open soldering or short circuit during the soldering assembly between the chip and the substrate and between adjacent two layers of the package, affecting the assembly yield and efficiency of the terminal manufacturer, and even affecting the reliability of the terminal product in actual applications. Summary of the Invention
[0004] The present disclosure aims to solve at least one of the technical problems in the related art to some extent.
[0005] To this end, the first object of the present disclosure is to provide a packaging component to reduce the warping generated by stacked packaging.
[0006] The second object of the present disclosure is to provide a manufacturing method of a packaging component.
[0007] To achieve the above object, an embodiment of the first aspect of the present disclosure provides a packaging component, including: a plurality of stacked packaging structures, wherein a balance structure is provided on at least one of the plurality of stacked packaging structures to balance the warping deformation generated by the packaging structures.
[0008] Optionally, each packaging structure includes:
[0009] a substrate, and the substrates of the plurality of packaging structures are parallel to each other;
[0010] a chip disposed on a first surface of the substrate, wherein a balance structure is provided on the first surface and / or the second surface of the substrate of at least one packaging structure.
[0011] Optionally, the balance structure at least partially surrounds the chip.
[0012] Optionally, the balancing structure includes an annular structural block, and the chip is located at the center of the annular structural block.
[0013] Optionally, the balancing structure includes a first strip-shaped structural block and a second strip-shaped structural block, and the first strip-shaped structural block and the second strip-shaped structural block are arranged in parallel on both sides of the chip.
[0014] Optionally, the stiffness corresponding to the balancing structure is greater than a preset stiffness threshold.
[0015] Optionally, the material of the balancing structure is at least one of copper, stainless steel, and ceramic.
[0016] Optionally, the packaging component includes a first packaging structure and a second packaging structure arranged in a stacked manner. The first packaging structure includes a first substrate and a first chip, the second packaging structure includes a second substrate and a second chip, the first chip includes a logic chip, and the second chip includes a memory chip.
[0017] To achieve the above object, an embodiment of the second aspect of the present disclosure provides a manufacturing method of a packaging component, including:
[0018] During the manufacturing process of the packaging component, a balancing structure is provided on at least one of the multiple stacked packaging structures of the packaging component to balance the warpage deformation generated by the packaging structure.
[0019] Optionally, the packaging component includes a first packaging structure and a second packaging structure arranged in a stacked manner. The first packaging structure includes a first substrate and a first chip, the second packaging structure includes a second substrate and a second chip. Manufacturing the packaging component includes:
[0020] Providing a first chip on a first surface of the first substrate, and providing a balancing structure on the first surface of the first substrate and / or a second surface of the second substrate;
[0021] Connecting the first surface of the first substrate to the second surface of the second substrate through a connecting member, and making the balancing structure at least partially surround the first chip;
[0022] Encapsulating the first chip with a molding compound to obtain the first packaging structure;
[0023] Providing a second chip on a first surface of the second substrate to obtain the second packaging structure.
[0024] Optionally, the packaging component includes a first packaging structure and a second packaging structure arranged in a stacked manner. The first packaging structure includes a first substrate and a first chip, the second packaging structure includes a second substrate and a second chip. Manufacturing the packaging component includes:
[0025] Providing a first chip on a first surface of the first substrate;
[0026] Connect the first surface of the first substrate to the second surface of the second substrate through a connecting member;
[0027] Encapsulate the first chip with a molding compound to obtain a first encapsulation structure;
[0028] Dispose a second chip on the first surface of the second substrate to obtain a second encapsulation structure, and dispose a balancing structure on the first surface of the second substrate, the balancing structure at least partially surrounding the second chip.
[0029] Optionally, the encapsulation component includes a first encapsulation structure and a second encapsulation structure arranged in a stack. The first encapsulation structure includes a first substrate and a first chip, and the second encapsulation structure includes a second substrate and a second chip. Manufacturing the encapsulation component includes:
[0030] Dispose a connecting member, a first chip, and a balancing structure on the second surface of the second substrate, and the balancing structure at least partially surrounds the first chip;
[0031] Encapsulate the connecting member and the first chip with a molding compound;
[0032] Connect the first surface of the first substrate to the second surface of the second substrate through the connecting member to obtain a first encapsulation structure;
[0033] Dispose a second chip on the first surface of the second substrate to obtain a second encapsulation structure.
[0034] Optionally, the encapsulation component includes a first encapsulation structure and a second encapsulation structure arranged in a stack. The first encapsulation structure includes a first substrate and a first chip, and the second encapsulation structure includes a second substrate and a second chip. Manufacturing the encapsulation component includes:
[0035] Dispose a connecting member and a first chip on the second surface of the second substrate;
[0036] Encapsulate the connecting member and the first chip with a molding compound;
[0037] Connect the first surface of the first substrate to the second surface of the second substrate through the connecting member to obtain a first encapsulation structure;
[0038] Dispose a second chip on the first surface of the second substrate to obtain a second encapsulation structure, and dispose a balancing structure on the first surface of the second substrate, the balancing structure at least partially surrounding the second chip.
[0039] In summary, for the encapsulation component and the manufacturing method thereof provided by the present disclosure, by providing a balancing structure on at least one of the encapsulation structures arranged in multiple layers, when the entire encapsulation component undergoes temperature changes, the balancing structure can be used to balance the warping deformation generated by the encapsulation structure due to different coefficients of thermal expansion of various materials, reduce the warping generated by stacked encapsulation, thereby reducing soldering defects such as open solder joints or short circuits caused by warping in the encapsulation component, improving the assembly yield and efficiency of the terminal manufacturer, and enhancing the reliability in the actual application of the terminal product.
[0040] Additional aspects and advantages of the present disclosure will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of the embodiments in conjunction with the accompanying drawings, where:
[0042] Figure 1 is a schematic structural diagram of an encapsulation component provided by an embodiment of the present disclosure;
[0043] Figure 2 is a top view of an encapsulation structure provided by an embodiment of the present disclosure;
[0044] Figure 3 is a top view of an encapsulation structure provided by an embodiment of the present disclosure;
[0045] Figure 4 is a top view of an encapsulation structure provided by an embodiment of the present disclosure;
[0046] FIG. 5(a) is a cross-sectional view of an encapsulation component using the HBPoP encapsulation method provided by an embodiment of the present disclosure;
[0047] FIG. 5(b) is a cross-sectional view of an encapsulation component using the HBPoP encapsulation method provided by an embodiment of the present disclosure;
[0048] FIG. 5(c) is a cross-sectional view of an encapsulation component using the HBPoP encapsulation method provided by an embodiment of the present disclosure;
[0049] FIG. 6(a) is a cross-sectional view of an encapsulation component using the InFO-PoP encapsulation method provided by an embodiment of the present disclosure;
[0050] FIG. 6(b) is a cross-sectional view of an encapsulation component using the InFO-PoP encapsulation method provided by an embodiment of the present disclosure;
[0051] Figure 7 is a schematic flowchart of a manufacturing method of an encapsulation component provided by an embodiment of the present disclosure. Detailed implementation manners
[0052] Embodiments of the present disclosure will be described in detail below. Examples of the embodiments are shown in the accompanying drawings, in which the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as a limitation to the present disclosure.
[0053] The present disclosure will be described in detail below in conjunction with specific embodiments.
[0054] Figure 1 FIG. is a schematic structural diagram of a packaging component provided by an embodiment of the present disclosure. As Figure 1 shown, the packaging component includes a plurality of stacked packaging structures 1, and a balance structure 2 is provided on at least one of the plurality of stacked packaging structures 1.
[0055] It should be noted that when the entire packaging component undergoes a temperature change, the balance structure 2 can be used to balance the warping deformation generated by the packaging structure 1 due to different thermal expansion coefficients of various materials, reduce the warping generated by stacked packaging, thereby reducing welding defects such as open solder joints or short circuits caused by warping in the packaging component, improving the assembly yield and efficiency of the terminal manufacturer, and improving the reliability of the terminal product in actual application.
[0056] Optionally, the packaging method adopted by the packaging component includes, but is not limited to, PoP packaging methods such as high bandwidth package on package (HBPoP), integrated fanout package-on-package (InFO-PoP), etc.
[0057] Optionally, the stiffness corresponding to the balance structure 2 is greater than a preset stiffness threshold, so that the balance effect when balancing the warping deformation generated by the packaging structure 1 can be improved.
[0058] According to some embodiments, the preset stiffness threshold does not specifically refer to a certain fixed threshold. The preset stiffness threshold can be determined according to the actual application scenario, for example.
[0059] In some embodiments, the material of the balance structure 2 can be, for example, at least one of copper, stainless steel, and ceramic.
[0060] Optionally, each packaging structure 1 includes:
[0061] a substrate 3, and the substrates 3 of the plurality of packaging structures 1 are parallel to each other;
[0062] A chip 4 disposed on the first surface of a substrate 3;
[0063] Wherein, a balancing structure 2 is disposed on the first surface and / or the second surface of the substrate 3 of at least one packaging structure 1.
[0064] Wherein, the substrate 3 includes, but is not limited to, a printed circuit board (PCB), a Redistribution Layer interposer (RDL interposer), an organic substrate, etc.
[0065] According to some embodiments, the chip 4 includes, but is not limited to, a logic chip, a memory chip, etc.
[0066] For example, when the packaging component includes a first packaging structure 11 and a second packaging structure 12 arranged in a stacked manner, the first packaging structure includes a first substrate 113 and a first chip 114, and the second packaging structure 12 includes a second substrate 123 and a second chip 124, the first chip may include a logic chip, and the second chip may include a memory chip.
[0067] Wherein, the logic chip includes, but is not limited to, an Application Processor (AP) die, an AP chip, etc. The memory chip includes, but is not limited to, a Double Data Rate Random Access Memory (DDR RAM) chip, a DDR RAM package, a DDR particle, etc.
[0068] According to some embodiments, the chip 4 may be a single chip or a chip package obtained by encapsulating at least one chip.
[0069] For example, an AP die, an AP chip, and a DDR RAM chip are single chips; a DDR RAM package and a DDR particle are chip packages obtained by encapsulating at least one chip.
[0070] Wherein, when the chip 4 is a single chip, the single chip may be obtained by back grinding the wafer, laser grooving, or wafer sawing.
[0071] According to some embodiments, the balancing structure 2 may at least partially surround the chip 4. Wherein, when the balancing structure 2 is disposed on the second surface of the substrate 3, the balancing structure 2 may at least partially surround the chip 4 in the packaging structure 2 adjacent to the packaging structure 2 where it is located.
[0072] In some embodiments, Figure 2 is a top view of a packaging structure provided by an embodiment of the present disclosure. As Figure 2 shown, the balance structure 2 includes an annular structure block, and the chip 4 is located at the center of the annular structure block.
[0073] In some embodiments, Figure 3 is a top view of a packaging structure provided by an embodiment of the present disclosure. As Figure 3 shown, the balance structure 2 includes a first strip structure block and a second strip structure block, and the first strip structure block and the second strip structure block are arranged in parallel on both sides of the chip 4; wherein, the balance structure 2 includes the following arrangement modes:
[0074] The first strip structure block and the second strip structure block are arranged in parallel on the left and right sides of the chip 4, as shown in Figure 3 (a) in;
[0075] The first strip structure block and the second strip structure block are arranged in parallel on the upper and lower sides of the chip 4, as shown in Figure 3 (b) in.
[0076] In some embodiments, Figure 4 is a top view of a packaging structure provided by an embodiment of the present disclosure. As Figure 4 shown, the balance structure 2 includes a third strip structure block, a fourth strip structure block, a fifth strip structure block, and a sixth strip structure block. The third strip structure block and the fourth strip structure block are arranged in parallel on the left and right sides of the chip 4, and the fifth strip structure block and the sixth strip structure block are arranged in parallel on the upper and lower sides of the chip 4.
[0077] Exemplarily, the packaging component may include a first packaging structure 11 and a second packaging structure 12 arranged in a stacked manner. The first packaging structure includes a first substrate 113 and a first chip 114. The second packaging structure 12 includes a second substrate 123 and a second chip 124. The second chip 124 may be a chip package obtained by encapsulating multiple chips;
[0078] Wherein, when the packaging component adopts the HBPoP packaging method, the first chip 114 is disposed on and in contact with the first surface of the first substrate 113, and the second chip 124 is disposed on and in contact with the first surface of the second substrate 123. The balance structure 2 may adopt at least one of the following arrangement modes:
[0079] The balance structure 2 is disposed on the first surface of the first substrate 113, and the balance structure 2 at least partially surrounds the first chip 114, as shown in Fig. 5(a);
[0080] The balance structure 2 is disposed on the second surface of the second substrate 123, and the balance structure 2 at least partially surrounds the first chip 114, as shown in FIG. 5(b);
[0081] The balance structure 2 is disposed on the first surface of the second substrate 123, and the balance structure 2 at least partially surrounds the second chip 124, as shown in FIG. 5(c).
[0082] Wherein, in the case where the packaging component adopts the InFO-PoP packaging method, the first chip 114 is disposed on the first surface of the first substrate 113 and in contact with the second surface of the second substrate 123, the second chip 124 is disposed on the first surface of the second substrate 123 and in contact with the first surface of the second substrate 123, and the balance structure 2 can adopt at least one of the following setting methods:
[0083] The balance structure 2 is disposed on the second surface of the second substrate 123, and the balance structure 2 at least partially surrounds the first chip 114, as shown in FIG. 6(a);
[0084] The balance structure 2 is disposed on the first surface of the second substrate 123, and the balance structure 2 at least partially surrounds the second chip 124, as shown in FIG. 6(b).
[0085] Taking a scenario as an example, in the case where the packaging component adopts the HBPoP packaging method and the balance structure 2 is a copper material annular structure block (abbreviated as copper ring), simulation tests are respectively carried out on the first packaging component corresponding to FIG. 5(a), the second packaging component corresponding to FIG. 5(b), the third packaging component corresponding to FIG. 5(c), and the original packaging component without the balance structure 2, and the test results are shown in the following table:
[0086] Warpage in heating stage @ 25°C (μm) Warpage @ 260°C (μm) Warpage in cooling stage @ 25°C (μm) Original encapsulation component 63.4 -117.8 107.9 First encapsulation component 64.3 -117.2 109.1 Second encapsulation component 66.9 -109.5 111.4 Third encapsulation component -69.1 -24.3 -46.1
[0087] Wherein, the warpage @ 25°C (μm) in the heating section represents the warpage value of the packaging component at room temperature (25°C) before heating; the warpage @ 260°C (μm) represents the warpage value of the packaging component at a high temperature of 260°C; the warpage @ 25°C (μm) in the cooling section represents the warpage value of the packaging component at room temperature (25°C) after cooling.
[0088] Wherein, in the case of horizontally placing the packaging component, the warpage value is negative when the packaging component is concave, the warpage value is positive when the packaging component is convex, and the warpage value is zero when the packaging component is neither concave nor convex.
[0089] From the test results, it can be seen that for the first and second packaging components with the copper ring design introduced, compared with the original packaging component, there is a benefit of 0.6 - 8.3 um in packaging warpage at a high temperature of 260 °C; the high-temperature warpage of the third packaging component with the copper ring design is reduced to -24.3 um, and the room-temperature warpage after cooling is also reduced to -46.1 um, which is very beneficial for subsequent soldering and assembly of surface mount technology (SMT).
[0090] In summary, for the packaging component provided in this embodiment, by providing a balance structure 2 on at least one of the packaging structures 1 provided in multiple stacked layers, when the entire packaging component undergoes temperature changes, the balance structure 2 can be used to balance the warping deformation generated by the packaging structure 1 due to different thermal expansion coefficients of various materials, reduce the warping generated by stacked packaging, thereby reducing soldering defects such as open solder or short circuit caused by warping in the packaging component, improving the assembly yield and efficiency of the terminal manufacturer, and improving the reliability in the actual application of the terminal product.
[0091] To implement the above embodiment, the present disclosure also proposes a manufacturing method of a packaging component, as Figure 7 shown, Figure 7 is a schematic flowchart of a manufacturing method of a packaging component provided by an embodiment of the present disclosure.
[0092] Exemplarily, the manufacturing method of the packaging component may include the following steps:
[0093] S101, during the manufacturing process of the packaging component, a balance structure is provided on at least one of the packaging structures provided in multiple stacked layers of the packaging component to balance the warping deformation generated by the packaging structure.
[0094] According to some embodiments, when manufacturing the packaging component using the HBPoP packaging method, and the packaging component includes a first packaging structure 11 and a second packaging structure 12 provided in a stacked manner, the first packaging structure includes a first substrate 113 and a first chip 114, and the second packaging structure 12 includes a second substrate 123 and a second chip 124, the following steps may be included:
[0095] S201, a first chip 114 is provided on the first surface of the first substrate 113, and a balance structure 2 is provided on the first surface of the first substrate 113 and / or the second surface of the second substrate 123;
[0096] S202, the first surface of the first substrate 113 is connected to the second surface of the second substrate 123 through a connecting member 5, and the balance structure 2 at least partially surrounds the first chip 114;
[0097] S203, encapsulate the first chip 114 with the encapsulant 6 to obtain the first encapsulation structure 11;
[0098] S204, dispose the second chip 124 on the first surface of the second substrate 123 to obtain the second encapsulation structure 12.
[0099] Wherein, when the balance structure 2 is disposed on the first surface of the first substrate 113 and the second chip 124 is a chip package obtained by encapsulating multiple chips, the cross-sectional view of the obtained encapsulation component can be as shown in FIG. 5(a).
[0100] Wherein, when the balance structure 2 is disposed on the second surface of the second substrate 123 and the second chip 124 is a chip package obtained by encapsulating multiple chips, the obtained encapsulation component can be as shown in FIG. 5(b).
[0101] According to some embodiments, when manufacturing the encapsulation component by using the HBPoP encapsulation method, and the encapsulation component includes the first encapsulation structure 11 and the second encapsulation structure 12 which are stacked, the first encapsulation structure includes the first substrate 113 and the first chip 114, and the second encapsulation structure 12 includes the second substrate 123 and the second chip 124, the following steps may further be included:
[0102] S301, dispose the first chip 114 on the first surface of the first substrate 113;
[0103] S302, connect the first surface of the first substrate 113 and the second surface of the second substrate 123 through the connecting member 5;
[0104] S303, encapsulate the first chip 114 with the encapsulant 6 to obtain the first encapsulation structure 11;
[0105] S304, dispose the second chip 124 on the first surface of the second substrate 123 to obtain the second encapsulation structure 12, and dispose the balance structure 2 on the first surface of the second substrate 123, and the balance structure 2 at least partially surrounds the second chip 124.
[0106] Wherein, when the second chip 124 is a chip package obtained by encapsulating multiple chips, the cross-sectional view of the obtained encapsulation component can be as shown in FIG. 5(c).
[0107] It should be noted that steps S201 to S204 and steps S301 to S304 can also be combined, that is, the balance structure 2 is disposed on the first surface of the first substrate 113 and / or the second surface of the second substrate 123, and the balance structure 2 is also disposed on the first surface of the second substrate 123, and the specific steps will not be repeated here.
[0108] In some embodiments, the connecting member 5 includes but is not limited to stud bumps, copper core bumps (such asFigures 5(a) to 5(c) as shown), copper pillars (as shown in FIGS. 6(a) and 6(b)), etc.
[0109] In some embodiments, when the first chip 114 is disposed on the first surface of the first substrate 113, the first chip 114 can be flip-chip soldered through solder ball bumps to form an interconnect structure on the first surface of the first substrate 113.
[0110] In some embodiments, when the balance structure 2 is provided, the balance structure 2 can be mounted on the surface of the substrate 3 by an adhesive.
[0111] In some embodiments, when the first surface of the first substrate 113 is connected to the second surface of the second substrate 123 through the connecting member 5, the connecting member 5 can be mounted on the second surface of the second substrate 123, and the position corresponding to the connecting member 5 on the first surface of the first substrate 113 is cut to obtain the cut first substrate 113. Finally, the first substrate 113 and the cut second substrate 123 are assembled through the connecting member 5.
[0112] According to some embodiments, when manufacturing a packaging component by using the InFO-PoP packaging method, and the packaging component includes a first packaging structure 11 and a second packaging structure 12 which are stacked, the first packaging structure includes a first substrate 113 and a first chip 114, and the second packaging structure 12 includes a second substrate 123 and a second chip 124, the following steps may be included:
[0113] S401, disposing the connecting member 5, the first chip 114, and the balance structure 2 on the second surface of the second substrate 123, and the balance structure 2 at least partially surrounds the first chip 114;
[0114] S402, encapsulating the connecting member 5 and the first chip 114 with a molding compound 6;
[0115] S403, connecting the first surface of the first substrate 113 to the second surface of the second substrate 123 through the connecting member 5 to obtain the first packaging structure 11;
[0116] S404, disposing the second chip 123 on the first surface of the second substrate 123 to obtain the second packaging structure 12.
[0117] According to some embodiments, when manufacturing a packaging component by using the InFO-PoP packaging method, and the packaging component includes a first packaging structure 11 and a second packaging structure 12 which are stacked, the first packaging structure includes a first substrate 113 and a first chip 114, and the second packaging structure 12 includes a second substrate 123 and a second chip 124, the following steps may also be included:
[0118] S501. On the second surface of the second substrate 123, dispose a connecting member 5 and a first chip 114;
[0119] S502. Use a molding compound 6 to encapsulate the connecting member 5 and the first chip 114;
[0120] S503. Connect the first surface of the first substrate 113 to the second surface of the second substrate 123 through the connecting member 5 to obtain a first package structure 11;
[0121] S504. On the first surface of the second substrate 123, dispose a second chip 124 to obtain a second package structure 12, and on the first surface of the second substrate 123, dispose a balancing structure 2, and the balancing structure 2 at least partially surrounds the second chip 124.
[0122] Wherein, after using the molding compound 6 to encapsulate the connecting member 5 and the first chip 114, the obtained component after encapsulation can also be polished.
[0123] Wherein, after connecting the first surface of the first substrate 113 to the second surface of the second substrate 123 through the connecting member 5 to obtain the first package structure 11, ball implantation can also be performed inside the first substrate 113 and the second substrate 123, so that the first chip 114 and the second chip 124 can form an interconnection structure with the first surface of the first substrate 113 and the second surface of the second substrate 123 through the balls 7 implanted inside the first substrate 113 and the second substrate 123 and the connecting member 5;
[0124] Wherein, the mounting of the second chip 124 and the balancing structure 2 can be completed at a site such as a wafer fab or a packaging factory that supports mounting.
[0125] It should be noted that steps S401 to S404 and steps S501 to S504 can also be combined, that is, a balancing structure 2 is disposed on the second surface of the second substrate 123 and also on the first surface of the second substrate 123, and the specific steps will not be repeated here.
[0126] In summary, in the method provided in this embodiment, by disposing the balancing structure 2 on at least one of the package structures 1 in the multiple stacked package structures 1, when the entire package component undergoes a temperature change, the balancing structure 2 can be used to balance the warping deformation generated by the package structure 1 due to the different coefficients of thermal expansion of various materials, can reduce the warping generated by the stacked package, thereby reducing soldering defects such as open solder joints or short circuits caused by warping in the package component, and can improve the assembly yield and efficiency of the terminal manufacturer and the reliability in the actual application of the terminal product.
[0127] The collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved in this disclosure all comply with the provisions of relevant laws and regulations and do not violate public order and good customs.
[0128] It should be noted that personal information from users should be collected for legal and reasonable purposes and should not be shared or sold outside of these legal uses. Additionally, such collection / sharing should be carried out after obtaining the informed consent of the user, including but not limited to notifying the user to read the user agreement / user notice and sign an agreement / authorization including authorizing relevant user information before the user uses the function. Furthermore, any necessary steps should be taken to safeguard and secure access to such personal information data and ensure that others with access to the personal information data comply with their privacy policies and procedures.
[0129] This disclosure anticipates providing embodiments that allow users to selectively block the use or access of personal information data. That is, this disclosure anticipates providing hardware and / or software to prevent or block access to such personal information data. Once personal information data is no longer needed, the risk can be minimized by restricting data collection and deleting the data. Additionally, when applicable, personal identifiers are removed from such personal information to protect the privacy of the user.
[0130] In the description of the foregoing embodiments, the descriptions referring to terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of this disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. Additionally, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0131] Furthermore, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of such features. In the description of this disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined.
[0132] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations in which functions may be executed not in the order shown or discussed, including in a substantially simultaneous manner according to the involved functions or in a reverse order, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.
[0133] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered a sequenced list of executable instructions for implementing a logical function and can be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. As used in this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection having one or more wires (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable medium on which a program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, interpretation, or otherwise processing as appropriate, and then storing it in a computer memory.
[0134] It should be understood that various parts of the present disclosure can be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, multiple steps or methods can be implemented in software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one of the following techniques known in the art or a combination thereof can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.
[0135] Those of ordinary skill in the art can understand that all or part of the steps carried out in implementing the above-described embodiment methods can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiment.
[0136] In addition, in each of the various embodiments of the present disclosure, the functional units can be integrated in a processing module, or each unit can exist physically alone, or two or more units can be integrated in a module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.
[0137] The above-mentioned storage medium can be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present disclosure.
Claims
1. An encapsulation component, characterized in that, The encapsulation component includes a plurality of encapsulation structures arranged in a stacked manner, wherein a balance structure is provided on at least one of the plurality of encapsulation structures arranged in a stacked manner to balance the warping deformation generated by the encapsulation structure.
2. The encapsulation component according to claim 1, wherein Each of the encapsulation structures includes: a substrate, and the substrates of the plurality of encapsulation structures are parallel to each other; a chip disposed on the first surface of the substrate, wherein the balance structure is provided on the first surface and / or the second surface of the substrate of the at least one encapsulation structure.
3. The encapsulation component according to claim 2, wherein The balance structure at least partially surrounds the chip.
4. The encapsulation component according to claim 3, characterized in that, The balance structure includes an annular structural block, and the chip is located at the center of the annular structural block.
5. The encapsulation component according to claim 3, characterized in that The balance structure includes a first strip-shaped structural block and a second strip-shaped structural block, and the first strip-shaped structural block and the second strip-shaped structural block are arranged in parallel on both sides of the chip.
6. The encapsulation component according to claim 1, characterized in that The stiffness corresponding to the balance structure is greater than a preset stiffness threshold.
7. The encapsulation component according to claim 1, wherein The material of the balance structure is at least one of copper, stainless steel, and ceramic.
8. The encapsulation component according to any one of claims 1-7, the encapsulation component includes a first encapsulation structure and a second encapsulation structure arranged in a stacked manner, the first encapsulation structure includes a first substrate and a first chip, the second encapsulation structure includes a second substrate and a second chip, the first chip includes a logic chip, and the second chip includes a storage chip.
9. A manufacturing method of a packaging component, characterized in that, including: During the manufacturing process of the encapsulation component, a balance structure is provided on at least one of the plurality of encapsulation structures arranged in a stacked manner of the encapsulation component to balance the warping deformation generated by the encapsulation structure.
10. The manufacturing method according to claim 9, characterized in that, The encapsulation component includes a first encapsulation structure and a second encapsulation structure arranged in a stacked manner, the first encapsulation structure includes a first substrate and a first chip, the second encapsulation structure includes a second substrate and a second chip, manufacturing the encapsulation component includes: setting the first chip on the first surface of the first substrate, and setting the balance structure on the first surface of the first substrate and / or the second surface of the second substrate; connecting the first surface of the first substrate to the second surface of the second substrate through a connecting member, and making the balance structure at least partially surround the first chip; encapsulating the first chip with a molding compound to obtain the first encapsulation structure; setting the second chip on the first surface of the second substrate to obtain the second encapsulation structure.
11. The manufacturing method according to claim 9, characterized in that, The encapsulation component includes a first encapsulation structure and a second encapsulation structure arranged in a stacked manner, the first encapsulation structure includes a first substrate and a first chip, the second encapsulation structure includes a second substrate and a second chip, manufacturing the encapsulation component includes: setting the first chip on the first surface of the first substrate; connecting the first surface of the first substrate to the second surface of the second substrate through a connecting member; encapsulating the first chip with a molding compound to obtain the first encapsulation structure; setting the second chip on the first surface of the second substrate to obtain the second encapsulation structure, and setting the balance structure on the first surface of the second substrate, the balance structure at least partially surrounds the second chip.
12. The manufacturing method according to claim 9, characterized in that, The encapsulation component includes a first encapsulation structure and a second encapsulation structure which are stacked. The first encapsulation structure includes a first substrate and a first chip, and the second encapsulation structure includes a second substrate and a second chip. Manufacturing the encapsulation component includes: Providing a connecting member, the first chip, and the balancing structure on a second surface of the second substrate, and the balancing structure at least partially surrounds the first chip; Encapsulating the connecting member and the first chip with a molding compound; Connecting a first surface of the first substrate to the second surface of the second substrate through the connecting member to obtain the first encapsulation structure; Providing the second chip on a first surface of the second substrate to obtain the second encapsulation structure.
13. The manufacturing method according to claim 9, characterized in that, The encapsulation component includes a first encapsulation structure and a second encapsulation structure which are stacked. The first encapsulation structure includes a first substrate and a first chip, and the second encapsulation structure includes a second substrate and a second chip. Manufacturing the encapsulation component includes: Providing a connecting member and the first chip on a second surface of the second substrate; Encapsulating the connecting member and the first chip with a molding compound; Connecting a first surface of the first substrate to the second surface of the second substrate through the connecting member to obtain the first encapsulation structure; Providing the second chip on a first surface of the second substrate to obtain the second encapsulation structure, and providing the balancing structure on the first surface of the second substrate, and the balancing structure at least partially surrounds the second chip.