Bootstrap circuit-based undervoltage locking protection circuit
The BOOST-SW voltage monitoring of the BUCK chip is optimized through the bootstrap circuit, and the bandgap reference voltage and zero temperature coefficient current are used to solve the problem of poor consistency of the BOOST-SW voltage monitoring threshold, achieving high-precision and low-power undervoltage locking protection.
Patent Information
- Application Number
- CN202510479339.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-16
- Publication Date
- 2025-07-25
AI Technical Summary
In the prior art, the BOOST-SW voltage monitoring threshold of the BUCK chip is affected by the MOS tube threshold and resistance value, resulting in process and temperature sensitivity, poor threshold consistency, and difficult to meet high-precision requirements.
The undervoltage locking protection circuit is adopted based on the bootstrap circuit, and composed of a voltage divider unit, a comparison unit and a adjustment unit, and the bandgap reference voltage and zero temperature coefficient current are used to optimize the detection threshold, making it insensitive to process and temperature, and hysteresis is introduced to prevent output jitter.
It realizes that the detection threshold deviation range is small, the consistency is strong, and the current consumption is low. The process deviation can be eliminated without increasing the area and the monitoring threshold accuracy can be improved.
Smart Images
Figure CN120377175A_ABST
Abstract
Description
Technical Field
[0001] The present invention belongs to the technical field of power management chips, and particularly relates to an undervoltage lockout protection circuit based on a bootstrap circuit. Background Art
[0002] When an N-type MOS transistor is used as the upper power transistor in a DC buck converter circuit (BUCK), the voltage domain in which its driving stage circuit operates needs to be higher than the input voltage. Therefore, most BUCK chips need to design a BOOST-SW voltage domain. The ground of this voltage domain is the power switch node voltage (SW). Since this voltage is a floating voltage, the BOOST voltage is a floating voltage, and the voltage difference between it and SW is a constant voltage. The driving circuit of the upper power transistor operates in the BOOST-SW voltage domain. To ensure the normal operation of the driving circuit, it is necessary to monitor the BOOST-SW voltage. When it is lower than the set threshold, the driving circuit is set, thereby protecting the BUCK chip.
[0003] For monitoring the BOOST-SW voltage, the prior art usually uses the threshold of the MOS transistor for monitoring, and the circuit structure is as Figure 1 shown, where R3 can be replaced by a MOS transistor. The working principle of this architecture is as follows: As the BOOST-SW voltage difference increases, the voltage VA at point A increases accordingly. When the pulling-down ability of M3 by the VA voltage is greater than the pulling-up ability of M2, the level at point B changes from high to low, and BST_UVLO outputs high, indicating that the BOOST-SW voltage is normal. At this time, M4 will be turned on to short-circuit R3, further increasing the pulling-down ability of M3. When the BOOST-SW voltage difference decreases to reach the threshold, the pulling-down ability of M3 is weaker than that of M2. At this time, point B is pulled up to a high level, BST_UVLO outputs low, and M4 is turned off, further reducing the pulling-down ability of M3. The detection threshold of this circuit is affected by the threshold of MOS transistor M3 and the resistance value of resistor R2. Since these two items are sensitive to process deviations and temperature, when in use, the threshold will deviate greatly due to process and temperature, resulting in poor consistency of the monitoring threshold. When a high threshold accuracy of BST_UVLO is required, Figure 1 the circuit is difficult to meet the standard. In addition, in practical applications, it is more desirable that the threshold change range is small. Summary of the Invention
[0004] The purpose of the present invention is to provide an undervoltage lockout protection circuit based on a bootstrap circuit to solve the technical problem in the above background art that the detection threshold voltage of the prior art is determined by the resistance value of the resistor and the threshold of the MOS transistor, resulting in large threshold deviations affected by process and temperature.
[0005] To achieve the above purpose, the present invention provides the following technical solutions:
[0006] An undervoltage lockout protection circuit based on a bootstrap circuit, which consists of a voltage division unit, a comparison unit, and a trimming unit. The voltage division unit includes resistor R21, resistor R22, resistor R23, and NMOS transistor M25. The comparison unit includes PMOS transistors M21, M22, M23, M24, NMOS transistors M26, M27, resistor R24, resistor R25, bipolar transistors Q21, Q22, and inverter inv21. The trimming unit includes a trimming signal and a level conversion circuit from a low-voltage domain to a high-voltage domain.
[0007] Further, the source of PMOS transistor M21 is connected to the sources of PMOS transistors M22, M23, and M24 and the BOOST port. The source of PMOS transistor M21 also sequentially passes through resistors R21, R22, and R23 and is connected to the SW port. The drain of PMOS transistor M21 is connected to the drains, gates of NMOS transistors M26 and M27. The gate of PMOS transistor M21 is connected to the gates of PMOS transistors M22, the drain of PMOS transistor M22, and the collector of bipolar transistor Q21. The drain of PMOS transistor M23 is connected to the gates of PMOS transistors M23 and M24 and the collector of bipolar transistor Q22. The drain of PMOS transistor M24 is connected to the source of NMOS transistor M27. The drain of NMOS transistor M27 is connected to the sources of NMOS transistors M26 and M25 and the SW port. The base of bipolar transistor Q21 is connected to the connection node A between resistors R21 and R22 and the base of bipolar transistor Q22. The emitter of bipolar transistor Q21 sequentially passes through resistors R24 and R25 and is connected to the SW port. The emitter of bipolar transistor Q22 passes through resistor R25 and is connected to the SW port. The source of NMOS transistor M25 is connected to the connection node between resistors R22 and R23. The gate of NMOS transistor M25 is connected to the output of inverter inv21 and the BST_UVLO port. The input of inverter inv21 is connected to the connection node B between the drain of PMOS transistor M24 and the source of NMOS transistor M27.
[0008] Further, by designing the ratio of resistor R21 to R22 + R23, the detection threshold voltage is set. By controlling the access and short circuit of R23 through NMOS transistor M25, the ratio relationship is adjusted to form a flip hysteresis to prevent output jitter.
[0009] Another object of the present invention is to provide an under-voltage lockout protection circuit based on a bootstrap circuit, which consists of a voltage division unit, a comparison unit, and a reference voltage generation unit. The voltage division unit includes a resistor R41, a resistor R42, a resistor R43, and an NMOS transistor M47. The comparison unit includes a PMOS transistor M41, a PMOS transistor M42, an NMOS transistor M48, a current source IB, and a resistor R44. The reference voltage generation unit includes a PMOS transistor M43, a PMOS transistor M44, an NMOS transistor M45, an NMOS transistor M46, a resistor R45, and an inverter inv41.
[0010] Further, the source of the PMOS transistor M41 is connected to the sources of the PMOS transistor M42, the PMOS transistor M43, and the PMOS transistor M44 to the BOOST port. The source of the PMOS transistor M41 also sequentially passes through the resistor R41, the resistor R42, and the resistor R43 and is connected to the SW port. The drain of the PMOS transistor M41 is connected to the gate of the PMOS transistor M41, the gate of the PMOS transistor M42, the gate of the NMOS transistor M47, the source of the NMOS transistor M48, the output terminal of the inverter inv41, and the BST_UVLO port. The drain of the PMOS transistor M42 is connected to the connection node A between the resistor R41 and the resistor R42, the gate of the NMOS transistor M46, the gate of the NMOS transistor M45, and the connection node C at the upper end of the resistor R44. The lower end of the resistor R44 is connected to the lower end of the resistor R45, the drain of the NMOS transistor M47, and the SW port. The drain of the PMOS transistor M43 is connected to the gate of the PMOS transistor M43, the gate of the PMOS transistor M44, and the source of the NMOS transistor M45. The drain of the PMOS transistor M44 is connected to the connection node B between the input terminal of the inverter inv41 and the source of the NMOS transistor M46. The drain of the NMOS transistor M45 is connected to the drain of the NMOS transistor M46 and the upper end of the resistor R45. The source of the NMOS transistor M47 is connected to the connection node between the resistor R42 and the resistor R43. The gate of the NMOS transistor M48 is connected to the power supply voltage VDD, and the drain of the NMOS transistor M48 is connected to the ground voltage GND through the current source IB.
[0011] Further, the MOS transistors M43 to M46 and the resistor R45 form a comparator for threshold comparison; the resistors R41 to R43 determine the sampling ratio of BOOST-SW and introduce hysteresis; the PMOS transistors M41 to M42 and the resistor R44 form a reference voltage; the IB current is taken from the low-voltage domain, and the NMOS transistor M48 provides voltage withstand protection.
[0012] Further, the value of the IB current and the resistance value of the resistor R44 are determined to determine the input reference voltage value of the comparator. The IB current is taken from the zero-temperature coefficient current generated by the bandgap reference voltage BG, and the resistor R44 has the same resistance type as the bandgap reference voltage BG.
[0013] The present invention has the following beneficial effects:
[0014] 1. The detection flip threshold deviation range is small and the consistency is strong;
[0015] 2. The current consumption is small and can be controlled at about 10 μA;
[0016] 3. The threshold can be adjusted to eliminate the deviation caused by the process;
[0017] 4. Through structural optimization, while ensuring the detection accuracy of the threshold voltage, the threshold adjustment is achieved with little additional area, eliminating the deviation caused by the process.
[0018] The present invention adopts a brand-new detection circuit structure, which can optimize the detection threshold, making it insensitive to process corners and temperature, with better flip threshold consistency, improving the monitoring threshold accuracy and reducing its variation range at the same time. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.
[0020] Figure 1 It is a schematic diagram of the BOOST-SW voltage monitoring circuit structure of the prior art;
[0021] Figure 2 It is a schematic diagram of the circuit structure of Embodiment 1 of the present invention;
[0022] Figure 3 It is a schematic diagram of the design verification circuit structure of the BG circuit of Embodiment 1 of the present invention;
[0023] Figure 4 It is a schematic diagram of the circuit structure of Embodiment 2 of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0024] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts belong to the scope of protection of the present invention.
[0025] Example 1 :
[0026] Refer to Figure 2As shown, an undervoltage lockout protection circuit based on a bootstrap circuit is composed of a voltage division unit, a comparison unit, and a trimming unit. The voltage division unit includes resistor R21, resistor R22, resistor R23, and NMOS transistor M25. The comparison unit includes PMOS transistors M21, M22, M23, M24, NMOS transistors M26, M27, resistor R24, resistor R25, bipolar transistors Q21, Q22, and inverter inv21. The trimming unit includes a trimming signal and a level conversion circuit in the low-voltage to high-voltage domain.
[0027] The source of PMOS transistor M21 is connected to the sources of PMOS transistors M22, M23, and M24 and the BOOST port. The source of PMOS transistor M21 also sequentially passes through resistors R21, R22, and R23 and is connected to the SW port. The drain of PMOS transistor M21 is connected to the drains, gates of NMOS transistors M26 and M27. The gate of PMOS transistor M21 is connected to the gates of PMOS transistors M22, the drain of PMOS transistor M22, and the collector of bipolar transistor Q21. The drain of PMOS transistor M23 is connected to the gates of PMOS transistors M23 and M24 and the collector of bipolar transistor Q22. The drain of PMOS transistor M24 is connected to the source of NMOS transistor M27. The drain of NMOS transistor M27 is connected to the sources of NMOS transistors M26 and M25 and the SW port. The base of bipolar transistor Q21 is connected to the connection node A between resistors R21 and R22 and the base of bipolar transistor Q22. The emitter of bipolar transistor Q21 sequentially passes through resistors R24 and R25 and is connected to the SW port. The emitter of bipolar transistor Q22 passes through resistor R25 and is connected to the SW port. The source of NMOS transistor M25 is connected to the connection node between resistors R22 and R23. The gate of NMOS transistor M25 is connected to the output of inverter inv21 and the BST_UVLO port. The input of inverter inv21 is connected to the connection node B between the drain of PMOS transistor M24 and the source of NMOS transistor M27. Figure 2 In it, "Q21 = 8" and "Q22 = 1" represent proportional relationships.
[0028] The detection voltage of BOOST-SW in this embodiment is determined by voltage-dividing resistors, eliminating the influence of resistor values. Although the resistance value will deviate with temperature and process, if the resistors are matched, their ratio will be fixed, so the detected voltage will not change with the process corner. In addition, by introducing an NPN transistor, the original comparison threshold is converted from the threshold voltage of the MOS transistor to the bandgap voltage reference (BG). By adjusting the circuit, BG can be controlled within a reasonable range and its deviation with temperature can be reduced. Since the threshold voltage still fluctuates greatly with process deviation, to solve this problem, the circuit is generally trimmed to ensure accuracy. Figure 2 In [it], trimming is performed by a trimming unit composed of an input trim signal and a level shift from the low-voltage to high-voltage domain.
[0029] Figure 2 For the circuit structure shown, the circuit on the left side of the dotted line uses resistor voltage division to detect the interpolation of the BOOST-SW voltage. The corresponding voltage-dividing point VA (the voltage of the connection node A) is also the comparison threshold of the circuit on the right side of the dotted line. Therefore, by reasonably designing the ratio of resistors R21 and R22+R23, the detection threshold voltage can be set. At the same time, by controlling the access and short circuit of R23 through NMOS transistor M25, the proportional relationship can be adjusted to form a flip hysteresis to prevent the jitter of the output. Therefore, for the resistance value setting of R21 to R23, the setting of the detection threshold and the hysteresis can be achieved.
[0030] Figure 2 The shown circuit can be modified to Figure 3 the circuit in [it]. Since NMOS transistor M38 and resistor R36 are added, there is a loop in the circuit, and the circuit architecture basically becomes BG. By adjusting resistor R34 and resistor R35, the voltage VA of the connection node A can be adjusted. Regarding the voltage at this point as the BG output voltage for adjustment, the optimal temperature coefficient can be achieved. At this time, the voltage VC of the connection node C is the detection flip threshold voltage. Figure 3The circuit includes PMOS transistors M31, M32, M33, M34, NMOS transistors M36, M37, M38, resistors R31, R32, R33, R34, R35, R36, and bipolar transistors Q31, Q32. The source connection node C of PMOS transistor M31, the sources of PMOS transistors M32, M33, M34, and the source of NMOS transistor M38 are connected to the BOOST port through resistor R36. The source of PMOS transistor M31 is also sequentially connected to the SW port through resistors R31, R32, R33. The drain of PMOS transistor M31 is connected to the drain of NMOS transistor M36, the gate of NMOS transistor M36, and the gate of NMOS transistor M37. The gate of PMOS transistor M31 is connected to the gate of PMOS transistor M32, the drain of PMOS transistor M32, and the collector of bipolar transistor Q31. The drain of PMOS transistor M33 is connected to the gate of PMOS transistor M33, the gate of PMOS transistor M34, and the collector of bipolar transistor Q32. The drain of PMOS transistor M34 is connected to the connection node B between the source of NMOS transistor M37 and the gate of NMOS transistor M38. The drain of NMOS transistor M37 is connected to the source of NMOS transistor M36 and the drain of NMOS transistor M38, which is connected to the SW port. The base of bipolar transistor Q31 is connected to the connection node A between resistors R31 and R32 and the base of bipolar transistor Q32. The emitter of bipolar transistor Q31 is sequentially connected to the SW port through resistors R34, R35. The emitter of bipolar transistor Q32 is connected to the SW port through resistor R35. Figure 3 In “Q31 = 8” and “Q32 = 1”, they represent a proportional relationship.
[0031] Example 2 :
[0032] Refer to Figure 4 As shown, an undervoltage lockout protection circuit based on a bootstrap circuit is composed of a voltage division unit, a comparison unit, and a reference voltage generation unit. The voltage division unit includes resistors R41, R42, R43, and NMOS transistor M47. The comparison unit includes PMOS transistors M41, M42, NMOS transistor M48, current source IB, and resistor R44. The reference voltage generation unit includes PMOS transistors M43, M44, NMOS transistors M45, M46, resistor R45, and inverter inv41.
[0033] The source of PMOS transistor M41 is connected to the BOOST port together with the sources of PMOS transistors M42, M43, and M44. The source of PMOS transistor M41 also sequentially passes through resistors R41, R42, and R43 and is connected to the SW port. The drain of PMOS transistor M41 is connected to the gates of PMOS transistor M41, PMOS transistor M42, the gate of NMOS transistor M47, the source of NMOS transistor M48, the output of inverter inv41, and the BST_UVLO port; the drain of PMOS transistor M42 is connected to the connection node A between resistor R41 and resistor R42, the gate of NMOS transistor M46, the gate of NMOS transistor M45, and the upper end connection node C of resistor R44. The lower end of resistor R44 is connected to the lower end of resistor R45, the drain of NMOS transistor M47, and the SW port; the drain of PMOS transistor M43 is connected to the gate of PMOS transistor M43, the gate of PMOS transistor M44, and the source of NMOS transistor M45; the drain of PMOS transistor M44 is connected to the connection node B between the input of inverter inv41 and the source of NMOS transistor M46; the drain of NMOS transistor M45 is connected to the drain of NMOS transistor M46 and the upper end of resistor R45; the source of NMOS transistor M47 is connected to the connection node between resistor R42 and resistor R43; the gate of NMOS transistor M48 is connected to the power supply voltage VDD, and the drain of NMOS transistor M48 is connected to the ground voltage GND through the current source IB.
[0034] Figure 4 In the circuit, MOS transistors M43 to M46 and resistor R45 form a comparator for threshold comparison; resistors R41 to R43 determine the sampling ratio of BOOST-SW and introduce hysteresis; PMOS transistors M41 to M42 and resistor R44 form a reference voltage. Therefore, the comparison point of this circuit is determined by the two voltages VA (the voltage at connection node A) and VC (the voltage at connection node C). In this embodiment, the IB current is taken from the low-voltage domain, so trimming control can be performed, but the NMOS transistor M48 is required for breakdown voltage protection.
[0035] Figure 4 The circuit determines the input reference voltage value of the comparator by determining the IB current and the resistance value of resistor R44. The current IB is taken from the zero-temperature coefficient current generated by BG. Resistor R44 and BG use the same resistor type to minimize the deviation of the voltage VC at point C. At the same time, trimming is reserved for the current IB. The sizes of PMOS transistors M41 to M42 are preferably taken as large as possible to reduce mismatch. By designing the sizes of PMOS transistors M41 to M42 and resistor R44, while controlling the current consumption, the normal operation of the comparator is ensured. According to the designed value of the reference voltage VC and the flip threshold index, the resistance ratio of resistors R41 to R43 is determined.
[0036] The detection voltage of BOOST-SW in the circuit of this embodiment is determined by voltage-dividing resistors, eliminating the influence of resistor values. Although the resistance values will deviate with temperature and process, if the resistors are matched, their ratio will be fixed, so the detected voltage will not change with the process corner. At the same time, a zero-temperature-coefficient current and a resistor are used to generate a reference threshold voltage, optimizing the consumption area of the triode. Since there is a bandgap reference voltage BG module in the BUCK chip, no additional circuit is required to generate the zero-temperature-coefficient current, and as long as the resistor is of the same type as the resistor in the bandgap reference voltage BG, the generated reference voltage varies little with temperature, reducing its deviation with temperature. In addition, since the reference voltage is generated by a current and a resistor, the current can be trimmed in the low-voltage domain, thereby achieving trimming of the reference voltage. Figure 4 Trimming is performed by inputting a trim signal. By trimming the current in the low-voltage domain, the consumption area of the level shift from low voltage to high voltage can be saved, and the detection threshold accuracy can be ensured. Through structural optimization, the detection threshold voltage can be increased, and while ensuring the detection accuracy of the threshold voltage, the area is basically not increased additionally, realizing trimming of the threshold and eliminating the deviation caused by the process.
[0037] The preferred embodiments of the present invention disclosed above are only used to help illustrate the present invention. The preferred embodiments do not describe all the details in detail, nor limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. These embodiments are selected and specifically described in this specification to better explain the principle and practical application of the present invention, so that those skilled in the relevant technical field can understand and utilize the present invention well.
Claims
1. An undervoltage lockout protection circuit based on a bootstrap circuit, characterized in that It consists of a voltage division unit, a comparison unit, and a trimming unit. The voltage division unit includes resistor R21, resistor R22, resistor R23, and NMOS transistor M25. The comparison unit includes PMOS transistors M21, M22, M23, M24, NMOS transistors M26, M27, resistor R24, resistor R25, bipolar transistors Q21, Q22, and inverter inv21. The trimming unit includes a trimming signal and a level conversion circuit from the low-voltage to high-voltage domain.
2. The under-voltage lockout protection circuit based on a bootstrap circuit according to claim 1, characterized in that, The source of PMOS transistor M21 is connected to the sources of PMOS transistors M22, M23, and M24 at the BOOST port. The source of PMOS transistor M21 also sequentially passes through resistors R21, R22, and R23 and is connected to the SW port. The drain of PMOS transistor M21 is connected to the drains, gates of NMOS transistors M26 and M27. The gate of PMOS transistor M21 is connected to the gates of PMOS transistors M22, the drain of PMOS transistor M22, and the collector of bipolar transistor Q21. The drain of PMOS transistor M23 is connected to the gates of PMOS transistors M23 and M24 and the collector of bipolar transistor Q22. The drain of PMOS transistor M24 is connected to the source of NMOS transistor M27. The drain of NMOS transistor M27 is connected to the sources of NMOS transistors M26 and M25 and the SW port. The base of bipolar transistor Q21 is connected to the connection node A between resistors R21 and R22 and the base of bipolar transistor Q22. The emitter of bipolar transistor Q21 sequentially passes through resistors R24 and R25 and is connected to the SW port. The emitter of bipolar transistor Q22 passes through resistor R25 and is connected to the SW port. The source of NMOS transistor M25 is connected to the connection node between resistors R22 and R23. The gate of NMOS transistor M25 is connected to the output of inverter inv21 and the BST_UVLO port. The input of inverter inv21 is connected to the connection node B between the drain of PMOS transistor M24 and the source of NMOS transistor M27.
3. The undervoltage lockout protection circuit based on a bootstrap circuit according to claim 2, wherein By designing the ratio of resistor R21 to R22 + R23, the detection threshold voltage is set. By controlling the access and short circuit of R23 through NMOS transistor M25, the ratio relationship is adjusted to form a flip hysteresis to prevent output jitter.
4. An undervoltage lockout protection circuit based on a bootstrap circuit, characterized in that It consists of a voltage division unit, a comparison unit, and a reference voltage generation unit. The voltage division unit includes resistor R41, resistor R42, resistor R43, and NMOS transistor M47. The comparison unit includes PMOS transistors M41, M42, NMOS transistor M48, current source IB, and resistor R44. The reference voltage generation unit includes PMOS transistors M43, M44, NMOS transistors M45, M46, resistor R45, and inverter inv41.
5. The under-voltage lockout protection circuit based on a bootstrap circuit according to claim 4, characterized in that, The source of PMOS transistor M41 is connected to the BOOST port together with the sources of PMOS transistors M42, M43, and M44. The source of PMOS transistor M41 also sequentially passes through resistors R41, R42, and R43 and is connected to the SW port. The drain of PMOS transistor M41 is connected to the gates of PMOS transistors M41, M42, the gate of NMOS transistor M47, the source of NMOS transistor M48, the output of inverter inv41, and the BST_UVLO port. The drain of PMOS transistor M42 is connected to the connection node A between resistors R41 and R42, the gate of NMOS transistor M46, the gate of NMOS transistor M45, and the connection node C at the upper end of resistor R44. The lower end of resistor R44 is connected to the lower end of resistor R45, the drain of NMOS transistor M47, and the SW port. The drain of PMOS transistor M43 is connected to the gates of PMOS transistors M43, M44, and the source of NMOS transistor M45. The drain of PMOS transistor M44 is connected to the connection node B between the input of inverter inv41 and the source of NMOS transistor M46. The drain of NMOS transistor M45 is connected to the drains of NMOS transistors M46 and the upper end of resistor R45. The source of NMOS transistor M47 is connected to the connection node between resistors R42 and R43. The gate of NMOS transistor M48 is connected to the power supply voltage VDD, and the drain of NMOS transistor M48 is connected to the ground voltage GND through current source IB.
6. The under-voltage lockout protection circuit based on a bootstrap circuit according to claim 5, characterized in that, MOS transistors M43 to M46 and resistor R45 form a comparator for threshold comparison; resistors R41 to R43 determine the sampling ratio of BOOST - SW and introduce hysteresis. PMOS transistors M41 to M42 and resistor R44 form a reference voltage; the IB current is taken from the low - voltage domain, and NMOS transistor M48 provides breakdown voltage protection.
7. The under-voltage lockout protection circuit based on a bootstrap circuit according to claim 6, characterized in that, Determine the value of the IB current and the resistance value of resistor R44, determine the input reference voltage value of the comparator. The IB current is taken from the zero - temperature - coefficient current generated by the bandgap reference voltage BG, and resistor R44 has the same resistor type as the bandgap reference voltage BG.