THD optimization circuit and control method

Abstract

The THD optimization circuit comprises a COT control circuit, a comparator CMP3, a comparator CMP4, an inverter G2, an NAND gate G3, an NAND gate G4 and an AND gate G5, the inverted input end of the comparator CMP3 is connected with a reference voltage Reference 2, the normal input end of the comparator CMP3 is connected with the output end of a slope generation circuit, the normal input end of the comparator CMP4 is connected with a signal VCS, the inverted input end of the comparator CMP4 is connected with a reference voltage Reference 3, and the output end of the slope generation circuit is connected with the output end of the AND gate G5. The output end of the comparator CMP4 is connected with the input end of the phase inverter G2, the output ends of the phase inverter G2 and the comparator CMP3 are connected with the input end of the NAND gate G3, the output ends of the phase inverter G2 and the NAND gate G3 are connected with the input end of the NAND gate G4, and the output end of the NAND gate G4 is connected with the second input end of the AND gate G5. The THD of the AC / DC power supply is reduced, and the power supply efficiency is improved.

Description

Technical Field

[0001] The present invention relates to an optimized circuit and control method, in particular to a THD optimized circuit and control method, belonging to the technical field of semiconductor integrated circuits. Background Art

[0002] More and more electrical devices are connected to the power grid, and most of these electrical devices adopt an efficient switched-mode power supply architecture rather than a pure resistive power supply. This will cause the input current not to accurately follow the change of the input voltage. Since the input AC voltage is a periodic sine wave, harmonic current is used to characterize the deviation between the input current and the sine wave. The harmonic current will generate reactive power, increase power grid losses, accelerate the aging of the power grid and electrical devices, and interfere with communication and audio / video devices in the power grid. Total harmonic distortion THD is the sum of all additional harmonic levels. With the continuous increase in the scale of electrical devices and the power of individual electrical devices, the requirements for the THD parameter of the power supply are also getting higher and higher.

[0003] As Figure 5 shown, the AC / DC power supply system with the COT control method in the prior art includes a rectifier bridge B1, a capacitor C1, a capacitor C2, a capacitor C3, a freewheeling diode D1, a resistor RO, a resistor RS, an inductor L1, a power switch M1, and a power supply controller U1. The first input terminal of the rectifier bridge B1 is connected to the AC L line, the second input terminal of the rectifier bridge B1 is connected to the AC N line, the first output terminal of the rectifier bridge B1 is connected to one end of the capacitor C1, the VIN pin of the power supply controller U1, the cathode of the freewheeling diode D1, one end of the capacitor C2, and one end of the resistor R0 to generate a signal VIN. The second output terminal of the rectifier bridge B1 and the other end of the capacitor C1 are grounded. The VCC pin of the power supply controller U1 is connected to one end of the capacitor C3, and the other end of the capacitor C3 and the GND pin of the power supply controller U1 are grounded. The GATE pin of the power supply controller U1 is connected to the gate of the power switch M1. The CS pin of the power supply controller U1 is connected to one end of the power switch M1 and one end of the resistor RS, and the other end of the resistor RS is grounded. The other end of the power switch M1 is connected to the anode of the freewheeling diode D1 and one end of the inductor L1 to generate a signal VDRAIN. The other end of the inductor L1 is connected to the other end of the capacitor C2 and the other end of the resistor R0.

[0004] As Figure 6As shown in the figure, the COT control circuit of the prior art is included in the power controller U1, and the COT control circuit includes a sample and hold module Sample&Hold, a ramp generation circuit Ramp Generator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS flip-flop G1, and a drive circuit module Driver. The input terminal of the sample and hold module Sample&Hold is connected to the signal VCS. The output terminal of the sample and hold module Sample&Hold is connected to the inverting input terminal of the error amplifier EA. The non-inverting input terminal of the error amplifier EA is connected to the reference voltage Reference1. The output terminal of the error amplifier EA is connected to the inverting input terminal of the comparator CMP1. The output terminal of the ramp generation circuit Ramp Generator is connected to the non-inverting input terminal of the comparator CMP1. The output terminal of the comparator CMP1 is connected to the R terminal of the RS flip-flop G1. The non-inverting input terminal of the comparator CMP2 is grounded. The output terminal of the comparator CMP2 is connected to the S terminal of the RS flip-flop G1 and generates the signal ZCD. The Q terminal of the RS flip-flop G1 is connected to the input terminal of the drive circuit module Driver and generates the signal PWM. The output terminal of the drive circuit module Driver is connected to the inverting input terminal of the comparator CMP2 and generates the signal GATE.

[0005] As Figure 7The figure shows a schematic waveform diagram of an existing AC / DC power supply system. Among them, the signal VIN is the voltage of the VIN pin of the power supply controller U1, the signal GATE is the voltage of the GATE pin of the power supply controller U1, the signal VDRAIN is the drain voltage of the power switch M1, the signal VCS is the voltage of the CS pin of the power supply controller U1, and the signal VOUT is the voltage across the second capacitor C2. At time T0, the signal VIN enters the AC valley region. As the signal VIN decreases, the rising slope of the signal VCS during the conduction time of the power switch M1, that is, during the time when the GATE voltage is high, gradually becomes smaller. Until time T1, controlled by the COT control method, the conduction time of the power switch M1 in this stage remains the first fixed TON time, and the turn-off time gradually decreases. At time T1, the turn-off time of the power switch M1 reaches the minimum. At the same time, the VIN voltage is also very close to the VOUT level. In this stage, the conduction time of the power switch M1 is still fixed at the first fixed TON time or close to the first fixed TON time, and the turn-off time remains the minimum until time T3. In the stage from T1 to T3 including time T2, since the first fixed TON time comes from the COT loop, in some system parameters and / or operating conditions, it will be relatively small, resulting in a very low peak value of the signal VCS for each switching cycle and a high switching frequency. Due to the existence of parasitics and delays, in the stage from T1 to T3, the signal VCS will generate relatively large negative current spikes at high frequency and for each cycle, thereby increasing the THD of the entire power supply. At time T3, the amplitude of the input AC voltage enters the rising cycle and is significantly higher than the signal VOUT. The VIN voltage follows the amplitude of the input AC voltage and starts to rise. The conduction time of the power switch M1 is still the first fixed TON time, and the turn-off time of the power switch M1 gradually increases until time T4. At time T4, the signal VIN exits the AC valley region.

[0006] As can be seen from the above, an existing buck AC / DC converter architecture using the COT control method is widely used because of its simple control method, stable operation, and simple and low-cost peripherals. However, as the power of the power supply increases and the output voltage VOUT rises, in the estimated region of the input AC voltage, the deviation of the input current from the sinusoidal trajectory of the input voltage becomes larger, the total harmonic distortion increases, and the switching frequency in the valley region is relatively high. At this time, because the inductor excitation energy is extremely small, the high switching frequency will cause the power device to release more negative current spikes. This negative current spike is unexpected and will also increase the total harmonic distortion. Moreover, the power switch of the power supply also increases losses at this time. Summary of the Invention

[0007] The technical problem to be solved by the present invention is to provide a THD optimization circuit and a control method to reduce the THD of a buck AC / DC power supply in COT control mode.

[0008] To solve the above technical problem, the technical solution adopted by the present invention is: A THD optimization circuit includes a COT control circuit, a comparator CMP3, a comparator CMP4, an inverter G2, a NAND gate G3, a NAND gate G4, and an AND gate G5. The inverting input terminal of the comparator CMP3 is connected to a reference voltage Reference2. The non-inverting input terminal of the comparator CMP3 is connected to the output terminal of a ramp generation circuit Ramp Generator of the COT control circuit. The output terminal of the comparator CMP3 is connected to the first input terminal of the NAND gate G3. The non-inverting input terminal of the comparator CMP4 is connected to a signal VCS. The inverting input terminal of the comparator CMP4 is connected to a reference voltage Reference3. The output terminal of the comparator CMP4 is connected to the input terminal of the inverter G2. The output terminal of the inverter G2 is connected to the second input terminal of the NAND gate G3 and the second input terminal of the NAND gate G4. The output terminal of the NAND gate G3 is connected to the first input terminal of the NAND gate G4. The output terminal of the NAND gate G4 is connected to the second input terminal of the AND gate G5. The output terminal of the AND gate G5 is connected to the R terminal of an RS flip-flop G1 of the COT control circuit.

[0009] Further, the COT control circuit includes a sample and hold module Sample&Hold, a ramp generation circuit RampGenerator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS flip-flop G1, and a drive circuit module Driver. The input terminal of the sample and hold module Sample&Hold is connected to a signal VCS. The output terminal of the sample and hold module Sample&Hold is connected to the inverting input terminal of the error amplifier EA. The non-inverting input terminal of the error amplifier EA is connected to a reference voltage Reference1. The output terminal of the error amplifier EA is connected to the inverting input terminal of the comparator CMP1. The output terminal of the ramp generation circuit Ramp Generator is connected to the non-inverting input terminal of the comparator CMP1. The output terminal of the comparator CMP1 is connected to the first input terminal of the AND gate G5. The output terminal of the AND gate G5 is connected to the R terminal of the RS flip-flop G1. The non-inverting input terminal of the comparator CMP2 is grounded. The inverting input terminal of the comparator CMP2 is connected to a signal VCS. The output terminal of the comparator CMP2 is connected to the S terminal of the RS flip-flop G1 and generates a signal ZCD. The Q terminal of the RS flip-flop G1 is connected to the input terminal of the drive circuit module Driver and generates a signal PWM. The output terminal of the drive circuit module Driver generates a signal GATE.

[0010] Further, only one of the reference voltages Reference2 and Reference3 is a variable comparison reference voltage.

[0011] Further, the variable comparison reference voltage is generated by a variable comparison reference voltage circuit, which includes a voltage division and peak detection module Divider&Peak Sample and a compensation circuit module Compensation. The input end of the voltage division and peak detection module Divider&Peak Sample is connected to the signal VIN. The output end of the voltage division and peak detection module Divider&Peak Sample is connected to the input end of the compensation circuit module Compensation and generates a peak sampling voltage VIN_PEAK. The output end of the compensation circuit module Compensation generates a variable comparison reference voltage.

[0012] Further, when the reference voltage Reference3 is the variable comparison reference voltage, within the range [PEAK1, PEAK2], the value of the reference voltage Reference3 decreases as the peak sampling voltage VIN_PEAK increases, where PEAK1 and PEAK2 are constants.

[0013] Further, when the reference voltage Reference2 is the variable comparison reference voltage, within the range [PEAK1, PEAK2], the value of the reference voltage Reference2 increases as the peak sampling voltage VIN_PEAK increases, where PEAK1 and PEAK2 are constants.

[0014] A control method for a THD optimization circuit includes the following steps: The voltage divider and peak detection module Divider & Peak Sample obtains the peak sampling voltage VIN_PEAK through voltage division and peak sampling. The compensation circuit module Compensation generates a variable comparison reference voltage Reference3 according to the peak sampling voltage VIN_PEAK. The comparator CMP4 obtains the signal of the first section of the GATE pulse width by comparing the signal VCS with the variable comparison reference voltage Reference3. The comparator CMP3 obtains the signal of the first section of the GATE pulse width by comparing the ramp generation circuit Ramp The output signal of the Generator and the reference voltage Reference2 are used to obtain the signal of the second section that takes over the GATE pulse width; when the moment when the output signal of the comparator CMP1 flips to logic high is after the moment when the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP1 flips to logic high; when the moment when the output signal of the comparator CMP1 flips to logic high is before the moment when the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP4 flips to logic high; when the output signal of the comparator CMP3 flips to logic high and the output signal of the comparator CMP4 still remains logic low, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP3 flips to logic high.

[0015] A control method for a THD optimization circuit comprises the following steps: The Divider&Peak Sample module obtains the peak sampled voltage VIN_PEAK through voltage division and peak sampling. The Compensation circuit module generates a varying comparison reference voltage Reference2 based on the peak sampled voltage VIN_PEAK. The comparator CMP4 obtains the signal for the first-stage takeover GATE pulse width duration by comparing the signal VCS and the reference voltage Reference3. The comparator CMP3 obtains the signal for the second-stage takeover GATE pulse width duration by comparing the output signal of the Ramp Generator and the varying comparison reference voltage Reference2. When the output signal of the comparator CMP1 flips to logic high after the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse is determined by the moment when the output signal of the comparator CMP1 flips to logic high. When the output signal of the comparator CMP1 flips to logic high before the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse is determined by the moment when the output signal of the comparator CMP4 flips to logic high. When the output signal of the comparator CMP3 flips to logic high and the output signal of the comparator CMP4 remains logic low, the duration of the GATE pulse is determined by the moment when the output signal of the comparator CMP3 flips to logic high.

[0016] Compared with the prior art, the present invention has the following advantages and effects: 1. The present invention performs a series of compensations on the control method in the valley region of the input AC voltage, enabling the input current to better follow the sinusoidal trajectory of the input AC voltage, improving the PF value of the power supply, and reducing the THD value of the power supply. 2. The present invention reduces the switching frequency in the valley region and reduces the negative current disturbance caused by switching in the valley region, thereby reducing the THD of the buck-type AC / DC power supply with the COT control method and improving the power supply efficiency. Brief Description of the Drawings

[0017] Figure 1 is a schematic diagram of Embodiment 1 of a THD optimization circuit of the present invention.

[0018] Figure 2 is a schematic diagram of Embodiment 2 of a THD optimization circuit of the present invention.

[0019] Figure 3 is a waveform schematic diagram of the varying comparison reference voltage of the present invention.

[0020] Figure 4 is a waveform schematic diagram of the AC / DC power supply system where the THD optimization circuit of the present invention is located.

[0021] Figure 5 It is a schematic diagram of an AC / DC power supply system with a COT control method of the prior art.

[0022] Figure 6 It is a schematic diagram of a COT control circuit of the prior art.

[0023] Figure 7 It is a waveform schematic diagram of an AC / DC power supply system of the prior art. Specific embodiments

[0024] In order to elaborate in detail the technical solutions adopted by the present invention to achieve the predetermined technical objectives, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only partial embodiments of the present invention, rather than all embodiments, and, without creative efforts, the technical means or technical features in the embodiments of the present invention can be replaced. The present invention will be described in detail below with reference to the drawings and in conjunction with the embodiments.

[0025] Embodiment 1. As Figure 1 shown, a THD optimization circuit of the present invention includes a COT control circuit, a comparator CMP3, a comparator CMP4, an inverter G2, a NAND gate G3, a NAND gate G4, and an AND gate G5. The inverting input terminal of the comparator CMP3 is connected to a reference voltage Reference2, the non-inverting input terminal of the comparator CMP3 is connected to the output terminal of a ramp generation circuit RampGenerator of the COT control circuit, the output terminal of the comparator CMP3 is connected to the first input terminal of the NAND gate G3, the non-inverting input terminal of the comparator CMP4 is connected to a signal VCS, the inverting input terminal of the comparator CMP4 is connected to a reference voltage Reference3, the output terminal of the comparator CMP4 is connected to the input terminal of the inverter G2, the output terminal of the inverter G2 is connected to the second input terminal of the NAND gate G3 and the second input terminal of the NAND gate G4, the output terminal of the NAND gate G3 is connected to the first input terminal of the NAND gate G4, the output terminal of the NAND gate G4 is connected to the second input terminal of the AND gate G5, and the output terminal of the AND gate G5 is connected to the R terminal of an RS flip-flop G1 of the COT control circuit.

[0026] The COT control circuit includes a sample and hold module Sample&Hold, a ramp generation circuit Ramp Generator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS flip-flop G1, and a drive circuit module Driver. The input terminal of the sample and hold module Sample&Hold is connected to the signal VCS. The output terminal of the sample and hold module Sample&Hold is connected to the inverting input terminal of the error amplifier EA. The non-inverting input terminal of the error amplifier EA is connected to the reference voltage Reference1. The output terminal of the error amplifier EA is connected to the inverting input terminal of the comparator CMP1. The output terminal of the ramp generation circuit Ramp Generator is connected to the non-inverting input terminal of the comparator CMP1. The output terminal of the comparator CMP1 is connected to the first input terminal of the AND gate G5. The output terminal of the AND gate G5 is connected to the R terminal of the RS flip-flop G1. The non-inverting input terminal of the comparator CMP2 is grounded. The inverting input terminal of the comparator CMP2 is connected to the signal VCS. The output terminal of the comparator CMP2 is connected to the S terminal of the RS flip-flop G1 and generates the signal ZCD. The Q terminal of the RS flip-flop G1 is connected to the input terminal of the drive circuit module Driver and generates the signal PWM. The output terminal of the drive circuit module Driver generates the signal GATE.

[0027] The reference voltage Reference3 is a variable comparison reference voltage. The variable comparison reference voltage is generated by a variable comparison reference voltage circuit. The variable comparison reference voltage circuit includes a voltage division and peak detection module Divider&Peak Sample and a compensation circuit module Compensation. The input terminal of the voltage division and peak detection module Divider&Peak Sample is connected to the signal VIN. The output terminal of the voltage division and peak detection module Divider&Peak Sample is connected to the input terminal of the compensation circuit module Compensation and generates the peak sampled voltage VIN_PEAK. The output terminal of the compensation circuit module Compensation generates the variable comparison reference voltage.

[0028] Such as Figure 3As shown in (a) of the figure, Vref1 and Vref2 are a set of constant values, where Vref1 > Vref2. When the reference voltage Reference3 is a variable comparison reference voltage, within the interval [PEAK1, PEAK2], the value of the reference voltage Reference3 decreases as the peak sampling voltage VIN_PEAK increases, that is, it gradually changes from Vref1 to Vref2, where PEAK1 and PEAK2 are constant values, and PEAK2 > PEAK1. When VIN_PEAK ≤ PEAK1, Reference3 remains unchanged at Vref1; when VIN ≥ PEAK2, Reference3 remains unchanged at Vref2.

[0029] A control method for a THD optimization circuit, comprising the following steps: The voltage divider and peak detection module Divider&Peak Sample obtains the peak sampling voltage VIN_PEAK through voltage division and peak sampling. The compensation circuit module Compensation generates a variable comparison reference voltage Reference3 based on the peak sampling voltage VIN_PEAK. The comparator CMP4 obtains the signal for the first-stage takeover GATE pulse width duration by comparing the signal VCS and the variable comparison reference voltage Reference3. The comparator CMP3 obtains the signal for the second-stage takeover GATE pulse width duration by comparing the output signal of the ramp generation circuit Ramp Generator and the reference voltage Reference2. When the moment when the output signal of the comparator CMP1 flips to logic high is after the moment when the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP1 flips to logic high. When the moment when the output signal of the comparator CMP1 flips to logic high is before the moment when the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP4 flips to logic high. When the output signal of the comparator CMP3 flips to logic high and the output signal of the comparator CMP4 still remains logic low, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP3 flips to logic high.

[0030] Example 2. As Figure 2As shown in the figure, a THD optimization circuit of the present invention includes a COT control circuit, a comparator CMP3, a comparator CMP4, an inverter G2, a NAND gate G3, a NAND gate G4, and an AND gate G5. The inverting input terminal of the comparator CMP3 is connected to a reference voltage Reference2. The non-inverting input terminal of the comparator CMP3 is connected to the output terminal of the ramp generation circuit RampGenerator of the COT control circuit. The output terminal of the comparator CMP3 is connected to the first input terminal of the NAND gate G3. The non-inverting input terminal of the comparator CMP4 is connected to a signal VCS. The inverting input terminal of the comparator CMP4 is connected to a reference voltage Reference3. The output terminal of the comparator CMP4 is connected to the input terminal of the inverter G2. The output terminal of the inverter G2 is connected to the second input terminal of the NAND gate G3 and the second input terminal of the NAND gate G4. The output terminal of the NAND gate G3 is connected to the first input terminal of the NAND gate G4. The output terminal of the NAND gate G4 is connected to the second input terminal of the AND gate G5. The output terminal of the AND gate G5 is connected to the R terminal of the RS flip-flop G1 of the COT control circuit.

[0031] The COT control circuit includes a sample and hold module Sample&Hold, a ramp generation circuit Ramp Generator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS flip-flop G1, and a driver circuit module Driver. The input terminal of the sample and hold module Sample&Hold is connected to a signal VCS. The output terminal of the sample and hold module Sample&Hold is connected to the inverting input terminal of the error amplifier EA. The non-inverting input terminal of the error amplifier EA is connected to a reference voltage Reference1. The output terminal of the error amplifier EA is connected to the inverting input terminal of the comparator CMP1. The output terminal of the ramp generation circuit Ramp Generator is connected to the non-inverting input terminal of the comparator CMP1. The output terminal of the comparator CMP1 is connected to the first input terminal of the AND gate G5. The output terminal of the AND gate G5 is connected to the R terminal of the RS flip-flop G1. The non-inverting input terminal of the comparator CMP2 is grounded. The inverting input terminal of the comparator CMP2 is connected to a signal VCS. The output terminal of the comparator CMP2 is connected to the S terminal of the RS flip-flop G1 and generates a signal ZCD. The Q terminal of the RS flip-flop G1 is connected to the input terminal of the driver circuit module Driver and generates a signal PWM. The output terminal of the driver circuit module Driver generates a signal GATE.

[0032] The reference voltage Reference2 is a variable comparison reference voltage. The variable comparison reference voltage is generated by a variable comparison reference voltage circuit, which includes a voltage division and peak detection module Divider&Peak Sample and a compensation circuit module Compensation. The input terminal of the voltage division and peak detection module Divider&Peak Sample is connected to the signal VIN. The output terminal of the voltage division and peak detection module Divider&Peak Sample is connected to the input terminal of the compensation circuit module Compensation and generates a peak sampling voltage VIN_PEAK. The output terminal of the compensation circuit module Compensation generates the variable comparison reference voltage.

[0033] As Figure 3 shown in (b) of, Vref3 and Vref4 are a set of constants, and Vref3 > Vref4. When the reference voltage Reference2 is the variable comparison reference voltage, the value of the reference voltage Reference2 increases with the increase of the peak sampling voltage VIN_PEAK in the interval [PEAK1, PEAK2], that is, it gradually changes from Vref4 to Vref3, where PEAK1 and PEAK2 are constants, and PEAK2 > PEAK1. When VIN_PEAK ≤ PEAK1, Reference2 remains unchanged at Vref4. When VIN ≥ PEAK2, Reference2 remains unchanged at Vref3.

[0034] A control method for a THD optimization circuit includes the following steps: The Divider&Peak Sample module obtains the peak sampled voltage VIN_PEAK through voltage division and peak sampling. The Compensation circuit module generates a varying comparison reference voltage Reference2 based on the peak sampled voltage VIN_PEAK. The comparator CMP4 obtains the signal for the first-stage takeover GATE pulse width duration by comparing the signal VCS and the reference voltage Reference3. The comparator CMP3 obtains the signal for the second-stage takeover GATE pulse width duration by comparing the output signal of the Ramp Generator and the varying comparison reference voltage Reference2. When the output signal of the comparator CMP1 flips to logic high after the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP1 flips to logic high. When the output signal of the comparator CMP1 flips to logic high before the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP4 flips to logic high. When the output signal of the comparator CMP3 flips to logic high and the output signal of the comparator CMP4 remains logic low, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP3 flips to logic high.

[0035] Such as Figure 4As shown, at time T0, the signal VIN enters the AC valley region. As the signal VIN decreases, the rising slope of the signal VCS during the conduction time of the power switch M1, that is, during the time when the voltage of the signal GATE is at a high level, gradually becomes smaller. Until time T1, controlled by the COT control method, the conduction time of the power switch M1 during this stage remains at the first fixed TON time, and the turn-off time gradually decreases. At time T1, the peak value of the signal VCS reaches the level of the reference voltage Reference2. After that, the per-cycle peak value of the signal VCS will be locked at the level of the reference voltage Reference2 until time T2. During this stage, since the per-cycle peak value of the signal VCS is fixed while the rising slope continues to slow down, the TON time of the power switch M1 gradually increases. At time T2, the TON time of the power switch M1 increases to the second fixed TON time, and then remains fixed at the second fixed TON time until time T3. Since the second fixed TON time is significantly greater than the first fixed TON time, the per-cycle peak value of the signal VCS still has an amplitude greater than zero, which is used to offset the per-cycle negative current spikes caused by parasitics and delays, thereby reducing the THD. And the switching frequency during this stage is low, and the component of the harmonic disturbance in this stage in the THD decreases, thereby reducing the THD. At time T3, the amplitude of the input AC voltage enters the rising cycle and is significantly higher than the signal VOUT. The voltage of the signal VIN follows the amplitude of the input AC voltage and starts to rise. The conduction time of the power switch M1 remains at the first fixed TON time, and the turn-off time of the power switch M1 gradually increases until time T4. At time T4, the signal VIN exits the AC valley region.

[0036] The present invention performs a series of compensations on the control method for the input AC voltage valley region, enabling the input current to better follow the sinusoidal trajectory of the input AC voltage, improving the PF value of the power supply, and reducing the THD value of the power supply; the present invention reduces the switching frequency in the valley region and reduces the negative current disturbance caused by the switching in the valley region, thereby reducing the THD of the buck-type AC / DC power supply with the COT control method and improving the power supply efficiency.

[0037] The above are only the preferred embodiments of the present invention, and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some changes or modifications to equivalent embodiments by using the above-disclosed technical content within the scope of the technical solution of the present invention. However, as long as it does not depart from the content of the technical solution of the present invention, according to the technical essence of the present invention, any simple modification, equivalent replacement, and improvement of the above embodiments within the spirit and principle of the present invention still fall within the protection scope of the technical solution of the present invention.

Claims

1. A THD optimization circuit, characterized in that: It includes a COT control circuit, comparator CMP3, comparator CMP4, inverter G2, NAND gate G3, NAND gate G4 and AND gate G5. The inverting input terminal of comparator CMP3 is connected to reference voltage Reference2. The non-inverting input terminal of comparator CMP3 is connected to the output terminal of the ramp generation circuit Ramp Generator of the COT control circuit. The output terminal of comparator CMP3 is connected to the first input terminal of NAND gate G3. The non-inverting input terminal of comparator CMP4 is connected to signal VCS. The inverting input terminal of comparator CMP4 is connected to reference voltage Reference3. The output terminal of comparator CMP4 is connected to the input terminal of inverter G2. The output terminal of inverter G2 is connected to the second input terminal of NAND gate G3 and the second input terminal of NAND gate G4. The output terminal of NAND gate G3 is connected to the first input terminal of NAND gate G4. The output terminal of NAND gate G4 is connected to the second input terminal of AND gate G5. The output terminal of AND gate G5 is connected to the R terminal of RS flip-flop G1 of the COT control circuit.

2. The THD optimization circuit according to claim 1, wherein: The COT control circuit includes a sample and hold module Sample&Hold, a ramp generation circuit Ramp Generator, an error amplifier EA, a comparator CMP1, a comparator CMP2, an RS flip-flop G1 and a driver circuit module Driver. The input terminal of the sample and hold module Sample&Hold is connected to signal VCS. The output terminal of the sample and hold module Sample&Hold is connected to the inverting input terminal of the error amplifier EA. The non-inverting input terminal of the error amplifier EA is connected to reference voltage Reference1. The output terminal of the error amplifier EA is connected to the inverting input terminal of comparator CMP1. The output terminal of the ramp generation circuit Ramp Generator is connected to the non-inverting input terminal of comparator CMP1. The output terminal of comparator CMP1 is connected to the first input terminal of AND gate G5. The output terminal of AND gate G5 is connected to the R terminal of RS flip-flop G1. The non-inverting input terminal of comparator CMP2 is grounded. The inverting input terminal of comparator CMP2 is connected to signal VCS. The output terminal of comparator CMP2 is connected to the S terminal of RS flip-flop G1 and generates signal ZCD. The Q terminal of RS flip-flop G1 is connected to the input terminal of the driver circuit module Driver and generates signal PWM. The output terminal of the driver circuit module Driver generates signal GATE.

3. The THD optimization circuit according to claim 1, wherein: Only one of the reference voltage Reference2 and the reference voltage Reference3 is a variable comparison reference voltage.

4. A THD optimization circuit according to claim 3, characterized in that: The varying comparison reference voltage is generated by a varying comparison reference voltage circuit, which includes a voltage division and peak detection module Divider&Peak Sample and a compensation circuit module Compensation. The input end of the voltage division and peak detection module Divider&Peak Sample is connected to the signal VIN. The output end of the voltage division and peak detection module Divider&Peak Sample is connected to the input end of the compensation circuit module Compensation and generates a peak sampling voltage VIN_PEAK. The output end of the compensation circuit module Compensation generates the varying comparison reference voltage.

5. The THD optimization circuit according to claim 3, wherein: When the reference voltage Reference3 is the varying comparison reference voltage, within the range [PEAK1, PEAK2] of the peak sampling voltage VIN_PEAK, the value of the reference voltage Reference3 decreases as the peak sampling voltage VIN_PEAK increases, where PEAK1 and PEAK2 are constants.

6. The THD optimization circuit according to claim 3, wherein: When the reference voltage Reference2 is the varying comparison reference voltage, within the range [PEAK1, PEAK2] of the peak sampling voltage VIN_PEAK, the value of the reference voltage Reference2 increases as the peak sampling voltage VIN_PEAK increases, where PEAK1 and PEAK2 are constants.

7. A control method for the THD optimization circuit according to claim 5, characterized in that Including the following steps: The voltage division and peak detection module Divider&Peak Sample obtains the peak sampling voltage VIN_PEAK through voltage division and peak sampling. The compensation circuit module Compensation generates the varying comparison reference voltage Reference3 based on the peak sampling voltage VIN_PEAK. The comparator CMP4 obtains the signal for the first-stage takeover GATE pulse width duration by comparing the signal VCS and the varying comparison reference voltage Reference3. The comparator CMP3 obtains the signal for the second-stage takeover GATE pulse width duration by comparing the output signal of the ramp generation circuit Ramp Generator and the reference voltage Reference2. When the moment when the output signal of the comparator CMP1 flips to logic high is after the moment when the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP1 flips to logic high. When the moment when the output signal of the comparator CMP1 flips to logic high is before the moment when the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP4 flips to logic high. When the output signal of the comparator CMP3 flips to logic high and the output signal of the comparator CMP4 remains logic low, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP3 flips to logic high.

8. A control method for the THD optimization circuit according to claim 6, characterized in that Including the following steps: The Divider&Peak Sample module obtains the peak sampled voltage VIN_PEAK through voltage division and peak sampling. The Compensation circuit module generates a variable comparison reference voltage Reference2 based on the peak sampled voltage VIN_PEAK. The comparator CMP4 obtains the signal for the first-stage takeover GATE pulse width duration by comparing the signal VCS and the reference voltage Reference3. The comparator CMP3 obtains the signal for the second-stage takeover GATE pulse width duration by comparing the output signal of the Ramp Generator and the variable comparison reference voltage Reference2. When the output signal of the comparator CMP1 flips to logic high after the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP1 flips to logic high. When the output signal of the comparator CMP1 flips to logic high before the output signal of the comparator CMP4 flips to logic high, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP4 flips to logic high. When the output signal of the comparator CMP3 flips to logic high and the output signal of the comparator CMP4 remains logic low, the duration of the GATE pulse width is determined by the moment when the output signal of the comparator CMP3 flips to logic high.

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