Charge pump system

Abstract

The invention relates to a charge pump system. In the charge pump system, a second clock signal for controlling a second charge pump circuit has phase delay compared with a first clock signal for controlling a first charge pump circuit, an output feedback module samples output voltage and forms a corresponding feedback signal, and a clock generation module receives the feedback signal and forms a first clock signal and a second clock signal. When the enabling time of the feedback signal exceeds the set time length, the second clock signal works along with the first clock signal, fast transient response can be achieved under the condition that the filter capacitance does not need to be increased, and when the enabling time of the feedback signal does not exceed the set time length, the second clock signal works along with the first clock signal. And the second clock signal is latched in a state before the feedback signal is converted from enabling to disenabling at the time so as to enable the second charge pump circuit to stop working, so that the output signal can be prevented from generating relatively large burrs, the ripple can be effectively inhibited, and the power consumption of the system can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of circuit technologies, and in particular, to a charge pump system. Background Art

[0002] Many types of chips (such as flash memories, display chips, etc.) contain charge pump circuits to use the charge pump circuits for voltage conversion to generate a potential higher than the power supply voltage. The basic working principle of the charge pump circuit is to charge a capacitor using a continuously flipped clock to generate a potential higher than the base voltage. In theory, the higher the clock frequency, the faster the transient response speed of the charge pump circuit, and the faster a stable output can be established. However, for a single charge pump circuit, increasing the clock frequency means that a higher-frequency oscillator circuit needs to be used, but the higher the frequency of the oscillator circuit, the greater the power consumption, which has limitations. To increase the clock frequency, the industry has proposed an architecture in which multiple charge pump circuits work simultaneously. Among them, the multiple charge pump circuits are connected in parallel, and the clock signals of each charge pump circuit have a certain phase difference, so as to form a relatively large capacitor charging frequency and accelerate the establishment of the output voltage.

[0003] However, it has been found that for a charge pump system with multiple charge pump circuits, when only one charge pump circuit is working, when the clock flips, the output signal of the charge pump system will not generate large glitches, that is, the ripple is small. However, when two or more charge pump circuits work together, if the clock signal is directly stopped to make a corresponding part of the charge pump circuits stop working, the output signal will generate large glitches, and through the feedback loop, it may also cause invalid flips of the clock signal, resulting in an increase in ripple and wasting power consumption. Although selecting a larger filter capacitor helps to reduce glitches, a larger filter capacitor will reduce the transient response speed. Summary of the Invention

[0004] In order to suppress the glitches of the output signal, reduce the ripple, and at the same time ensure the transient response speed of the charge pump circuit and reduce the power consumption, the present invention provides a charge pump system.

[0005] The charge pump system provided by the present invention includes:

[0006] A first charge pump circuit for charging an output capacitor under the drive of an inverted clock formed by a first clock signal;

[0007] A second charge pump circuit for charging the output capacitor under the drive of an inverted clock formed by a second clock signal, and the second clock signal has a phase delay compared with the first clock signal;

[0008] An output feedback module for sampling the output voltage formed on the output capacitor and forming a corresponding feedback signal, and the feedback signal enables or disables as the output voltage fluctuates; and

[0009] A clock generation module, configured to receive the feedback signal and generate the first clock signal and the second clock signal. When the enable time of the feedback signal exceeds a set duration, the second clock signal operates following the first clock signal. When the enable time of the feedback signal does not exceed the set duration, the second clock signal is latched in the state before the feedback signal changes from enabled to disabled for the current time, so that the second charge pump circuit stops operating.

[0010] Optionally, the output feedback module includes:

[0011] A sampling circuit, configured to access the output voltage and the base voltage and output the increase amount of the output voltage relative to the base voltage; and

[0012] An operational amplifier circuit, configured to perform operational amplification on the voltage difference between the increase amount and a reference voltage to generate the feedback signal. When the increase amount is less than the reference voltage, the feedback signal is enabled. When the increase amount is not less than the reference voltage, the feedback signal is disabled.

[0013] Optionally, the clock generation module includes:

[0014] A first clock signal generation circuit, configured to generate an original clock signal and generate the first clock signal according to the original clock signal; and

[0015] A second clock signal generation circuit, coupled to the first clock signal generation circuit to form the second clock signal having a phase delay relative to the first clock signal. When the enable time of the feedback signal does not exceed the set duration, the second clock signal is latched in the state before the feedback signal changes from enabled to disabled for the current time.

[0016] Optionally, the first clock signal generation circuit includes:

[0017] An original clock generation circuit, including a first inverter, a second inverter, a third inverter, a fourth inverter and a NAND logic connected in series with the same delay time. The output terminal of the fourth inverter is coupled to an input terminal of the NAND logic. The other input terminal of the NAND logic is coupled to a system enable signal. The output terminal of the NAND logic is coupled to the input terminal of the first inverter; and

[0018] A first latch unit, including a first latch enable terminal, a first latch data input terminal and a first latch output terminal. The first latch enable terminal is coupled to the feedback signal. The first latch data input terminal is coupled to the output terminal of the NAND logic. The first latch output terminal outputs the first clock signal.

[0019] Optionally, the second clock signal generation circuit includes:

[0020] A phase delay unit, including at least two D flip - flops connected in series. The total data input terminals of the at least two D flip - flops are coupled to a constant high - level signal. The RN input terminals of each D flip - flop are coupled to the feedback signal. The clock input terminals of each D flip - flop are coupled to the output terminal of the second inverter;

[0021] A second latch unit, including a second latch enable terminal, a second latch data input terminal, and a second latch output terminal. The second latch enable terminal is coupled to the total output terminal of the at least two D flip - flops. The second latch output terminal outputs the second clock signal; and

[0022] A fifth inverter, the input terminal of the fifth inverter is coupled to the output terminal of the second inverter, and the output terminal of the fifth inverter is coupled to the second latch data input terminal.

[0023] Optionally, the phase delay unit includes a first D flip - flop and a second D flip - flop connected in series. The data input terminal of the first D flip - flop is coupled to the constant high - level signal, and the data output terminal of the second D flip - flop is coupled to the second latch enable terminal.

[0024] Optionally, the set duration is the duration between two adjacent clock edges of the signal at the output terminal of the second inverter.

[0025] Optionally, the second clock signal has a 90 - degree phase delay compared to the first clock signal.

[0026] Optionally, the first charge pump circuit and the second charge pump circuit are connected to the same base voltage.

[0027] Optionally, the first charge pump circuit or the second charge pump circuit includes a first capacitor, a second capacitor, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; the sources of the first NMOS transistor and the second NMOS transistor are connected and coupled to the base voltage, the drains of the first PMOS transistor and the second PMOS transistor are respectively coupled to the drain of the first NMOS transistor and the drain of the second NMOS transistor, the sources of the first PMOS transistor and the second PMOS transistor are connected and coupled to the output capacitor, the connection point of the first NMOS transistor and the first PMOS transistor, one end of the first capacitor, and the control terminals of the second NMOS transistor and the second PMOS transistor are coupled, the connection point of the second NMOS transistor and the second PMOS transistor, one end of the second capacitor, and the connection point of the first NMOS transistor and the second PMOS transistor are coupled, and the other ends of the first capacitor and the second capacitor are respectively coupled to a pair of reverse clocks.

[0028] In the charge pump system provided by the present invention, the second clock signal for controlling the second charge pump circuit has a phase delay compared with the first clock signal for controlling the first charge pump circuit. The clock generation module is configured to receive the feedback signal and generate the first clock signal and the second clock signal. Wherein, when the enable time of the feedback signal exceeds a set duration, the second clock signal operates following the first clock signal, and fast transient response can be achieved without increasing the filter capacitor. Moreover, when the enable time of the feedback signal does not exceed the set duration, the second clock signal is latched in the state before the feedback signal changes from enabled to disabled for the current time to stop the second charge pump circuit, which can avoid large glitches in the output signal, thereby effectively suppressing ripples and helping to reduce system power consumption. Description of the Drawings

[0029] Figure 1 is a loop schematic diagram of a charge pump system according to an embodiment of the present invention.

[0030] Figure 2 is a waveform schematic diagram of multiple signals before and after output establishment of a charge pump system according to an embodiment of the present invention.

[0031] Figure 3 is a circuit schematic diagram of a clock generation module in a charge pump system according to an embodiment of the present invention.

[0032] Figure 4 is adopted Figure 3 is a waveform schematic diagram of multiple node signals during output establishment of the clock generation module shown. Detailed Embodiments

[0033] The charge pump system of the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments. According to the following description, the advantages and features of the present invention will be clearer. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0034] An embodiment of the present invention relates to a charge pump system. The charge pump system adopts an architecture of multiple charge pump circuits, that is, it has two or more than two charge pump circuits to generate a stable voltage higher than the basic voltage. And, the charge pump circuit forms a loop using output feedback to regulate the clock signals required for the operation of each charge pump circuit, and controls all or only the first charge pump circuit to work. It can achieve fast transient response without increasing the filter capacitor. When some charge pump circuits stop working, it can avoid large spikes in the output signal, and can effectively suppress ripples and reduce power consumption.

[0035] Refer to Figure 1 , in an embodiment of the present invention, the charge pump system includes a first charge pump circuit PMP1, a second charge pump circuit PMP2, an output feedback module 110, and a clock generation module 120.

[0036] Exemplarily, the first charge pump circuit PMP1 and the second charge pump circuit PMP2 are two charge pump circuits in the charge pump system. Among them, the first charge pump circuit PMP1 is used to charge an output capacitor (not shown in the figure) under the drive of the inverted clock formed by the first clock signal CLK1, and the second charge pump circuit PMP2 is used to charge the output capacitor under the drive of the inverted clock formed by the second clock signal CLK2. And, the second clock signal CLK2 has a phase delay compared with the first clock signal CLK1, so as to form a larger clock frequency to charge the output capacitor. Exemplarily, the second clock signal CLK2 has a 90-degree phase delay compared with the first clock signal CLK1. The phase delay of the second clock signal CLK2 compared with the first clock signal CLK1 can be set according to the specific architecture of the multiple charge pump circuits.

[0037] The first charge pump circuit PMP1 and the second charge pump circuit PMP2 are connected to the same basic voltage (VIN), and the basic voltage can be the power supply voltage or its divided voltage. The first charge pump circuit PMP1 and the second charge pump circuit PMP2 can adopt the same or similar circuit structures. As an example, at least one of the first charge pump circuit PMP1 and the second charge pump circuit PMP2 has a charge pump structure 10 as shown in Figure 1 shown, refer to Figure 1, the charge pump structure 10 of the first charge pump circuit PMP1 or the second charge pump circuit PMP2, for example, includes a first capacitor C1, a second capacitor C2, a first NMOS transistor N1, a second NMOS transistor N2, a first PMOS transistor P1, and a second PMOS transistor P2; the sources of the first NMOS transistor N1 and the second NMOS transistor N2 are connected and coupled to the base voltage VIN, the drains of the first PMOS transistor P1 and the second PMOS transistor P2 are respectively coupled to the drain of the first NMOS transistor N1 and the drain of the second NMOS transistor N2, the sources of the first PMOS transistor P1 and the second PMOS transistor P2 are connected and coupled to an output capacitor (not shown in the figure), and moreover, the connection point of the first NMOS transistor N1 and the first PMOS transistor P1, one end of the first capacitor C1, and the control terminals of the second NMOS transistor N1 and the second PMOS transistor P1 are coupled, the connection point of the second NMOS transistor N2 and the second PMOS transistor P2, one end of the second capacitor C2, and the control terminals of the first NMOS transistor N1 and the first PMOS transistor P1 are coupled, the other end of the first capacitor C1 and the other end of the second capacitor C2 are coupled to a pair of inverted clocks CLKN and CLKP. The first clock signal CLK1 and the second clock signal CLK2 can respectively form a pair of inverted clocks CLKN and CLKP through inverters, so as to respectively control the operation of the first charge pump circuit PMP1 and the second charge pump circuit PMP2. Using the above charge pump structure 10, the first charge pump circuit PMP1 and the second charge pump circuit PMP1 can generate a higher and more stable output voltage VPUMP based on the base voltage VIN, and the output voltage VPUMP is equal to the voltage on the output capacitor.

[0038] The output feedback module 110 is used to sample the output voltage VPUMP formed on the output capacitor and form a corresponding feedback signal FB, and the feedback signal FB is enabled or disabled as the output voltage VPUMP fluctuates.

[0039] As an example, the output feedback module 110 generates a corresponding feedback signal FB by monitoring the pressure difference between the output voltage VPUMP and the base voltage VIN. Refer to Figure 1 , the output feedback module 110 includes a sampling circuit 111 (such as Figure 1The “sample” shown) and the operational amplifier circuit 112; wherein, the sampling circuit 111 is used to access the output voltage VPUMP and the base voltage VIN, and output the increment VM of the output voltage VPUMP and the base voltage VIN, and the operational amplifier circuit 112 is used to perform operational amplification on the voltage difference between the increment VM and a reference voltage VREF to form the feedback signal FB. In this embodiment, the operational amplifier circuit 112 includes an operational amplifier EA, the increment VM is input to the inverting input terminal of the operational amplifier EA, the reference voltage VREF is input to the non-inverting input terminal of the operational amplifier EA, and the output terminal of the operational amplifier EA outputs the feedback signal FB.

[0040] Figure 2 The waveforms of the output voltage VPUMP, the feedback signal FB, and the first clock signal CLK1 and the second clock signal CLK2 before and after the output of the charge pump system is established are shown. As Figure 2 shown, when the increment VM of the output voltage VPUMP relative to the base voltage VIN is less than the reference voltage VREF, the feedback signal FB is enabled and appears as a high level. When the increment VM is not less than the reference voltage VREF, the feedback signal FB is not enabled and appears as a low level. At the initial stage of output establishment, the value of the output voltage VPUMP is very low, and the feedback signal FB remains high. As the output is established, the enabling situation of the feedback signal FB will change, and the high-level duration gradually becomes shorter. When the output voltage VPUMP gradually stabilizes and fluctuates near the target value, accordingly, the feedback signal FB switches between high and low levels to regulate the output voltage VPUMP.

[0041] In the embodiment of the present invention, the first clock signal CLK1 and the first clock signal CLK2 are both controlled by the feedback signal FB. As the enabling situation of the feedback signal FB changes, the first clock signal CLK1 and the first clock signal CLK2 can be changed, thereby changing the operating states of the first charge pump circuit PMP1 and the second charge pump circuit PMP2.

[0042] Refer to Figure 1 , the clock generation module 120 is used to receive the feedback signal FB and form the first clock signal CLK1 and the first clock signal CLK2. Wherein, when the enabling time of the feedback signal FB exceeds the set duration, the second clock signal CLK2 follows the first clock signal CLK1 to work. When the enabling time of the feedback signal FB does not exceed the set duration, the second clock signal CLK2 is latched in the state before the feedback signal FB changes from enabling to disabling this time, so that the second charge pump circuit PMP2 stops working. As an example, the set duration is the duration between two adjacent clock edges of the signal at the output terminal of the second inverter.

[0043] In this embodiment, the first charge pump circuit PMP1 is the main boost circuit during output establishment and output stabilization, and other charge pump circuits (such as the second charge pump circuit PMP2 for example) are auxiliary boost circuits. The auxiliary charge pump circuit works together with the first charge pump circuit before output stabilization, which can achieve fast transient response and increase the output voltage VPUMP at a relatively high clock frequency. As the output voltage VPUMP increases, the enable time of the feedback signal FB shortens. By latching the second clock signal CLK2 when the enable time of the feedback signal FB does not exceed the set duration, and maintaining the output by the first charge pump circuit PMP1, not only can large output signal glitches be avoided, effectively suppressing the ripple, but also it helps to reduce power consumption and avoid power waste.

[0044] Figure 3 The circuit of the clock generation module 120 is shown. Referring to Figure 1 and Figure 3 , the clock generation module 120 may include a first clock signal generation circuit 121 and a second clock signal generation circuit 122. Both the first clock signal generation circuit 121 and the second clock signal generation circuit 122 may include a clock signal generation part (OSC) and a filter and latch part ("Filter&latch") as shown in Figure 1 .

[0045] The first clock signal generation circuit 121 is used to generate an original clock signal and generate the first clock signal CLK1 according to the original clock signal. Referring to Figure 3 , the first clock signal generation circuit 121 includes, for example, an original clock generation circuit 121a and a first latch unit 121b. The original clock generation circuit 121a includes a first inverter INV1, a second inverter INV2, a third inverter INV3, a fourth inverter INV4 and a NAND logic connected in series with the same delay time. The output end of the fourth inverter INV4 is coupled to an input end of the NAND logic. The system enable signal EN is coupled to the other input end of the NAND logic. The output end of the NAND logic is coupled to the input end of the first inverter INV1. The first latch unit 121b includes a first latch enable end ("EN"), a first latch data input end ("IN") and a first latch output end ("OUT"). The first latch enable end is coupled to the above-mentioned feedback signal FB. The first latch data input end is coupled to the output end of the NAND logic. The first latch output end outputs the first clock signal CLK1.

[0046] The second clock signal generation circuit 122 is coupled to the first clock signal generation circuit 121 to form a second clock signal CLK2 having a set phase delay relative to the first clock signal CLK1. And when the enable time of the feedback signal FB does not exceed a set duration, the second clock signal CLK2 is latched in the state before the feedback signal FB changes from enabled to disabled this time. Refer to Figure 3 , for example, the second clock signal generation circuit 122 includes a phase delay unit 122a, a second latch unit 122b, and a fifth inverter INV5. Wherein, the phase delay unit 122a includes at least two D flip-flops connected in series. The total data input terminals of the at least two D flip-flops are coupled to a constant high-level signal VHigh. The RN input terminals of each D flip-flop are coupled to the feedback signal FB. The clock input terminals ("CLK") of each D flip-flop are coupled to the output terminal of the second inverter INV2. The second latch unit 122b includes a second latch enable terminal ("EN"), a second latch data input terminal ("IN"), and a second latch output terminal ("OUT"). The second latch enable terminal is coupled to the total output terminal of the at least two D flip-flops. The second latch output terminal outputs the second clock signal CLK2. The input terminal of the fifth inverter INV5 is coupled to the output terminal of the second inverter INV2. The output terminal of the fifth inverter INV5 is coupled to the second latch data input terminal.

[0047] In this embodiment, the D flip-flops in the phase delay unit 122a are used to prevent mis-triggering, and the number thereof can be set as required. As Figure 3 shown, as an example, the phase delay unit 122a includes a first D flip-flop D1 and a second D flip-flop D2 connected in series. The data input terminal of the first D flip-flop D1 is coupled to the constant high-level signal VHigh. The data output terminal of the second D flip-flop D2 is coupled to the second latch enable terminal.

[0048] In the above first clock signal generation circuit 121, the four inverters INV1, INV2, INV3, and INV4 and the NAND logic form an original clock circuit. The delay time generated by these four inverters is 1 / 2 cycle of the original clock signal. The system enable signal EN is at a high level when the charge pump system is working, and the charge pump system can be turned off by changing the system enable signal to a low level. When the charge pump system includes more than two charge pump circuits, in order to form a corresponding phase delay, the number of inverters in the first clock signal generation circuit 121 and the position of the first clock signal generation circuit 121 to which the second clock signal generation circuit 122 is coupled can be different from Figure 3 the circuit shown.

[0049] Figure 4 shows the waveforms of multiple node signals during the output establishment process using the Figure 3 clock generation module 120 shown. Referring to Figures 1 to 4 , the operation of the charge pump system is as follows:

[0050] At the initial stage of output establishment, since the value of the output voltage VPUMP is very low, the feedback signal FB remains high all the time. The first latch enable terminal of the first latch unit 121a is valid, and the clock signal P3N generated by the original clock circuit is transmitted to the first latch output terminal to form the first clock signal CLK1. When the high-level time of the feedback signal FB is less than one cycle, the data output terminal of the second D flip-flop D2, that is, the FBN signal, is low. At this time, only the first clock signal CLK1 is generated (such as Figure 4 shown in the "CLK1" stage). Due to the setting of the first latch unit 121a, there is a 1 / 4 cycle delay at the output terminal of the second inverter INV2 (i.e., the P1 signal) relative to the output terminal of the NAND logic (i.e., the P3N signal);

[0051] Since the clock input terminals of the first D flip-flop D1 and the second D flip-flop D2 are coupled to the output terminal of the second inverter INV2, when the high-level duration of the feedback signal FB exceeds two rising edges of the P1 signal (i.e., during the enable period of the feedback signal FB, the P1 signal completes two flips), the data output terminal of the second D flip-flop D2, that is, the FBN signal, becomes high, and the second clock signal CLK2 starts to work. It forms a 90-degree phase delay with the first clock signal CLK1, and the system enters the stage where the first clock signal CLK1 and the second clock signal CLK2 work simultaneously (such as Figure 4 shown in the "CLK1&CLK2" stage). At this time, the operating frequency of the charge pump system is twice the frequency of the original clock signal;

[0052] As the output voltage VPUMP gradually stabilizes, the enable time of the feedback signal FB, that is, the high-level duration, shortens, and the frequencies of the first clock signal CLK1 and the second clock signal CLK2 decrease. When the high-level duration of the feedback signal FB is less than two clock edges of the P1 signal, the FBN signal becomes low, and the second clock signal CLK2 is latched in the state before the FBN signal changes from high to low this time (that is, the state before the feedback signal FB changes from high to low this time, such as Figure 4In the "Latch" stage shown, since the second clock signal CLK2 no longer toggles, the second charge pump circuit PMP2 gradually stops working. In this embodiment, when the enable time of the feedback signal FB does not exceed the set duration, the second clock signal CLK2 is latched in the state before the feedback signal FB changes from enabled to disabled for the current time. The set duration is, for example, the duration between two adjacent clock edges of the signal at the output terminal of the second inverter INV2.

[0053] When the second clock signal CLK2 is latched, the first clock signal CLK1 is latched in the state before the feedback signal FB becomes low level due to the feedback signal FB becoming low level. However, since the output of the first clock signal CLK1 is directly controlled by the feedback signal FB, the first clock signal CLK1 will continue to work as the feedback signal FB toggles later, and its frequency gradually decreases until it stabilizes. The power consumption of the charge pump system loop also decreases to the lowest value as the frequency of the first clock signal CLK1 decreases.

[0054] In this embodiment, the first clock signal CLK1 and the second clock signal CLK2 are respectively generated by two high-frequency signals, the P3N signal and the P1N signal, and the first clock signal CLK1 and the second clock signal CLK2 are also respectively controlled by two low-frequency signals, the feedback signal FB and the FBN signal. At the initial stage of system output establishment, the first clock signal CLK1 and the second clock signal CLK2 work simultaneously. During the process of the output gradually stabilizing, the frequencies of the first clock signal CLK1 and the second clock signal CLK2 gradually decrease until the second clock signal CLK2 is latched in the state before the FBN signal changes to low level as the enable time of the feedback signal VFB shortens, thereby suppressing the ripple of the output voltage when the second clock signal CLK2 is turned off. No glitches are generated during the operation of the first clock signal CLK1 and the second clock signal CLK2. Therefore, there is no need to increase the filter capacitor to suppress glitches, and no additional power consumption is added. While suppressing glitches, the transient response speed of the charge pump circuit can be ensured.

[0055] The loop of the charge pump system adaptively regulates the frequencies of the first clock signal CLK1 and the second clock signal CLK2 and invokes the charge pump circuit. After the output is established and the second clock signal CLK2 stops working, the first clock signal CLK1 works under the control of the feedback signal FB. When the subsequent output voltage VPUMP is lower than the target voltage to such an extent that a stronger driving ability is required to resume fluctuating near the target voltage, the first clock signal CLK1 will recover alone. If the first clock signal CLK1 fails to pull the output voltage VPUMP to the target voltage within the set number of flips (such as two cycles), since the enabling time of the feedback signal VFB will be extended, the second clock signal CLK2 can work again to accelerate the recovery of the output voltage VPUMP.

[0056] The above description is only a description of the preferred embodiments of the present invention and does not limit any scope of the rights of the present invention. Any person skilled in the art can make possible changes and modifications to the technical solutions of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and decorations made to the above embodiments according to the technical essence of the present invention without departing from the technical solutions of the present invention all fall within the protection scope of the technical solutions of the present invention.

Claims

1. A charge pump system, characterized in that, Comprising: A first charge pump circuit for charging an output capacitor under the drive of an inverted clock formed by a first clock signal; A second charge pump circuit for charging the output capacitor under the drive of an inverted clock formed by a second clock signal, the second clock signal having a phase delay with respect to the first clock signal; An output feedback module for sampling an output voltage formed on the output capacitor and forming a corresponding feedback signal, the feedback signal being enabled or disabled as the output voltage fluctuates; And A clock generation module for receiving the feedback signal and forming the first clock signal and the second clock signal, wherein when the enable time of the feedback signal exceeds a set duration, the second clock signal operates following the first clock signal, and when the enable time of the feedback signal does not exceed the set duration, the second clock signal is latched in the state before the feedback signal changes from enabled to disabled for the current time, so as to stop the second charge pump circuit from operating.

2. The charge pump system according to claim 1, wherein The output feedback module includes: A sampling circuit for accessing the output voltage and a reference voltage and outputting an increase amount of the output voltage relative to the reference voltage; and An operational amplifier circuit for performing operational amplification on the voltage difference between the increase amount and a reference voltage to form the feedback signal, wherein when the increase amount is less than the reference voltage, the feedback signal is enabled, and when the increase amount is not less than the reference voltage, the feedback signal is disabled.

3. The charge pump system according to claim 1, wherein The clock generation module includes: A first clock signal generation circuit for generating an original clock signal and generating the first clock signal according to the original clock signal; and A second clock signal generation circuit coupled to the first clock signal generation circuit to form the second clock signal having the phase delay with respect to the first clock signal, and when the enable time of the feedback signal does not exceed the set duration, latching the second clock signal in the state before the feedback signal changes from enabled to disabled for the current time.

4. The charge pump system according to claim 3, wherein, The first clock signal generation circuit includes: An original clock generation circuit including a first inverter, a second inverter, a third inverter, a fourth inverter and a NAND logic connected in series with the same delay time, an output end of the fourth inverter being coupled to an input end of the NAND logic, another input end of the NAND logic being coupled to a system enable signal, and an output end of the NAND logic being coupled to an input end of the first inverter; and A first latch unit including a first latch enable end, a first latch data input end and a first latch output end, the first latch enable end being coupled to the feedback signal, the first latch data input end being coupled to the output end of the NAND logic, and the first latch output end outputting the first clock signal.

5. The charge pump system according to claim 4, wherein The second clock signal generation circuit includes: A phase delay unit, comprising at least two D flip-flops connected in series, a total data input terminal of the at least two D flip-flops being coupled to a constant high-level signal, an RN input terminal of each of the D flip-flops being coupled to the feedback signal, and a clock input terminal of each of the D flip-flops being coupled to an output terminal of the second inverter; A second latch unit, comprising a second latch enable terminal, a second latch data input terminal, and a second latch output terminal, the second latch enable terminal being coupled to an output terminal of the at least two D flip-flops in total, and the second latch output terminal outputting the second clock signal; and A fifth inverter, an input terminal of the fifth inverter being coupled to the output terminal of the second inverter, and an output terminal of the fifth inverter being coupled to the second latch data input terminal.

6. The charge pump system according to claim 5, wherein The phase delay unit includes a first D flip-flop and a second D flip-flop connected in series, a data input terminal of the first D flip-flop being coupled to the constant high-level signal, and a data output terminal of the second D flip-flop being coupled to the second latch enable terminal.

7. The charge pump system according to claim 5, wherein The set duration is the duration between two adjacent clock edges of the signal at the output terminal of the second inverter.

8. The charge pump system according to claim 1, wherein, The second clock signal has a 90-degree phase delay compared to the first clock signal.

9. The charge pump system according to any one of claims 1 to 8, characterized in that The first charge pump circuit and the second charge pump circuit are connected to the same basic voltage.

10. The charge pump system according to any one of claims 1 to 8, characterized in that, The first charge pump circuit or the second charge pump circuit includes a first capacitor, a second capacitor, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; wherein, sources of the first NMOS transistor and the second NMOS transistor are connected together and coupled to the basic voltage, drains of the first PMOS transistor and the second PMOS transistor are respectively coupled to the drain of the first NMOS transistor and the drain of the second NMOS transistor, sources of the first PMOS transistor and the second PMOS transistor are connected together and coupled to the output capacitor, a connection point of the first NMOS transistor and the first PMOS transistor, one end of the first capacitor, and control terminals of the second NMOS transistor and the second PMOS transistor are coupled, a connection point of the second NMOS transistor and the second PMOS transistor, one end of the second capacitor, and control terminals of the first NMOS transistor and the first PMOS transistor are coupled, and the other end of the first capacitor and the other end of the second capacitor are coupled to a pair of reverse clocks.

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