Voltage conversion circuit, method, device and system and storage medium

Abstract

The invention relates to the technical field of circuits, in particular to a voltage conversion circuit, method, device and system and a storage medium. The circuit comprises a first switch, a second switch, a third switch, a fourth switch, a capacitor and an inductor, wherein a connection point between a first end of the first switch and a first end of the second switch is an input end of the voltage conversion circuit, a second end of the first switch is respectively connected with a first end of the capacitor, a first end of the third switch and a first end of the fourth switch, and a second end of the second switch is respectively connected with a second end of the capacitor and a first end of the inductor. The connection point between the second end of the inductor and the second end of the third switch is the output end of the voltage conversion circuit, and the second end of the fourth switch is grounded; when the voltage conversion circuit is in the boost working mode, the inductive current corresponding to the inductor is not zero. According to the technical scheme, the technical problem that the circuit has a right half plane zero point in the boost working mode, so that the transient state of the circuit is poor can be solved.

Description

Technical Field

[0001] The present disclosure relates to the field of circuit technologies, and in particular, to a voltage conversion circuit, method, device, system, and storage medium. Background Art

[0002] A buck-boost circuit is a commonly used direct current-direct current (DC-DC) conversion circuit. Its output voltage can be either lower or higher than the input voltage, but the polarity of the output voltage is opposite to that of the input voltage. However, in the case of the boost working mode, the inductor in the buck-boost circuit cannot continuously transfer energy to the output end, and there is a right-half plane zero, resulting in poor transient performance of the voltage conversion circuit. Summary of the Invention

[0003] The present disclosure aims to at least partly solve one of the technical problems in the related art.

[0004] To this end, the first object of the present disclosure is to propose a voltage conversion circuit to solve the technical problem that the buck-boost circuit has a right-half plane zero in the boost working mode, resulting in poor transient performance.

[0005] The second object of the present disclosure is to propose a voltage conversion method.

[0006] The third object of the present disclosure is to propose a voltage conversion device.

[0007] The fourth object of the present disclosure is to propose a voltage conversion system.

[0008] The fifth object of the present disclosure is to propose a computer-readable storage medium.

[0009] The sixth object of the present disclosure is to propose a computer program product.

[0010] To achieve the above object, an embodiment of the first aspect of the present disclosure proposes a voltage conversion circuit, including: a first switch, a second switch, a third switch, a fourth switch, a capacitor, and an inductor; wherein,

[0011] The connection point between the first end of the first switch and the first end of the second switch is the input end of the voltage conversion circuit. The second end of the first switch is respectively connected to the first end of the capacitor, the first end of the third switch, and the first end of the fourth switch. The second end of the second switch is respectively connected to the second end of the capacitor and the first end of the inductor. The connection point between the second end of the inductor and the second end of the third switch is the output end of the voltage conversion circuit. The second end of the fourth switch is grounded;

[0012] When the voltage conversion circuit is in the boost operation mode, the inductor current corresponding to the inductor is not zero.

[0013] Optionally, the boost operation mode includes at least one boost operation cycle, and the boost operation cycle includes a first boost stage and a second boost stage, where

[0014] When the voltage conversion circuit is in the first boost stage, the second switch and the fourth switch are both in the on state, and the first switch and the third switch are both in the off state;

[0015] When the voltage conversion circuit is in the second boost stage, the first switch is in the on state, and the second switch, the third switch, and the fourth switch are all in the off state.

[0016] Optionally, the inductor current corresponding to the inductor in the first boost stage, the inductor current corresponding to the inductor in the second boost stage, and the average inductor current corresponding to the inductor in the boost operation cycle are all the output current corresponding to the output terminal of the voltage conversion circuit.

[0017] Optionally, the operation mode of the voltage conversion circuit further includes a buck operation mode. The buck operation mode includes at least one buck operation cycle, and the buck operation cycle includes a first buck stage and a second buck stage, where

[0018] When the voltage conversion circuit is in the first buck stage, the second switch and the third switch are both in the on state, and the first switch and the fourth switch are both in the off state;

[0019] When the voltage conversion circuit is in the second buck stage, the fourth switch is in the on state, and the first switch, the second switch, and the third switch are all in the off state.

[0020] Optionally, the average inductor current corresponding to the inductor in the buck operation mode is the product of the voltage conversion ratio and the output current corresponding to the output terminal of the voltage conversion circuit, and the voltage conversion ratio is the ratio of the output voltage to the input voltage of the voltage conversion circuit.

[0021] To achieve the above object, a second aspect embodiment of the present disclosure proposes a voltage conversion method, which is applied to a voltage conversion system. The voltage conversion system includes the voltage conversion circuit shown in any one of the foregoing first aspects. The method includes:

[0022] In response to receiving a work instruction for the voltage conversion circuit, determine the work mode corresponding to the work instruction;

[0023] Determine the first control signal, the second control signal, the third control signal, and the fourth control signal corresponding to the working mode;

[0024] Input the first control signal to the control terminal of the first switch, input the second control signal to the control terminal of the second switch, input the third control signal to the control terminal of the third switch, and input the fourth control signal to the control terminal of the fourth switch, so that the voltage conversion circuit is in the working mode corresponding to the working instruction.

[0025] Optionally, the duty cycles of the first control signal, the second control signal, the third control signal, and the fourth control signal are the same.

[0026] To achieve the above object, an embodiment of the third aspect of the present disclosure provides a voltage conversion device, which is applied to a voltage conversion system. The voltage conversion system includes the voltage conversion circuit shown in any one of the foregoing first aspects, and includes:

[0027] An instruction receiving unit, configured to determine the working mode corresponding to the working instruction in response to receiving a working instruction for the voltage conversion circuit;

[0028] A signal determining unit, configured to determine the first control signal, the second control signal, the third control signal, and the fourth control signal corresponding to the working mode;

[0029] A circuit control unit, configured to input the first control signal to the control terminal of the first switch, input the second control signal to the control terminal of the second switch, input the third control signal to the control terminal of the third switch, and input the fourth control signal to the control terminal of the fourth switch, so that the voltage conversion circuit is in the working mode corresponding to the working instruction.

[0030] To achieve the above object, an embodiment of the fourth aspect of the present disclosure provides a voltage conversion system, including:

[0031] The voltage conversion circuit shown in any one of the foregoing first aspects;

[0032] A processor, and a memory communicatively connected to the processor;

[0033] The memory stores computer execution instructions;

[0034] The processor executes the computer execution instructions stored in the memory to implement the method shown in any one of the foregoing second aspects.

[0035] To achieve the above object, an embodiment of the fifth aspect of the present disclosure provides a computer-readable storage medium storing computer-executable instructions, which are used to implement the method shown in any one of the foregoing second aspects when executed by a processor.

[0036] To achieve the above object, an embodiment of the sixth aspect of the present disclosure provides a computer program product including a computer program, which implements the method shown in any one of the foregoing second aspects when executed by a processor.

[0037] In summary, for the circuit, method, device, system, and storage medium provided by the present disclosure, when in the boost working mode, the inductor current corresponding to the inductor in the voltage conversion circuit is non-zero. Therefore, there is no right-half plane zero in the voltage conversion circuit, thus solving the technical problem of poor circuit transient caused by the existence of the right-half plane zero.

[0038] Additional aspects and advantages of the present disclosure will be partially given in the following description, partially become apparent from the following description, or be understood through the practice of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The above and / or additional aspects and advantages of the present disclosure will become apparent and be readily understood from the following description of the embodiments in conjunction with the drawings, where:

[0040] Figure 1 is a schematic structural diagram of a BUCK-BOOST circuit in a related art provided by an embodiment of the present disclosure;

[0041] Figure 2 is a schematic structural diagram of a voltage conversion circuit provided by an embodiment of the present disclosure;

[0042] Figure 3 is a schematic flowchart of a voltage conversion method provided by an embodiment of the present disclosure;

[0043] Figure 4 is a schematic structural diagram of the first boost stage provided by an embodiment of the present disclosure;

[0044] Figure 5 is a schematic structural diagram of the second boost stage provided by an embodiment of the present disclosure;

[0045] Figure 6 is a schematic structural diagram of the first buck stage provided by an embodiment of the present disclosure;

[0046] Figure 7 is a schematic structural diagram of the second buck stage provided by an embodiment of the present disclosure;

[0047] Figure 8Schematic diagram of a voltage conversion device provided by an embodiment of the present disclosure. Detailed implementation manners

[0048] The embodiments of the present disclosure will be described in detail below. The examples of the embodiments are shown in the accompanying drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to explain the present disclosure, and should not be construed as a limitation to the present disclosure.

[0049] It should be noted that Figure 1 Schematic diagram of a BUCK - BOOST circuit in the related art provided by an embodiment of the present disclosure. As Figure 1 shown, the BUCK - BOOST circuit includes an eleventh capacitor C11, a twelfth capacitor C12, an eleventh switching transistor Q11, a twelfth switching transistor Q12, a thirteenth switching transistor Q13, a fourteenth switching transistor Q14, and an eleventh inductor L11; among them,

[0050] The connection point between the first end of the eleventh capacitor C11 and the drain of the eleventh switching transistor Q11 is the positive input terminal of the BUCK - BOOST circuit. The connection point between the second end of the eleventh capacitor C12 and the source of the twelfth switching transistor Q12 is the negative input terminal of the BUCK - BOOST circuit. The connection point between the first end of the twelfth capacitor C12 and the drain of the fourteenth switching transistor Q14 is the positive output terminal of the BUCK - BOOST circuit. The connection point between the second end of the twelfth capacitor C12 and the source of the thirteenth switching transistor Q13 is the negative output terminal of the BUCK - BOOST circuit. The first end of the eleventh inductor L11 is respectively connected to the source of the eleventh switching transistor Q11 and the drain of the twelfth switching transistor Q12. The second end of the eleventh inductor L11 is respectively connected to the source of the fourteenth switching transistor Q14 and the drain of the thirteenth switching transistor Q13;

[0051] When the BUCK - BOOST circuit is in the buck working mode, the fourteenth switching transistor Q14 is in the normally - on state, the thirteenth switching transistor Q13 is in the normally - closed state, M11 = VOUT / VIN = D1, I L11 = I OUT ; where D1 is the duty cycle of the control signals input to the eleventh switching transistor Q11, the twelfth switching transistor Q12, the thirteenth switching transistor Q13, and the fourteenth switching transistor Q14, VOUT is the output voltage of the BUCK - BOOST circuit, VIN is the input voltage of the BUCK - BOOST circuit, I L11 is the average inductor current of the eleventh inductor L11 in one working cycle of the BUCK - BOOST circuit, I OUTis the output current of the BUCK - BOOST circuit, M11 is the voltage conversion ratio of the BUCK - BOOST circuit in the buck - working mode, and the voltage conversion ratio is the ratio between the input voltage and the output voltage.

[0052] When the BUCK - BOOST circuit is in the boost - working mode, the eleventh switching transistor Q11 is in the always - on state, the twelfth switching transistor Q12 is in the always - off state, M12 = VOUT / VIN = D1 / (1 - D1), I L11 = I OUT *M12, where M12 is the voltage conversion ratio of the BUCK - BOOST circuit in the boost - working mode.

[0053] In summary, when the BUCK - BOOST circuit is in the boost - working mode, the eleventh inductor L11 cannot continuously transfer energy to the output terminal, there is a right - half - plane zero, resulting in poor transient performance of the BUCK - BOOST circuit; in addition, the inductor current I L11 of the eleventh inductor L11 is relatively large, making it difficult to improve the conversion efficiency of the entire circuit.

[0054] Next, the voltage conversion circuit, method, device, system, and storage medium of the present disclosure will be described in detail with specific embodiments.

[0055] Figure 2 is a schematic structural diagram of a voltage conversion circuit provided by an embodiment of the present disclosure.

[0056] As Figure 2 shown, the voltage conversion circuit includes: a first switch S1, a second switch S2, a third switch S3, a fourth switch S4, a capacitor C1, and an inductor L1; where

[0057] The connection point between the first end of the first switch S1 and the first end of the second switch S2 is the input end of the voltage conversion circuit. The second end of the first switch S1 is respectively connected to the first end of the capacitor C1, the first end of the third switch S3, and the first end of the fourth switch S4. The second end of the second switch S2 is respectively connected to the second end of the capacitor C1 and the first end of the inductor L1. The connection point between the second end of the inductor L1 and the second end of the third switch S3 is the output end of the voltage conversion circuit, and the second end of the fourth switch S4 is grounded to GND.

[0058] It should be noted that when the voltage conversion circuit is in the boost - working mode, the inductor current corresponding to the inductor L1 is not zero. Therefore, the voltage conversion circuit does not have a right - half - plane zero, thus solving the technical problem of poor circuit transient performance caused by the existence of the right - half - plane zero.

[0059] Figure 3The flowchart shows a voltage conversion method provided by an embodiment of the present disclosure. As Figure 3 shown, this method can be implemented depending on a computer program and can run on a voltage conversion system, which includes a voltage conversion circuit as Figure 2 shown. This computer program can be integrated into an application or run as an independent tool application.

[0060] Among them, the voltage conversion system can be an electronic device with voltage conversion function.

[0061] Specifically, the voltage conversion method includes the following steps:

[0062] S101, in response to receiving a working instruction for the voltage conversion circuit, determine the working mode corresponding to the working instruction;

[0063] S102, determine the first control signal, the second control signal, the third control signal, and the fourth control signal corresponding to the working mode;

[0064] S103, input the first control signal to the control end of the first switch, input the second control signal to the control end of the second switch, input the third control signal to the control end of the third switch, and input the fourth control signal to the control end of the fourth switch, so that the voltage conversion circuit is in the working mode corresponding to the working instruction.

[0065] According to some embodiments, the duty ratios of the first control signal, the second control signal, the third control signal, and the fourth control signal are the same, and the value of the duty ratio is D.

[0066] In some embodiments, the value D of the duty ratio does not specifically refer to a certain fixed value and can be adjusted according to the actual application scenario.

[0067] According to some embodiments, the working mode includes a boost working mode, where the boost working mode includes at least one boost working cycle, and the boost working cycle includes a first boost stage and a second boost stage.

[0068] In some embodiments, Figure 4 The structural schematic diagram of the first boost stage provided by an embodiment of the present disclosure. As Figure 4 shown, when the voltage conversion circuit is in the first boost stage, the second switch S2 and the fourth switch S4 are both in the on state, and the first switch S1 and the third switch S3 are both in the off state. From Figure 4 it can be obtained that in the first boost stage, V C1 = VI, V L1 = VO - VI, where V C1 is the capacitance voltage across the capacitor C1, V L1is the inductor voltage across inductor L1, VI is the input voltage input to the voltage conversion circuit, and VO is the output voltage of the voltage conversion circuit.

[0069] In some embodiments, Figure 5 is a schematic structural diagram of the second boost stage provided by the embodiments of the present disclosure. As Figure 5 shown, when the voltage conversion circuit is in the second boost stage, the first switch S1 is in the on state, and the second switch S2, the third switch S3, and the fourth switch S4 are all in the off state. From Figure 5 it can be obtained that in the second boost stage, V L1 = VO - V C1 - VI. Since V C1 is charged to VI in the first boost stage, and the second boost stage is after the first boost stage, therefore, V L1 = VO - 2VI.

[0070] Thus, in a boost operating cycle, from the volt-second balance principle, the following equation can be obtained:

[0071] D * (VO - VI) = (2VI - VO) * (1 - D)

[0072] Simplifying the above equation, it can be deduced that: M1 = VO / VI = 2 - D; where M1 is the voltage conversion ratio of the voltage conversion circuit in the boost operating mode.

[0073] In addition, the inductor current I L1 corresponding to the inductor L1 in the first boost stage, the inductor current I L1 corresponding to the inductor L1 in the second boost stage, and the average inductor current corresponding to the inductor L1 in the boost operating cycle are all the output current I O corresponding to the output terminal of the voltage conversion circuit.

[0074] That is to say, the inductor L1 outputs current to the output terminal of the voltage conversion circuit in both phases of the first boost stage and the second boost stage, that is, it transfers energy to the output terminal in both phases, and there is no right half-plane zero point, thereby solving the technical problem of poor transient performance of the BUCK-BOOST circuit due to the existence of the right half-plane zero point.

[0075] Secondly, the average inductor current of the voltage conversion circuit provided by the embodiments of the present disclosure in the boost operating mode is I O , which is less than the average inductor current I OUT * M11 of the BUCK-BOOST circuit in the boost operating mode in the related art. That is to say, in the boost operating mode, the inductor current of the voltage conversion circuit provided by the embodiments of the present disclosure is relatively small, and the conversion efficiency of the entire circuit is relatively high.

[0076] According to some embodiments, the operating mode further includes a step-down operating mode, wherein the step-down operating mode includes at least one step-down operating cycle, and the step-down operating cycle includes a first step-down stage and a second step-down stage.

[0077] In some embodiments, Figure 6 is a schematic structural diagram of the first step-down stage provided by the embodiments of the present disclosure. As Figure 6 shown, when the voltage conversion circuit is in the first step-down stage, the second switch S2 and the third switch S3 are both in the on state, and the first switch S1 and the fourth switch S4 are both in the off state. From Figure 6 it can be obtained that in the first step-down stage, V C1 =V L1 =VI - VO.

[0078] In some embodiments, Figure 7 is a schematic structural diagram of the second step-down stage provided by the embodiments of the present disclosure. As Figure 7 shown, when the voltage conversion circuit is in the second step-down stage, the fourth switch S4 is in the on state, and the first switch S1, the second switch S2, and the third switch S3 are all in the off state. From Figure 7 it can be obtained that in the second step-down stage, V L1 =V C1 -VO. Since V C1 is charged to VI - VO in the first step-down stage and the second step-down stage is after the first step-down stage, therefore, V L1 =VI - 2VO.

[0079] Thus, in one step-down operating cycle, the following formula can be obtained from the volt-second balance principle:

[0080] D*(VI - VO)=(2VO - VI)*(1 - D)

[0081] Simplifying the above formula, it can be deduced that: M2 = VO / VI = 1 / (2 - D), where M2 is the voltage conversion ratio of the voltage conversion circuit in the step-down operating mode.

[0082] In addition, it can also be determined that in the first step-down stage, I L1 +I C1 -q1 = I O , where I C1 is the current flowing through the capacitor C1, I O is the output current of the voltage conversion circuit, and q1 is the charge amount of the capacitor C1 in the first step-down stage; in the second step-down stage, I C1 -q2 = I L1 =I O, where q2 is the electric charge of capacitor C1 in the second step-down stage.

[0083] Furthermore, based on the principle of capacitor charge ampere-second balance, it can be deduced that:

[0084] I C1 -q1*D = I C1 -q2*(1 - D)

[0085] I C1 -q1 = IL*(1 - D) / D

[0086] I O =(IL + IL*(1 - D) / D)*D + IL*(1 - D)=IL*(2 - D)

[0087] IL = M2*I O

[0088] where IL is the average inductor current corresponding to inductor L1 in a step-down working cycle.

[0089] Secondly, the average inductor current of the voltage conversion circuit provided in the embodiment of the present disclosure in the step-down working mode is M2*I O = I O / (2 - D), which is less than the average inductor current I of the BUCK - BOOST circuit in the step-down working mode in the related art OUT . That is to say, in the step-down working mode, the inductor current of the voltage conversion circuit provided in the embodiment of the present disclosure is relatively small, and the conversion efficiency of the entire circuit is relatively high.

[0090] It should be noted that the switch types of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 include but are not limited to switching transistors, mechanical switches, optoelectronic switches, etc.

[0091] In summary, for the circuit and method provided in this embodiment, when in the boost working mode, the inductor current corresponding to the inductor in the voltage conversion circuit is not zero. Therefore, there is no right-half plane zero in this voltage conversion circuit, thus solving the technical problem of poor circuit transient caused by the existence of the right-half plane zero.

[0092] To implement the above embodiment, the present disclosure also proposes a voltage conversion device. This device can operate on a voltage conversion system, and this voltage conversion system includes a voltage conversion circuit as Figure 2 shown.

[0093] As Figure 8 shown, this voltage conversion device 800 includes:

[0094] An instruction receiving unit 801, configured to determine a working mode corresponding to a working instruction in response to receiving a working instruction for a voltage conversion circuit;

[0095] A signal determining unit 802, configured to determine a first control signal, a second control signal, a third control signal, and a fourth control signal corresponding to the working mode;

[0096] A circuit control unit 803, configured to input the first control signal to a control end of a first switch, input the second control signal to a control end of a second switch, input the third control signal to a control end of a third switch, and input the fourth control signal to a control end of a fourth switch, so that the voltage conversion circuit is in the working mode corresponding to the working instruction.

[0097] It should be noted that the foregoing explanations of the embodiments of the voltage conversion circuit and the voltage conversion method are also applicable to the voltage conversion device of this embodiment, and will not be elaborated here.

[0098] In summary, for the device provided in the embodiments of the present disclosure, when in the boost working mode, the inductor currents corresponding to the inductors in the voltage conversion circuit are all non-zero. Therefore, there is no right-half plane zero in this voltage conversion circuit, thereby solving the technical problem of poor circuit transient caused by the existence of the right-half plane zero.

[0099] To implement the above embodiments, the present disclosure also proposes a voltage conversion system, including: as Figure 2 the voltage conversion circuit shown; a processor, and a memory communicatively connected to the processor; the memory stores computer-executable instructions; the processor executes the computer-executable instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0100] To implement the above embodiments, the present disclosure also proposes a computer-readable storage medium storing computer-executable instructions, which are used to implement the method provided in the foregoing embodiments when executed by a processor.

[0101] To implement the above embodiments, the present disclosure also proposes a computer program product, including a computer program, which implements the method provided in the foregoing embodiments when executed by a processor.

[0102] The collection, storage, use, processing, transmission, provision, and disclosure of the user's personal information involved in the present disclosure all comply with the provisions of relevant laws and regulations and do not violate public order and good customs.

[0103] It should be noted that personal information from users should be collected for legal and reasonable purposes and not shared or sold outside of such legal uses. In addition, such collection / sharing should be carried out after obtaining the informed consent of the users, including but not limited to notifying the users to read the user agreement / user notice and sign an agreement / authorization including authorizing the relevant user information before the users use the function. In addition, any necessary steps should be taken to safeguard and protect access to such personal information data and ensure that others with access to the personal information data comply with their privacy policies and procedures.

[0104] The present disclosure anticipates embodiments that can provide users with the option to block the use or access of personal information data. That is, the present disclosure anticipates that hardware and / or software can be provided to prevent or block access to such personal information data. Once the personal information data is no longer needed, the risk can be minimized by restricting data collection and deleting the data. In addition, when applicable, personal identifiers are removed from such personal information to protect the privacy of the users.

[0105] In the description of the foregoing embodiments, the descriptions referring to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc. mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present disclosure. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples.

[0106] In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of the present disclosure, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0107] Any process or method description shown in the flowchart or described in other ways herein can be understood as representing a module, segment, or part of code including one or more executable instructions for implementing a customized logical function or process, and the scope of the preferred embodiments of the present disclosure includes additional implementations, where the functions can be executed in a substantially simultaneous manner or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present disclosure pertain.

[0108] The logic and / or steps represented in the flowchart or otherwise described herein can, for example, be considered as a definable sequence list of executable instructions for implementing logical functions, and can be specifically implemented in any computer-readable medium for use by an instruction execution system, apparatus, or device (such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device), or used in combination with these instruction execution systems, apparatus, or devices. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (non-exhaustive list) of computer-readable media include the following: electrical connection parts with one or more wirings (electronic devices), portable computer disk cartridges (magnetic devices), random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), fiber optic devices, and portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which a program can be printed, because the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0109] It should be understood that various parts of the present disclosure can be implemented using hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented using software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented using hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application-specific integrated circuits having suitable combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), etc.

[0110] Those of ordinary skill in the art of this technology can understand that all or part of the steps carried by the method of implementing the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0111] In addition, in various embodiments of the present disclosure, each functional unit may be integrated in a processing module, may exist physically alone for each unit, or two or more units may be integrated in a module. The above integrated module may be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it may also be stored in a computer-readable storage medium.

[0112] The above-mentioned storage medium may be a read-only memory, a magnetic disk or an optical disc, etc. Although the embodiments of the present disclosure have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present disclosure. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present disclosure.

Claims

1. A voltage conversion circuit, characterized in that, Comprising: A first switch, a second switch, a third switch, a fourth switch, a capacitor, and an inductor; wherein, The connection point between the first ends of the first switch and the second switch is the input end of the voltage conversion circuit. The second end of the first switch is respectively connected to the first end of the capacitor, the first end of the third switch, and the first end of the fourth switch. The second end of the second switch is respectively connected to the second end of the capacitor and the first end of the inductor. The connection point between the second end of the inductor and the second end of the third switch is the output end of the voltage conversion circuit. The second end of the fourth switch is grounded; When the voltage conversion circuit is in the boost working mode, the inductor current corresponding to the inductor is not zero.

2. The voltage conversion circuit according to claim 1, wherein The boost working mode includes at least one boost working cycle, and the boost working cycle includes a first boost stage and a second boost stage, wherein, When the voltage conversion circuit is in the first boost stage, the second switch and the fourth switch are both in the conducting state, and the first switch and the third switch are both in the off state; When the voltage conversion circuit is in the second boost stage, the first switch is in the conducting state, and the second switch, the third switch, and the fourth switch are all in the off state.

3. The voltage conversion circuit according to claim 2, wherein The inductor current corresponding to the inductor in the first boost stage, the inductor current corresponding to the inductor in the second boost stage, and the average inductor current corresponding to the inductor in the boost working cycle are all the output current corresponding to the output end of the voltage conversion circuit.

4. The voltage conversion circuit according to claim 1, wherein The working mode of the voltage conversion circuit further includes a buck working mode. The buck working mode includes at least one buck working cycle, and the buck working cycle includes a first buck stage and a second buck stage, wherein, When the voltage conversion circuit is in the first buck stage, the second switch and the third switch are both in the conducting state, and the first switch and the fourth switch are both in the off state; When the voltage conversion circuit is in the second buck stage, the fourth switch is in the conducting state, and the first switch, the second switch, and the third switch are all in the off state.

5. The voltage conversion circuit according to claim 4, characterized in that, The average inductor current corresponding to the inductor in the buck working mode is the product of the voltage conversion ratio and the output current corresponding to the output end of the voltage conversion circuit. The voltage conversion ratio is the ratio of the output voltage to the input voltage of the voltage conversion circuit.

6. A voltage conversion method, characterized in that, Applied to a voltage conversion system, the voltage conversion system includes the voltage conversion circuit according to any one of claims 1 to 5, and the method includes: In response to receiving a working instruction for the voltage conversion circuit, determining the working mode corresponding to the working instruction; Determining the first control signal, the second control signal, the third control signal, and the fourth control signal corresponding to the working mode; Input the first control signal to the control terminal of the first switch, input the second control signal to the control terminal of the second switch, input the third control signal to the control terminal of the third switch, and input the fourth control signal to the control terminal of the fourth switch, so that the voltage conversion circuit is in the working mode corresponding to the working instruction.

7. The voltage conversion method according to claim 6, wherein The duty cycles of the first control signal, the second control signal, the third control signal, and the fourth control signal are the same.

8. A voltage conversion device, characterized in that, Applied to a voltage conversion system, the voltage conversion system includes the voltage conversion circuit according to any one of claims 1 to 5, and includes: An instruction receiving unit, configured to determine the working mode corresponding to the working instruction in response to receiving the working instruction for the voltage conversion circuit; A signal determining unit, configured to determine the first control signal, the second control signal, the third control signal, and the fourth control signal corresponding to the working mode; A circuit control unit, configured to input the first control signal to the control terminal of the first switch, input the second control signal to the control terminal of the second switch, input the third control signal to the control terminal of the third switch, and input the fourth control signal to the control terminal of the fourth switch, so that the voltage conversion circuit is in the working mode corresponding to the working instruction.

9. A voltage conversion system, characterized in that, Includes: The voltage conversion circuit according to any one of claims 1 to 5; A processor and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to claim 6 or 7.

10. A computer-readable storage medium, characterized in that, Computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, they are used to implement the method according to claim 6 or 7.

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