Chip test packaging method of integrated IPD structure and chip packaging structure

Abstract

The invention discloses a chip testing and packaging method of an integrated IPD structure and a chip packaging structure, and the method comprises the steps: providing a device wafer which comprises a functional region and an electrode region; a cover plate wafer is provided, the device wafer and the cover plate wafer are connected in a bonding mode to form a wafer-level packaging structure, a working cavity is formed between the device wafer and the cover plate wafer, and the working cavity comprises the functional area; an IPD structure is manufactured on the surface, away from the working cavity, of the cover plate wafer, and the IPD structure is connected to the electrode area; connecting the wafer-level packaging structure integrated with the IPD structure to test equipment; in the manufacturing process, wafer-level batch testing is conducted on the wafer-level packaging structure, the IPD structure is adjusted in time according to the testing result, and the wafer packaging manufacturing and iterative optimization cost is reduced while the optimal performance of the wafer-level packaging structure is achieved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor packaging and testing, and particularly to a chip testing and packaging method and a chip packaging structure integrating an IPD structure. Background Art

[0002] In the prior art, a filter is an important component of a mobile communication terminal product. For the integrated packaging method of a filter, an IPD chip is usually obtained through an Integrated Passive Devices (IPD) technology. The IPD chip can realize the performance regulation of the filter. The IPD chip and the filter chip are arranged in parallel on a substrate for integrated packaging. The filter chip and the IPD chip are respectively designed and manufactured on wafers. After the two groups of wafers are cut into single chips respectively, they are parallelly mounted on the substrate, occupying the areas of two chips. And when performing the performance regulation of the filter, it is necessary to repeatedly iterate the design of the IPD chip wafer and remanufacture it, which increases the product iteration cost and causes resource waste. Summary of the Invention

[0003] One object of the present invention is to provide a chip testing and packaging method integrating an IPD structure, so as to at least solve the technical problems of high product iteration cost and resource waste in the filter packaging and manufacturing in the prior art.

[0004] One object of the present invention is to provide a chip packaging structure integrating an IPD structure.

[0005] To achieve one of the above-mentioned objects of the present invention, an embodiment of the present invention provides a chip testing and packaging method integrating an IPD structure, including the following steps:

[0006] Provide a device wafer, including a functional area and an electrode area;

[0007] Provide a cover wafer, and bond and connect the device wafer and the cover wafer to form a wafer-level packaging structure. A working cavity is formed between the device wafer and the cover wafer, and the working cavity includes a functional area;

[0008] Fabricate an IPD structure on the surface of the cover wafer facing away from the working cavity, and connect the IPD structure to the electrode area;

[0009] Connect the wafer-level packaging structure integrating the IPD structure to a testing device.

[0010] As a further improvement of an embodiment of the present invention, it includes the step of:

[0011] Fabricate pads on the surface of the cover wafer facing away from the working cavity, and connect the pads to the IPD structure;

[0012] "Connecting a wafer-level packaging structure integrating an IPD structure to a test device" includes the steps of connecting pads to the test device.

[0013] As a further improvement of an embodiment of the present invention, it includes the steps of:

[0014] Fabricate through-silicon vias on the surface of the cover wafer facing away from the working cavity, fabricate a redistribution layer on the surface of the cover wafer facing away from the working cavity and the surface of the through-silicon vias, the redistribution layer is connected to the electrode region, and the redistribution layer includes an IPD structure and pads.

[0015] As a further improvement of an embodiment of the present invention, it includes the steps of:

[0016] If the performance of the wafer-level packaging structure does not meet the expected requirements, readjust the design of the IPD structure.

[0017] As a further improvement of an embodiment of the present invention, "readjusting the design of the IPD structure" includes the steps of adjusting the line width and / or line pitch of the passive device layer.

[0018] As a further improvement of an embodiment of the present invention, "readjusting the design of the IPD structure" includes the steps of remaking the redistribution layer and reconnecting the IPD structure to the test device.

[0019] As a further improvement of an embodiment of the present invention, it includes the steps of: if the performance of the wafer-level packaging structure meets the expected requirements, fabricate an electrical connection structure on the surface of the redistribution layer, and the electrical connection structure is used to connect to an external circuit.

[0020] As a further improvement of an embodiment of the present invention, it includes the steps of dicing the wafer-level packaging structure to obtain a chip packaging structure integrating a single IPD structure.

[0021] As a further improvement of an embodiment of the present invention, the device wafer includes a piezoelectric thin film, the piezoelectric thin film corresponds to the functional region and the outer periphery of the piezoelectric thin film is coupled to the electrode region.

[0022] As a further improvement of an embodiment of the present invention, the working cavity includes a second cavity located between the cover and the piezoelectric thin film.

[0023] As a further improvement of an embodiment of the present invention, the working cavity includes a first cavity located between the functional region and the piezoelectric thin film.

[0024] As a further improvement of an embodiment of the present invention, the piezoelectric thin film includes an opening, and the opening communicates the first cavity and the second cavity.

[0025] As a further improvement of an embodiment of the present invention, the cover wafer is provided with a dam, the dam is disposed around the outer periphery of the second cavity, and the through-silicon via penetrates through the dam to expose the electrode region.

[0026] To achieve one of the above-mentioned invention purposes, an embodiment of the present invention provides a packaging structure of a surface acoustic wave filter chip, which is fabricated by using the packaging method of the surface acoustic wave filter chip according to any one of the above technical solutions.

[0027] Compared with the prior art, the present invention provides a chip test packaging method with an integrated IPD structure. After bonding the cover wafer and the device wafer, an IPD structure is fabricated on the surface of the cover wafer facing away from the working cavity, and the wafer-level packaging structure with the integrated IPD structure is connected to a test device to perform performance testing on the overall wafer-level packaging structure, and the IPD structure is adjusted in a timely manner, so as to achieve the optimal performance of the wafer-level packaging structure while reducing the wafer packaging manufacturing and iterative optimization costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a flowchart of the chip test packaging method with an integrated IPD structure in an embodiment of the present invention.

[0029] Figure 2 It is a schematic diagram of providing a device wafer and bonding the device wafer and the cover wafer in an embodiment of the present invention.

[0030] Figure 3 It is a schematic diagram of fabricating an IPD structure in an embodiment of the present invention.

[0031] Figure 4 It is a schematic diagram of connecting the IPD structure to a test device in an embodiment of the present invention.

[0032] Figure 5 It is a schematic diagram of adjusting the IPD structure in an embodiment of the present invention.

[0033] Figure 6 It is a schematic diagram of fabricating a solder mask and an electrical connection structure in an embodiment of the present invention.

[0034] Figure 7 It is a schematic diagram of cutting the wafer-level packaging structure in an embodiment of the present invention.

[0035] Figure 8 It is a schematic diagram of the chip packaging structure with an integrated IPD structure in an embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0036] The present invention will be described in detail below in conjunction with the specific embodiments shown in the accompanying drawings. However, these embodiments do not limit the present invention, and any structural, methodical, or functional transformations made by those of ordinary skill in the art based on these embodiments are included within the protection scope of the present invention.

[0037] It should be noted that the term "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements that are inherent to such process, method, article, or device. In addition, the terms "first", "second", "third", "fourth", etc. are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0038] The term "connected", "connected to" or any other variant is intended to cover various relative positions of existing connection relationships, so as to include direct connection or indirect connection. Among them, the direct connection can be formed through the construction of a gas pipeline, and the indirect connection can be a connection relationship constructed through devices such as valve bodies and sensors, can be a connection relationship constructed through gas circuit components such as a brake control unit, or can be a connection relationship constructed through any other medium such as air.

[0039] Please refer to Figure 1 , which is a schematic diagram of the steps of a chip test packaging method for an integrated IPD structure provided by an embodiment of the present invention. In a specific embodiment, the chip type is a bulk acoustic wave filter chip, and in other embodiments, it can also be a surface acoustic wave filter chip.

[0040] The chip test packaging method for the integrated IPD structure includes the following steps: providing a device wafer 100, including a functional area 11 and an electrode area 12; providing a cover wafer 300, and bonding and connecting the device wafer 100 and the cover wafer 300 to form a wafer-level packaging structure 500, a working cavity 110 is formed between the device wafer 100 and the cover wafer 300, and the working cavity 110 includes the functional area 11; fabricating an IPD structure 32 on the surface of the cover wafer 300 facing away from the working cavity 110, and the IPD structure 32 is connected to the electrode area 12; connecting the wafer-level packaging structure integrated with the IPD structure 32 to a test device; to perform a functional test on the overall structure.

[0041] Next, in conjunction with Figures 2 to 8 , the chip test packaging method for the integrated IPD structure 32 of the present invention will be elaborated in detail.

[0042] Step S1: Provide a device wafer 100, including a functional area 11 and an electrode area 12. Please refer to Figure 2, In a specific embodiment, the device wafer 100 is a filter wafer, including a plurality of filter chips arranged in an array and a cutting area located between adjacent filter chips, facilitating subsequent cutting to form a chip package structure of a single integrated IPD structure 32.

[0043] Each of the chips includes a functional area 11 on the same side and an electrode area 12 coupled to the functional area 11. The substrate of the chip can be silicon, silicon oxide, silicon carbide, etc., and then the functional area 11 and the electrode area 12 are fabricated through processes such as etching, deposition, patterning, and so on.

[0044] The electrode area 12 is also a pad area, located at the outer peripheral position of the chip and arranged around the functional area 11, facilitating subsequent coupling connection with an external circuit. In other embodiments, the positions of the electrode area 12 and the functional area 11 can also be flexibly adjusted according to wiring requirements.

[0045] In one embodiment, the functional area 11 is located at the middle position of the chip. The functional area 11 can include structures such as piezoelectric materials and transducers, and its filtering characteristics are completed by the excitation, propagation, and reception of surface acoustic waves on the piezoelectric material.

[0046] In one embodiment, the functional area 11 is located at the middle position of the chip. The functional area 11 includes a piezoelectric thin film 13 for realizing filtering performance, and the outer periphery of the piezoelectric thin film 13 is coupled to the electrode area 12.

[0047] In one embodiment, a stepped structure is formed on the surface of the device wafer 100 to facilitate the placement of the piezoelectric thin film 13. The functional area 11 includes a first cavity 111 located between the surface of the device wafer 100 and the piezoelectric thin film 13, which is equivalent to forming a first cavity 111 between the piezoelectric thin film 13 and the stepped structure.

[0048] In combination with the specific embodiment, the surface of the device wafer 100 corresponding to the functional area 11 and the electrode area 12 are not on the same horizontal plane. Figure 1 As described above, the surface of the device wafer 100 corresponding to the functional area 11 is lower than the electrode area 12. Optionally, a groove is first formed on the substrate surface through processes such as etching and patterning, and then the functional area 11 and the electrode area 12 are fabricated through processes such as wiring.

[0049] The piezoelectric thin film 13 is disposed on the stepped structure, and the outer periphery of the piezoelectric thin film 13 is connected to the electrode area 12, which is equivalent to connecting the piezoelectric thin film 13 into the circuit. The piezoelectric thin film 13 is electrically connected to the electrode area 12, thereby leading out the signal through the electrode area 12.

[0050] Step S2: Provide a cover wafer 300, and bond and connect the device wafer 100 and the cover wafer 300 to form a wafer-level packaging structure 500. A working cavity 110 is formed between the device wafer 100 and the cover wafer 300. The working cavity 110 includes a functional area 11. Further, the working cavity 110 includes a piezoelectric thin film 13 and a first cavity 111 located between the surface of the device wafer 100 and the piezoelectric thin film 13. In other words, the functional area 11 is within the working cavity 110.

[0051] Continue to refer to Figure 2 , the cover wafer 300 can be made of materials such as silicon wafers or glass, and a sealed cavity is formed between it and the functional area 11, thereby protecting the chip and forming a cavity without interference required for operation.

[0052] The cover wafer 300 includes a dam 310. The dam 310 can be formed by etching and patterning. In other words, the dam 310 can be integrally formed with the cover wafer 300. Alternatively, "raising the cover wafer 300" includes: the cover wafer 300 fabricates the dam 310 and forms it by means of deposition and bonding connection.

[0053] The dam 310 is bonded and connected to the device wafer 100 and is used to form the working cavity 110 with the device wafer 100. The dam 310 at least overlaps with part of the electrode area 12, facilitating the exposure of the electrode area 12 in the subsequent through-silicon via process.

[0054] In other embodiments, the dam 310 can also be formed on the device wafer 100 and then bonded and connected to the cover wafer 300. Optionally, the bonding connection method is glue, organic bonding, metal bonding, etc.

[0055] In this way, the device wafer 100 and the cover wafer 300 are provided independently in sequence, reducing the wafer processing cost and resource consumption. Then, the device wafer 100 and the cover wafer 300 are bonded and connected to form the wafer-level packaging structure 500, reducing the occupied area of the subsequent external substrate and facilitating the miniaturization of the subsequent packaging structure.

[0056] In one embodiment, the working cavity 110 includes a second cavity 112 located between the cover wafer 300 and the piezoelectric thin film 13. The dam 310 surrounds the outer periphery of the second cavity 112. In this case, the working cavity 110 includes the piezoelectric thin film 13 and the corresponding first cavity 111 and second cavity 112 above and below it.

[0057] In one embodiment, the piezoelectric thin film 13 includes an opening, and the opening communicates the first cavity 111 and the second cavity 112.

[0058] In a specific embodiment of the present case, a stepped structure is formed on the surface of the device wafer 100 corresponding to the surface of the functional area 11, and the piezoelectric thin film 13 is disposed on the stepped structure and coupled to the electrode area 12, so that a first cavity 111 is formed between the piezoelectric thin film 13 and the surface of the device wafer 100. The cover wafer 300 integrally forms a dam 310, and the dam 310 is bonded to the non-functional area and at least overlaps a part of the electrode area 12. The piezoelectric thin film 13 is located in the middle of the working cavity 110, thus dividing the working cavity 110 into a first cavity 111 and a second cavity 112.

[0059] Step S3: Fabricate an IPD structure 32 on the surface of the cover wafer 300 facing away from the working cavity 110. The IPD structure 32 is connected to the electrode area 12 for subsequent testing. The IPD structure 32 is a capacitance and inductance filtering network formed by one or more layers of metal lines.

[0060] Combined Figure 3 As shown, the IPD structure 32 is fabricated outside the chip working cavity 110. The IPD structure 32 is coupled to the electrode area 12 and then connected to the functional area 11 to achieve electrical interconnection with the device wafer 100, enabling high-throughput batch testing of the performance of the entire wafer-level packaging structure.

[0061] Among them, "fabricating the IPD structure 32" includes step S31:

[0062] Fabricate pads on the surface of the cover wafer 300 facing away from the working cavity 110. The pads are connected to the IPD structure 32 and are used for testing. "Connecting the wafer-level packaging structure 200 integrated with the IPD structure 32 to a testing device" includes the steps of: connecting the pads to the testing device. The testing device is coupled to the pads and then coupled to the IPD structure 32 and the functional area 11, thereby testing the filtering performance of the wafer-level packaging structure.

[0063] Among them, "fabricating the IPD structure 32" includes step S32:

[0064] Fabricate through-silicon vias 33 on the surface of the cover wafer 300 facing away from the working cavity 110, and fabricate a redistribution layer 31 on the surface of the cover wafer 300 facing away from the working cavity 110 and the surface of the through-silicon vias 33. The redistribution layer 31 is connected to the electrode area 12. The redistribution layer 31 includes the IPD structure 32 and pads. The through-silicon vias 33 penetrate the dam 310 to expose the electrode area 12.

[0065] The through-silicon via 33 penetrates through the cover wafer 300 and the connection between the cover wafer 300 and the device wafer 100, thereby exposing the electrode region 12 of the device wafer 100 and facilitating the extraction of signals from the electrode region 12. The redistribution layer 31 can be a single-layer or multi-layer metal line, including the IPD structure 32 and pads for testing.

[0066] Combined Figure 3 As shown, in a specific embodiment of this case, the steps of the test packaging method include: after the cover wafer 300 and the device wafer 100 are bonded and connected, a through-silicon via 33 is fabricated on the side of the cover wafer 300 facing away from the working cavity 110. The through-silicon via 33 penetrates through the cover wafer 300 and the dam 310, and exposes the electrode region 12; a redistribution layer 31 is fabricated on the surface of the cover wafer 300 facing away from the working cavity 110 and the wall surface of the through-silicon via 33. The redistribution layer 31 includes the IPD structure 32 and pads, and the region of the redistribution layer 31 at the bottom of the through-silicon via 33 is electrically connected to the electrode region 12.

[0067] Step S4: Connect the wafer-level packaging structure integrated with the IPD structure 32 to the test equipment. Combined Figure 4 As shown, connect the pads to the test equipment. Perform wafer-level testing on the wafer-level packaging structure 500 integrated with the IPD structure 32, and collect test data to evaluate whether the filter wafer of the integrated IPD structure 32 meets filtering performance such as broadband, low insertion loss, and high out-of-band rejection. Compare the bandwidth, in-band insertion loss value, out-of-band characteristic frequency band / frequency point rejection value, etc. of the wafer-level packaging structure 500 of the integrated IPD structure 32 obtained from the test with the design expected values to determine whether the performance of the cover wafer 300 and the filter wafer meets the expected requirements.

[0068] Step S5: If the performance of the wafer-level packaging structure does not meet the expected requirements, readjust the design of the IPD structure 32 until the wafer-level packaging structure 500 meets the expected requirements.

[0069] Among them, "readjusting the design of the IPD structure 32" includes the steps of: adjusting the line width and / or line pitch of the IPD structure 32. Combined Figure 5 As shown, if the performance of the wafer-level packaging structure 500 integrated with the IPD structure is close to but does not meet the requirements, fine-tuning actions such as lithography / etching, laser ablation, or focused ion beam (FIB) are performed on the line width / line pitch, etc. of the IPD structure 32 circuit, that is, conditioning of the wafer-level packaging structure is realized on the surface of the wafer-level packaging structure 500, so that the performance of the wafer-level packaging structure 500 integrated with the IPD after conditioning is closer to the design requirements, and the test process of step S4 is repeated.

[0070] Among them, "readjusting the design of the IPD structure 32" includes the steps of: remaking the redistribution layer 31 and reconnecting the IPD structure 32 to the test equipment. If the performance of the wafer-level package structure 500 integrated with the IPD has a large gap from the expected requirements, or if major adjustments are needed to the shape, size, etc. of the IPD structure 32, the metal layer on the surface of the cover wafer 300 is removed by methods such as full-surface etching and polishing. Subsequently, steps S3 and S4 are repeated to remake the IPD structure 32 on the surface of the cover wafer 300 facing away from the working cavity 110 and perform test adjustments until the performance of the filter integrated with the IPD meets the requirements.

[0071] In this way, by fabricating the IPD structure 32 outside the working cavity 110, wafer-level high-throughput filtering performance testing can be directly designed without cutting into individual chips and mounting them on a substrate for testing, reducing labor costs and other resource consumption.

[0072] Moreover, the IPD structure 32 on the wafer-level package structure 500 can be immediately fine-tuned according to the test results, or removed and reintegrated. In this way, on several surface acoustic wave filter chips, the fabrication of the integrated IPD structure 32, the filtering performance testing of the IPD structure 32, and the adjustment or removal of the IPD structure 32 can be sequentially performed, and such iterative cycles are carried out to achieve the optimal performance of the wafer-level package structure 500 integrated with the IPD, greatly reducing the wafer manufacturing and iterative optimization costs.

[0073] Step S6: If the performance of the wafer-level package structure 500 meets the expected requirements, an electrical connection structure 34 is fabricated on the surface of the redistribution layer 31, and the electrical connection structure 34 is used to connect to an external circuit. The electrical connection structure 34 can be selected as solder balls. As shown in Figure 6 figure, a solder mask 35 is fabricated on the surface of the redistribution layer 31 and solder balls are implanted.

[0074] If the performance of the wafer-level package structure 500 meets the expected requirements during the initial test, the electrical connection structure 34 can be directly fabricated to complete dicing and encapsulation; if the performance test of the wafer-level package structure 500 cannot meet the expected requirements, the processes of repeated testing, fine-tuning / remaking, and testing can be carried out until the requirements are met.

[0075] Step S7: The wafer-level package structure 500 is diced to obtain a chip package structure 1000 with a single integrated IPD structure 32, as shown in Figures 7 - 8As shown, the wafer-level packaging structure 500 after the above steps has been optimized, and the integrated circuits of each corresponding chip and IPD structure 32 have achieved the expected test performance. Along the scribe line area between two adjacent chips, the device wafer 100 and the cover wafer 300 are cut. The specific cutting process will not be elaborated here. The chip packaging structure 1000 integrating the IPD structure 32 is hereinafter referred to as the chip packaging structure 1000. After the chip packaging structure 1000 is electrically connected to the external substrate, it is then integrally encapsulated and fixed.

[0076] The chip packaging structure 1000 includes a chip and a cover. The chip is cut from the device wafer 100, and the cover is cut from the cover wafer 300. A working cavity 110 is formed between the chip and the cover. The chip includes a functional area 11 and an electrode area 12 that are coupled. The functional area is located within the working cavity 110, and the electrode area 12 is disposed around the functional area 11.

[0077] The chip packaging structure 1000 includes a piezoelectric thin film 13, and the outer periphery of the piezoelectric thin film 13 is coupled to the electrode area 12.

[0078] A stepped structure is formed on the surface of the chip, and the piezoelectric thin film 13 is disposed on the stepped structure. The functional area 11 includes the piezoelectric thin film 13 and a first cavity 111 located between the piezoelectric thin film 13 and the surface of the chip. The working cavity 110 includes the functional area 11 and a second cavity 112 located between the cover and the piezoelectric thin film 13. In other words, the working cavity includes the piezoelectric thin film 13 and the first cavity 111 and the second cavity 112 above and below it.

[0079] The piezoelectric thin film 13 includes an opening that communicates the first cavity 111 and the second cavity 112.

[0080] The cover is provided with through-silicon vias 33 on the side facing away from the working cavity 110, and the cover includes a redistribution layer 31 disposed on the surface facing away from the working cavity 110 and the surface of the through-silicon vias 33. The redistribution layer 31 includes the IPD structure 32; the chip packaging structure 1000 includes a solder mask layer 35 and an electrical connection structure 34 disposed on the redistribution layer 31, and the electrical connection structure 34 is used to electrically connect to the external substrate.

[0081] The encapsulation layer wraps the peripheries of the chip and the cover and fills the gap between the cover and the external substrate.

[0082] The beneficial effects of the present invention are as follows: After bonding and connecting the cover wafer 300 and the device wafer 100, an IPD structure 32 is fabricated on the surface of the cover wafer 300 facing away from the working cavity 110, and the wafer-level packaging structure integrated with the IPD structure 32 is connected to a testing device to perform performance testing on the overall wafer-level packaging structure 500, and the IPD structure is adjusted in a timely manner. Based on the test data, the IPD structure 32 can be optionally fine-tuned or removed and remade, achieving the optimal performance of the wafer-level packaging structure 500 while reducing the manufacturing and iterative optimization costs of wafer packaging.

[0083] It can be formed corresponding to any of the technical solutions provided above, and will not be elaborated here.

[0084] It should be understood that although this specification is described according to embodiments, not every embodiment only contains an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

[0085] The series of detailed descriptions listed above are only specific descriptions of the feasible embodiments of the present invention, and they are not intended to limit the protection scope of the present invention. Any equivalent embodiments or changes made without departing from the technical spirit of the present invention should be included in the protection scope of the present invention.

Claims

1. A chip test packaging method with an integrated IPD structure, characterized in that, Including the following steps: Providing a device wafer, including a functional area and an electrode area; Providing a cover wafer, and bonding and connecting the device wafer and the cover wafer to form a wafer-level packaging structure, a working cavity is formed between the device wafer and the cover wafer, and the working cavity includes the functional area; Fabricating an IPD structure on the surface of the cover wafer facing away from the working cavity, and the IPD structure is connected to the electrode area; Connecting the wafer-level packaging structure integrated with the IPD structure to a test device.

2. The chip test packaging method of the integrated IPD structure according to claim 1, wherein Including steps: Fabricating pads on the surface of the cover wafer facing away from the working cavity, and the pads are connected to the IPD structure; "Connecting the wafer-level packaging structure integrated with the IPD structure to a test device" includes the step of connecting the pads to the test device.

3. The chip test packaging method of the integrated IPD structure according to claim 1, wherein Including steps: Fabricating through-silicon vias on the surface of the cover wafer facing away from the working cavity, and fabricating a redistribution layer on the surface of the cover wafer facing away from the working cavity and the surface of the through-silicon vias, the redistribution layer is connected to the electrode area, and the redistribution layer includes an IPD structure and pads.

4. The chip test packaging method of the integrated IPD structure according to claim 3, characterized in that Including steps: If the performance of the wafer-level packaging structure does not meet the expected requirements, readjusting and designing the IPD structure.

5. The chip test packaging method of the integrated IPD structure according to claim 4, characterized in that, "Readjusting and designing the IPD structure" includes the steps of adjusting the line width and / or line pitch of the IPD structure.

6. The chip test packaging method of the integrated IPD structure according to claim 4, wherein "Readjusting and designing the IPD structure" includes the steps of remaking the redistribution layer and connecting the wafer-level packaging structure integrated with the IPD structure to the test device again.

7. The chip test packaging method for the integrated IPD structure according to claim 3, characterized in that, Including steps: If the performance of the wafer-level packaging structure meets the expected requirements, fabricating an electrical connection structure on the surface of the redistribution layer, and the electrical connection structure is used to connect to an external circuit.

8. The chip test packaging method of the integrated IPD structure according to claim 7, characterized in that, Including steps: Cutting the wafer-level packaging structure to obtain a chip packaging structure with a single integrated IPD structure.

9. The chip test packaging method of the integrated IPD structure according to claim 3, characterized in that, The functional area includes a piezoelectric thin film, and the outer periphery of the piezoelectric thin film is coupled to the electrode area.

10. The chip test packaging method of the integrated IPD structure according to claim 9, characterized in that, The functional area includes a first cavity located between the surface of the device wafer and the piezoelectric thin film.

11. The chip test packaging method of the integrated IPD structure according to claim 10, wherein, The working cavity includes a functional area and a second cavity located between the cover wafer and the piezoelectric thin film.

12. The chip test packaging method of the integrated IPD structure according to claim 11, wherein The piezoelectric thin film includes an opening, and the opening communicates the first cavity and the second cavity.

13. The chip test packaging method of the integrated IPD structure according to claim 11, wherein The cover wafer is provided with a dam, the dam surrounds the outer periphery of the second cavity, and the through hole penetrates the dam to expose the electrode area.

14. An integrated chip packaging structure with an IPD structure, characterized in that: Applied and fabricated by the chip test packaging method of the integrated IPD structure according to any one of claims 1-13.

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