High-speed clock duty ratio calibration circuit

Abstract

The invention provides a high-speed clock duty ratio calibration circuit. The high-speed clock duty ratio calibration circuit comprises an upper-path adjustment sub-circuit and a lower-path adjustment sub-circuit, wherein a feedback control sub-circuit is arranged between the upper-path adjustment sub-circuit and the lower-path adjustment sub-circuit; clock signals input by the input ends of the upper adjusting sub-circuit and the lower adjusting sub-circuit form clock differential signals. The feedback control sub-circuit is used for generating optimal duty ratio control codes of an upper path and a lower path; and the upper adjusting sub-circuit and the lower adjusting sub-circuit control rising edges and falling edges of own clocks according to the corresponding optimal duty ratio control codes, so that the duty ratio is adjusted. The duty ratio calibration circuit can be applied to the CMOS technology of 28 nm or below, high-speed ADC, DAC and SERDES chip design for duty ratio calibration, and the duty ratio calibration circuit has the advantages of being high in precision, low in power consumption and small in area.

Description

Technical Field

[0001] The invention belongs to the technical field of high-speed chip systems, and in particular relates to a high-speed clock duty cycle calibration circuit. Background Art

[0002] In high-speed ADC applications, the problem caused by duty cycle imbalance is more prominent. Due to the imbalance of the duty cycle, the timing of the rising and falling edges of the sampling clock will be asymmetric. This asymmetry further increases the clock jitter, which is one of the key factors affecting the performance of the ADC. Especially when the input signal frequency is high, the clock jitter has a more obvious negative impact on the signal-to-noise ratio (SNR) of the ADC, resulting in a decrease in the accuracy of the ADC when processing high-frequency signals, and the inability to accurately convert analog signals into digital signals, which greatly affects the system's ability to collect and process analog signals.

[0003] In high-speed DAC design, duty cycle error can cause serious timing problems. It can disrupt the normal timing of the digital logic inside the DAC, such as causing the clock edge of the trigger latch to shift. These shifts will be directly transmitted to the analog output link, introducing glitches and nonlinear distortion in the analog output. In addition, duty cycle deviation can cause the clock signal spectrum to change, introducing even-order harmonic distortion (such as 2nd and 4th harmonics), thereby reducing the spurious-free dynamic range (SFDR), greatly reducing the quality of the DAC output signal, and failing to meet the needs of high-speed, high-precision signal conversion.

[0004] For high-speed SERDES chips, their normal operation depends on high-speed clocks to accurately sample and recover serial data. However, duty cycle deviation can seriously hinder this process. Duty cycle deviation can cause eye closure, significantly reducing the effective data window width. This means that the time window available for data transmission and processing becomes smaller, and the communication fault tolerance becomes worse, which significantly increases the bit error rate (BER). Moreover, duty cycle imbalance can also increase the harmonic components of the clock signal. Excessive harmonic components can radiate electromagnetic interference (EMI) into the surrounding space, and even cause electromagnetic interference to exceed the standard, which not only affects the performance of the chip itself, but may also interfere with other surrounding electronic devices, endangering the stability and reliability of the entire electronic system.

[0005] In chip design, high-speed clock duty cycle calibration is a key technology to ensure the quality of clock signals, especially in the field of high-speed chip design with advanced processes of 28 nm and below. Specifically, it has a crucial clock duty cycle calibration function in the design of high-speed ADC (analog-to-digital converter), DAC (digital-to-analog converter), and SERDES (serializer / deserializer) chips with frequencies in the dozens of GHz range. In the design of this specific process and chip type, there is usually a stringent requirement of a 50% ratio for the clock duty cycle. Deviations in the duty cycle will directly affect performance parameters, timing convergence, data sampling windows, and system reliability, etc.

[0006] As Figures 1-4 shown, the duty cycle calibration of existing technologies usually adopts a method implemented by a partially analog circuit. In the implementation scheme, a continuous-time integrator is realized using a fully differential amplifier to convert the duty cycle deviation into a voltage signal. Through a feedback loop, the input buffer and transconductance amplifier are adjusted, and then the rising / falling edges of the clock are adjusted, ultimately achieving duty cycle calibration.

[0007] However, in the methods of existing technologies, since a fully differential amplifier is used to implement the integration device, the circuit complexity is high, the power consumption is high, and the area is large. The specific reason is that a fully differential amplifier requires a symmetric circuit structure to ensure the common-mode rejection ratio (CMRR), resulting in a significant increase in static current and dynamic power consumption. The continuous-time integrator needs to maintain a high-gain state for a long time, further exacerbating the power consumption problem. For example, the operational amplifier of the integrator needs a wide-bandwidth design at high-speed clocks, and its bias current may reach the level of several milliamperes; and the inherent input offset voltage of the fully differential amplifier (typical value is about 0.5 - 5 mV) will be directly superimposed on the duty cycle detection signal. For example, if the integrator converts a 1% duty cycle deviation into a 10 mV error, a 5 mV offset will introduce a 50% detection error, and additional circuits or algorithms must be used for offset calibration, thereby increasing the implementation complexity and also increasing the implementation power consumption again. Summary of the Invention

[0008] To solve the above problems existing in the prior art, the present invention provides a high-speed clock duty cycle calibration method. The technical problems to be solved by the present invention are achieved through the following technical solutions:

[0009] A high-speed clock duty cycle calibration circuit includes: an upper path adjustment sub-circuit and a lower path adjustment sub-circuit, and a feedback control sub-circuit is arranged between the upper path adjustment sub-circuit and the lower path adjustment sub-circuit; the clock signals input to the inputs of the upper path adjustment sub-circuit and the lower path adjustment sub-circuit form a clock differential signal; the feedback control sub-circuit is used to generate the optimal duty cycle control codes for the upper and lower paths; the upper path adjustment sub-circuit and the lower path adjustment sub-circuit control the rising and falling edges of their own clocks according to the corresponding optimal duty cycle control codes, thereby adjusting the duty cycle.

[0010] Beneficial effects:

[0011] The present invention provides a high-speed clock duty cycle calibration circuit, which includes: an upper path adjustment sub-circuit and a lower path adjustment sub-circuit, and a feedback control sub-circuit is arranged between the upper path adjustment sub-circuit and the lower path adjustment sub-circuit; the clock signals input at the input ends of the upper path adjustment sub-circuit and the lower path adjustment sub-circuit form a clock differential signal; the feedback control sub-circuit is used to generate the optimal duty cycle control codes for the upper path and the lower path; the upper path adjustment sub-circuit and the lower path adjustment sub-circuit control the rising edge and the falling edge of their own clocks according to the corresponding optimal duty cycle control codes, so as to adjust the duty cycle. The present invention can be applied to the duty cycle calibration in the chip designs of high-speed ADC (analog-to-digital converter), DAC (digital-to-analog converter), and SERDES (serializer / deserializer) under the CMOS process of 28 nm and below, and the present invention has the advantages of high precision, low power consumption, and small area.

[0012] The following will further describe the present invention in detail with reference to the accompanying drawings and embodiments. Brief description of the drawings

[0013] Figures 1-4 is the structural diagram of the prior art solution;

[0014] Figure 5 is the schematic diagram of a high-speed clock duty cycle calibration circuit provided by the present invention;

[0015] Figure 6 is the schematic diagram of the integrator module provided by the present invention;

[0016] Figure 7 is the schematic diagram of the comparator module provided by the present invention;

[0017] Figure 8 is the schematic diagram of duty cycle adjustment module example 1 provided by the present invention;

[0018] Figure 9 is the schematic diagram of duty cycle adjustment module example 2 provided by the present invention;

[0019] Figure 10 is the schematic diagram of duty cycle adjustment module example 3 provided by the present invention. Detailed implementation manners

[0020] The following will further describe the present invention in detail with reference to specific embodiments, but the implementation manners of the present invention are not limited thereto.

[0021] As Figure 5As shown in the figure, the present invention provides a high-speed clock duty cycle calibration circuit, which includes: an upper path adjustment sub-circuit and a lower path adjustment sub-circuit, and a feedback control sub-circuit is arranged between the upper path adjustment sub-circuit and the lower path adjustment sub-circuit; the clock signals input at the inputs of the upper path adjustment sub-circuit and the lower path adjustment sub-circuit form a clock differential signal; the feedback control sub-circuit is used to generate the optimal duty cycle control codes for the upper path and the lower path; the upper path adjustment sub-circuit and the lower path adjustment sub-circuit control the rising edge and the falling edge of their own clocks according to the corresponding optimal duty cycle control codes, so as to adjust the duty cycle.

[0022] Among them, both the upper path adjustment sub-circuit and the lower path adjustment sub-circuit include four inverter units and a duty cycle adjustment module. Among them, the first inverter unit, the second inverter unit, the duty cycle adjustment module, the third inverter unit and the fourth inverter unit are connected in sequence, and the first inverter unit inputs a clock signal; the output of the duty cycle adjustment module is also connected to the input of the feedback control sub-circuit, and the output of the feedback control sub-circuit is connected to the input of the duty cycle adjustment module.

[0023] Reference Figure 5 , the clock differential input signals CLKINP and CLKINN respectively pass through the inverter basic unit (standard CMOS inverter) and enter the duty cycle comparison and adjustment module (module 1 in the following figure). This module controls the duty cycle adjustment module through the control codes (dccp<7:0>, dccn<7:0>) generated by the feedback control path (the red frame in the following figure), mainly controlling the rising and falling edges of the inverter to achieve duty cycle adjustment.

[0024] Reference Figure 5 , the reverse control sub-circuit includes an integrator module, a comparator module and a search control logic module connected in sequence; the input of the integrator module is respectively connected to the outputs of the duty cycle adjustment modules in the two path adjustment sub-circuits, and the output of the search control logic module is connected to the input of the duty cycle adjustment modules in the two path adjustment sub-circuits.

[0025] The integrator module is used to convert the duty cycle value output by the duty cycle adjustment module into a voltage value and output it to the comparator module; the comparator module is used to compare whether the two input voltage values are the same. If they are the same, it means the duty cycle is 50%. If the duty cycle is greater than 50%, a high level is output, otherwise a low level is output; the search control module is used to perform two searches in the positive and negative directions according to the output of the comparator module to find the optimal duty cycle control code, and then output it.

[0026] The feedback control sub - circuit consists of an integrator (Module 2), a comparator (Module 3), and a search control logic (Module 4). The integrator mainly uses an inverter + RC filtering method to convert the duty cycle ratio into a voltage value. The comparator is mainly used to compare the duty cycles. If the duty cycle of the clock is 50%, the high and low levels are balanced, and at this time, the two inputs of the comparator should be the same. If the duty cycle is greater than 50%, the comparator outputs a high level. If the duty cycle is less than 50%, the comparator outputs a low level. The search control logic, based on the output of the comparator, uses forward and reverse directions to search twice, eliminating the comparator offset while finding the optimal duty - cycle control word to achieve precise 50% duty - cycle calibration.

[0027] Reference Figure 6 As shown, the integrator module includes a PMOS transistor P1, an NMOS transistor P2, and a capacitor C1. Among them, the gate of the PMOS transistor P1 and the gate of the NMOS transistor P2 are connected to the output of the duty - cycle adjustment module. The source of the PMOS transistor P1 and the drain of the NMOS transistor P2 are connected to the first end of the capacitor C1. The second end of the capacitor C1 and the source of the NMOS transistor P2 are both grounded, and the drain of the PMOS transistor P1 is connected to the power supply.

[0028] The comparator module uses an open - loop comparator. In the present invention, precise offset calibration can be achieved without adding additional circuits. Therefore, the comparator module (Module 3) can use a common open - loop comparator, which has a simple structure and is easy to implement. Taking the NMOS differential input as an example, the circuit diagram is as Figure 7 shown.

[0029] The duty - cycle adjustment module (Module 1) mainly realizes the control of the rising edge and falling edge of the clock signal, thereby adjusting the duty cycle. Taking the P - end input as an example, three implementation examples are given, which are respectively Figures 8-10 shown.

[0030] As Figure 8As shown, the duty cycle adjustment module includes PMOS transistors H0 - H7, G0 - G7, and N1, and NMOS transistors M0 - M7, D0 - D7, and N2. Among them, the gates of PMOS transistors H0 - H7 are correspondingly connected to duty cycle control codes dccp<0> - dccp<7>, and the sources are correspondingly connected to the drains. The sources of PMOS transistors G0 - G7 are correspondingly connected to the drains of NMOS transistors M0 - M7. The gates of PMOS transistors G0 - G7 are correspondingly connected to the gates of NMOS transistors M0 - M7 and are connected to the clock signal output by the second inverter unit. The sources of NMOS transistors M0 - M7 are correspondingly connected to the drains of NMOS transistors D0 - D7 and serve as the output terminals. The gates of NMOS transistors D0 - D7 are correspondingly connected to duty cycle control codes dccn<0> - dccn<7>, and the sources are grounded. The gates of PMOS transistor N1, NMOS transistor N2, and the sources of PMOS transistors G0 - G7 are connected together. The source of PMOS transistor N1 is connected to the drain of NMOS transistor N2. The drain of PMOS transistor N1 is connected to the power supply, and the source of NMOS transistor N2 is grounded.

[0031] In Figure 8 Example 1 of, the present application realizes edge control by controlling the number of inverter units connected, and further adjusts the duty cycle.

[0032] As Figure 9 shown, the duty cycle adjustment module includes PMOS transistors H0 - H7, N1, and F1, and NMOS transistors D0 - D7, N2, and F2. Among them, the gates of PMOS transistors H0 - H7 are correspondingly connected to duty cycle control codes dccp<0> - dccp<7>, and the sources are connected together with the source of PMOS transistor F1, the drain of NMOS transistor F2, the gate of PMOS transistor N1, the gate of NMOS transistor N2, and the drains of NMOS transistors D0 - D7. The drains of PMOS transistors H0 - H7, PMOS transistor F1, and PMOS transistor N1 are connected to the power supply. The sources of NMOS transistors D0 - D7, NMOS transistor F2, and NMOS transistor N2 are grounded. The gates of NMOS transistor F2 and PMOS transistor F1 are connected and are connected to the clock signal output by the second inverter unit. The drain of NMOS transistor N2 and the source of PMOS transistor N1 are connected and serve as the output terminal.

[0033] In Figure 9 Example 2 of, the present application realizes edge control by controlling the number of PMOS and NMOS of the inverter connected, and further adjusts the duty cycle.

[0034] As Figure 10As shown, the duty cycle adjustment module includes NMOS transistors D0 - D7, F2, and N2, PMOS transistors F1 and N1, and capacitors C0 - C7. Among them, the gates of NMOS transistors D0 - D7 are correspondingly connected to duty cycle control codes dccn<0> - dccn<7>. The drains of NMOS transistors D0 - D7 are correspondingly connected to the first ends of capacitors C0 - C7, and the second ends of capacitors C0 - C7 are connected to the source of PMOS transistor F1. The gate of NMOS transistor F2 is connected to the gate of PMOS transistor F1 and is connected to the clock signal output by the second inverter unit. The drains of PMOS transistors F1 and N1 are connected to the power supply. The drain of NMOS transistor F2 is connected to the source of PMOS transistor F1. The source of PMOS transistor N1 is connected to the drain of NMOS transistor N2 and serves as the output terminal. The gate of PMOS transistor N1 is connected to the gate of NMOS transistor N2 and the second end of capacitor C3. The sources of NMOS transistors D0 - D7, F2, and N2 are all grounded.

[0035] In Figure 10 Example 3 of Figure 10 it is single - end control, and dccp<7:0> is floating.

[0036] The search control logic module of the present invention is specifically used for:

[0037] Scanning all duty cycle control codes and setting the duty cycle control codes to the lowest;

[0038] Gradually increasing the duty cycle control codes until the duty cycle is close to 50%. When the output jumps from 1 to 0 at each duty cycle control code, record the duty cycle control code A;

[0039] Adjusting the scanning direction and scanning the duty cycle control codes from the highest downwards. Gradually decreasing the duty cycle control codes until the duty cycle is close to 50%. When the output jumps from 0 to 1 at each duty cycle control code, record the duty cycle control code B;

[0040] According to the duty cycle control codes that jump from 1 to 0 and from 0 to 1, locking the output duty cycle control code to floor((A + B) / 2), where floor represents rounding down.

[0041] It should be noted that the practice of two - way scanning avoids the measurement inaccuracy introduced by the offset of the comparator, thereby achieving precise control. During two - way scanning, each scan can be executed multiple times and then averaged to achieve higher - precision duty cycle calibration.

[0042] The duty cycle calibration of the present invention is implemented by digital circuits. The integrator design is realized by using an inverter + RC method. The duty cycle adjustment path uses digital signals to control the rising and falling edges of the inverter. As the digital control code increases, the duty cycle gradually shrinks. In terms of duty cycle comparison, a comparator is used. If the duty cycle of the clock is 50%, the high and low levels are balanced, and at this time the two inputs of the comparator should be the same. If the duty cycle is greater than 50%, the comparator outputs a high level. If the duty cycle is less than 50%, the comparator outputs a low level. By using the forward and reverse directions and performing multiple averaging operations during each search, the comparator offset is eliminated while the optimal duty cycle control word is found, achieving precise 50% duty cycle calibration.

[0043] It should be noted that the terms "first" and "second" in the present invention are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present invention, "a plurality" means two or more unless otherwise specifically defined.

[0044] Although the present application has been described in connection with various embodiments herein, however, in the process of implementing the claimed present application, those skilled in the art can understand and realize other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosed content, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality of cases.

[0045] The above content is a further detailed description of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is only limited to these descriptions. For those of ordinary skill in the technical field to which the present invention pertains, without departing from the concept of the present invention, several simple deductions or substitutions can be made, and all should be regarded as belonging to the protection scope of the present invention.

Claims

1. A high-speed clock duty cycle calibration circuit, characterized in that, Comprising: An up - path adjustment sub - circuit and a down - path adjustment sub - circuit, with a feedback control sub - circuit arranged between the up - path adjustment sub - circuit and the down - path adjustment sub - circuit; The clock signals input at the inputs of the up - path adjustment sub - circuit and the down - path adjustment sub - circuit form a clock differential signal; The feedback control sub - circuit is used to generate the optimal duty - cycle control codes for the up - path and the down - path; the up - path adjustment sub - circuit and the down - path adjustment sub - circuit control the rising edge and the falling edge of their own clocks according to the corresponding optimal duty - cycle control codes, so as to adjust the duty - cycle.

2. The high-speed clock duty cycle calibration circuit according to claim 1, characterized in that, Both the up - path adjustment sub - circuit and the down - path adjustment sub - circuit include four inverter units and a duty - cycle adjustment module. Among them, the first inverter unit, the second inverter unit, the duty - cycle adjustment module, the third inverter unit, and the fourth inverter unit are connected in sequence. The first inverter unit inputs the clock signal; the output of the duty - cycle adjustment module is also connected to the input of the feedback control sub - circuit, and the output of the feedback control sub - circuit is connected to the input of the duty - cycle adjustment module.

3. The high-speed clock duty cycle calibration circuit according to claim 2, wherein The reverse control sub - circuit includes an integrator module, a comparator module, and a search control logic module connected in sequence; the input of the integrator module is respectively connected to the outputs of the duty - cycle adjustment modules in the two adjustment sub - circuits, and the output of the search control logic module is connected to the input of the duty - cycle adjustment modules in the two adjustment sub - circuits.

4. The high-speed clock duty cycle calibration circuit according to claim 3, wherein The integrator is used to convert the duty - cycle value output by the duty - cycle adjustment module into a voltage value and output it to the comparator module; The comparator module is used to compare whether the two input voltage values are the same. If they are the same, it means the duty - cycle is 50%. If the duty - cycle is greater than 50%, it outputs a high level, otherwise it outputs a low level; The search control module is used to perform two searches in the positive and negative directions according to the output of the comparator module to find the optimal duty - cycle control code, and then output it.

5. The high-speed clock duty cycle calibration circuit according to claim 3, wherein The integrator module includes a PMOS transistor P1, an NMOS transistor P2, and a capacitor C1. Among them, the gate of the PMOS transistor P1 and the gate of the NMOS transistor P2 are connected to the output of the duty - cycle adjustment module. The source of the PMOS transistor P1 and the drain of the NMOS transistor P2 are connected to the first end of the capacitor C1. The second end of the capacitor C1 and the source of the NMOS transistor P2 are both grounded, and the drain of the PMOS transistor P1 is connected to the power supply.

6. The high-speed clock duty cycle calibration circuit according to claim 3, wherein The comparator module uses an open - loop comparator.

7. The high-speed clock duty cycle calibration circuit according to claim 3, wherein The search control logic module is specifically used for: Scanning all the duty - cycle control codes and setting the duty - cycle control code to the lowest; Gradually increasing the duty - cycle control code until the duty - cycle is close to 50%. When the output jumps from 1 to 0 at each duty - cycle control code, record this duty - cycle control code A; Adjusting the scanning direction and scanning the duty - cycle control codes from the highest downwards, gradually decreasing the duty - cycle control code until the duty - cycle is close to 50%. When the output jumps from 0 to 1 at each duty - cycle control code, record this duty - cycle control code B; According to the duty - cycle control codes that jump from 1 to 0 and from 0 to 1, locking the output duty - cycle control code to floor((A + B) / 2), where floor represents rounding down.

8. The high-speed clock duty cycle calibration circuit according to claim 3, wherein The duty cycle adjustment module includes PMOS transistors H0 - H7, G0 - G7 and N1, and NMOS transistors M0 - M7, D0 - D7 and N2. Among them, the gates of PMOS transistors H0 - H7 are correspondingly connected to the duty cycle control codes dccp<0> - dccp<7>, and the sources are correspondingly connected to the drains. The sources of PMOS transistors G0 - G7 are correspondingly connected to the drains of NMOS transistors M0 - M7. The gates of PMOS transistors G0 - G7 are correspondingly connected to the gates of NMOS transistors M0 - M7 and are connected to the clock signal output by the second inverter unit. The sources of NMOS transistors M0 - M7 are correspondingly connected to the drains of NMOS transistors D0 - D7 and serve as output terminals. The gates of NMOS transistors D0 - D7 are correspondingly connected to the duty cycle control codes dccn<0> - dccn<7>, and the sources are grounded. The gates of PMOS transistor N1, NMOS transistor N2, and the sources of PMOS transistors G0 - G7 are connected together. The source of PMOS transistor N1 is connected to the drain of NMOS transistor N2. The drain of PMOS transistor N1 is connected to the power supply, and the source of NMOS transistor N2 is grounded.

9. The high-speed clock duty cycle calibration circuit according to claim 3, wherein The duty cycle adjustment module includes PMOS transistors H0 - H7, N1 and F1, and NMOS transistors D0 - D7, N2 and F2; Among them, the gates of PMOS transistors H0 - H7 are correspondingly connected to the duty cycle control codes dccp<0> - dccp<7>, and the sources are connected together with the source of PMOS transistor F1, the drain of NMOS transistor F2, the gate of PMOS transistor N1, the gate of NMOS transistor N2, and the drains of NMOS transistors D0 - D7. The drains of PMOS transistors H0 - H7, PMOS transistor F1 and PMOS transistor N1 are connected to the power supply. The sources of NMOS transistors D0 - D7, NMOS transistor F2 and NMOS transistor N2 are grounded. The gates of NMOS transistor F2 and PMOS transistor F1 are connected and are connected to the clock signal output by the second inverter unit. The drain of NMOS transistor N2 and the source of PMOS transistor N1 are connected and serve as the output terminal.

10. The high-speed clock duty cycle calibration circuit according to claim 3, wherein The duty cycle adjustment module includes NMOS transistors D0 - D7, F2 and N2, PMOS transistors F1 and N1, and capacitors C0 - C7. Among them, the gates of NMOS transistors D0 - D7 are correspondingly connected to the duty cycle control codes dccn<0> - dccn<7>. The drains of NMOS transistors D0 - D7 are correspondingly connected to the first ends of capacitors C0 - C7. The second ends of capacitors C0 - C7 are connected to the source of PMOS transistor F1. The gate of NMOS transistor F2 is connected to the gate of PMOS transistor F1 and is connected to the clock signal output by the second inverter unit. The drains of PMOS transistor F1 and N1 are connected to the power supply. The drain of NMOS transistor F2 is connected to the source of PMOS transistor F1. The source of PMOS transistor N1 is connected to the drain of NMOS transistor N2 and serves as the output terminal. The gate of the PMOS transistor N1 is connected to the gate of the NMOS transistor N2 and the second end of the capacitor C3. The sources of NMOS transistors D0 - D7, F2 and N2 are all grounded.

Images