High-frequency digital low-level phase automatic calibration method

Abstract

The invention discloses a high-frequency digital low-level phase automatic calibration method, which comprises the following steps of: 1) changing a clock edge of a digital control oscillator (NCO) for non-orthogonal sampling of an analog-to-digital converter signal, and finishing the clock edge calibration of the NCO when the phase of a reference signal is recovered to a correct value; 2) directly performing intermediate frequency digital signal Non-iq sampling on the direct digital frequency synthesis DDS excitation output signal to obtain the phase of the DDS excitation signal; 3) changing an NCO signal clock edge used for generating a DDS excitation signal, and when the DDS signal phase recovers to a correct value, completing the clock edge calibration of the NCO so as to complete digital low-level phase calibration; and 4) automatically adjusting an NCO clock edge for ADC sampling and an NCO clock edge for DDS excitation signals to obtain a correct reference signal phase and a correct DDS signal phase so as to complete phase calibration of the digital low-level system. The intelligent degree of phase calibration is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of accelerators, and particularly relates to a high-frequency digital low-level phase automatic calibration method, which is used to realize the automatic recovery of the high-frequency digital low-level phase after the high-frequency low-level device loses power or is restarted after shutdown, and can also be applied to the calibration and recovery of phase parameters of digital systems in other fields. Background Art

[0002] The high-frequency system is crucial in the accelerator device and is the "engine" of the entire accelerator system. An RF electric field is established in the high-frequency resonant cavity. Charged particles move along the longitudinal orbit. When they pass through the RF electric field, they obtain energy in the acceleration phase and are accelerated or longitudinally bunched. If the RF field phase of the high-frequency cavity is incorrect, the beam particles will not be able to obtain the correct energy for acceleration or even deceleration, resulting in the abnormal operation of the light source device. Thus, the importance of the RF field phase of the high-frequency cavity can be seen.

[0003] The high-frequency low-level control system is one of the basic components of the accelerator high-frequency system. Its most important function is to control the amplitude and phase of the RF electric field in the high-frequency cavity so that particles can obtain appropriate energy supply when passing through the high-frequency cavity. The high-frequency low-level control system is a digital control system. When the system loses power or is restarted, due to the change of the clock acquisition edge of the low-level digital signal processing board, the phase value of the low-level control system will change and phase calibration is required. Otherwise, at the same low-level set phase, the RF field phase of the high-frequency cavity will change, resulting in the abnormal operation of the light source.

[0004] If the low-level phase is not calibrated, the accelerator physics needs to perform a 360-degree phase sweep on the high-frequency phase to find the previous correct phase, which is time-consuming and laborious. The conventional low-level phase calibration method is to use the analog phase discrimination method to perform analog phase discrimination on the cavity field signal and the reference line signal to obtain the phase difference φ cav , and as long as the set phase of the low-level is adjusted so that the phase difference φ cav is consistent with the phase value before the low-level loses power or is restarted, the correct set phase of the low-level is found, the calibration and recovery of the low-level phase are completed, and it is ensured that the RF field of the high-frequency cavity can perform normal energy supply to the beam. Although this method can ensure the normal operation of the high-frequency system, the phase parameters of the low-level have all changed compared with those before power loss or restart, and the low-level data parameters are inconsistent before and after, which is not conducive to the long-term data analysis and stable operation of the low-level system. Summary of the Invention

[0005] In view of the various adverse results caused by the change of phase parameters in the digital low-level system after power-off or restart, the present invention provides a high-frequency digital low-level phase automatic calibration method. Two sets of NCO quadrature signal pairs are generated inside the digital low level, which are respectively used for the Non-IQ sampling of the ADC signal and the DAC output of the DDS excitation signal. By changing the clock edges of these two sets of NCO quadrature signal pairs, the phase of the reference signal and the phase of the DDS excitation signal can be restored, and the calibration of the digital low-level phase is completed. To improve efficiency, a python program is used. First, the clock edge of the NCO for ADC sampling is automatically adjusted, and the phase of the current reference signal is compared with the correct phase of the reference signal. When the absolute value of the difference between the two is within 5 degrees, the adjustment of the clock edge of the NCO signal for ADC sampling is completed. Next, the clock edge of the NCO for DAC excitation output is automatically adjusted, and the phase of the current DDS excitation signal is compared with the correct phase of the DDS excitation signal. When the absolute value of the difference between the two is within 5 degrees, the adjustment of the clock edge of the NCO for DAC excitation output is stopped, and the phase calibration of the digital low-level system is completed.

[0006] The technical solution of the present invention is as follows:

[0007] A high-frequency digital low-level phase automatic calibration method, the steps of which include:

[0008] 1) Generate two sets of NCO quadrature signal pairs with the same frequency as the intermediate frequency IF signal inside the low-level control system of the accelerator high-frequency system, namely the sin_adc / cos_adc quadrature signal pair and the sin_dac / cos_dac quadrature signal pair; set two NCO clock edge control input signals to respectively control the clock edges of the two sets of NCO quadrature signal pairs;

[0009] 2) Assign the values of ref_pha and dds_pha at any moment during the normal operation of the accelerator device to ref_old_pha and dds_old_pha as the reference values for low-level phase calibration; where, ref_old_pha is the correct low-level phase of the reference signal and dds_old_pha is the correct low-level phase of the DDS excitation signal;

[0010] 3) Down-convert the reference signal of the accelerator high-frequency system into an IF intermediate frequency signal and sample it by an ADC to obtain an IF intermediate frequency sampling signal; use the sin_adc / cos_adc quadrature signal pair to perform a Non-iq sampling algorithm on the IF intermediate frequency sampling signal to obtain the I / Q quantity of the reference signal, and then obtain the amplitude and phase of the reference signal according to the I / Q quantity of the reference signal;

[0011] 4) The sin_dac signal and cos_dac signal in the sin_dac / cos_dac orthogonal signal pair are respectively multiplied by the I / Q quantities of the low-level system-set cavity pressure signal and then added to obtain the DDS excitation signal. The DDS excitation signal is output as an intermediate-frequency IF excitation signal after being converted by DAC digital-to-analog conversion and then up-converted to obtain a high-frequency RF excitation signal; and the DDS excitation signal is sampled non-iq to obtain the I / Q quantities of the DDS excitation signal, and then the amplitude and phase of the DDS excitation signal are obtained according to the I / Q quantities of the DDS excitation signal.

[0012] 5) When the accelerator high-frequency system loses power or restarts, the automatic calibration function of the high-frequency low-level control system is enabled.

[0013] 51) Online and in real-time read the current low-level phase ref_pha of the reference signal and the current low-level phase dds_pha of the DDS excitation signal.

[0014] 52) Compare in real-time to obtain the deviation δ1 between the current low-level phase ref_pha of the reference signal and the correct low-level phase ref_old_pha of the reference signal, and the deviation δ2 between the current low-voltage phase dds_pha of the DDS excitation signal and the correct low-level phase dds_old_pha of the DDS excitation signal.

[0015] 53) When the absolute value of δ1 is less than the set threshold, set the phase logic status quantity ref_pha_flag of the reference signal to high level, otherwise to low level; when the absolute value of δ2 is less than the set threshold, set the phase logic status quantity dds_pha_flag of the DDS excitation signal to high level, otherwise to low level.

[0016] 54) When the phase logic status quantity ref_pha_flag of the reference signal is at low level, control the input signal through the NCO clock edge to change the clock edge of the sin_adc / cos_adc orthogonal signal pair until the phase logic status quantity of the reference signal becomes high level.

[0017] 55) When the phase logic status quantity ref_pha_flag of the reference signal is at high level and the phase logic status quantity of the DDS excitation signal is at low level, control the input signal through the NCO clock edge to change the clock edge of the sin_dac / cos_dac orthogonal signal pair until the phase logic status quantity of the DDS excitation signal becomes high level.

[0018] 56) When the phase logic status quantity ref_pha_flag of the reference signal and the phase logic status quantity dds_pha_flag of the DDS excitation signal are both at high level, the automatic calibration function is completed.

[0019] Further, the set threshold is 5 degrees.

[0020] Further, the automatic calibration function is completed based on the Python programming language.

[0021] Further, the I / Q values of the DDS excitation signal are converted by the coordinate rotation digital computation method algorithm to obtain the amplitude and phase of the DDS excitation signal.

[0022] Further, the amplitude and phase of the reference signal are obtained by using the CORDIC algorithm according to the I / Q quantity of the reference signal.

[0023] Further, a cascaded integrator comb filter or an averaging filter is used to perform Non-iq sampling on the input signal to obtain the I / Q quantity of the reference signal.

[0024] Further, a cascaded integrator comb filter or an averaging filter is used to perform Non-iq sampling on the input signal to obtain the I / Q quantity of the DDS excitation signal.

[0025] Further, the method of using the sin_adc / cos_adc orthogonal signal to perform the Non-iq sampling algorithm on the IF intermediate frequency sampling signal is: multiplying and accumulating the IF intermediate frequency sampling signal with the sin_adc signal and the cos_adc signal in the sin_adc / cos_adc orthogonal signal pair respectively and filtering to obtain the I / Q quantity of the reference signal.

[0026] A high-frequency digital low-level phase automatic calibration method, the steps of which include:

[0027] The low-level system FPGA firmware algorithm completes the acquisition of the intermediate frequency IF signal, the generation of the DDS excitation signal, the control of the internal NCO controller, etc.

[0028] Two groups of NCO orthogonal signal pairs (sinω0n and cosω0n) with an angular frequency of the intermediate frequency ω0 are generated inside the digital low level, namely the sin_adc / cos_adc orthogonal signal pair and the sin_dac / cos_dac orthogonal signal pair. The sin_adc / cos_adc orthogonal signal pair is used for Non-IQ sampling of the digital IF intermediate frequency signal; the sin_dac / cos_dac orthogonal signal pair is used to generate the DDS excitation signal, which is output as an intermediate frequency excitation signal after passing through the DAC, and then is up-converted to generate a high-frequency low-level RF excitation signal and sent to the high-frequency power source for amplification. The low-level system adds clock edge control input signals to the two NCOs respectively, so as to realize the clock edge control of the two groups of NCO orthogonal signal pairs.

[0029] The direct Non-IQ sampling DDS excitation output signal is sampled using the sin_adc / cos_adc orthogonal signal pair to obtain the I / Q values of the DDS excitation signal, and then the amplitude and phase of the DDS excitation signal are obtained by converting the I / Q values of the DDS excitation signal through the Coordinate Rotation Digital Computer (CORDIC) algorithm.

[0030] The automatic calibration algorithm is an upper-layer algorithm implemented based on the Python programming language. It reads the process variable (PV) of the low-level system to implement the logic control of automatic phase calibration.

[0031] When the automatic phase calibration enable switch pha_recover is at a high level, the automatic calibration function is enabled. After the phase calibration is completed, the enable switch is automatically set to a low level. When the automatic phase calibration enable switch is at a low level, no calibration action is performed.

[0032] The correct low-level phases of the reference signal and the DDS excitation signal are ref_old_pha and dds_old_pha respectively. These two phase values are the reference values for low-level phase calibration. Before performing low-level phase calibration, the correctness of these two phases needs to be ensured. These two phases are from the phase ref_pha of the reference signal and the phase dds_pha of the DDS excitation signal of the high-frequency system during the normal operation of the accelerator device. Usually, during the normal operation of the accelerator device, the values of ref_pha and dds_pha at a certain moment are assigned to ref_old_pha and dds_old_pha as the reference values for low-level phase calibration.

[0033] During automatic calibration, the current low-level phases ref_pha and dds_pha of the reference signal and the DDS excitation signal are read online in real time. The deviation δ1 between the current low-level phase ref_pha of the reference signal and the correct low-level phase ref_old_pha of the reference signal, and the deviation δ2 between the current low-voltage phase dds_pha of the DDS excitation signal and the correct low-level phase dds_old_pha of the DDS excitation signal are compared in real time.

[0034] The phase logic status variable of the reference signal is ref_pha_flag. When the absolute value of the deviation value δ1 between the current phase and the correct phase of the reference signal is less than 5 degrees, the phase logic status variable ref_pha_flag of the reference signal is set to a high level, otherwise it is set to a low level.

[0035] The phase logic state variable dds_pha_flag of the DDS excitation signal. When the absolute value of the deviation δ2 between the current phase and the correct phase of the DDS excitation signal is less than 5 degrees, the phase logic state variable dds_pha_flag of the DDS excitation signal is set to high level, otherwise it is set to low level.

[0036] When the phase logic state variable ref_pha_flag of the reference signal is at low level, adjust the NCO clock edge control input signal amount, thereby changing the NCO clock edge corresponding to the sin_adc / cos_adc quadrature signal pair, so that the phase of the sin_adc / cos_adc quadrature signal pair changes. When the phase logic state variable of the reference signal becomes high level, stop changing the NCO clock edge control input signal.

[0037] Similarly, when the phase logic state variable dds_pha_flag of the DDS excitation signal is high level and at the same time the phase logic state variable of the DDS excitation signal is low level, change the NCO clock edge of the sin_dac / cos_dac quadrature signal pair until the phase logic state variable of the DDS excitation signal becomes high level.

[0038] When the phase logic state variables ref_pha_flag of the reference signal and dds_pha_flag of the DDS excitation signal are both at high level, the automatic calibration function is completed.

[0039] The automatic calibration method is only applicable to the low-level open-loop state, and there may be phase compensation due to loop feedback in the closed-loop state, resulting in a deviation in the DDS phase.

[0040] The phase automatic calibration algorithm uses the pyepics module to establish an interface between Python and the Experimental Physics and Industrial Control System (EPICS), and realizes the access of Python language to the PV quantity of the EPICS system.

[0041] The advantages of the present invention are as follows:

[0042] 1) Compared with the method of analog phase discrimination to recover the low-level phase, this method simplifies the hardware system and only needs to implement phase calibration and recovery by writing the firmware algorithm of the low-level system and the upper-layer software control.

[0043] 2) The analog phase discrimination method can only ensure the recovery of the correct cavity field phase and cannot recover the low-level setting parameters. The present invention can completely recover the state of the low-level system, and at the same time ensure that the low-level parameters, the cavity field phase are exactly the same as before power-off or restart.

[0044] 3) This method develops an automatic phase calibration program, which can complete the automatic calibration of the phase of the digital low-level system with one key, improving the intelligence level of phase calibration. Description of the Drawings

[0045] Figure 1 It is the schematic diagram of Non-IQ sampling for the ADC intermediate frequency signal.

[0046] Figure 2 It is the schematic diagram of the DAC output and Non-IQ sampling for the DDS excitation signal.

[0047] Figure 3 It is the block diagram of the low-level phase automatic calibration state. Specific Embodiments

[0048] The present invention will be further described in detail below with reference to the drawings. The examples given are only used to explain the present invention and are not intended to limit the scope of the present invention.

[0049] Sampling of the ADC intermediate frequency signal in the low-level system: The sampling schematic diagram of the ADC intermediate frequency signal is as Figure 1 shown. The NCO generates in-phase and quadrature sinω0n and cosω0n signals with the same frequency as the sampled intermediate frequency (IF) signal. The Non-IQ algorithm of multiplying and accumulating the IF intermediate frequency sampling signal with sinω0n and cosω0n respectively is adopted, and then the high-frequency signal can be filtered out by using a cascade integrator comb (CIC) or an averaging filter to obtain the I / Q DC in-phase and quadrature signal quantities. Changing the clock edge of the NCO will obtain different I / Q quantities, thus obtaining different sampling signal phases.

[0050] DAC signal output in the low-level system: The schematic diagram of the DDS excitation signal output of the DAC is as Figure 2 shown. The NCO is used to generate in-phase and quadrature sinω0n and cosω0n signals with the same frequency as the sampled IF signal. The I / Q quantities are multiplied with sinω0n and cosω0n respectively, that is, digital domain mixing, to obtain the DDS intermediate frequency output signal. Changing the clock edge of the NCO will change the phase of the in-phase and quadrature signals output by the NCO, and then change the phase of the signal output by the DDS, and finally change the phase of the intermediate frequency excitation signal output by the DAC.

[0051] Direct sampling of the DDS output: The DDS excitation output signal is directly sampled by the Non-IQ algorithm in the firmware algorithm to obtain the I / Q quantities of the DDS excitation signal, and then the amplitude and phase of the DDS output are obtained through the CORDIC algorithm.

[0052] Sampling of reference signal: After the reference signal is down-converted to an IF intermediate-frequency signal, the I / Q quantities of the reference signal are obtained through ADC sampling, analog-to-digital conversion, and Non-IQ sampling, and then the amplitude and phase of the reference signal are obtained through the CORDIC algorithm.

[0053] PV quantities of the EPICS control system: Add the NCO clock edge control PV quantity Phi_adc for ADC sampling and the NCO clock edge control PV quantity Phi_dac for DAC output. The NCO output phase of the corresponding firmware algorithm can be changed through upper-layer control.

[0054] Installation of the pyepics module: pyepics is the Python interface of the EPICS Channel Access (CA) library of the EPICS control system, which enables Python programs to read and write PV quantities of the EPICS system.

[0055] Automatic phase calibration algorithm: The state block diagram of the low-level phase automatic calibration is as Figure 3 shown. The algorithm is implemented using a Python program to continuously read the phase ref_pha of the reference signal, the phase dds_pha of the DDS excitation signal, the reference signal reference phase ref_old_pha, the DDS excitation signal reference phase dds_old_pha, the reference signal phase logic status quantity ref_pha_flag, the DDS excitation signal phase logic status quantity dds_pha_flag, and the automatic calibration enable switch pha_recover. When the automatic calibration enable switch is at a low level, no calibration action is performed. When the automatic calibration enable switch is at a high level, automatic calibration starts: First, judge the reference signal phase logic status quantity ref_pha_falg. When it is at a low level, change the Phi_adc control quantity and monitor the reference phase logic status quantity until the reference signal phase logic status quantity ref_pha_flag becomes high, then stop changing the Phi_adc control quantity, and the NCO clock edge of the ADC sampling completes the calibration. Then judge the phase logic status quantity dds_pha_flag of the DDS excitation signal. When it is at a low level, change the Phi_dac control quantity and monitor the DDS excitation signal phase logic status quantity until the DDS excitation signal phase logic status quantity dds_pha_flag becomes high, then stop changing the Phi_dac control quantity, and the NCO clock edge of the DAC excitation output completes the calibration. When the phase logic status quantities of the reference signal and the DDS excitation signal are both high, it indicates that the low-level phase calibration is completed, and the low-level phase calibration enable switch quantity pha_recover is automatically set to zero to end the automatic phase calibration work.

[0056] Although specific embodiments of the present invention are disclosed for illustrative purposes, which are intended to help understand the content of the present invention and implement it accordingly, those skilled in the art can understand that various substitutions, changes, and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the best embodiments, and the scope of protection claimed by the present invention shall be defined by the scope defined in the claims.

Claims

1. A high-frequency digital low-level phase automatic calibration method, the steps of which include: 1) Generate two groups of NCO quadrature signal pairs with the same frequency as the intermediate frequency IF signal inside the low-level control system of the accelerator high-frequency system, namely the sin_adc / cos_adc quadrature signal pair and the sin_dac / cos_dac quadrature signal pair; Set two NCO clock edge control input signals to control the clock edges of the two groups of NCO quadrature signal pairs respectively; 2) Assign the values of ref_pha and dds_pha at any moment during the normal operation of the accelerator device to ref_old_pha and dds_old_pha respectively as the reference values for low-level phase calibration; where, ref_old_pha is the correct low-level phase of the reference signal and dds_old_pha is the correct low-level phase of the DDS excitation signal; 3) Down-convert the reference signal of the accelerator high-frequency system into an IF intermediate frequency signal and sample it by ADC to obtain an IF intermediate frequency sampling signal; Use the sin_adc / cos_adc quadrature signal pair to perform a Non-iq sampling algorithm on the IF intermediate frequency sampling signal to obtain the I / Q quantities of the reference signal, and then obtain the amplitude and phase of the reference signal according to the I / Q quantities of the reference signal; 4) Multiply and add the sin_dac signal and cos_dac signal in the sin_dac / cos_dac quadrature signal pair with the I / Q quantities of the set cavity voltage signal of the low-level system respectively to obtain a DDS excitation signal, convert the DDS excitation signal into an intermediate frequency IF excitation signal through DAC digital-to-analog conversion and then obtain a high-frequency RF excitation signal through up-conversion; And perform Non-iq sampling on the DDS excitation signal to obtain the I / Q quantities of the DDS excitation signal, and then obtain the amplitude and phase of the DDS excitation signal according to the I / Q quantities of the DDS excitation signal; 5) When the accelerator high-frequency system loses power or restarts, turn on the automatic calibration function of the high-frequency low-level control system; 51) Read the current low-level phase ref_pha of the reference signal and the current low-level phase dds_pha of the DDS excitation signal online in real time; 52) Compare in real time to obtain the deviation δ1 between the current low-level phase ref_pha of the reference signal and the correct low-level phase ref_old_pha of the reference signal, and the deviation δ2 between the current low-voltage phase dds_pha of the DDS excitation signal and the correct low-level phase dds_old_pha of the DDS excitation signal; 53) When the absolute value of δ1 is less than the set threshold, set the phase logic status quantity ref_pha_flag of the reference signal to high level, otherwise to low level; When the absolute value of δ2 is less than the set threshold, set the phase logic status quantity dds_pha_flag of the DDS excitation signal to high level, otherwise to low level; 54) When the phase logic state quantity ref_pha_flag of the reference signal is at a low level, the input signal is controlled by the NCO clock edge to change the clock edge of the sin_adc / cos_adc quadrature signal pair until the phase logic state quantity of the reference signal becomes high level; 55) When the phase logic state quantity ref_pha_flag of the reference signal is at a high level and the phase logic state quantity of the DDS excitation signal is at a low level, the input signal is controlled by the NCO clock edge to change the clock edge of the sin_dac / cos_dac quadrature signal pair until the phase logic state quantity of the DDS excitation signal becomes high level; 56) When the phase logic state quantity ref_pha_flag of the reference signal and the phase logic state quantity dds_pha_flag of the DDS excitation signal are both at a high level, the automatic calibration function is completed.

2. The method according to claim 1, wherein The set threshold is 5 degrees.

3. The method according to claim 1, wherein The automatic calibration function is completed based on the python programming language.

4. The method according to claim 1 or 2 or 3, characterized in that, The amplitude and phase of the DDS excitation signal are obtained by converting the I / Q values of the DDS excitation signal through the coordinate rotation digital calculation method algorithm.

5. The method according to claim 1 or 2 or 3, characterized in that, The amplitude and phase of the reference signal are obtained by using the CORDIC algorithm according to the I / Q quantity of the reference signal.

6. The method according to claim 1 or 2 or 3, characterized in that, The input signal is sampled by a cascaded integrator comb filter or an averaging filter for Non-iq sampling to obtain the I / Q quantity of the reference signal.

7. The method according to claim 1 or 2 or 3, characterized in that, The input signal is sampled by a cascaded integrator comb filter or an averaging filter for Non-iq sampling to obtain the I / Q quantity of the DDS excitation signal.

8. The method according to claim 1 or 2 or 3, characterized in that, The method of using the sin_adc / cos_adc quadrature signal pair to perform the Non-iq sampling algorithm on the IF intermediate frequency sampling signal is: multiplying and accumulating the IF intermediate frequency sampling signal with the sin_adc signal and the cos_adc signal in the sin_adc / cos_adc quadrature signal pair respectively and filtering to obtain the I / Q quantity of the reference signal.

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