High-speed optical chaos sequential logic device

Abstract

The invention discloses a high-speed optical chaos sequential logic device, which is characterized in that a logic input signal and a clock signal are generated through a distributed feedback laser, an intensity modulator and a polarization controller, and are injected into a first vertical cavity surface emitting laser through an optical coupler to generate chaos polarized light; the polarization chaotic state of the second vertical cavity surface emitting laser is dynamically regulated and controlled by utilizing the electro-optical effect of the periodically poled lithium niobate crystal under the action of an external electric field, so that the function switching of the data latch and the data trigger is realized; and carrying out sampling mean value demodulation on the X polarized light and the Y polarized light output by the second vertical cavity surface emitting laser through a digital communication analyzer, and judging a logic output state. The all-optical chaotic circuit has the advantages that based on all-optical chaotic signal processing, the electro-optical conversion rate bottleneck is broken through, dynamic reconstruction of the latch and the trigger is achieved, the multi-mode communication requirement is met, a mean value difference demodulation mechanism is adopted, and the operation speed, the anti-noise capacity and the logic stability are remarkably improved.

Description

Technical Field

[0001] The present invention relates to the technical field of optoelectronic devices, and particularly to a high-speed reconfigurable multi-triggered optical chaotic D-latch and D-flip-flop under clock synchronization. Background Art

[0002] In modern high-speed data communication and photonic computing systems, there is an urgent need for ultra-high-speed, low-latency, and highly reliable optical logic devices. Optical chaotic D-latches and D-flip-flops, relying on the randomness, anti-interference ability, and high-speed response characteristics of chaotic signals, have become the core components for realizing optical-domain timing logic operations. For example, in an optical fiber communication system with a speed exceeding 100 Gb / s, traditional electronic logic devices are limited by the electro-optic conversion bottleneck, while optical chaotic D-latches / flip-flops can directly complete signal storage and synchronization in the optical domain, reducing the delay and distortion in the electro-optic conversion link and significantly improving data processing efficiency. In addition, in scenarios such as quantum key distribution and chaotic secure communication, the dynamic reconfigurability and signal unpredictability of optical chaotic devices can effectively resist side-channel attacks and signal interception, providing physical-layer encryption protection for sensitive data.

[0003] However, the existing optical chaotic timing logic devices still have the following technical bottlenecks:

[0004] Contradiction between speed and noise tolerance: Most solutions need to extend the bit time to the order of 1 ns (rate ≤ 1 GHz) to ensure anti-noise performance, making it difficult to meet the Tb / s-level data processing requirements in 5G / 6G communications;

[0005] System complexity and functional singularity: Existing technologies mostly rely on cascaded architectures of multiple lasers, resulting in a large system volume, high power consumption, and limited trigger modes to a single clock edge (such as the rising edge), and unable to dynamically switch the latch / trigger function;

[0006] Insufficient synchronization accuracy: Non-standard duty cycle clock signals are prone to clock drift in precise timing control scenarios, leading to logical state mismatches;

[0007] Defects in security and scalability: Logic demodulation mechanisms based on fixed thresholds or polarization states are easily cracked by reverse engineering and difficult to adapt to multi-modal encryption protocols.

[0008] In current mainstream solutions, polarization light mean square error threshold demodulation mechanisms are commonly used in optical chaos logic devices. This mechanism is extremely sensitive to system noise and initial conditions. When external interference or noise intensity increases, the polarization light mean square error is easily beyond the threshold range, leading to a significant increase in the bit error rate of the logic output. In addition, existing systems often require multiple semiconductor lasers to work in coordination with complex optical paths, which not only incurs high costs but also causes system stability problems due to parameter mismatches between devices. The non-standardized design of the duty cycle of the optical clock signal further restricts its application in strict synchronization scenarios. At the same time, the single trigger condition (such as only supporting rising edge triggering) of existing flip-flops reduces the flexibility of the operation mode and is difficult to meet the requirements of multiple encryption and dynamic reconstruction.

[0009] Therefore, there is an urgent need to develop a high-speed, highly noise-resistant, reconfigurable and easily integrable optical chaos timing logic device to break through the limitations of existing technologies on communication rate, noise tolerance and functional flexibility, and meet the requirements of future optical networks and photonic computing systems for high-performance logic units. Summary of the Invention

[0010] The present invention aims at the defects of the existing technology and provides a high-speed optical chaos timing logic device.

[0011] In order to achieve the above invention purposes, the technical solutions adopted by the present invention are as follows:

[0012] A high-speed optical chaos timing logic device includes: a first distributed feedback laser 1, a second distributed feedback laser 2, a signal source 3, a first intensity modulator 4, a second intensity modulator 5, a first polarization controller 6, a second polarization controller 7, an optical coupler 8, a variable optical attenuator 9, an optical fiber splitter 10, a first vertical cavity surface emitting laser 13, a first optical isolator 14, a first fiber optic polarization beam splitter 15, a periodically poled lithium niobate crystal 18, a second vertical cavity surface emitting laser 23, a second optical isolator 24, a second fiber optic polarization beam splitter 25 and a digital communication analyzer 26;

[0013] The first distributed feedback laser 1 and the second distributed feedback laser 2 are used to generate initial laser signals;

[0014] The signal source 3 is used to output a logic input signal and a clock signal with a duty cycle of 50%;

[0015] The first intensity modulator 4 and the second intensity modulator 5 are respectively used to modulate the laser signals into optical D pulses and optical clock pulses;

[0016] The first polarization controller 6 and the second polarization controller 7 are used to align the optical D pulses and optical clock pulses to the X polarization direction;

[0017] An optical coupler 8, a variable optical attenuator 9, and an optical fiber splitter 10 are used to couple, attenuate, and split optical signals;

[0018] A first vertical cavity surface emitting laser 13 receives the X-polarized light from the optical fiber splitter 10 and the Y-polarized light converted by the first Faraday rotator 11 and the first half-wave plate 12, and outputs chaotic polarized light;

[0019] A first optical isolator 14 is connected between the first vertical cavity surface emitting laser 13 and the first fiber optic polarization beam splitter 15 to block the interference of the backward reflected light on the first vertical cavity surface emitting laser 13;

[0020] A periodically poled lithium niobate crystal 18 receives the X / Y polarized light from the first fiber optic polarization beam splitter 15, generates an electro-optic effect under the action of an external electric field, and outputs the modulated ordinary light and extraordinary light;

[0021] A second vertical cavity surface emitting laser 23 receives the amplified ordinary light from the periodically poled lithium niobate crystal 18 and the extraordinary light converted by the third Faraday rotator 19 and the third half-wave plate 20, and outputs chaotic polarized light;

[0022] A digital communication analyzer 26 is used to measure and analyze the logic output signal, and demodulate the logic output by comparing the mean values of the 40% sampled data of the X-polarized light and the Y-polarized light output by the second vertical cavity surface emitting laser 23 after each bit time.

[0023] Further, the first intensity modulator 4 and the first polarization controller 6 are sequentially connected between the first distributed feedback laser 1 and the optical coupler 8; the second intensity modulator 5 and the second polarization controller 7 are sequentially connected between the second distributed feedback laser 2 and the optical coupler 8; the signal source 3 controls the first intensity modulator 4 and the second intensity modulator 5 respectively;

[0024] The variable optical attenuator 9, the optical fiber splitter 10, the first vertical cavity surface emitting laser 13, the first optical isolator 14, the first fiber optic polarization beam splitter 15, the periodically poled lithium niobate crystal 18, the second vertical cavity surface emitting laser 23, the second optical isolator 24, and the second fiber optic polarization beam splitter 25 are sequentially connected between the optical coupler 8 and the digital communication analyzer 26;

[0025] Preferably, the threshold current of the second vertical cavity surface emitting laser 23 is I th = 6.8 mA.

[0026] Preferably, the bit time of the logic input signal D and the optical clock signal CK is T = 10 ps.

[0027] Preferably, the optical injection intensity of the second vertical cavity surface emitting laser 23 is kinjx = k injy =

[0028] 600 ns -1 。

[0029] Preferably, the frequency detuning between the first distributed feedback laser 1, the second distributed feedback laser 2 and the second vertical cavity surface emitting laser 23 is Δω = 150 GHz.

[0030] Preferably, the digital communication analyzer 26 demodulates the logic output through the following formula:

[0031]

[0032] Where: A x and A y are respectively the mean values of the last 40% sampling data of the X-polarized light and Y-polarized light output by the second vertical cavity surface emitting laser (23) within the bit time T * ; I 2xi(j) represents the optical intensity value of the j-th sampling of the X-polarized light in the i-th bit time, and I 2yi(j) represents the optical intensity value of the j-th sampling of the Y-polarized light in the i-th bit time; M represents the total number of samplings within each bit time. M0 represents the starting serial number of the last 40% sampling data, which is determined by

[0033] When A x ≥ A y , the logic output Q = 1; when A x < A y , the logic output Q = 0.

[0034] Preferably, the dynamic behavior of the second vertical cavity surface emitting laser (23) is controlled by the following rate equation:

[0035]

[0036] Where: t represents time, E 2x , E 2y represent the complex amplitudes of the X-polarized light and Y-polarized light fields of the second vertical cavity surface emitting laser, including optical intensity and phase information, k represents the field decay rate, a represents the linewidth enhancement factor, N2 represents the total carrier density, n2 represents the difference in the number of spin-reversed carriers, γ a represents linear dichroism, γ p represents birefringence, β sp represents the spontaneous emission factor, γ e represents the total carrier loss rate, including non-radiative recombination and carrier leakage, ξ x , ξ yrepresents the Gaussian white noise term, simulating spontaneous emission noise and environmental interference, k injx ,k injy represents the injection intensity of X / Y polarized light, indicating the driving ability of the external optical signal on the laser, Δω s represents the frequency detuning, E Px ,E Py represents the complex amplitude of the X / Y polarized light field injected from the periodically poled lithium niobate crystal into the second vertical cavity surface emitting laser.

[0037] Preferably, the output optical field amplitude of the periodically poled lithium niobate crystal 18 satisfies the following formula:

[0038]

[0039] where: S A represents the effective spot area, T L represents the round-trip time in the laser cavity, v c represents the speed of light in vacuum, n1, n2 represent the effective refractive indices of the o-ray and e-ray in the crystal, represents the photon energy, where is the reduced Planck constant, ω0 is the laser center frequency, V represents the volume of the active layer of the laser, U o,e (L,t) represents the analytical solution of the complex amplitude of the o-ray and e-ray in the crystal, related to the position L and time t, describing the propagation characteristics of the optical field in the crystal.

[0040] Compared with the prior art, the advantages of the present invention are as follows:

[0041] 1. Through the optimization of optical chaos dynamics and all-optical domain signal processing, the electro-optical conversion bottleneck of traditional electronic devices is broken through, significantly improving the logic operation speed and meeting the requirements of ultra-low latency for high-speed fiber optic communication and real-time photon computing.

[0042] 2. Based on the external electric field regulation mechanism, the dynamic switching of the functions of the D latch and D flip-flop is realized, without physical reconstruction of the optical path or replacement of devices, significantly improving the system flexibility and being applicable to multi-modal communication and adaptive computing scenarios.

[0043] 3. By adopting the post-stage sampling mean comparison mechanism (non-traditional threshold determination), transient noise and initial condition perturbations are effectively suppressed, ensuring the stability of the logical output and being applicable to complex electromagnetic environments and high-noise scenarios.

[0044] 4. Utilizing the randomness and unpredictability of the optical chaos signal, physical layer encryption protection is provided for data storage and transmission, preventing signal interception and reverse engineering cracking, and enhancing the security of sensitive information.

[0045] 5. Through the collaborative design of a laser, a modulator, and a polarization control component, the number of discrete components is reduced, the system complexity and power consumption are lowered, and it is convenient for the deployment of large-scale photonic integrated chips. Description of the Drawings

[0046] Figure 1 It is a schematic structural diagram of the high-speed optical chaotic timing logic device according to an embodiment of the present invention.

[0047] Figure 2 It is a schematic diagram of the optical path connection and component layout of the high-speed optical chaotic timing logic device according to an embodiment of the present invention

[0048] Figure 3 It is an evolution diagram of the dynamic state of the second vertical cavity surface emitting laser in the parameter space according to an embodiment of the present invention, where (a) is the chaotic state distribution of the X-polarized light, and (b) is the chaotic state distribution of the Y-polarized light;

[0049] Figure 4 It is an evolution diagram of the polarization bistability of the second vertical cavity surface emitting laser according to an embodiment of the present invention, where (a) is the suppression relationship between the X / Y polarized light when E0 = 11 kV / mm, and (b) is the Y-polarized light dominant state when E0 = 25 kV / mm;

[0050] Figure 5 It is a timing diagram A of the logical operation of the high-speed optical chaotic D-latch under clock synchronization according to an embodiment of the present invention, where (a) is the optical clock signal CK; (b) is the optical logic input signal D; (c) is the logical output Q; (d) is the externally applied electric field E0; (e) is the combination of the X-polarized light intensity and the logical output Q; (f) is the combination of the Y-polarized light intensity and the logical output Q;

[0051] Figure 6 It is a timing diagram B of the logical operation of the high-speed optical chaotic D-flip-flop under clock synchronization according to an embodiment of the present invention, where (a) is the optical clock signal CK; (b) is the optical logic input signal D; (c) is the logical output Q; (d) is the externally applied electric field E0; (e) is the combination of the X-polarized light intensity and the logical output Q; (f) is the combination of the Y-polarized light intensity and the logical output Q;

[0052] Figure 7 It is a switching schematic diagram of the high-speed reconfigurable optical chaotic D-latch and D-flip-flop under clock synchronization according to an embodiment of the present invention; (a) is the optical clock signal CK; (b) is the optical logic input signal D; (c) is the logical output Q; (d) is the externally applied electric field E0; (e) is the combination of the X-polarized light intensity and the logical output Q; (f) is the combination of the Y-polarized light intensity and the logical output Q;

[0053] Figure 8 It is the success probability of the optical chaotic D-latch and D-flip-flop in the parameter space k according to an embodiment of the present invention x (k x = ky ) and the evolution diagram within T, where (a) the SP of the D latch with respect to k x and the evolution of T, (b) the SP of the D flip - flop with respect to k x and the evolution of T;

[0054] Figure 9 are the curves showing the dependence of the success probability of the optical chaotic D latch and D flip - flop in the embodiments of the present invention on the intensity of spontaneous emission noise. Detailed implementation manners

[0055] To make the objectives, technical solutions and advantages of the present invention more clear and understandable, the following further describes the present invention in detail with reference to the drawings and by way of examples.

[0056] The embodiments of the present invention are described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals represent the same or similar elements or elements with the same or similar functions throughout. The embodiments described below by referring to the drawings are exemplary and are only used to explain the present invention and should not be construed as a limitation of the present invention.

[0057] In the description of the present invention, it should be understood that for the orientation description, such as the orientation or positional relationship indicated by up, down, front, back, left, right, etc. is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0058] In the description of the present invention, the meaning of several is more than one, the meaning of multiple is more than two, greater than, less than, exceeding, etc. are understood as not including the present number, and above, below, within, etc. are understood as including the present number. If there is a description of first and second, it is only for the purpose of distinguishing technical features and should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0059] In the description of the present invention, unless otherwise clearly defined, words such as setting, installation, connection, etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0060] In the description of the present invention, the descriptions with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples.

[0061] As Figure 1 shown, a high-speed optical chaotic timing logic device includes: a first distributed feedback laser 1, a second distributed feedback laser 2, a signal source 3, a first intensity modulator 4, a second intensity modulator 5, a first polarization controller 6, a second polarization controller 7, an optical coupler 8, a variable optical attenuator 9, an optical fiber splitter 10, a first vertical cavity surface emitting laser 13, a first optical isolator 14, a first fiber optic polarization beam splitter 15, a periodically poled lithium niobate crystal 18, a second vertical cavity surface emitting laser 23, a second optical isolator 24, a second fiber optic polarization beam splitter 25, and a digital communication analyzer 26.

[0062] The first intensity modulator 4 and the first polarization controller 6 are sequentially arranged between the first distributed feedback laser 1 and the optical coupler 8 and are connected in sequence by optical signals; the second intensity modulator 5 and the second polarization controller 7 are sequentially arranged between the second distributed feedback laser 2 and the optical coupler 8 and are connected in sequence by optical signals; the signal source 3 is respectively connected to the first intensity modulator 4 and the second intensity modulator 5; the variable optical attenuator 9, the optical fiber splitter 10, the first vertical cavity surface emitting laser 13, the first optical isolator 14, the first fiber optic polarization beam splitter 15, the periodically poled lithium niobate crystal 18, the second vertical cavity surface emitting laser 23, the second optical isolator 24, and the second fiber optic polarization beam splitter 25 are sequentially arranged between the optical coupler 8 and the digital communication analyzer 26 and are connected in sequence by optical signals;

[0063] The optical fiber splitter 10 includes a first output end and a second output end, the first vertical cavity surface emitting laser 13 includes a first input end and a second input end, the first output end is directly connected to the first input end by an optical signal, and a first Faraday rotator 11 and a first half-wave plate 12 are sequentially arranged between the second output end and the second input end and are connected in sequence by optical signals;

[0064] The first fiber optic polarization beam splitter 15 includes a third output end and a fourth output end. The periodically poled lithium niobate crystal 18 includes a third input end and a fourth input end. The third output end is directly optically connected to the third input end, and a second Faraday rotator 16 and a second half-wave plate 17 are sequentially arranged between the fourth output end and the fourth input end and are optically connected in sequence;

[0065] The periodically poled lithium niobate crystal 18 includes a fifth output end and a sixth output end. The second vertical cavity surface emitting laser 23 includes a fifth input end and a sixth input end. A first optical amplifier 22 is connected between the fifth output end and the fifth input end; a third Faraday rotator 19, a third half-wave plate 20 and a second optical amplifier 21 are sequentially arranged between the sixth output end and the sixth input end and are optically connected in sequence;

[0066] The second fiber optic polarization beam splitter 25 includes a seventh output end and an eighth output end. The digital communication analyzer 26 includes a seventh input end and an eighth input end. The seventh output end is directly optically connected to the seventh input end, and the eighth output end is directly optically connected to the eighth input end;

[0067] The threshold current I injected into the second vertical cavity surface emitting laser 23 th = 6.8 mA.

[0068] The bit duration T of the second vertical cavity surface emitting laser 23 = 10 ps.

[0069] The optical injection intensity k injected into the second vertical cavity surface emitting laser 23 injx = k injy = 600 ns -1 .

[0070] The frequency detuning Δω between the first distributed feedback laser 1, the second distributed feedback laser 2 and the vertical cavity surface emitting laser 23 = 150 GHz.

[0071] Experiments show the influence of spontaneous emission noise on the reliability of D latches and D flip-flops. It is found that when the intensity of spontaneous emission noise is as high as 207.5 dBw, the success probability is still equal to 1; when the noise intensity is between 207.5 dBw and 276.5 dBw, the success probability remains above 0.92. The above shows that D latches and D flip-flops have excellent anti-noise performance.

[0072] DFB: Distributed Feedback Laser; IM: Intensity Modulator; PG: Signal Generator; PC: Polarization Controller; OC: Optical Coupler; VOA: Variable Optical Attenuator; FBS: Fiber Beam Splitter; FR: Faraday Rotator; HWP: Half-Wave Plate; VCSEL: Vertical-Cavity Surface-Emitting Laser; FPBS: Fiber Polarization Beam Splitter; PPLN: Periodic Poled LiNbO3; OA: Optical Amplifier; IS: Optical Isolator; DCA: Digital Communication Analyzer; E0: Applied External Electric Field.

[0073] Figure 2 The detailed optical path diagrams of an optical chaotic D-latch and a D-flip-flop for realizing high-speed reconfigurable multiple triggering under clock synchronization are given. The light beams output from DFB1 and DFB2 lasers are respectively modulated by intensity modulators IM1 and IM2 into optical D pulses (logic inputs) and optical clock pulses for the D-latch and D-flip-flop. Polarization controllers PC1 and PC2 align the D pulse beam and the clock pulse beam to the X polarization mode direction of the VCSEL, that is, both the D pulse and the clock pulse are X-polarized light. The D pulse and the clock pulse are incident into the 1×2 FBS1 through the optical coupler OC and the variable optical attenuator VOA. Here, the VOA is used to control the light intensity. For the two X-polarized light beams output from FBS1, one X-polarized light beam is directly injected into VCSEL1, and the other X-polarized light beam is converted into Y-polarized light by the Faraday rotator FR1 and the half-wave plate HWP1 and then injected into VCSEL1. The light beam output from VCSEL1 passes through the optical isolator IS1, and then the X-polarized light and the Y-polarized light are separated by the fiber polarization beam splitter FPBS1. Here, the function of IS1 is to prevent the light in FPBS1 from feeding back to VCSEL1. The X-polarized light output from FPBS1 will be directly injected into the periodically poled lithium niobate crystal as the o-ray. The Y-polarized light is converted into the e-ray by FR2 and HWP2 and then injected into the PPLN. Here, the functions of FR2 and HWP2 are to convert the polarization direction of the Y-polarized light to the z-axis direction of the crystal. Under the action of the applied external electric field E0, the electro-optic effect occurs in the PPLN crystal. The o-ray output from the PPLN is amplified by OA1 and then injected into VCSEL2, and the output e-ray is converted into Y-polarized light by FR3 and HWP3, and then amplified by OA2 and injected into VCSEL2. The chaotic light beam output from VCSEL2 passes through IS2, and then the chaotic X-polarized light and the chaotic Y-polarized light are separated by FPBS2. Finally, the digital communication analyzer measures and analyzes these two chaotic polarized light beams to obtain the logic output.

[0074] Based on the spin-flip model of the VCSEL, when VCSEL1 is injected by external light, its rate equation can be expressed as:

[0075]

[0076] Here, t represents time, and the subscripts "1x" and "1y" represent the X-polarized light and Y-polarized light output by VCSEL1 respectively; E is the complex amplitude of the optical field. where g represents the differential material gain, γ e is the loss rate of the total carriers, A is the slowly varying amplitude; a is the linewidth enhancement factor; k x and k y represent the injection intensities of the X-polarized light and Y-polarized light respectively; Δω is the frequency detuning between the DFB and VCSEL1; μ1 is the normalized injection current of VCSEL1; k is the field decay rate; γ s is the optical spin rate; N is the total number of inverted carriers between the interband and the conduction band; γ a represents linear dichroism; n is the difference between the number of upper-spin and lower-spin radiative carriers; γ p represents linear birefringence. is the noise term, β sp is the spontaneous emission factor, here N se is used to represent the noise intensity, and ξ x and ξ y are two independent Gaussian white noises with a mean of 0 and a variance of 1. E inj represents the amplitude of the external light injected into VCSEL1, and E inj = E D + E CK , here E D and E CK represent the amplitudes of the optical D pulse and the optical clock pulse respectively; the superscript * is the conjugate symbol, and i is the imaginary symbol.

[0077] The X-polarized light and Y-polarized light from VCSEL1 are used as the initial inputs of the o-light and e-light in the PPLN crystal respectively, and their amplitudes satisfy the following relationship:

[0078]

[0079] where U o and U e are the complex amplitudes of the o-light and e-light respectively; n1 and n2 are the refractive indices of the X-polarized light and Y-polarized light when not perturbed; ω0 is the center frequency of VCSEL1; is the Planck constant; S A is the effective spot area; V is the volume of the active layer of VCSEL1; υ c is the speed of light in vacuum; T L = 2n g υ c / L v represents the round-trip time in the laser cavity, L v is the laser cavity length, n gis the effective refractive index of the laser active layer. Under the conditions of phase mismatch and weak second-order nonlinear effects, the analytical solutions of the coupled-wave equations for the linear electro-optic effects of the o-wave and e-wave in the PPLN crystal are as follows:

[0080] U o,e (L, t) = ρ o,e (L, t)exp(iβ0L)exp[iφ o,e (L, t)] (6)

[0081] where

[0082]

[0083] where L is the crystal length; the wave vector mismatch Δk = k x1 - k y1 + K1, K1 = 2π / Λ is the first-order reciprocal lattice vector of the crystal, Λ is the polarization period, k x1 = 2πn1v c / ω0 and k y1 = 2πn2v c / ω0 represent the wave vectors of the o-wave and e-wave at ω0, respectively; d1, d2, d3, and d4 are electro-optic coefficients.

[0084] The complex amplitudes of the X-polarized light and Y-polarized light output from the PPLN satisfy the following relationship:

[0085]

[0086] VCSEL2 is strongly injected by the light from the PPLN crystal, and its rate equation can be expressed as:

[0087]

[0088] In the above formula, the subscripts 2 and P represent VCSEL2 and PPLN, respectively; k injx and k injy are the injection intensities of the X-polarized light and Y-polarized light, respectively, and k injx = 50k x , k injy = 50k y ; Δω S is the central frequency detuning between VCSEL1 and VCSEL2, where Δω S = 0 GHz; μ2 is the normalized injection current of VCSEL2.

[0089] Results and Discussion

[0090] Table 1 System Parameters

[0091]

[0092]

[0093] To ensure that VCSEL2 outputs chaotic laser, in this embodiment, the evolution of the dynamic state of VCSEL2 in the parameter space of the externally applied electric field E0 and the optical injection amplitude E is studied, as inj shown. It can be seen from the figure that under different parameter conditions, the polarized light output by VCSEL2 may exhibit different states, such as one-period oscillation (P1), two-period oscillation (P2), quasi-periodic oscillation (QP), and chaotic state (CO). Here, this embodiment only focuses on the evolution of the chaotic state. From Figure 3 (a), it can be obtained that when E is in the range of 0.1 - 10 and E0 is in the range of 0 - 42 kV / mm, the X-polarized light is in a chaotic state; when the externally applied electric field E0 is greater than 42 kV / mm and E is in the ranges of 0.18 - 0.23, 0.88 - 0.93, 1.59 - 1.64, 2.30 - 2.35, etc., the X-polarized light is also in a chaotic state, and the chaotic state of the X-polarized light is a quasi-periodic function of E. From Figure 3 (a), it can be seen that when E0 takes values in the ranges of 0 kV / mm - 0.6 kV / mm and 42 kV / mm - 58 kV / mm, the chaotic state of the Y-polarized light changes quasi-periodically with E inj ; in most regions within the ranges of 0.1 - 10 (E inj ) and 0.6 kV / mm - 42 kV / mm (E0), the Y-polarized light is in a chaotic state, but in a small region near several coordinates such as (0.7, 30.8), (2.1, 30), (2.8, 28), (8.4, 35), etc., the Y-polarized light is in a non-chaotic state. inj From Figure 3 (b), it can be seen that when E0 takes values in the ranges of 0 kV / mm - 0.6 kV / mm and 42 kV / mm - 58 kV / mm, the chaotic state of the Y-polarized light changes quasi-periodically with E inj ; in most regions within the ranges of 0.1 - 10 (E inj ) and 0.6 kV / mm - 42 kV / mm (E0), the Y-polarized light is in a chaotic state, but in a small region near several coordinates such as (0.7, 30.8), (2.1, 30), (2.8, 28), (8.4, 35), etc., the Y-polarized light is in a non-chaotic state.

[0094] On the premise of ensuring that VCSEL2 outputs chaotic laser, in order to determine the value of E inj for modulating the logic input, as well as a suitable logic output demodulation mechanism, in this embodiment, the evolution of the polarization bistability of VCSEL2 with the optical injection amplitude E inj is calculated when the externally applied electric field E0 is 11 kV / mm and 25 kV / mm respectively, as Figure 4 shown. Under the condition of E0 = 11 kV / mm, from Figure 4 (a), it can be seen that when E inj varies in the range of 0 - 4.7, the Y-polarized light is inhibited by the X-polarized light and the X-polarized light dominates; and when E inj is in the range of 3.9 - 4.7, both the X-polarized light and the Y-polarized light exhibit double-stable loops; as E inj increases from 4.7 to 10, the Y-polarized light is completely inhibited by the X-polarized light and the X-polarized light occupies an absolute dominant position. FromFigure 4 (b) It can be seen that E0 = 25 kV / mm, E inj When it varies within the range of 0 - 4.7, the X-polarized light is inhibited by the Y-polarized light, and the Y-polarized light dominates; and E inj Within the range of 3.9 - 4.7, both the X-polarized light and the Y-polarized light exhibit bistable loops; E inj Within the range of 4.7 - 10, the X-polarized light is completely inhibited by the Y-polarized light, and the Y-polarized light occupies an absolute dominant position. Through the above analysis, it can be obtained that when the externally applied electric field value is switched between 11 kV / mm and 25 kV / mm, it can induce the polarization conversion dynamic behavior of VCSEL2, and E inj When it is greater than 4.7, the degree of mutual inhibition between the X-polarized light and the Y-polarized light reaches the maximum. Therefore, in this embodiment, the externally applied electric field is considered as the control signal, and at the same time, the difference in the light intensities of the X-polarized light and the Y-polarized light is taken to demodulate the logic output (see the detailed description below), and E inj should be greater than 4.7.

[0095] The optical injection amplitude E inj is equal to the sum of the optical D-pulse amplitude E D and the optical clock pulse amplitude E CK , that is, E inj = E D + E CK , where E D and E CK are respectively modulated into the optical logic input D and the optical clock logic signal CK with a duty cycle of 50%. Since the logical input D and the optical clock logic signal CK take values of 0 or 1, in this embodiment, when E D = E CK = 2.69 (E inj = 5.38), D = CK = 0, and when E D = E CK = 2.73 (E inj = 5.46), D = CK = 1, and the bit time T of the optical logic input D and the optical clock logic signal CK is set to 10 ps. The demodulation mechanism of the logic output is described as follows: Assume that the bit time of the logic output Q is T * , and the total sampling time length t is K times of T * , that is, t = KT * . The number of sampling times within each T * is represented by M, and M = T * / h, where h represents the sampling interval. The mean values of the light intensities of the X-polarized light and the Y-polarized light output by VCSEL2 within the i-th (i = 1, 2...K) T * are respectively defined as A x and A y. Since it takes a certain amount of time for the mutual suppression between the X-polarized light and the Y-polarized light to reach the maximum and stable state after the optical clock signal is triggered, in order to enhance the robustness of the logic output and reduce the bit error rate, their means are calculated by using the last 40% of the number of samples within the \(i\)-th \(T\). * Therefore, their means can be respectively expressed as:

[0096]

[0097] I 2xi(j) and \(I\) 2yi(j) respectively represent the \(j\)-th sampling value of the light intensity of the X-polarized light and the Y-polarized light within the \(i\)-th \(T\). * The symbol represents the ceiling operation. Within the \(i\)-th \(T\), * if \(A\) x ≥ \(A\) y , then \(Q = 1\); if \(A\) x < \(A\) y , then \(Q = 0\). In this embodiment, \(t = 5\mathrm{ns}\), \(K = 500\), \(T\) * = 10\mathrm{ps}\), \(h = 0.01\mathrm{ps}\), \(M = 1000\).

[0098] According to the above logic input modulation and logic output demodulation rules, this embodiment realizes the high-speed optical chaotic D-latch operation with a bit time equal to 10\mathrm{ps}, as Figure 5 shown. Figure 5 (a) is the clock signal triggered by a high level. From 2\mathrm{ns} to 2.01\mathrm{ns}, the optical clock signal \(CK = 1\), the logic input \(D = 1\). According to formulas (16) and (17), it is calculated that \(A\) x = 0.41, \(A\) y = 0.04, \(A\) x > \(A\) y , so the logic output \(Q = 1\); from 2.01\mathrm{ns} to 2.02\mathrm{ns}, \(CK = 0\), \(D = 1\), \(A\) x = 0.47, \(A\) y = 0.01, \(A\) x > \(A\) y , so \(Q = 1\); from 2.02\mathrm{ns} to 2.03\mathrm{ns}, \(CK = 1\), \(D = 0\), \(A\) x = 0.19, \(A\) y = 0.76, \(A\) x < \(A\) y , so \(Q = 0\); from 2.03\mathrm{ns} to 2.04\mathrm{ns}, \(CK = 0\), \(D = 0\), \(A\) x = 0.03, \(A\) y = 1.21, \(A\) x < \(A\) y, the output Q is still equal to 0; in the time range of 2.04 ns - 2.05 ns, CK = 1, D = 1, A x = 0.47, A y = 0.34, A x > A y , thus Q = 1; in the time range of 2.05 ns - 2.06 ns, CK = 0, D = 1, because A x = 0.42 > A y = 0.04, so Q = 1. Since the implementation mechanism is the same, the implementation process of the latch operation within 2.06 ns - 2.2 ns will not be described in detail here. The function table of the D latch is shown in Table 2, where "×" represents that the value of D is 0 or 1, Q n represents the current state of the logical output, that is, the logical output state when the input signal has not arrived, Q n+1 represents the next state, that is, the logical output state after the input signal arrives. Through the above analysis, it can be obtained that when CK = 1, the logical output Q n+1 is consistent with the logical input D, that is, Q n+1 = D; when CK = 0, the logical output Q n+1 maintains the previous state unchanged, that is, the high-speed optical chaotic D latch under clock synchronization is successfully realized, and can be expressed by the logical function as: Q n+1 = D, CK = 1.

[0099] Table 2 Truth table of D latch

[0100]

[0101] The present invention further explores the implementation of a high-speed optical chaotic D flip-flop under clock synchronization, as Figure 6 shown. Figure 6 (a) is an optical clock signal triggered by the rising edge. In the clock interval [2 ns, 2.02 ns), there is no rising edge of the optical clock signal CK, and the logical input D = 0. According to formulas (16) and (17), we calculate A x = 0.01, A y = 0.96. Since A x < A y , the output Q = 0 (see Figure 5 (c)). The optical clock signal CK has its first rising edge at 2.02 ns. In the intervals [2.02 ns, 2.025 ns) and [2.025 ns, 2.03 ns), the logical inputs D are 0 and 1 respectively. We calculate A x = 7.57×10 -4 , A y = 0.67. Since A x < A y, Q remains 0. In the interval [2.03 ns, 2.04 ns), D = 1, and it is calculated that A x = 5.57×10 -4 , A y = 0.87. Since A x <A y , Q = 0. The second rising edge of CK appears at 2.04 ns. In the intervals [2.04 ns, 2.045 ns) and [2.045 ns, 2.05 ns), D is 1 and 0 respectively. It is calculated that A x = 0.56, A y = 0.37. Since A x >A y , the output Q jumps to 1. In the subsequent interval [2.05 ns, 2.06 ns), D is 0 in the first 5 ps and 1 in the last 5 ps. It is calculated that A x = 0.40, A y = 0.05. Since A x >A y , Q remains 1. The third rising edge of CK appears at 2.06 ns. In the first 5 ps of the time interval [2.06 ns, 2.07 ns), D = 1, and in the last 5 ps, D = 0. It is calculated that A x = 0.45, A y = 0.01. Since A x >A y , Q = 1. In the time interval [2.07 ns, 2.08 ns), D remains 0 in the first 5 ps and switches to 1 in the last 5 ps. It is calculated that A x = 0.40, A y = 0. Since A x >A y , Q continues to remain 1. Since the implementation mechanism is the same, the implementation process of the flip-flop operation within 2.08 ns - 2.2 ns will not be described in detail here. The function table of the D flip-flop is shown in Table 3, where ↑ represents the rising edge state of the optical clock signal CK, and * represents all states of the optical clock signal CK other than the rising edge, such as CK = 0, CK = 1, or the falling edge state. From the above analysis, it can be obtained that the system only receives the input signal at the rising edge of CK, and the input signal is blocked at CK = 0, CK = 1, and the falling edge of CK, maintaining the previous output state. That is, the high-speed optical chaotic D flip-flop under clock synchronization is successfully implemented and can be represented by the logical function as: Q n+1 = D, CK↑.

[0102] Table 3 Truth table of D flip-flop

[0103]

[0104] By controlling the externally applied electric field, this embodiment further demonstrates the reconfigurable performance of the operation, achieving a high-speed reconfigurable optical chaotic D-latch and D-flip-flop under clock synchronization, as Figure 7 shown. Within 2 ns - 2.05 ns, the optical clock signal contains a high level with a time length of 3 bit times, and the logical output changes its state only under the action of the high level of the optical clock signal. Therefore, the D-latch operation is achieved; within 2.05 ns - 2.09 ns, the optical clock signal contains 2 rising edges, and the logical output changes its state only at the moment of the change of the rising edge of the optical clock signal. Thus, the D-flip-flop operation is achieved; within 2.09 - 2.15 ns, the system switches from the D-flip-flop operation to the D-latch operation; finally, within 2.15 ns - 2.2 ns, the system switches back to the D-flip-flop operation. The above analysis shows that the system can flexibly switch between the D-latch and the D-flip-flop, and has excellent reconfigurable performance.

[0105] It should be noted that the optical chaotic D-latch and D-flip-flop depend on some important system parameters such as the optical injection intensity k x (k x = k y ), and the bit time T. These parameters may introduce bit errors, thus damaging the integrity of the logical operation. For this reason, this embodiment introduces the success probability (SP) to evaluate the reliability of the D-latch and D-flip-flop. It is equal to the ratio of the number of bits with correct logical output to the total number of bits. According to the definition, this embodiment calculates the dependence of the success probabilities of the D-latch and D-flip-flop on the optical injection intensity k x (k y ) and the bit time T, as Figure 8 shown. From Figure 8 (a), it can be seen that when the optical injection intensity k x (k y ) is less than 9 ns -1 , the success probability of the D-latch is less than 1, indicating that bit errors occur in the logical output; when k x (k y ) is greater than 9 ns -1 and T is greater than 12 ps, the success probability is always equal to 1, indicating that no bit errors occur in the logical output. As k x (k y ) gradually increases, under the condition of ensuring that the success probability is always 1, the lower limit value of T becomes smaller and smaller. For example, when k x (k y ) is 18 ns -1 , the lower limit value of T is 5 ps; when k x (k y ) increases to 35 ns -1 , the lower limit value of T drops to 4 ps; when k x (k y ) exceeds 36 ns-1 When it reaches this point, the lower limit value of T stably drops to 3 ps, that is, the operation speed reaches 333.3 Gb / s. Figure 8 The evolution of the success probability of the D flip-flop in (b) is Figure 8 approximately the same as that in (a). When the optical injection intensity k x (k y ) is less than 9 ns -1 the success probability of the D flip-flop is less than 1; under the condition of ensuring that the success probability is constantly 1, as k x (k y ) gradually increases, the lower limit value of T also becomes smaller and smaller. And when k x (k y ) exceeds 43 ns -1 the lower limit value of T also stably drops to 3 ps. Therefore, from the above analysis, it can be seen that when k x (k y ) is less than 9 ns -1 error codes will occur in the logical outputs of the D latch and the D flip-flop, and the normal logical operation function cannot be realized. On the premise of ensuring the normal operation of the D latch and the D flip-flop, by increasing the optical injection intensity k x (k y ) can effectively reduce the lower limit value of T and improve the operation speed, and the highest operation speed can reach 333.3 Gb / s.

[0106] The spontaneous emission noise in the system also has a great impact on the reliability of the D latch and the D flip-flop. For this reason, this embodiment further studies the dependence of the success probability on the intensity of the spontaneous emission noise, as Figure 9As shown in the figure. The evolution curves of the success probabilities of the D latch and the D flip-flop in the figure are almost completely coincident. When the spontaneous noise intensity is as high as 207.5 dBw, their success probabilities are still 1. When the noise intensity increases from 207.5 dBw to 276.5 dBw, the success probability curves oscillate and become more and more intense, but the success probability remains above 0.92. After the noise intensity exceeds 276.5 dBw, the success probability drops sharply and the logic operation fails completely. On the premise of ensuring that there are no error codes in the logic output, the bit time of the optical clock signal in the present invention is set to 10 ps, which is only one percent of the optical clock bit time in the literature [Dongzhou Zhong, Guangze Yang, Neng Zeng, Hua Yang, Zhe Xu, and Jiangtao Xi, "Optical chaotic flip-flop operations with multiple triggering under clock synchronization in the VCSEL with polarization-preserved optical injection," Opt. Express 28(7), 10363-10377(2020)], that is, the operation speed is 100 times faster than that in the literature, and the system noise tolerance is 67 dBw higher than that in the literature. The above shows that the D latch and the D flip-flop implemented in this embodiment have extremely fast operation speeds and excellent anti-noise performance.

[0107] Those of ordinary skill in the art will realize that the embodiments described herein are for helping the reader understand the implementation methods of the present invention, and should be understood that the protection scope of the present invention is not limited to such specific statements and embodiments. Those of ordinary skill in the art can make various other specific deformations and combinations that do not depart from the essence of the present invention according to these technical revelations disclosed in the present invention, and these deformations and combinations are still within the protection scope of the present invention.

Claims

1. A high-speed optical chaotic timing logic device, characterized in that Including: A first distributed feedback laser (1), a second distributed feedback laser (2), a signal source (3), a first intensity modulator (4), a second intensity modulator (5), a first polarization controller (6), a second polarization controller (7), an optical coupler (8), a variable optical attenuator (9), an optical fiber splitter (10), a first vertical cavity surface emitting laser (13), a first optical isolator (14), a first fiber optic polarization beam splitter (15), a periodically poled lithium niobate crystal (18), a second vertical cavity surface emitting laser (23), a second optical isolator (24), a second fiber optic polarization beam splitter (25), and a digital communication analyzer (26); The first distributed feedback laser (1) and the second distributed feedback laser (2) are used to generate an initial laser signal; The signal source (3) is used to output a logic input signal and a clock signal with a duty cycle of 50%; The first intensity modulator (4) and the second intensity modulator (5) are respectively used to modulate the laser signal into an optical D pulse and an optical clock pulse; The first polarization controller (6) and the second polarization controller (7) are used to align the optical D pulse and the optical clock pulse to the X polarization direction; The optical coupler (8), the variable optical attenuator (9), and the optical fiber splitter (10) are used to couple, attenuate, and split the optical signal; The first vertical cavity surface emitting laser (13) receives the X-polarized light from the optical fiber splitter (10) and the Y-polarized light converted by the first Faraday rotator (11) and the first half-wave plate (12), and outputs chaotic polarized light; The first optical isolator (14) is connected between the first vertical cavity surface emitting laser (13) and the first fiber optic polarization beam splitter (15), and is used to block the interference of the backward reflected light on the first vertical cavity surface emitting laser (13); The periodically poled lithium niobate crystal (18) receives the X / Y polarized light from the first fiber optic polarization beam splitter (15), and generates an electro-optic effect under the action of an external electric field, and outputs the modulated ordinary light and extraordinary light; The second vertical cavity surface emitting laser (23) receives the amplified ordinary light from the periodically poled lithium niobate crystal (18) and the extraordinary light converted by the third Faraday rotator (19) and the third half-wave plate (20), and outputs chaotic polarized light; The digital communication analyzer (26) is used to measure and analyze the logic output signal, and demodulate the logic output by comparing the mean values of the 40% sampled data of the X-polarized light and the Y-polarized light output by the second vertical cavity surface emitting laser (23) after each bit time.

2. The high-speed optical chaotic timing logic device according to claim 1, characterized in that: The first intensity modulator (4) and the first polarization controller (6) are sequentially connected between the first distributed feedback laser (1) and the optical coupler (8); the second intensity modulator (5) and the second polarization controller (7) are sequentially connected between the second distributed feedback laser (2) and the optical coupler (8); the signal source (3) respectively controls the first intensity modulator (4) and the second intensity modulator (5); The variable optical attenuator (9), optical fiber splitter (10), first vertical cavity surface emitting laser (13), first optical isolator (14), first fiber optic polarization beam splitter (15), periodically poled lithium niobate crystal (18), second vertical cavity surface emitting laser (23), second optical isolator (24), and second fiber optic polarization beam splitter (25) are sequentially connected between the optical coupler (8) and the digital communication analyzer (26).

3. The high-speed optical chaotic timing logic device according to claim 1, characterized in that: The threshold current of the second vertical cavity surface emitting laser (23) is I th = 6.8 mA.

4. The high-speed optical chaotic timing logic device according to claim 1, wherein: The bit time of the logic input signal D and the optical clock signal CK is T = 10 ps.

5. The high-speed optical chaotic timing logic device according to claim 1, wherein: The optical injection intensity of the second vertical cavity surface emitting laser (23) is k injx = k injy = 600 ns -1 .

6. The high-speed optical chaotic timing logic device according to claim 1, wherein: The frequency detuning between the first distributed feedback laser (1), the second distributed feedback laser (2), and the second vertical cavity surface emitting laser (23) is Δω = 150 GHz.

7. The high-speed optical chaotic timing logic device according to claim 1, characterized in that: The digital communication analyzer demodulates the logic output through the following formula: Where: A x and A y are respectively the mean values of the last 40% sampled data of the X-polarized light and the Y-polarized light output by the second vertical cavity surface emitting laser (23) within the bit time T * ; I {2xi(j)} represents the light intensity value of the j-th sampling of the X-polarized light in the i-th bit time, and I {2yi(j)} represents the light intensity value of the j-th sampling of the Y-polarized light in the i-th bit time; M represents the total number of samplings within each bit time, and M0 represents the starting serial number of the last 40% sampled data, which is determined by When A x ≥ A y then the logical output Q = 1; when A x < A y then the logical output Q = 0.

8. The high-speed optical chaotic timing logic device according to claim 1, characterized in that: The dynamic behavior of the second vertical cavity surface emitting laser (23) is controlled by the following rate equation: where: t represents time, E 2x , E 2y represent the complex amplitudes of the X - polarized and Y - polarized light fields of the second vertical - cavity surface - emitting laser, including light intensity and phase information, k represents the field decay rate, a represents the linewidth enhancement factor, N2 represents the total carrier density, n2 represents the difference in the number of spin - flipped carriers, γ a represents linear dichroism, γ p represents birefringence, β sp represents the spontaneous emission factor, γ e represents the total carrier loss rate, including non - radiative recombination and carrier leakage, ξ x , ξ y represents the Gaussian white - noise term, simulating spontaneous emission noise and environmental interference, k injx , k injy represents the injection intensity of the X / Y - polarized light, representing the driving ability of the external optical signal on the laser, Δω s represents the frequency detuning, E Px , E Py represents the complex amplitude of the X / Y - polarized light field injected from the periodically poled lithium niobate crystal into the second vertical - cavity surface - emitting laser.

9. The high-speed optical chaotic timing logic device according to claim 1, characterized in that: The output optical field amplitude of the periodically poled lithium niobate crystal (18) satisfies the following formula: Where: S A represents the effective area of the light spot, T L represents the round-trip time in the laser cavity, v c represents the speed of light in vacuum, n1 and n2 represent the effective refractive indices of the o-ray and e-ray in the crystal, represents the photon energy, where is the Planck constant, ω0 is the laser center frequency, V represents the volume of the active layer of the laser, Uo ,e (L, t) represents the complex amplitude analytical solutions of the o-ray and e-ray in the crystal, which are related to the position L and time t, and describe the propagation characteristics of the light field in the crystal.

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