Two-stage comparator, reading circuit and image sensor

Abstract

The invention provides a two-stage comparator, a reading circuit and an image sensor, and the two-stage comparator comprises a first-stage comparison circuit which is used for comparing a pixel signal with a ramp signal under a first power supply voltage so as to output a first comparison signal; and the second-stage comparison circuit is used for carrying out voltage division on the first comparison signal so as to carry out amplification processing on the first comparison signal after voltage division under a second power supply voltage to obtain a second comparison signal. Therefore, the working voltages of the two stages of comparators are separated, and the second-stage comparison circuit works normally under the second power supply voltage; the second-stage comparison circuit is used for carrying out voltage division on the first comparison signal, so that the second-stage semaphore amplitude is in a second power supply voltage range, the power consumption of the second-stage comparison circuit is reduced, the generated dynamic IR voltage drop is eliminated, the adverse effect of the dynamic IR voltage drop on a quantization result is eliminated, and the quantization accuracy is improved. The problem of how to reduce the dynamic power consumption of the second-stage comparison circuit in the two-stage comparator is solved.

Description

Technical Field

[0001] The present invention relates to the technical field of circuit design, and particularly to a two-stage comparator, a readout circuit, and an image sensor. Background Art

[0002] CIS (CMOS Image Sensor) is irreplaceable in the field of images and is widely used in fields such as security monitoring, consumer electronics, and vehicle-mounted devices. Existing CIS usually uses a two-stage comparator to implement the quantization of pixel signals. During the quantization process, CDS (Correlated Double Sampling) is used to read out the reset signal and the photosensitive signal. By subtracting the quantization result of the reset signal from the quantization result of the photosensitive signal, the final quantization result of the pixel signal can be obtained.

[0003] However, in the existing two-stage comparator, the power consumption of the second-stage comparison circuit is dynamic power consumption. That is, when the signal is read out, different signal amounts will cause the second-stage comparison circuit to flip at different times, thereby generating different IR-drop (IR voltage drop) on the power supply voltage, making the power consumption of the second-stage comparison circuit change with the change of IR-drop. At the same time, this dynamic IR-drop will affect the first-stage comparison circuit and other analog circuits working at the same power supply voltage, thereby introducing power supply noise that cannot be eliminated by correlated double sampling in the two readouts of CDS, and further affecting the quantization result of the readout circuit of the image sensor, causing problems such as horizontal bands. Summary of the Invention

[0004] The purpose of the present invention is to provide a two-stage comparator, a readout circuit, and an image sensor to solve the problem of how to reduce the dynamic power consumption of the second-stage comparison circuit in the two-stage comparator.

[0005] To solve the above technical problems, the present invention provides a two-stage comparator, including: A first-stage comparison circuit for comparing and quantifying a pixel signal with a ramp signal under a first power supply voltage to output a first comparison signal; A second-stage comparison circuit for dividing the voltage of the first comparison signal and amplifying the divided first comparison signal under a second power supply voltage to obtain a second comparison signal; Wherein, the first power supply voltage and the second power supply voltage are different types of power supply voltages.

[0006] Optionally, in the two-stage comparator, the second-stage comparison circuit includes a first voltage-dividing capacitor and a second voltage-dividing capacitor; The positive electrode plate of the first voltage-dividing capacitor is connected to the first comparison signal, the negative electrode plate of the first voltage-dividing capacitor is connected to the negative electrode plate of the second voltage-dividing capacitor, and the positive electrode plate of the second voltage-dividing capacitor is connected to the second power supply voltage; the second voltage-dividing capacitor is used to perform voltage division processing on the first comparison signal so that the voltage amplitude of the voltage-divided first comparison signal is within the range of the second power supply voltage.

[0007] Optionally, in the two-stage comparator, the second-stage comparison circuit further includes a first reset transistor, an amplifier transistor, and a current mirror load transistor; The negative electrode plate of the first voltage-dividing capacitor is further connected to the source electrode of the first reset transistor and the gate electrode of the amplifier transistor; the gate electrode of the first reset transistor is connected to the second-stage reset signal, and the drain electrode is connected to the drain electrode of the amplifier transistor and the drain electrode of the current mirror load transistor; the source electrode of the amplifier transistor is connected to the second power supply voltage; the gate electrode of the current mirror load transistor is connected to the second-stage bias signal, the source electrode is connected to the second ground, and the drain electrode leads out an output terminal to output the second comparison signal.

[0008] Optionally, in the two-stage comparator, the second-stage comparison circuit further includes a bias capacitor, a first reset transistor, a second reset transistor, an amplifier transistor, and a current mirror load transistor; The negative electrode plate of the first voltage-dividing capacitor is further connected to the drain electrode of the first reset transistor and the gate electrode of the amplifier transistor; the gate electrode of the first reset transistor is connected to the second-stage first reset signal, and the source electrode is connected to the reset voltage; the source electrode of the amplifier transistor is connected to the second power supply voltage, and the drain electrode is connected to the drain electrode of the second reset transistor and the drain electrode of the current mirror load transistor; the gate electrode of the second reset transistor is connected to the second-stage second reset signal, the source electrode is connected to the gate electrode of the current mirror load transistor and the positive electrode plate of the bias capacitor; the negative electrode plate of the bias capacitor is connected to the second ground; the source electrode of the current mirror load transistor is connected to the second ground, and the drain electrode leads out an output terminal to output the second comparison signal.

[0009] Optionally, in the two-stage comparator, the first reset transistor is a PMOS, the second reset transistor is an NMOS, the amplifier transistor is a PMOS, and the current mirror load transistor is an NMOS.

[0010] Optionally, in the two-stage comparator, the first voltage-dividing capacitor and the second voltage-dividing capacitor are configured with different capacitance values to perform voltage division on the first comparison signal so that the voltage amplitude input to the gate electrode of the amplifier transistor is within the range of the second power supply voltage.

[0011] Optionally, in the two-stage comparator, the first power supply voltage is an analog power supply voltage; the second power supply voltage is a digital power supply voltage or an IO power supply voltage.

[0012] Optionally, in the two-stage comparator, the first-stage comparison circuit includes a first input capacitor, a second input capacitor, a first differential transistor, a second differential transistor, a first load transistor, a second load transistor, a third reset transistor, a fourth reset transistor, and a tail current source transistor; The positive plate of the first input capacitor is connected to the ramp signal, and the negative plate is connected to the gate of the first differential transistor and the source of the third reset transistor; the positive plate of the second input capacitor is connected to the pixel signal, and the negative plate is connected to the gate of the second differential transistor and the drain of the fourth reset transistor; the source of the first differential transistor is connected to the drain of the tail current source transistor, and the drain is connected to the drain of the third reset transistor and the drain of the first load transistor; the source of the second differential transistor is connected to the drain of the tail current source transistor, and the drain is connected to the source of the fourth reset transistor and the drain of the second load transistor; the gates of the third reset transistor and the fourth reset transistor are connected to the first-stage reset signal; the gate of the tail current source transistor is connected to the first-stage bias signal, and the source is connected to the first ground; the source of the first load transistor is connected to the first power supply voltage, and the gate is short-circuited to the drain; the source of the second load transistor is connected to the first power supply voltage, the gate is connected to the gate of the first load transistor, and the drain leads out an output terminal to output the first comparison signal.

[0013] To solve the above technical problems, the present invention also provides a readout circuit, including the two-stage comparator described in any one of the above.

[0014] Optionally, in the readout circuit, the readout circuit further includes a pixel array and a ramp generator; the pixel array is used to provide the pixel signal to the two-stage comparator; the ramp generator is used to provide the ramp signal to the two-stage comparator.

[0015] To solve the above technical problems, the present invention also provides an image sensor, including the readout circuit described above.

[0016] The two-stage comparator, readout circuit, and image sensor provided by the present invention include: a first-stage comparison circuit configured to compare and quantize a pixel signal with a ramp signal under a first power supply voltage to output a first comparison signal; a second-stage comparison circuit configured to divide the voltage of the first comparison signal and amplify the divided first comparison signal under a second power supply voltage to obtain a second comparison signal; wherein the first power supply voltage and the second power supply voltage are different types of power supply voltages. By making the second power supply voltage different from the first power supply voltage, the two-stage comparison circuit is controlled by different power supply voltages, which not only realizes the separation of the operating voltages of the two-stage comparator, but also enables the second-stage comparison circuit to operate normally under the second power supply voltage. At the same time, by dividing and amplifying the first comparison signal through the second-stage comparison circuit, the amplitude of the signal quantity for the second-stage comparison is within the range of the second power supply voltage, thereby reducing the power consumption of the second-stage comparison circuit while eliminating the dynamic IR voltage drop generated by the second-stage comparison circuit, and further eliminating the adverse effect of the dynamic IR voltage drop on the quantization result, and solving the problem of how to reduce the dynamic power consumption of the second-stage comparison circuit in the two-stage comparator. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a circuit block diagram of the two-stage comparator provided in this embodiment; Figure 2 is a schematic diagram of the first circuit structure of the two-stage comparator provided in this embodiment; Figure 3 is a schematic diagram of the second circuit structure of the two-stage comparator provided in this embodiment; Figures 4(a) to 4(d) are respectively timing diagrams of the two-stage comparator provided in this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0018] The following further describes in detail the two-stage comparator, readout circuit, and image sensor proposed by the present invention with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise scales, only for the purpose of conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the focuses to be shown in each drawing are different, and sometimes different scales are used.

[0019] It should be noted that the "first", "second", etc. in the description, claims and drawings of the present invention are used to distinguish similar objects for describing the embodiments of the present invention, rather than for describing a specific order or sequence. It should be understood that such structures can be interchanged under appropriate circumstances. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units need not be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0020] This embodiment provides a two-stage comparator, as Figure 1 shown, including: A first-stage comparison circuit for comparing and quantifying a pixel signal with a ramp signal under a first power supply voltage to output a first comparison signal; A second-stage comparison circuit for dividing the voltage of the first comparison signal and amplifying the divided first comparison signal under a second power supply voltage to obtain a second comparison signal; wherein, the first power supply voltage and the second power supply voltage are different types of power supply voltages.

[0021] For the two-stage comparator provided in this embodiment, by making the second power supply voltage different from the first power supply voltage, the two-stage comparison circuit is controlled by different power supply voltages, which not only realizes the separation of the operating voltages of the two-stage comparator, but also enables the second-stage comparison circuit to work properly under the second power supply voltage. At the same time, by dividing the voltage and amplifying the first comparison signal through the second-stage comparison circuit, the amplitude of the signal quantity for the second-stage comparison is within the range of the second power supply voltage, thereby reducing the power consumption of the second-stage comparison circuit while eliminating the dynamic IR voltage drop generated by the second-stage comparison circuit, and further eliminating the adverse effect of the dynamic IR voltage drop on the quantization result, thus solving the problem of how to reduce the dynamic power consumption of the second-stage comparison circuit in the two-stage comparator.

[0022] In practical applications, the second power supply voltage is a power supply voltage that is insensitive to voltage fluctuations. Specifically, the first power supply voltage can be an analog power supply voltage; the second power supply voltage can be a digital power supply voltage or an IO power supply voltage, etc. Correspondingly, the ground (the first ground) connected to the first-stage comparison circuit is an analog ground wire; the ground (the second ground) connected to the second-stage comparison circuit is a digital ground wire or an IO ground wire. Since the second power supply voltage connected to the second-stage comparison circuit is a power supply voltage for digital circuits such as a digital power supply voltage or an IO power supply voltage, and digital circuits generally have only two working states, effective (high) and ineffective (low), therefore, the second power supply voltage has a higher tolerance for small IR-drop, which can ensure that the second-stage comparison circuit will not have situations such as logic errors or timing misjudgments, and ensure the accuracy of the quantization result of the readout circuit.

[0023] Further, in this embodiment, as Figure 2 and Figure 3 shown, the first-stage comparison circuit includes a first input capacitor C0, a second input capacitor C1, a first differential transistor NM0, a second differential transistor NM1, a first load transistor PM0, a second load transistor PM1, a third reset transistor PM2, a fourth reset transistor PM3, and a tail current source transistor NM2.

[0024] Specifically, the positive plate of the first input capacitor C0 is connected to the ramp signal V RAMP , and the negative plate is connected to the gate of the first differential transistor NM0 and the source of the third reset transistor PM2; the positive plate of the second input capacitor C1 is connected to the pixel signal V PIX_OUT , and the negative plate is connected to the gate of the second differential transistor NM1 and the drain of the fourth reset transistor PM3; the source of the first differential transistor NM0 is connected to the drain of the tail current source transistor NM2, and the drain is connected to the drain of the third reset transistor PM2 and the drain of the first load transistor PM0; the source of the second differential transistor NM1 is connected to the drain of the tail current source transistor NM2, and the drain is connected to the source of the fourth reset transistor PM3 and the drain of the second load transistor PM1; the gates of the third reset transistor PM2 and the fourth reset transistor PM3 are connected to the first-stage reset signal RSTN_CM1; the gate of the tail current source transistor NM2 is connected to the first-stage bias signal NB0, and the source is connected to the first ground AGND; the source of the first load transistor PM0 is connected to the first power supply voltage AVDD, and the gate is short-circuited with the drain; the source of the second load transistor PM1 is connected to the first power supply voltage AVDD, the gate is connected to the gate of the first load transistor PM0, and the drain leads out an output terminal to output the first comparison signal VCM1_OUT.

[0025] In practical applications, the first differential transistor NM0 and the second differential transistor NM1 are both NMOS, the first load transistor PM0 and the second load transistor PM1 are both PMOS, the third reset transistor PM2 and the fourth reset transistor PM3 are both PMOS, and the tail current source transistor NM2 is NMOS.

[0026] In this embodiment, the first differential transistor NM0 and the second differential transistor NM1 form a differential input pair. Therefore, in other embodiments, a differential input pair with other circuit structures can also be used to replace the first differential transistor NM0 and the second differential transistor NM1 adopted in this embodiment. The specific replacement scheme is well known to those skilled in the art and will not be elaborated in this application. It should be noted that, without departing from the gist of this application, a two-stage comparator using other differential input pair circuits should also fall within the protection scope of this application.

[0027] Of course, in other embodiments, the first-stage comparison circuit can also adopt the structure of the first-stage comparison circuit in existing conventional two-stage comparators, and this application does not limit this.

[0028] Furthermore, in this embodiment, as Figure 2 and Figure 3 shown, the second-stage comparison circuit includes a first voltage-dividing capacitor C2 and a second voltage-dividing capacitor C3; The positive electrode plate of the first voltage-dividing capacitor C2 is connected to the first comparison signal VCM1_OUT, the negative electrode plate of the first voltage-dividing capacitor C2 is connected to the negative electrode plate of the second voltage-dividing capacitor C3, and the positive electrode plate of the second voltage-dividing capacitor C3 is connected to the second power supply voltage DVDD; the second voltage-dividing capacitor is used to perform voltage division processing on the first comparison signal so that the voltage amplitude of the voltage-divided first comparison signal is within the range of the second power supply voltage DVDD. In this way, not only can the power consumption of the second-stage comparison circuit be reduced while eliminating the dynamic IR-drop generated by the second-stage comparison circuit, ensuring that the two-stage comparator does not have phenomena such as logic errors or timing misjudgments, thereby ensuring the accuracy of the quantization result; but also the original power supply of the second-stage comparison circuit by the first power supply voltage AVDD to provide the working current for processing the first comparison signal VCM1_OUT is changed to be provided by the second power supply voltage DVDD, separating the working voltages of the two-stage comparison circuit.

[0029] Specifically, in a specific embodiment, as Figure 2 shown, a circuit structure of the second-stage comparison circuit is given. The second-stage comparison circuit further includes an amplifier transistor PM4, a first reset transistor PM5, and a current mirror load transistor NM3.

[0030] Specifically, the negative electrode plate of the first voltage-dividing capacitor C2 is also connected to the source electrode of the first reset transistor PM5 and the gate electrode of the amplifier transistor PM4; the gate electrode of the first reset transistor PM5 is connected to the second-stage reset signal RSTN_CM2, and the drain electrode is connected to the drain electrode of the amplifier transistor PM4 and the drain electrode of the current mirror load transistor NM3; the source electrode of the amplifier transistor PM4 is connected to the second power supply voltage DVDD; the gate electrode of the current mirror load transistor NM3 is connected to the second-stage bias signal NB1, the source electrode is connected to the second ground DGND, and the drain electrode leads out an output terminal to output the second comparison signal VCM2_OUT.

[0031] In practical applications, Figure 2 In the circuit structure of the second-stage comparison circuit shown, the first reset transistor PM5 is a PMOS, the amplifier transistor PM4 is a PMOS, and the current mirror load transistor NM3 is an NMOS.

[0032] In addition, this embodiment also provides another circuit structure of the second-stage comparison circuit, as Figure 3 shown, the second-stage comparison circuit further includes a bias capacitor C4, a first reset transistor PM5, a second reset transistor NM4, an amplifier transistor PM4, and a current mirror load transistor NM3; The negative electrode plate of the first voltage-dividing capacitor C2 is also connected to the drain electrode of the first reset transistor PM5 and the gate electrode of the amplifier transistor PM4; the gate electrode of the first reset transistor PM5 is connected to the second-stage first reset signal RSTN_CM2, and the source electrode is connected to the reset voltage VRST2; the source electrode of the amplifier transistor PM4 is connected to the second power supply voltage DVDD, and the drain electrode is connected to the drain electrode of the second reset transistor NM4 and the drain electrode of the current mirror load transistor NM3; the gate electrode of the second reset transistor NM4 is connected to the second-stage second reset signal RST_CM2, and the source electrode is connected to the gate electrode of the current mirror load transistor NM3 and the positive electrode plate of the bias capacitor C4; the negative electrode plate of the bias capacitor C4 is connected to the second ground DGND; the source electrode of the current mirror load transistor NM3 is connected to the second ground DGND, and the drain electrode leads out an output terminal to output the second comparison signal VCM2_OUT.

[0033] In practical applications, Figure 3 In the circuit structure of the second-stage comparison circuit shown, the first reset transistor PM5 is a PMOS, the second reset transistor NM4 is an NMOS, the amplifier transistor PM4 is a PMOS, and the current mirror load transistor NM3 is an NMOS.

[0034] It should be noted that in practical applications, Figure 2 and Figure 3 in the two-stage comparator shown, the ramp signal V RAMP is provided by a ramp generator, and the pixel signal V PIX_OUTProvided by pixels in the pixel array of the image sensor; the first-stage reset signal RSTN_CM1, the second-stage reset signal (the second-stage first reset signal) RSTN_CM2, and the second-stage second reset signal RST_CM2 are provided by corresponding control circuits to reset the comparator; the first-stage bias signal NB0 and the second-stage bias signal NB1 are provided by an additional bias circuit; the reset voltage VRST2 is provided by an additional voltage circuit. Those skilled in the art can design the control circuit, bias circuit, and voltage circuit according to actual requirements, and the present application does not limit the specific circuit structures of the control circuit, bias circuit, and voltage circuit.

[0035] In specific applications, the first voltage-dividing capacitor C2 and the second voltage-dividing capacitor C3 can be configured with different capacitance values to divide the first comparison signal VCM1_OUT, so that the amplitude of the voltage VCM2_IN (i.e., the voltage of the divided first comparison signal) input to the gate of the amplifier transistor PM4 is within the range of the second power supply voltage DVDD. Thus, while reducing the power consumption of the second-stage comparison circuit, the dynamic IR-drop generated by the second-stage comparison circuit is eliminated, ensuring that no logical errors or timing misjudgments occur in the two-stage comparator, and further ensuring the accuracy of the quantization result.

[0036] Refer to Figures 4(a) to 4(b) , for the two-stage comparator provided in this embodiment Figure 2 The working principle is described as follows: Self-reset stage (0~t0): As shown in FIGS. 4(a) and 4(b), under the control of the first-stage reset signal RSTN_CM1 and the second-stage reset signal RSTN_CM2, the first-stage comparison circuit and the second-stage comparison circuit reset the third reset transistor PM2, the fourth reset transistor PM3, and the reset transistor PM5. At this time, the voltages V INP and V INN at the gates of the first differential transistor NM0 and the second differential transistor NM1 are reset to the reset voltage VRST1; the voltage VCM2_IN at the gate of the amplifier transistor PM4 is connected to the voltage VCM2_OUT at the drain to achieve self-reset and is reset to the reset voltage VRST2.

[0037] Lifting stage (t0~t1): As shown in FIGS. 4(a) and 4(b), the ramp signal V RAMP input to the first-stage comparison circuit rises based on the voltage in the self-reset stage. At this time, the voltage V INP at the gate of the first differential transistor NM0 is coupled through the first input capacitor C0, and the voltage follows V RAMP and rises based on the reset voltage VRST1; at the same time, since the pixel signal V PIX_OUTis the pixel reset signal, so the voltage V at the gate of the second differential transistor NM1 INN follows the pixel reset signal and remains at the reset voltage VRST1. The first comparison signal VCM1_OUT output by the first-stage comparison circuit amplifies the difference between the positive and negative input terminals and rises to approach the first power supply voltage AVDD. After the first comparison signal VCM1_OUT is divided by the first voltage-dividing capacitor C2 and the second voltage-dividing capacitor C3 of the second-stage comparison circuit, the voltage VCM2_IN at the gate of the amplifier transistor PM4 is VRST2 + k × (AVDD - VRST1), where k represents the voltage division coefficient; when considering the gate capacitance Cgg_PM4 of the amplifier transistor PM4, the voltage division coefficient k = C2 / (C2 + C3 + Cgg_PM4). In this way, by means of voltage division, the voltage swing of the first comparison signal VCM1_OUT is reduced, and then the voltage VCM2_IN at the gate of the amplifier transistor PM4 is adjusted to the digital voltage (second power supply voltage) domain, enabling the second-stage comparison circuit to operate normally under the second power supply voltage. The voltage of the second comparison signal VCM2_OUT output by the second-stage comparison circuit is DGND at this stage.

[0038] Quantization reset voltage stage (t1~t2): As shown in FIGS. 4(a) and 4(b), the ramp signal V RAMP uniformly decreases from the rising voltage. At this time, the voltage V at the gate of the first differential transistor NM0 INP is coupled through the first input capacitor C0, and the voltage follows V RAMP and decreases. During the decreasing process, the difference V between the positive and negative input terminals in the first-stage comparison circuit INP -V INN gradually decreases, and the output first comparison signal VCM1_OUT gradually decreases from AVDD. After the first comparison signal VCM1_OUT is divided by the first voltage-dividing capacitor C2 and the second voltage-dividing capacitor C3 of the second-stage comparison circuit, the voltage VCM2_IN at the gate of the amplifier transistor PM4 also decreases accordingly, and the second comparison signal VCM2_OUT output by the second-stage comparison circuit gradually rises from DGND to approach the second power supply voltage DVDD, realizing the output flip of the comparator and obtaining the flip time T0 of the pixel reset signal.

[0039] Rising stage (t2~t3): As shown in FIGS. 4(a) and 4(b), the pixel signal V at this time PIX_OUT is the pixel photosensitive signal. The pixel photosensitive signal is coupled through the second input capacitor C1 and transmitted to the gate of the second differential transistor NM1, making the voltage V at the gate INN follow the pixel photosensitive signal. When the photosensitive signal is 0, the voltage of V INN remains at the reset voltage VRST1 unchanged; when the value of the photosensitive signal is larger, the voltage of V INN decreases more.

[0040] Quantization reset voltage stage (t3~t4): As shown in FIGS. 4(a) and 4(b), similar to the quantization reset voltage stage, when the photosensitive signal is 0, the flip time of the pixel photosensitive signal is T0; as the value of the photosensitive signal increases, the flip time also increases from T0 to T1 and T2.

[0041] Finally, through correlated double sampling, the quantization time of the final pixel signal is obtained. As shown in FIG. 4(a), the time corresponding to the photosensitive signal of 0 (black) is T0 - T0 = 0, the time corresponding to the green signal amount is T1 - T0, and the time corresponding to the red signal amount is T2 - T0.

[0042] Referring to FIGS. 4(a) and 4(c), for the Figure 3 operating principle of the two-stage comparator provided in this embodiment is described as follows: Self-reset stage (0~t0): As shown in FIGS. 4(a) and 4(c), the first-stage comparison circuit and the second-stage comparison circuit are controlled by the first-stage reset signal RSTN_CM1, the second-stage first reset signal RSTN_CM2, and the second-stage second reset signal RST_CM2 to realize the reset of the third reset transistor PM2, the fourth reset transistor PM3, the first reset transistor PM5, and the second reset transistor NM4. At this time, the voltages V INP and V INN at the gates of the first differential transistor NM0 and the second differential transistor NM1 are reset to the reset voltage VRST1; the voltage VCM2_IN at the gate of the amplifier transistor PM4 is reset to the reset voltage VRST2 provided by the external voltage circuit; the drain of the current mirror load transistor is connected to its gate through the second reset transistor NM4 to realize the self-reset of the voltage VCM2_OUT at the drain, and is reset to the voltage VNB1.

[0043] Lifting stage (t0~t1): As shown in FIGS. 4(a) and 4(c), the ramp signal V RAMP input by the first-stage comparison circuit is lifted on the basis of the voltage in the self-reset stage. At this time, the voltage V INP at the gate of the first differential transistor NM0 is coupled through the first input capacitor C0, and the voltage follows V RAMP and is lifted on the basis of the reset voltage VRST1; at the same time, since the pixel signal V PIX_OUT at this time is the pixel reset signal, the voltage V INNFollowing the pixel reset signal, it remains at the reset voltage VRST1. The first comparison signal VCM1_OUT output by the first-stage comparison circuit amplifies the differential between the positive and negative input terminals and rises to approach the first power supply voltage AVDD. After the first comparison signal VCM1_OUT is divided by the first voltage-dividing capacitor C2 and the second voltage-dividing capacitor C3 of the second-stage comparison circuit, the voltage VCM2_IN at the gate of the amplifier transistor PM4 becomes VCM2_IN = VRST2 + k×(AVDD - VRST1), where k represents the voltage division coefficient; when considering the gate capacitance Cgg_PM4 of the amplifier transistor PM4, the voltage division coefficient k = C2 / (C2 + C3 + Cgg_PM4). In this way, by means of voltage division, the voltage swing of the first comparison signal VCM1_OUT is reduced, and then the voltage VCM2_IN at the gate of the amplifier transistor PM4 is adjusted to the digital voltage (second power supply voltage) domain, enabling the second-stage comparison circuit to operate normally under the second power supply voltage. The voltage of the second comparison signal VCM2_OUT output by the second-stage comparison circuit is DGND at this stage.

[0044] Quantization reset voltage stage (t1~t2): As shown in Figs. 4(a) and 4(c), the ramp signal V RAMP uniformly decreases from the rising voltage. At this time, the voltage V INP at the gate of the first differential transistor NM0 follows V RAMP coupled through the first input capacitor C0 and decreases. During the decrease, the differential V INP -V INN between the positive and negative input terminals in the first-stage comparison circuit gradually decreases, and the output first comparison signal VCM1_OUT gradually decreases from AVDD. After the first comparison signal VCM1_OUT is divided by the first voltage-dividing capacitor C2 and the second voltage-dividing capacitor C3 of the second-stage comparison circuit, the voltage VCM2_IN at the gate of the amplifier transistor PM4 also decreases accordingly, and the second comparison signal VCM2_OUT output by the second-stage comparison circuit gradually rises from DGND to approach the second power supply voltage DVDD, realizing the output flip of the comparator and obtaining the flip time T0 of the pixel reset signal.

[0045] Rising stage (t2~t3): As shown in Figs. 4(a) and 4(c), the pixel signal V PIX_OUT at this time is the pixel photosensitive signal. The pixel photosensitive signal is coupled through the second input capacitor C1 and transmitted to the gate of the second differential transistor NM1, making the voltage V INN at the gate follow the pixel photosensitive signal. When the photosensitive signal is 0, the voltage of V INN remains at the reset voltage VRST1 unchanged; when the value of the photosensitive signal is larger, the voltage of V INN decreases more.

[0046] Quantization reset voltage stage (t3~t4): As shown in Figs. 4(a) and 4(c), similar to the quantization reset voltage stage, when the photosensitive signal is 0, the inversion time of the pixel photosensitive signal is T0; as the photosensitive signal value increases, the inversion time also increases from T0 to T1 and T2.

[0047] Finally, through correlated double sampling, the quantization time of the final pixel signal is obtained. As shown in Fig. 4(a), the time corresponding to the photosensitive signal of 0 (black) is T0 - T0 = 0, the time corresponding to the green signal amount is T1 - T0, and the time corresponding to the red signal amount is T2 - T0.

[0048] The two-stage comparator provided in this embodiment, as shown in Fig. 4(d), in each stage of the two-stage comparator working, the working current I_CM1 of the first-stage comparison circuit hardly changes with time, that is, the power consumption of the first-stage comparison circuit is static power consumption; the working current I_CM2 of the second-stage comparison circuit changes in different working stages, that is, the power consumption of the second-stage comparison circuit is dynamic power consumption, and this dynamic current will only generate dynamic IR-drop in the digital power supply voltage (the second power supply voltage) DVDD. And the digital logic circuit generally works in two states of high (DVDD) and low (DGND), and has a relatively high tolerance for a small IR-drop. Since the IR-drop introduced by the second-stage comparison circuit is relatively small, it can ensure that the two-stage comparator will not have phenomena such as logic errors or timing misjudgments, thereby ensuring the accuracy of the quantization result.

[0049] This embodiment also provides a readout circuit, including the two-stage comparator described above.

[0050] Specifically, in practical applications, the readout circuit further includes a pixel array and a ramp generator; the pixel array is used to provide the pixel signal to the two-stage comparator; the ramp generator is used to provide the ramp signal to the two-stage comparator.

[0051] Moreover, in practical applications, the readout circuit may further include a counter, and the input end of the counter is connected to the second comparison signal, so that the comparator and the counter together form an analog-to-digital converter to realize the conversion of the analog pixel signal into a digital signal.

[0052] Moreover, this embodiment also provides an image sensor, including the readout circuit described above.

[0053] Specifically, the image sensor can be a CIS.

[0054] It should be noted that the various embodiments in this specification are described in a progressive manner. Each embodiment focuses on the differences from other embodiments. For the same or similar parts among the various embodiments, reference can be made to each other. In addition, the different parts among the various embodiments can also be combined and used, and the present invention does not make any limitations in this regard.

[0055] The two-stage comparator, readout circuit and image sensor provided in this embodiment include: a first-stage comparison circuit, configured to compare and quantize a pixel signal with a ramp signal under a first power supply voltage to output a first comparison signal; a second-stage comparison circuit, configured to divide the voltage of the first comparison signal and perform an amplification process on the divided first comparison signal under a second power supply voltage to obtain a second comparison signal; wherein, the first power supply voltage and the second power supply voltage are different types of power supply voltages. By making the second power supply voltage different from the first power supply voltage, the two-stage comparison circuit is controlled by different power supply voltages, which not only realizes the separation of the operating voltages of the two-stage comparator, but also enables the second-stage comparison circuit to operate normally under the second power supply voltage; at the same time, by dividing and amplifying the first comparison signal through the second-stage comparison circuit, the amplitude of the signal quantity for the second-stage comparison is within the range of the second power supply voltage, thereby reducing the power consumption of the second-stage comparison circuit while eliminating the dynamic IR voltage drop generated by the second-stage comparison circuit, and further eliminating the adverse effect of the dynamic IR voltage drop on the quantization result, and solving the problem of how to reduce the dynamic power consumption of the second-stage comparison circuit in the two-stage comparator.

[0056] The above description is only a description of the preferred embodiments of the present invention and does not limit the scope of the present invention in any way. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A two-stage comparator, characterized in that, Comprising: A first-stage comparison circuit for comparing and quantizing a pixel signal with a ramp signal under a first power supply voltage to output a first comparison signal; A second-stage comparison circuit for dividing the voltage of the first comparison signal and amplifying the divided first comparison signal under a second power supply voltage to obtain a second comparison signal; Wherein the first power supply voltage and the second power supply voltage are different types of power supply voltages.

2. The two-stage comparator according to claim 1, characterized in that, The second-stage comparison circuit includes a first voltage-dividing capacitor and a second voltage-dividing capacitor; The positive plate of the first voltage-dividing capacitor is connected to the first comparison signal, the negative plate of the first voltage-dividing capacitor is connected to the negative plate of the second voltage-dividing capacitor, and the positive plate of the second voltage-dividing capacitor is connected to the second power supply voltage; the second voltage-dividing capacitor is used for dividing the voltage of the first comparison signal so that the voltage amplitude of the divided first comparison signal is within the range of the second power supply voltage.

3. The two-stage comparator according to claim 2, characterized in that, The second-stage comparison circuit further includes a first reset transistor, an amplifier transistor, and a current mirror load transistor; The negative plate of the first voltage-dividing capacitor is further connected to the source of the first reset transistor and the gate of the amplifier transistor; the gate of the first reset transistor is connected to a second-stage reset signal, the drain is connected to the drain of the amplifier transistor and the drain of the current mirror load transistor; the source of the amplifier transistor is connected to the second power supply voltage; the gate of the current mirror load transistor is connected to a second-stage bias signal, the source is connected to a second ground, and the drain leads out an output terminal to output the second comparison signal.

4. The two-stage comparator according to claim 2, wherein The second-stage comparison circuit further includes a bias capacitor, a first reset transistor, a second reset transistor, an amplifier transistor, and a current mirror load transistor; The negative plate of the first voltage-dividing capacitor is further connected to the drain of the first reset transistor and the gate of the amplifier transistor; the gate of the first reset transistor is connected to a second-stage first reset signal, the source is connected to a reset voltage; the source of the amplifier transistor is connected to the second power supply voltage, the drain is connected to the drain of the second reset transistor and the drain of the current mirror load transistor; the gate of the second reset transistor is connected to a second-stage second reset signal, the source is connected to the gate of the current mirror load transistor and the positive plate of the bias capacitor; the negative plate of the bias capacitor is connected to a second ground; the source of the current mirror load transistor is connected to a second ground, and the drain leads out an output terminal to output the second comparison signal.

5. The two-stage comparator according to claim 3 or 4, characterized in that, The first reset transistor is a PMOS, the second reset transistor is an NMOS, the amplifier transistor is a PMOS, and the current mirror load transistor is an NMOS.

6. The two-stage comparator according to claim 2, wherein, The first voltage-dividing capacitor and the second voltage-dividing capacitor are configured with different capacitance values to divide the voltage of the first comparison signal so that the voltage amplitude input to the gate of the amplifier transistor is within the range of the second power supply voltage.

7. The two-stage comparator according to claim 1, wherein The first power supply voltage is an analog power supply voltage; the second power supply voltage is a digital power supply voltage or an IO power supply voltage.

8. The two-stage comparator according to claim 1, characterized in that, The first-stage comparison circuit includes a first input capacitor, a second input capacitor, a first differential transistor, a second differential transistor, a first load transistor, a second load transistor, a third reset transistor, a fourth reset transistor, and a tail current source transistor; The positive plate of the first input capacitor is connected to the ramp signal, and the negative plate is connected to the gate of the first differential transistor and the source of the third reset transistor; the positive plate of the second input capacitor is connected to the pixel signal, and the negative plate is connected to the gate of the second differential transistor and the drain of the fourth reset transistor; the source of the first differential transistor is connected to the drain of the tail current source transistor, and the drain is connected to the drain of the third reset transistor and the drain of the first load transistor; the source of the second differential transistor is connected to the drain of the tail current source transistor, and the drain is connected to the source of the fourth reset transistor and the drain of the second load transistor; the gates of the third reset transistor and the fourth reset transistor are connected to the first-stage reset signal; the gate of the tail current source transistor is connected to the first-stage bias signal, and the source is connected to the first ground; the source of the first load transistor is connected to the first power supply voltage, and the gate is shorted to the drain; The source of the second load transistor is connected to the first power supply voltage, the gate is connected to the gate of the first load transistor, and the drain leads out an output terminal to output the first comparison signal.

9. A readout circuit, characterized in that, It includes the two-stage comparator according to any one of claims 1 to 8.

10. An image sensor, characterized in that, It includes the readout circuit according to claim 9.

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