Circuit board for chip packaging and preparation method of circuit board

Abstract

The invention provides a circuit board for chip packaging and a preparation method of the circuit board, and relates to the field of semiconductor devices, in particular to the technical field of chip packaging. The circuit board used for chip packaging comprises a board body, wherein the board body comprises a first surface and a second surface which are oppositely arranged; the first bonding pad is arranged on the first surface of the board body and used for being connected with a chip, and the second bonding pad is arranged on the second surface of the board body and used for being connected with a substrate; the first interconnection layer, the intermediate layer and the second interconnection layer are arranged in the board body and are electrically contacted in sequence in a first direction; the first interconnection layer is electrically contacted with the first bonding pad through a first contact hole; a signal channel extending along a first direction and a shielding structure surrounding the signal channel are arranged in the intermediate layer; the shielding structure is in electric contact with the first interconnection layer and the second interconnection layer and is used for providing a backflow path for differential signals transmitted by the signal channel; and the second interconnection layer is electrically contacted with the second bonding pad, so that the differential signal is transmitted between the chip and the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor devices, in particular to the field of chip packaging technology, and specifically to a circuit board for chip packaging and a preparation method thereof. Background Art

[0002] With the development of artificial intelligence technology, the requirements for the computing power, cluster ability, and interconnection bandwidth between AI (Artificial Intelligence) chips are also getting higher and higher. When the total number of SerDes IOs (Serializer and Deserializer Input / Output interfaces) is limited by the chip size, it is urgent to improve the signal transmission rate of each input / output interface to meet the requirements of the interconnection bandwidth between AI chips. Summary of the Invention

[0003] The present disclosure provides a circuit board for chip packaging and a preparation method thereof.

[0004] According to one aspect of the present disclosure, a circuit board is provided, including: a board body, the board body including a first surface and a second surface arranged opposite to each other; a first pad arranged on the first surface of the board body for connecting with a chip, a second pad arranged on the second surface of the board body for connecting with a substrate; and a first interconnection layer, an intermediate layer, and a second interconnection layer that are electrically contacted in sequence in a first direction within the board body; wherein: the first interconnection layer is electrically contacted with the first pad through a first contact hole; a signal channel extending along the first direction and a shielding structure surrounding the signal channel are arranged within the intermediate layer; wherein, an insulating material is filled between the signal channel and the shielding structure; the shielding structure is electrically contacted with the first interconnection layer and the second interconnection layer respectively, and is used to provide a return path for differential signals transmitted by the signal channel; the second interconnection layer is electrically contacted with the second pad, so that the differential signals are transmitted between the chip and the substrate.

[0005] According to another aspect of the present disclosure, a method for manufacturing a circuit board is provided, including: preparing a via structure on a wafer, preparing a shielding structure within the via structure, and then preparing a signal channel to obtain an interposer; obtaining a board body by preparing a first interconnect layer on a first surface of the interposer and a second interconnect layer on a second surface of the interposer, so that the first interconnect layer, the interposer, and the second interconnect layer are in electrical contact with each other in a first direction in sequence; the first surface and the second surface are disposed opposite to each other; preparing a first contact hole for connecting a first pad on the first surface of the board body; preparing a first pad for connecting to a chip on a first surface of the first contact hole; and preparing a second pad for connecting to a substrate on a second surface of the board body.

[0006] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The drawings are used to better understand the solution and do not constitute a limitation to the present disclosure. Among them:

[0008] Figure 1 Schematically shows a circuit board structure diagram for transmitting differential signals between a chip and a substrate in related examples;

[0009] Figure 2 Schematically shows a pin distribution diagram of signal terminals and ground terminals of a SerDes IO interface according to an embodiment of the present disclosure;

[0010] Figure 3A Schematically shows a circuit board structure diagram for transmitting differential signals between a chip and a substrate according to an embodiment of the present disclosure;

[0011] Figure 3B Schematically shows a cross-sectional view of the A-A' of the circuit board according to an embodiment of the present disclosure;

[0012] Figure 4 Schematically shows a structure diagram of a circuit board according to another embodiment of the present disclosure;

[0013] Figure 5 Schematically shows the coupling paths of positive differential signals and negative differential signals inside the circuit board according to another embodiment of the present disclosure;

[0014] Figure 6 Schematically shows a cross-sectional view of the interposer of the circuit board according to another embodiment of the present disclosure;

[0015] Figure 7Schematically shows a cross-sectional view of an intermediate layer according to another embodiment of the present disclosure;

[0016] Figure 8 Schematically shows a comparison graph of insertion losses generated when a circuit board according to an embodiment of the present disclosure and a circuit board in a related example transmit differential signals;

[0017] Figure 9 Schematically shows a comparison graph of return losses generated when a circuit board according to an embodiment of the present disclosure and a circuit board in a related example transmit differential signals;

[0018] Figure 10 Schematically shows a comparison graph of TDR impedances generated when a circuit board according to an embodiment of the present disclosure and a circuit board in a related example transmit differential signals;

[0019] Figure 11 Schematically shows a flowchart of a method for manufacturing a circuit board according to an embodiment of the present disclosure;

[0020] Figures 12A to 12D Schematically shows a cross-sectional view during the manufacturing process of a circuit board according to an embodiment of the present disclosure. Detailed implementation manners

[0021] The technical solutions of the present disclosure will be further specifically described below through embodiments in conjunction with the accompanying drawings. In the specification, the same or similar reference numerals indicate the same or similar components. The description of the embodiments of the present disclosure with reference to the accompanying drawings herein is intended to explain the general inventive concept of the present disclosure and should not be construed as a limitation to the present disclosure.

[0022] In addition, in the following detailed description, for the sake of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can be implemented without these specific details.

[0023] It should be understood that although the terms first, second, etc. may be used herein to describe different elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the exemplary embodiments, the first element may be named the second element, and similarly, the second element may be named the first element. As used herein, the term "and / or" includes any combination and all combinations of one or more of the related listed items.

[0024] It should be understood that when an element or layer is referred to as being "formed on" another element or layer, the element or layer can be formed directly or indirectly on the other element or layer. That is, for example, there can be intermediate elements or intermediate layers. In contrast, when an element or layer is referred to as being "directly formed on" another element or layer, there are no intermediate elements or intermediate layers. Other words used to describe the relationship between elements or layers (such as "between" and "directly between", "adjacent" and "directly adjacent", etc.) should be interpreted in a similar manner. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z such as XYZ, XY, XZ, and YZ.

[0025] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the exemplary embodiments. As used herein, unless the context clearly dictates otherwise, the singular forms are also intended to include the plural forms. It will also be understood that when the terms "comprises" and / or "comprising" are used herein, it indicates the presence of the stated features, integers, steps, operations, elements, and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0026] As used herein, unless otherwise clearly specified and defined, the term "connected" should be understood in a broad sense. For example, "connected" can be a fixed connection, a detachable connection, or an integral one; it can be directly connected or indirectly connected through an intermediate medium.

[0027] As used herein, unless otherwise specified, the expression "the same layer" generally intends to convey the following meaning: at least two layers, patterns, elements, components, or parts are formed on the same substrate or film layer by the same lithography process.

[0028] Figure 1 A circuit board structure diagram for transmitting differential signals between a chip and a substrate in related examples is schematically shown.

[0029] In related examples, the transmission of SerDes differential signals between a chip and a substrate is all based on the structure as Figure 1 shown.

[0030] As Figure 1As shown, a TSV (Through Silicon Via) 131 is disposed within the silicon interposer 130. The TSV 131 is isolated from the silicon material through a thin layer of silicon dioxide layer 132. Above the TSV 131 is connected to the lower surface of the metal layer 110 and interconnected with the chip through the ubump (microbump) 160 of the signal terminal. Below the TSV 131 is connected to the C4 (Controlled Collapse Chip Connection) bump 150 through the UBM (UnderBump Metallization) 140 to achieve interconnection with the substrate.

[0031] However, since the TSV is buried in the structure of the silicon material, due to the relative dielectric constant of silicon being as high as 12, for differential signals, the transmission impedance of this structure is at least 20% lower than the system interconnection impedance. The impedance difference will cause a large signal energy reflection at the chip end, generating high insertion loss and return loss, which restricts the bandwidth of the interconnection channel.

[0032] In view of this, the embodiments of the present disclosure provide a circuit board for chip packaging. By arranging a shielding structure around the signal channel in the interposer, filling an insulating material between the signal channel and the shielding structure, and electrically contacting the shielding structure with the first interconnection layer and the second interconnection layer respectively, a return path is provided for the differential signals transmitted by the signal channel. Due to the low dielectric constant of the insulating material, the capacitance between the signal terminal and the ground terminal is reduced, the insertion loss and return loss at the chip end are lowered, and the bandwidth of the interconnection channel is further improved, which can support SerDes channels to meet the transmission requirements of 112G~448G bandwidth.

[0033] In an actual application scenario, the pin distributions of the signal terminal and the ground terminal of the SerDes IO interface need to ensure the impedance consistency requirement after interconnection to the silicon interposer. For example, the differential impedance of the circuit board for transmitting differential signals can be 85~100Ω, and the common-mode impedance can be 42.5~50Ω.

[0034] Figure 2 Schematically shows the pin distribution diagram of the signal terminal and the ground terminal of the SerDes IO interface according to the embodiments of the present disclosure.

[0035] As Figure 2 shown, the pins marked with the letter S are signal pins. For example: S1+, S1-, S2+, S2-, S3+, S3-, S4+, S4-. Each group with the same letter and number identifier represents a group of pins for transmitting a differential signal pair. For example: S1+, S1-, S1+ is used to transmit the positive differential signal, and S1- is used to transmit the negative differential signal.

[0036] In the embodiments of the present disclosure, differential signals can be transmitted in a G-S-S-G (Ground-Signal-Signal-Ground) wiring manner. Therefore, the position distribution of the ubumps on the circuit board for transmitting differential signals can be consistent with the pin distribution of the signal terminals and ground terminals of the SerDes IO interface.

[0037] For example, the position distribution of the ubumps on the circuit board for transmitting differential signal pair S1 is as shown in Figure 2 201. The differential impedance can represent the impedance of the loop between two ubumps for transmitting differential signal S1+ and for transmitting differential signal S1-. The common-mode impedance can include: the impedance between two ubumps for transmitting differential signal S1+ and for transmitting ground signal G01, and the impedance between two ubumps for transmitting differential signal S1- and for transmitting ground signal G02. The closer the distance between adjacent ubumps, the lower the impedance. Therefore, the distance between each ubump can be defined according to actual requirements to meet the requirement that the pin distribution of the signal terminals and ground terminals of the SerDes IO interface needs to ensure impedance consistency after being interconnected to the silicon interposer.

[0038] Next, taking the position distribution of the ubumps shown in Figure 2 201 as an example, the circuit board structure of the embodiments of the present disclosure will be described in detail.

[0039] Figure 3A Schematically shows a circuit board structure diagram for transmitting differential signals between a chip and a substrate according to an embodiment of the present disclosure.

[0040] As shown in Figure 3A , the circuit board 300A includes a board body 11, and the board body includes a first surface and a second surface disposed opposite to each other. For example, the first surface and the second surface can be disposed opposite to each other along the Y direction. For example, the first surface can be the top surface of the board body 11, and the second surface can be the bottom surface of the board body 11.

[0041] On the first surface of the board body 11, a first pad 12 for connecting to a chip is provided. The first pad can include a first signal pad connected to the signal pins of the chip and a first ground pad connected to the ground pins of the chip.

[0042] Referring to Figure 3A , the first signal pad can include: a positive signal pad 121 for transmitting positive differential signal S1+ and a negative signal pad 122 for transmitting negative differential signal S1-. The first ground pad can include: a ground pad 123 for transmitting ground signal G01 and a ground pad 124 for transmitting ground signal G02.

[0043] On the second surface of the above-mentioned board body 11, a second pad 13 for connecting to the substrate is provided. The second pad may include a second signal pad connected to the signal pin of the substrate and a second ground pad connected to the ground pin of the substrate.

[0044] Referring to Figure 3A , the second signal pad may include: a positive signal pad 131 for transmitting the positive differential signal S1+ and a negative signal pad 132 for transmitting the negative differential signal S1-. The second ground pad may include: a ground pad 133 for transmitting the ground signal G01 and a ground pad 134 for transmitting the ground signal G02.

[0045] In the embodiment of the present disclosure, a first interconnection layer 21, an intermediate layer 22, and a second interconnection layer 23 that are electrically contacted in sequence are arranged in the above-mentioned board body in the first direction. The first direction may be the Y direction.

[0046] Referring to Figure 3A , the first interconnection layer 21 is electrically contacted with the first pad 12 through a first contact hole 14, and the first contact hole extends along the Y direction. The intermediate layer 22 is used to achieve high-density interconnection between different chip particles on the package, such as: memory units, logic units, and input / output units, etc. Therefore, for the SerDes interface, the first interconnection layer 21 is mainly used to achieve the interconnection between the ubump and the intermediate layer. The second interconnection layer 23 is electrically contacted with the second pad 13 to enable the above-mentioned differential signal to be transmitted between the above-mentioned chip and the above-mentioned substrate.

[0047] Referring to Figure 3A , a signal channel 221 extending in the first direction and a shielding structure 222 surrounding the signal channel 221 are arranged in the intermediate layer 22. An insulating material 223 is filled between the signal channel 221 and the shielding structure 222. The insulating material may be a material with a dielectric constant less than 4, such as: silicon dioxide.

[0048] In some embodiments, the signal channels for transmitting the positive differential signal S1+ and the signal channel structure for transmitting the negative differential signal S1- may be respectively arranged in two TSV structures, as Figure 3A shown.

[0049] In some embodiments, according to actual needs, two or more signal channels may be arranged in one TSV structure, and a shielding structure is arranged around each signal channel. The embodiment of the present disclosure does not specifically limit the number of signal channels in each TSV structure.

[0050] Exemplarily, the signal channel may be a solid metal column, such as: a solid copper column. The shielding structure may be concentrically arranged around the circumference of the signal channel with the center of the signal channel as the center of the circle, as Figure 3Bas shown

[0051] Exemplarily, the shielding structure can also surround the circumference of the signal channel in a hole shape, or can surround the circumference of the signal channel in a semi-surrounding structure.

[0052] Referring to Figure 3A as shown, the TSV structure for transmitting the ground signal can still adopt the TSV structure in the related examples, which will not be elaborated here.

[0053] In the embodiment of the present disclosure, by arranging a shielding structure around the signal channel in the interposer layer, filling an insulating material between the signal channel and the shielding structure, and electrically contacting the shielding structure with the first interconnect layer and the second interconnect layer respectively, a return path is provided for the differential signal transmitted by the signal channel. Since the dielectric constant of the insulating material is low, the capacitance between the signal terminal and the ground terminal is reduced, the insertion loss and return loss at the chip end are reduced, and the bandwidth of the interconnect channel is further improved, which can support the SerDes channel to meet the transmission requirements of 112G~448G bandwidth.

[0054] Figure 4 Schematically shows a structural diagram of a circuit board according to another embodiment of the present disclosure.

[0055] As Figure 4 shown, in the structure shown in this embodiment 400, the first interconnect layer includes a first interconnect structure 202 and a second interconnect structure 201 that are arranged in a second direction intersecting the first direction and are insulated from each other. The first direction can be the Y direction, and the second direction can be the X direction. The first interconnect structure 202 is in electrical contact with the first signal pad 121. The second interconnect structure 201 is in electrical contact with the first ground pad 123.

[0056] Due to the skin effect in differential signal transmission, the signal current only flows on the two closest surfaces where the metals are mutually coupled. For example: the signal path can be transmitted along the left side of the first interconnect structure 202. The return path can be transmitted along the right side of the second interconnect structure 201.

[0057] Therefore, the distance between the first interconnect structure 202 and the second interconnect structure 201 can be adjusted. For example: the smaller the distance between the first interconnect structure 202 and the second interconnect structure 201, the stronger the coupling, and the smaller the common-mode impedance between the S1+ terminal and the G1 terminal. The larger the distance between the first interconnect structure 202 and the second interconnect structure 201, the weaker the coupling, and the larger the common-mode impedance between the S1+ terminal and the G1 terminal. So that the common-mode impedance between the signal terminal and the ground terminal is matched, signal transmission distortion is reduced, and common-mode interference is suppressed.

[0058] According to an embodiment of the present disclosure, the first interconnect layer may include a plurality of first sub - interconnect layers, and the plurality of first sub - interconnect layers are spaced apart in the first direction and extend in the second direction respectively.

[0059] Referring to Figure 4 , the first interconnect layer may include a plurality of first sub - interconnect layers 211, 212, 213. The first direction is the Y - direction, and the second direction is the X - direction. For example: the plurality of first sub - interconnect layers 211, 212, 213 are spaced apart in the Y - direction and extend in the X - direction respectively.

[0060] According to an embodiment of the present disclosure, a plurality of second contact holes arranged in the second direction are provided between at least two adjacent first sub - interconnect layers, and two end portions of the second contact holes in the first direction are in electrical contact with the at least two adjacent first sub - interconnect layers respectively.

[0061] Referring to Figure 4 , a plurality of second contact holes 214 are arranged in the X - direction between the first sub - interconnect layer 211 and the first sub - interconnect layer 212. A plurality of second contact holes 214 are arranged in the X - direction between the first sub - interconnect layer 212 and the first sub - interconnect layer 213.

[0062] In the first interconnect structure 202, the size of the first sub - interconnect layer is the same as the size of the signal channel, and the number of the second contact holes 214 between the first sub - interconnect layers in the first interconnect structure 202 is small, so that the parasitic capacitance in the first interconnect structure can be reduced and the impedance of the first interconnect structure can be improved.

[0063] In the second interconnect structure 201, the size of the first sub - interconnect layer is larger than the size of the first sub - interconnect layer in the first interconnect structure 202, and the number of the second contact holes 214 between the first sub - interconnect layers in the second interconnect structure 201 is larger than the number of the second contact holes 214 between the first sub - interconnect layers in the first interconnect structure 202.

[0064] Referring to Figure 4 , the number of the second contact holes 214 between the first sub - interconnect layers in the second interconnect structure 201 is 5, and the number of the second contact holes 214 between the first sub - interconnect layers in the first interconnect structure 202 is 1, so as to achieve electromagnetic crosstalk isolation from other differential signal pairs. At the same time, it is also convenient to horizontally and flexibly adjust the distance between the ubump of the signal terminal and the ubump of the ground terminal to meet the electrical performance requirements of the device.

[0065] Referring to Figure 4, the second interconnection layer may include a third interconnection structure 302 and a fourth interconnection structure 301 that are arranged in a second direction intersecting the first direction and insulated from each other. The third interconnection structure 302 is in electrical contact with the second signal pad 131; the fourth interconnection structure 301 is in electrical contact with the second ground pad 133.

[0066] In an embodiment of the present disclosure, the impedance between the signal terminal and the ground terminal can be adjusted by adjusting the interval between the second signal pad and the second ground pad, so as to make the impedance consistency between the signal terminal and the ground terminal in the vertical direction of the circuit board.

[0067] Referring to Figure 4 , the second interconnection layer may include second sub-interconnection layers 311, 312. The first direction is the Y direction, and the second direction is the X direction. For example: the second sub-interconnection layers 311, 312 are spaced apart in the Y direction and extend in the X direction respectively.

[0068] According to an embodiment of the present disclosure, a plurality of third contact holes arranged in the above-mentioned second direction are provided between at least two adjacent second sub-interconnection layers, and two end portions of the third contact holes in the above-mentioned first direction are respectively in electrical contact with the at least two adjacent first sub-interconnection layers.

[0069] Referring to Figure 4 , a plurality of third contact holes 313 are arranged in the X direction between the second sub-interconnection layer 311 and the second sub-interconnection layer 312.

[0070] The size of the second sub-interconnection layer in the third interconnection structure 302 is the same as the size of the signal channel. The number of third contact holes 313 between the second sub-interconnection layers in the third interconnection structure 202 is small, so that the parasitic capacitance in the third interconnection structure can be reduced and the impedance of the third interconnection structure can be improved.

[0071] The size of the second sub-interconnection layer in the fourth interconnection structure 301 is larger than the size of the second sub-interconnection layer in the third interconnection structure 302. The number of third contact holes 313 between the second sub-interconnection layers in the fourth interconnection structure 301 is greater than the number of second contact holes 313 between the second sub-interconnection layers in the third interconnection structure 302.

[0072] In the embodiments of the present disclosure, the cooperation between each second sub-interconnection layer in the fourth interconnection structure and the third contact hole realizes the isolation between the signal channel and the ground return path. The shielding structure arranged around the signal channel is laterally offset and connected to the TSV structure interconnected with the ground terminal through the second sub-interconnection layer 311. Therefore, the center of the second sub-interconnection layer 311 does not need to be aligned with the center of the C4 bump of the ground terminal, and the center of the second sub-interconnection layer 312 needs to be aligned with the center of the C4 bump of the ground terminal, so that the position of the C4 bump of the ground terminal can be flexibly adapted according to the position of the ground terminal on the substrate side.

[0073] Referring to Figure 4 , the number of the third contact holes 313 between each second sub-interconnection layer in the fourth interconnection structure 301 is 5, and the number of the third contact holes 313 between each second sub-interconnection layer in the third interconnection structure 202 is 1, so as to realize the electromagnetic crosstalk isolation from other differential signal pairs. At the same time, it is also convenient to laterally and flexibly adjust the distance between the C4 bump of the signal terminal and the C4 bump of the ground terminal to meet the electrical performance requirements of the device.

[0074] Figure 5 Schematically shows the coupling paths of the positive differential signal and the negative differential signal inside the circuit board according to another embodiment of the present disclosure.

[0075] As Figure 5 shown, the signal channel may include: the signal channel includes a first channel 2231 for transmitting the positive differential signal and a second channel 2232 for transmitting the negative differential signal. The shielding structure includes a first shielding structure 2221 around the first channel 2231 and a second shielding structure 2222 around the second channel 2232. The first shielding structure 2221 is in electrical contact with the first interconnection layer 21 and the second interconnection layer 31 respectively. The second shielding structure 2222 is in electrical contact with the first interconnection layer 21 and the second interconnection layer 31 respectively.

[0076] Referring to Figure 5 , since the first shielding structure 2221 and the second shielding structure 2222 are short-circuited through the first interconnection layer 21, a low-impedance coupling path is provided for the S1+ terminal and the S1- terminal, so that the ground signal in the first shielding structure can flow out through the first interconnection layer, the second shielding structure, and then from the S1- terminal. Thus, in addition to the coupling path between the signal terminal and the ground terminal, an additional low-impedance coupling path is provided for the positive differential signal and the negative differential signal, strengthening the cohesive coupling of the differential signal and improving the ability to resist external noise interference.

[0077] In some embodiments, the center of the first interconnection structure 202 is aligned with the center of the signal channel 223. Thus, the consistency of the transmission performance of the differential signal in the vertical direction is ensured.

[0078] In some embodiments, the first distance between the first channel and the second channel is the same as the second distance between the positive signal pad and the negative signal pad, thereby ensuring the consistency of the transmission performance of the differential signal in the vertical direction.

[0079] In some embodiments, the insulating material, the filling size of the insulating material, and the size of the signal channel can be adjusted according to actual requirements to meet the impedance requirements.

[0080] For example, the relationship between the dielectric constant of the insulating material, the filling size of the insulating material, and the size of the signal channel can be constrained according to Equation (1).

[0081] (1)

[0082] Where ε r represents the dielectric constant of the insulating material; D represents the filling size of the insulating material; d represents the size of the signal channel; Z o (Ohms) represents the common-mode impedance of the structure for transmitting differential signals.

[0083] In addition to Figure 3B the G-S-S-G distribution shown, a plurality of ground terminals can also be provided on the circumference around the signal terminal.

[0084] Figure 6 Schematically shows a cross-sectional view of an interposer of a circuit board according to another embodiment of the present disclosure.

[0085] As Figure 6 shown, a plurality of ground channels 603 are provided on the circumference of the circuit board 600 around the first channel 601 for transmitting positive differential signals. A plurality of ground terminals 603 are provided on the circumference around the second channel 602 for transmitting negative differential signals. Thereby, more ground return paths can be provided for the differential signal transmission process, further improving the transmission performance of the device.

[0086] In addition to Figure 3B providing independent shielding structures for the first channel for transmitting positive differential signals and the second channel for transmitting negative differential signals as shown, a common shielding structure can also be provided for surrounding the first channel and the second channel.

[0087] Figure 7 Schematically shows a cross-sectional view of an interposer according to still another embodiment of the present disclosure.

[0088] As Figure 7As shown, a common shielding structure 703 is provided on the circuit board 700 around the first channel 701 for transmitting positive differential signals and around the second channel 702 for transmitting negative differential signals, and an insulating material is filled between the common shielding structure 703 and the first channel 701 and the second channel 702 to provide a return path for the differential signals transmitted by the first channel and the second channel.

[0089] The following combines Figures 8 to 10 to illustrate the improvement in the differential signal transmission performance of the circuit board provided by the embodiments of the present disclosure by comparing the circuit board structure shown in the embodiments of the present disclosure ( Figure 4 ) and the related examples ( Figure 1 ).

[0090] It should be noted that in Figures 8 to 10 , the curve with a triangular mark represents the transmission performance of the differential signal in the related example, and the curve without any mark represents the transmission performance of the differential signal in the embodiments of the present disclosure.

[0091] Figure 8 Schematically shows a comparison diagram of the insertion loss generated when the circuit board according to the embodiments of the present disclosure and the circuit board in the related examples transmit differential signals.

[0092] As Figure 8 shown, the abscissa of the insertion loss comparison diagram 800 represents the frequency, and the ordinate represents the insertion loss. As the frequency of the differential signal increases, the insertion loss of the differential signal of the circuit board provided by the related example gradually increases. However, the insertion loss of the differential signal of the circuit board provided by the embodiments of the present disclosure has always been near 0, indicating that the insertion loss generated by the circuit board provided by the embodiments of the present disclosure in the differential signal transmission is small. Therefore, the transmission performance of the differential signal can be significantly improved.

[0093] Figure 9 Schematically shows a comparison diagram of the return loss generated when the circuit board according to the embodiments of the present disclosure and the circuit board in the related examples transmit differential signals.

[0094] As Figure 9 shown, the abscissa of the return loss comparison diagram represents the frequency, and the ordinate represents the return loss. When the frequencies of the differential signals are the same, the return loss of the differential signal of the circuit board provided by the related example is always greater than the return loss of the differential signal of the circuit board provided by the embodiments of the present disclosure, indicating that the return loss generated by the circuit board provided by the embodiments of the present disclosure in the differential signal transmission is small. Therefore, the transmission performance of the differential signal can be significantly improved.

[0095] Figure 10Schematically shows a TDR impedance comparison diagram generated when a circuit board according to an embodiment of the present disclosure and a circuit board in a related example transmit differential signals.

[0096] As Figure 10 shown, the abscissa of the TDR (Time Domain Reflectometry) impedance comparison diagram represents time, and the ordinate represents impedance. As time progresses, the impedance of the circuit board provided by the related example fluctuates greatly, but the impedance of the circuit board provided by the embodiment of the present disclosure fluctuates less, indicating that the circuit board provided by the embodiment of the present disclosure can reduce impedance fluctuations during the transmission of differential signals, thereby reducing the impact of signal energy reflection generated at the chip end due to impedance fluctuations on the interconnection channel bandwidth.

[0097] Figure 11 Schematically shows a flowchart of a method for manufacturing a circuit board according to an embodiment of the present disclosure.

[0098] Figures 12A to 12D Schematically shows a cross-sectional view during the manufacturing process of a circuit board according to an embodiment of the present disclosure.

[0099] As Figure 11 shown, the method 1100 may include operations S1110 to S1150.

[0100] In operation S1110, a via structure is prepared on a wafer, a shielding structure is prepared in the via structure, and then a signal channel is prepared to obtain an interposer.

[0101] In operation S1120, a first interconnection layer is prepared on the first surface of the interposer, and a second interconnection layer is prepared on the second surface of the interposer to obtain a board body, so that the first interconnection layer, the interposer, and the second interconnection layer are in electrical contact in a first direction in sequence.

[0102] In operation S1130, a first contact hole for connecting a first pad is prepared on the first surface of the board body.

[0103] In operation S1140, a first pad for connecting to a chip is prepared on the first surface of the first contact hole.

[0104] In operation S1150, a second pad for connecting to a substrate is prepared on the second surface of the above-mentioned board body.

[0105] According to an embodiment of the present disclosure, the via structure may be a TSV structure. For example: The TSV fist (via first) process may be used to first prepare a via structure as Figure 12A shown, and then a shielding structure 222 is prepared in the via structure, and then a signal channel 221 is prepared to obtain an interposer.

[0106] According to an embodiment of the present disclosure, the above method of obtaining an interposer by fabricating a via structure on a wafer, fabricating a shielding structure within the via structure, and then fabricating a signal channel may include the following operations: after fabricating the shielding structure on the inner wall of the via structure, filling the via structure with a dielectric material; etching a trench for growing the signal channel within the dielectric material; and growing the signal channel within the trench to obtain the interposer.

[0107] Exemplarily, referring to Figure 12A , for the ground terminal, first, through a photolithography process on the wafer, such as: coating with photoresist, exposure, and development, define the area where TSV needs to be fabricated, and etch a deep trench with an aspect ratio of 1:10 to 1:20 through a deep reactive ion etching (DRIE) process. Then, use a PECVD (Plasma Enhanced Chemical Vapor Deposition) / ALD (Atomic Layer Deposition) deposition process to fabricate an insulating layer (liner) layer 132, use a PVD (Physical Vapor Depositionr, physical vapor deposition, sputtering) to fabricate a barrier layer composed of metal (Ti / Ta) or metal compound (TiN / Ta / N), use a PVD to fabricate a metal seed layer (Cu), and then use an electro-chemical plating (ECP) process to fill the hole to fabricate the main part of the TSV copper column, that is, the ground channel 131. Subsequently, use chemical mechanical polishing (CMP) to remove the excess part grown on the wafer surface by the above PECVD / PVD / ECP processes.

[0108] Exemplarily, referring to Figure 12A, for the ground terminal, first, the area on the wafer where this type of TSV needs to be fabricated can be defined through a lithography process while protecting the TSV structures fabricated in the aforementioned process. Subsequently, an insulating layer and a barrier layer 224 are fabricated using DRIE, PECVD / ALD. In the subsequent steps, an outer copper metal layer is fabricated through PVD as a shielding structure 222 while retaining the trench structure. Subsequently, a dielectric material 223 is deposited in large quantities through the PECVD process to fill the space between the signal TSV and the shielding structure. Subsequently, the trench structure required for the central TSV copper pillar structure is defined and etched through a lithography process. Next, the barrier layer and the seed layer required for fabricating the central TSV copper pillar structure are completed through PVD. Subsequently, the copper pillar structure of the central TSV is filled and grown through ECP, i.e., the signal channel 221. Similarly, after completing the fabrication of this part of the TSV structure, the CMP process is required to remove the excess parts grown on the wafer surface by the above PECVD / PVD / ECP.

[0109] In some embodiments, the TSV structures of the ground terminal and the signal terminal can be carried out in parallel to shorten the process flow.

[0110] Exemplarily, referring to Figure 12B , a dual damascene process can be used on the first surface of the interposer to fabricate the second contact hole and the interconnect layer structure using processes such as dielectric layer deposition, spin coating, exposure, development, etching, stripping, sputtering, electroplating, and CMP. Multiple layers of the second contact holes 214 and the first interconnect layers 211 - 213 are fabricated through multiple cycles. The first pad 12 can be fabricated using deposition, exposure, and etching processes and is electrically contacted with the first interconnect layer through the first contact hole 14. The surface ubump and C4 bump are fabricated using a standard bumping process through steps such as sputtering, spin coating, exposure, development, electroplating, stripping, etching, and reflow.

[0111] Exemplarily, the exposure of the TSV can be completed using processes such as backside thinning, primary CMP, etching, dielectric layer (insulating layer) deposition, and secondary CMP commonly used in the industry. The structure after this part of the process is as Figure 12C shown.

[0112] Exemplarily, after the secondary CMP, processes such as sputtering, spin coating, exposure, development, electroplating, and stripping can be used to fabricate the second sub-interconnection layer 311. Through special circuit pattern design and mask pattern definition, the annular interconnection circuit structure shown in the figure can be achieved. Then, materials such as BCB (BenzoCycloButene) and PBO (PolybenzOxazole) can be coated above the second sub-interconnection layer 311 to act as the backside dielectric layer. Subsequently, through the photolithography process, the part of the second sub-interconnection layer 311 that needs to be interconnected with the third contact hole 313 is exposed. Subsequently, processes such as sputtering, spin coating, exposure, development, electroplating, and stripping are used to complete the fabrication of the third contact hole and the second sub-interconnection layer 312. Finally, the C4 bump structure is fabricated through PI coating and bumping processes. After this part of the process is completed, the structure is as shown in Figure 12D shown.

[0113] High-density interconnection between the chip and the substrate is achieved through the via-first process, improving the performance and efficiency of chip vertical integration.

[0114] As used herein, the terms "substantially", "about", "approximate" and other similar terms are used as approximate terms rather than as terms of degree, and they are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. Taking into account factors such as process variations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximate" as used herein includes the stated value and represents an acceptable deviation range for the particular value determined by a person of ordinary skill in the art. For example, "about" can mean within one or more standard deviations, or within ±10% or ±5% of the stated value.

[0115] Those skilled in the art will appreciate that the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly described in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features described in the various embodiments of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0116] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments have been described separately above, this does not mean that the measures in the various embodiments cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A circuit board for chip packaging, comprising: A board body, the board body including a first surface and a second surface arranged opposite to each other; A first pad provided on the first surface of the board body for connecting with a chip, and a second pad provided on the second surface of the board body for connecting with a substrate; and A first interconnect layer, an intermediate layer, and a second interconnect layer which are electrically contacted in sequence in a first direction and provided in the board body; Wherein: The first interconnect layer is electrically contacted with the first pad through a first contact hole; A signal channel extending in the first direction and a shielding structure surrounding the signal channel are provided in the intermediate layer; wherein, an insulating material is filled between the signal channel and the shielding structure; the shielding structure is electrically contacted with the first interconnect layer and the second interconnect layer respectively, and is used to provide a return path for differential signals transmitted by the signal channel; The second interconnect layer is electrically contacted with the second pad, so that the differential signals are transmitted between the chip and the substrate.

2. The circuit board according to claim 1, wherein The first pad includes a first signal pad and a first ground pad; the first interconnect layer includes a first interconnect structure and a second interconnect structure which are arranged in a second direction intersecting with the first direction and insulated from each other; The first interconnect structure is electrically contacted with the first signal pad; the second interconnect structure is electrically contacted with the first ground pad.

3. The circuit board according to claim 2, wherein, The first interconnect layer includes a plurality of first sub-interconnect layers, and the plurality of first sub-interconnect layers are spaced apart in the first direction and extend in the second direction respectively; A plurality of second contact holes arranged in the second direction are provided between at least two adjacent first sub-interconnect layers, and two end portions of the second contact holes in the first direction are electrically contacted with the at least two adjacent first sub-interconnect layers respectively; The number of second contact holes in the first interconnect structure is less than the number of second contact holes in the second interconnect structure.

4. The circuit board according to claim 2 or 3, wherein, The center of the first interconnect structure is aligned with the center of the signal channel.

5. The circuit board according to any one of claims 1-4, wherein, The signal channel includes a first channel for transmitting a positive differential signal and a second channel for transmitting a negative differential signal; the shielding structure includes a first shielding structure surrounding the first channel and a second shielding structure surrounding the second channel; The first shielding structure is electrically contacted with the first interconnect layer and the second interconnect layer; The second shielding structure is electrically contacted with the first interconnect layer and the second interconnect layer; so that the ground signal in the first shielding structure is coupled with the differential signal in the second shielding structure.

6. The circuit board according to claim 5, wherein, The first signal pad includes: a positive signal pad for transmitting a positive differential signal and a negative signal pad for transmitting a negative differential signal; a first distance between the first channel and the second channel is the same as a second distance between the positive signal pad and the negative signal pad.

7. The circuit board according to claim 1, wherein: The second pad includes a second signal pad and a second ground pad; the second interconnect layer includes a third interconnect structure and a fourth interconnect structure which are arranged in a second direction intersecting with the first direction and insulated from each other; The third interconnect structure is electrically contacted with the second signal pad; the fourth interconnect structure is electrically contacted with the second ground pad.

8. The circuit board according to claim 7, wherein, The second interconnection layer includes a plurality of second sub-interconnection layers, and the plurality of second sub-interconnection layers are spaced apart in the first direction and extend in the second direction respectively; A plurality of third contact holes arranged in the second direction are provided between at least two adjacent second sub-interconnection layers, and two end portions of the third contact holes in the first direction are in electrical contact with the at least two adjacent second sub-interconnection layers respectively; The number of the third contact holes in the third interconnection structure is less than the number of the third contact holes in the fourth interconnection structure.

9. A method for manufacturing a circuit board, the method comprising: Preparing a via structure on a wafer, preparing a shielding structure in the via structure, and then preparing a signal channel to obtain an interposer; Obtaining a board body by preparing a first interconnection layer on a first surface of the interposer and preparing a second interconnection layer on a second surface of the interposer, so that the first interconnection layer, the interposer and the second interconnection layer are in electrical contact with each other in sequence in the first direction; the first surface and the second surface are oppositely arranged; Preparing a first contact hole for connecting a first pad on the first surface of the board body; Preparing a first pad for connecting with a chip on a first surface of the first contact hole; and Preparing a second pad for connecting with a substrate on a second surface of the board body.

10. The method according to claim 9, wherein, The step of preparing a via structure on a wafer, preparing a shielding structure in the via structure, and then preparing a signal channel to obtain an interposer includes: After preparing the shielding structure on the inner wall of the via structure, filling a dielectric material in the via structure; Etching a trench for growing the signal channel in the dielectric material; and Growing the signal channel in the trench to obtain the interposer.

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