Printed circuit board, preparation method and electronic equipment

Abstract

This application discloses a printed circuit board, a manufacturing method, and an electronic device. The printed circuit board comprises: a via; a pad structure disposed on the inner wall of the via; and an electrical component disposed within the via, with the pins of the electrical component electrically connected to the pad structure via solder. Traditional surface-mounted electrical components are embedded within the via, freeing up surface space on the circuit board, allowing for the layout of more chips or signal lines.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit boards, and in particular to a printed circuit board, a preparation method, and an electronic device. Background Art

[0002] With the continuous advancement of electronic technology, signal speeds are constantly increasing, server boards are becoming increasingly complex, and the number of components on boards is constantly growing. Consequently, the layout and wiring design of printed circuit boards is moving towards higher density. As high-speed signal speeds continue to double, the requirements for signal integrity are becoming more stringent. As chip power supply voltages continue to decrease, the requirements for power supply signal decoupling and filtering are becoming increasingly stringent. Consequently, the number of components such as filter capacitors and resistors installed on printed circuit boards is increasing.

[0003] Currently, some signal transmission links require electrical components for filtering or impedance matching. In some cases, chips mounted on printed circuit boards (PCBs) also need to connect to these components. These components are typically located on the surface of the PCB, which consumes significant layout and routing space, hindering the development of high-density and miniaturized PCBs. Summary of the Invention

[0004] The present application provides a printed circuit board, a preparation method, and an electronic device to solve the problem in traditional solutions that electrical components occupy a large amount of layout and wiring space on the printed circuit board, which is not conducive to the high-density and miniaturization development of the printed circuit board.

[0005] In a first aspect, the present application provides a printed circuit board, comprising:

[0006] A via hole; an inner wall of the via hole is provided with a pad structure;

[0007] An electrical component is disposed in the via hole, and a pin of the electrical component is electrically connected to the pad structure through solder.

[0008] In a second aspect, the present application also provides a method for preparing a printed circuit board, comprising:

[0009] forming vias on a printed circuit board;

[0010] forming a pad structure on the inner wall of the via hole;

[0011] Solder is formed on the pad structure, an electrical component is disposed in the via hole, and the pin of the electrical component is electrically connected to the pad structure through the solder.

[0012] In a third aspect, the present application further provides an electronic device, comprising the printed circuit board in the first aspect.

[0013] The printed circuit board provided in this application includes vias with pad structures disposed on the inner walls of the vias. Electrical components are vertically embedded within the vias, and the pins of the electrical components are soldered to the inner pads using solder. Embedding conventional surface-mounted electrical components within the vias frees up surface space on the circuit board, allowing for the layout of more chips or signal lines. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0015] Figure 1 A schematic structural diagram of a printed circuit board provided in an embodiment of the present application;

[0016] Figure 2 A structural diagram of another printed circuit board is provided for an embodiment of the present application;

[0017] Figure 3 A schematic diagram of the structure of an etched pad on the inner wall of a via hole of a printed circuit board provided in an embodiment of the present application;

[0018] Figure 4 A schematic diagram of the structure of an etched pad on the inner wall of a via hole of a printed circuit board provided in an embodiment of the present application;

[0019] Figure 5 A schematic diagram of the structure of an etched pad on the inner wall of a via hole of another printed circuit board provided in an embodiment of the present application;

[0020] Figure 6 A schematic flow chart of a method for preparing a printed circuit board provided in an embodiment of the present application;

[0021] Figure 7 A light path diagram for exposing a photosensitive layer provided in an embodiment of the present application;

[0022] Figure 8 A flow chart of a specific example of a method for preparing a printed circuit board provided in an embodiment of the present application;

[0023] Figure 9 A flow chart of a specific example of another method for preparing a printed circuit board provided in an embodiment of the present application;

[0024] Figure 10 This is a schematic diagram of the structure after the capacitor is welded in the via hole provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0027] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0028] With the continuous advancement of electronic technology, signal speeds are constantly increasing, server boards are becoming increasingly complex, and the number of components on boards is constantly growing. Consequently, the layout and wiring design of printed circuit boards is moving towards higher density. As high-speed signal speeds continue to double, the requirements for signal integrity are becoming more stringent. As chip power supply voltages continue to decrease, the requirements for power supply signal decoupling and filtering are becoming increasingly stringent. Consequently, the number of components such as filter capacitors and resistors installed on printed circuit boards is increasing.

[0029] At present, for example, the transmission link of high-speed signals needs to be equipped with decoupling capacitors to achieve signal filtering and power supply stabilization. Decoupling capacitors are usually set near the connector or the fan-out area of ​​the gold finger. The specific connection relationship is: the printed circuit board line starts from the connector pin and is connected to the signal layer-changing via through the decoupling capacitor to form a complete signal transmission path. In the high-speed signal transmission link, the decoupling capacitor and the signal layer-changing via are key impedance discontinuity nodes, which are prone to cause signal loss and reflection effects, and have an adverse effect on the integrity of the high-speed signal. In addition, in the traditional design, the decoupling capacitor is configured on the surface of the printed circuit board, occupying a large amount of layout space near the connector or the gold finger fan-out area, which limits the high-density integration design of the printed circuit board.

[0030] In some cases, the chip mounted on a printed circuit board (PCB) also needs to be connected to electrical components. For example, the chip is typically placed on the front of the PCB, while the capacitor is located on the back of the PCB at the corresponding position of the chip. The chip pins and capacitor pads are directly electrically connected through vias. In this layout, the capacitors occupy a large amount of space on the back of the PCB, making it difficult to simultaneously place other resistors and capacitors on the back of the chip. It also makes it impossible to install a heat sink module close to the PCB, which restricts the high-density integration and miniaturization of the PCB.

[0031] In response to the above problems, an embodiment of the present application provides a printed circuit board. Figure 1 A schematic diagram of the structure of a printed circuit board provided in an embodiment of the present application is shown in FIG. Figure 1 As shown, the printed circuit board provided by the present application includes a via 10 and an electrical component 20 .

[0032] A pad structure 11 is provided on the inner wall of the via hole, and an electrical component 20 is provided in the via hole 10. The pins of the electrical component 20 are soldered to the pad structure 11 on the inner wall of the via hole through solder 12.

[0033] In the embodiment of the present application, the diameter of the via hole can be designed according to the external dimensions of the component. The pad structure can, for example, use an electroplating process to form a continuous conductive layer on the hole wall. After the pin is inserted, the solder is melted by reflow soldering to fill the gap between the pin and the pad structure.

[0034] The embodiments of the present application embed traditional surface-mounted electrical components within vias, freeing up surface space on the printed circuit board (PCB), allowing for the layout of more chips or signal lines. The electrical component pins are directly connected to the pad structure on the inner wall of the via, shortening signal transmission distances, reducing parasitic inductance, and improving signal integrity. The embodiments of the present application can utilize existing via processing and welding processes, eliminating the need for new equipment. The pad structure can be achieved through conventional electroplating, resulting in low production costs.

[0035] In response to the design of printed circuit boards for high-speed signals in the prior art, an embodiment of the present application provides a printed circuit board with vias, and electrical components are arranged in the vias. By integrating the signal layer switching vias with the electrical components, the impedance discontinuity nodes in the high-speed signal link are effectively reduced, and the layout and wiring space of the printed circuit board is significantly reduced.

[0036] Compared to the prior art structure where chips and electrical components are placed on opposite sides of a printed circuit board, the present embodiment places the electrical components in vias, placing them closer to the chip pins. This provides a better buffering effect when the chip voltage fluctuates, thereby maintaining chip voltage stability. This more effectively filters high-frequency noise on the power line, reducing interference from power noise on signal transmission, thereby maintaining signal purity, reducing signal distortion, and ensuring the integrity and accuracy of the power signal.

[0037] In some optional embodiments, a ring-shaped insulating layer is provided on the sidewall of the via hole. Figure 2 The present invention provides another structural diagram of a printed circuit board. Figure 2 As shown, the inner wall of the via 10 is provided with an annular insulating layer 13. The pad structure 11 includes a first electroplated pad 111 and a second electroplated pad 112. The first electroplated pad 111 covers the inner wall of the via above the annular insulating layer 13. The second electroplated pad 112 covers the inner wall of the via below the annular insulating layer 13. An annular insulating layer is provided in the middle of the inner wall of the via (the thickness can be set according to actual conditions, for example, 0.2 mm, using epoxy resin dispensing molding), dividing the hole wall into two upper and lower areas. After the annular insulating layer is provided, when the pad structure is subsequently electroplated, the electroplating layers above and below the annular insulating layer can be disconnected, and a first electroplated pad 111 is formed above the annular insulating layer, and the upper first electroplated pad 111 is connected to the top signal line. The second electroplated pad 112 is formed above the annular insulating layer, and the lower second electroplated pad 112 is connected to the bottom or inner layer wiring.

[0038] The annular insulating layer electrically isolates the first and second electroplated pads, preventing high-frequency signal coupling along the via wall and preventing the upper and lower ends of the via from being connected, causing a signal short circuit. The first and second electroplated pads can connect to circuits on different layers, enabling three-dimensional signal routing. For example, the output signal of the top chip is connected to the capacitor input via the upper first electroplated pad, while the capacitor output is directly connected to the inner layer trace via the lower second electroplated pad, shortening the cross-layer interconnect path.

[0039] In some optional embodiments, the inner wall of the annular insulating layer may be interference-fitted with the electrical component.

[0040] The inner wall of the annular insulation layer forms an interference fit with the outer diameter of the electrical component, providing mechanical support. This interference fit allows the electrical component to be pre-positioned before soldering, preventing shifting during reflow, improving soldering yield, reducing the need for additional adhesive, and streamlining the process.

[0041] The inner wall of the annular insulating layer forms an interference fit with the outer contour of the electrical component. For example, the inner diameter of the annular insulating layer is 0.005-0.01mm smaller than the outer diameter of the electrical component. The tight fit is achieved by utilizing the radial pressure generated by the elastic deformation of the material. This design breaks through the planar layout thinking of traditional surface mount technology and innovatively introduces the interference fit principle in mechanical engineering into the three-dimensional integrated structure of the printed circuit board. Through precise dimensional control of the insulating layer, a composite support structure with both electrical isolation and mechanical fixation functions is constructed inside the via. The interference fit structure pre-positions and locks the electrical components before soldering. It can achieve dual axial and radial fixation of the components without the need for additional auxiliary positioning structures (such as positioning glue or clamps), solving the problem of component displacement caused by gravity or welding thermal stress in traditional through-hole installation. Verified by the reflow soldering process, this structure significantly improves the soldering yield and reduces defects such as cold solder joints and short circuits caused by component displacement. At the same time, eliminating the reliance on fixing glue not only simplifies the process of gluing and curing, but also avoids the impact of dielectric loss of adhesives on high-frequency signal transmission, thereby improving production efficiency while ensuring signal integrity.

[0042] This design achieves composite value through the deep integration of mechanical structure and electrical function: the annular insulation layer serves as an electrical isolation medium between the upper and lower pads, and also becomes a mechanical support carrier for components, constructing a multifunctional composite structure within the narrow space of thickness.

[0043] In some optional implementations, the pad structure includes an etched pad and an etched signal line, and the etched pad is connected to the etched signal line.

[0044] In embodiments of the present application, a pad structure can be formed by etching, i.e., by etching the conductive layer inside the via to form a pad structure. The pad structure includes an etched pad and an etched signal line. The etched pad is connected to the etched signal line. The etched pad and the etched signal line utilize the same exposure and development process as the outer layer circuits, providing finer line width accuracy, etched pad size, etched pad spacing, and signal line spacing.

[0045] The pad structure is formed using an etching process, breaking through the limitations of traditional vias, which are limited to conductive pathways. This innovative approach extends the precision etching technology used for the outer layers of the printed circuit board to the three-dimensional space within the via. Specifically, by performing exposure, development, and etching processes directly on the conductive layer within the via (completely inline with the outer layer process), an integrated structure of etched pads and etched signal lines is simultaneously formed, achieving micron-level precision in the fabrication of circuit features.

[0046] The core innovation of this design lies in breaking away from the traditional functional definition of vias as conductive through-holes. Instead, it leverages established PCB etching processes to construct a precise circuit structure within the via's inner wall. Etched pads serve as solder carriers for electrical components, directly connecting to the etched signal lines and forming a low-impedance transmission path from the via's inner wall to the PCB's surface. Compared to traditional electroplated pad processes, this solution utilizes a standardized exposure and development process to achieve the same level of precision as the outer circuitry within the via's inner wall.

[0047] In some optional embodiments, the etched pads include positive differential signal pads and negative differential signal pads. The electrical component includes a first electrical component and a second electrical component. A pin of the first electrical component is electrically connected to the positive differential signal pads via solder. A pin of the second electrical component is electrically connected to the negative differential signal pads via solder.

[0048] The inner wall of the via hole of the printed circuit board of this embodiment is formed into a positive differential signal pad and a negative differential signal pad through an etching process. The etching process can strictly control the distance between the two to meet the characteristic impedance requirements of high-speed differential signal transmission. The pins of the first electrical component (such as a filter capacitor) are connected to the positive differential signal pad using solder through a reflow process to achieve a stable electrical connection; the pins of the second electrical component (which can also be a filter capacitor) are connected to the negative differential signal pad in the same welding method. At the same time, the positive differential signal pad is connected to the positive differential signal line of the outer layer, and the negative differential signal pad is connected to the negative differential signal line, forming a complete differential signal transmission link.

[0049] Differential signal transmission relies on the potential difference between two signal lines to transmit information. Strictly controlling the spacing between the two lines through the etching process ensures that the differential signal maintains good symmetry during transmission, effectively suppressing common-mode noise interference. Due to the precise connection of the positive and negative differential signal pads to the corresponding electrical components, the two differential signal lines are subject to approximately the same external interference. When processed by the differential amplifier at the receiving end, the common-mode interference signal is canceled out, retaining only the valid differential-mode signal.

[0050] Integrating positive differential signal pads, negative differential signal pads, and corresponding electrical components within the vias significantly reduces layout space compared to the traditional dispersed layout on the surface of the printed circuit board. This embodiment's structure enables the printed circuit board to carry more high-speed signal transmission links within the same area, making it particularly suitable for complex electronic devices such as server boards that require extremely high signal transmission density, significantly promoting the development of high-density integration in printed circuit boards.

[0051] The etched pads are formed using the same exposure, development, and etching processes as the outer layers of the PCB. Simply adding exposure technology to the inner via wall allows for uniform imaging and precise control of line widths to the desired dimensions. This eliminates the need for complex additional equipment and processes, allowing the structure to be seamlessly integrated into existing PCB manufacturing systems. This reduces production technology barriers and manufacturing costs, ensuring excellent process compatibility and scalability.

[0052] In some optional embodiments, Figure 3 A schematic diagram of a structure of an etched pad on the inner wall of a via hole of a printed circuit board provided in an embodiment of the present application is shown as follows: Figure 3 As shown, the spacing between the positive differential signal pads (including D and F) and the negative differential signal pads (including E and G) is a preset spacing S. The positive differential signal pads include positive differential signal input pads D and positive differential signal output pads F, and the negative differential signal pads include positive differential signal input pads E and negative differential signal output pads G. The etched signal lines include positive differential signal lines (including L1 and L2) and negative differential signal lines (including L3 and L4). The positive differential signal lines are electrically connected to the positive differential signal pads. The negative differential signal lines are electrically connected to the negative differential signal pads. The line widths of the positive and negative differential signal lines are preset line widths W.

[0053] Figure 3 The preset spacing S is exemplarily set to 8 mil, and the preset line width W is 8 mil. In the printed circuit board of this embodiment, the spacing between the pads D and F used for positive differential signal transmission is set to 0.2 mm; the spacing between the pads E and G used for the negative differential signal line is also 0.2 mm. The spacing S between the positive differential signal pads (including D and F) and the negative differential signal pads (including E and G) is 8 mil, which meets the minimum spacing requirement for soldering electrical components set in the vias. The line width W of the positive differential signal line and the negative differential signal line can be accurately calculated and determined by impedance calculation software based on the target impedance value and the differential line spacing condition of 8 mil. The line width value and the spacing parameter cooperate with each other to effectively ensure the characteristic impedance matching during the differential signal transmission process and meet the requirements of high-speed signal transmission.

[0054] In high-speed differential signal transmission, characteristic impedance consistency is crucial. Precise pad spacing and line width design can control the transmission impedance of differential signals, effectively avoiding signal reflections and losses caused by impedance discontinuities, and ensuring accurate and stable data transmission.

[0055] In the printed circuit board of the embodiment of the present application, a positive differential signal pad and a negative differential signal pad are formed on the inner wall of the via hole by an etching process, and the distance between the two is strictly set to a preset distance. The etched signal line includes a positive differential signal line and a negative differential signal line, wherein the positive differential signal line is electrically connected to the positive differential signal pad, and the negative differential signal line is connected to the negative differential signal pad. The line width of the positive differential signal line and the negative differential signal line can also be precisely controlled. The line width value has been accurately calculated and verified by simulation to ensure that the characteristic impedance is stable within the required range. The strictly controlled pad spacing and line width ensure that the positive and negative differential signal lines are subjected to approximately the same external interference during transmission. When the signal is transmitted to the receiving end, the signals of the two signal lines are processed by a differential amplifier, and the common-mode noise will be effectively offset, retaining only the differential-mode signal carrying valid information.

[0056] In some optional embodiments, multiple groups of electrical components may be disposed in the via hole. The pad structure includes multiple groups of etched pads. Each group of etched pads is electrically connected to each group of electrical components in a one-to-one correspondence.

[0057] Figure 4 This is a schematic diagram of the structure of the etched pad on the inner wall of a via hole of a printed circuit board provided in an embodiment of the present application. Figure 4 As shown, in the embodiment of the present application, multiple signal line transmission links can be set in one via hole, for example, two pairs of differential signals can be set in one via hole. Figure 4 For top view, see Figure 4 , exemplarily, two groups of electrical components are arranged in the via 10, namely a first group of electrical components 21 and a second group of electrical components 22. The pad structure includes two groups of etched pads, namely a first group of etched pads 113 and a second group of etched pads 114. Each group of electrical components includes two electrical components. The first group of electrical components 21 includes electrical components 211 and 212. The second group of electrical components 22 includes electrical components 221 and 222. Each group of etched pads, for example, includes a positive differential signal pad and a negative differential signal pad. The first group of etched pads 113 includes a positive differential signal pad DP1 and a negative differential signal pad DN1, and the second group of etched pads 114 includes a positive differential signal pad DP2 and a negative differential signal pad DN2. Each group of etched pads is electrically connected to each group of electrical components in a one-to-one correspondence. The positive differential signal pad DP1 is electrically connected to the electrical component 211 , the negative differential signal pad DN1 is electrically connected to the electrical component 212 , the positive differential signal pad DP2 is electrically connected to the electrical component 221 , and the negative differential signal pad DN2 is electrically connected to the electrical component 222 .

[0058] This embodiment establishes a "one-via, multiple-component" three-dimensional integrated architecture by providing multiple sets of etched pads on the inner walls of the vias, correspondingly connecting multiple sets of electrical components. This breaks through the single-function limitations of traditional vias. For example, using two sets of differential signals as an example, compared to two independent vias, each with a set of etched pads corresponding to the differential signal and an electrical component, this embodiment only requires a single via, significantly improving space utilization.

[0059] Furthermore, multiple groups of etched pads can also support the mixed integration of different types of components (such as capacitors, resistors, and inductors), and build a "filtering-matching-coupling" functional unit within a single via.

[0060] Multiple groups of etched pads can be realized by adjusting the mask pattern (such as expanding the mask of a single group of etched pads into a ring array), which is completely colinear with the exposure, development and etching process of the outer layer circuit, without the need for additional equipment or materials.

[0061] In some optional implementations, the etched pads disposed opposite to each other on the inner wall of the via hole are staggered.

[0062] like Figure 4 As shown, two sets of etched pads are distributed circumferentially along the inner wall of the via, with the opposing etched pads staggered. The positive differential signal pad DP2 corresponds to the middle position between the positive differential signal pad DP1 and the negative differential signal pad DN1. This can minimize mutual interference between the two pairs of differential signals and enhance signal stability and integrity.

[0063] In some optional implementations, a ground signal line is further provided on the inner wall of the via hole.

[0064] Figure 5 A schematic diagram of the structure of an etched pad on the inner wall of a via hole of another printed circuit board provided in an embodiment of the present application is shown as follows: Figure 5 As shown, a ground signal line GND is provided on the inner wall of the via 10, which can be connected to the ground plane of the inner layer of the printed circuit board through a blind via. The ground signal line GND can be provided around the pad structure, for example, wrapping the pad structure corresponding to the differential signal, providing good shielding to prevent the differential signal from being interfered with by other signals, which is beneficial to improving signal integrity, reducing signal jitter, noise, crosstalk and other problems, and improving signal quality.

[0065] In a preferred embodiment, the via's inner wall innovatively integrates a ground signal line structure, breaking through the traditional via's functional limitations of serving solely as a signal transmission channel and constructing a three-dimensional electromagnetic shielding system. A continuously encircling ground signal line forms a shielding ring around the via's inner wall, spatially isolating and protecting the differential signal pads.

[0066] This embodiment extends the shielding function of the ground plane to the inner wall of the via. By etching a circular ground signal line in the hole wall, it forms a "three-dimensional ground network" with the inner ground plane, solving the industry problem of traditional vias lacking effective shielding when used as signal layer switching nodes. The circular layout of the ground signal line creates a Faraday cage effect, physically severing the electromagnetic coupling path between external interference sources and the internal signal pads.

[0067] Furthermore, the etching process of the ground signal line is formed synchronously with the pad structure, and no additional process steps are required. The shielding function can be integrated by simply adding a ring-shaped ground pattern in the mask design.

[0068] In some optional embodiments, such as Figure 4 As shown, if the via hole includes multiple groups of etched pads, the ground signal line GND can be set between adjacent etched pads to avoid mutual interference between adjacent differential signals.

[0069] In this embodiment, to meet the layout requirements of multiple groups of etched pads within a via, a ground signal line (GND) is placed within the circumferential gap between adjacent etched pads, forming a three-dimensional "pad-ground-pad" isolation structure. This design breaks away from the conventional planar layout concept of ground signal lines existing only on the surface or inner layers of printed circuit boards. By constructing a distributed ground barrier in the three-dimensional space of the via's inner wall, it achieves physical isolation and electromagnetic shielding of adjacent differential signal pairs.

[0070] The ground signal trace utilizes the inherent gaps between adjacent pads, eliminating the need for additional layout space and maintaining the pad density within the via. Furthermore, the wraparound layout of the ground signal trace forms a coplanar waveguide-like structure, providing a low-loss return path for high-frequency signals and significantly reducing impedance compared to traditional surface ground traces.

[0071] In some optional embodiments, the electrical components include filter capacitors and / or impedance matching resistors.

[0072] When the electrical component is a filter capacitor, the embodiment of the present application provides a printed circuit board with a via, and the filter capacitor is set in the via. By integrating the signal layer switching via with the electrical component, the printed circuit board design for high-speed signals in the existing technology can effectively reduce the impedance discontinuity nodes in the high-speed signal link and significantly reduce the layout and wiring space of the printed circuit board.

[0073] Compared to the prior art method of setting the chip on the front of the printed circuit board and the filter capacitor on the back of the printed circuit board, the present application forms a "near-source filtering" architecture by embedding the filter capacitor in the pad structure on the inner wall of the via: the filter capacitor is directly connected to the chip power pin through the pad structure on the inner wall of the via. The filter capacitor is closer to the chip pin configuration, which can better play a buffering role when the chip voltage fluctuates, thereby maintaining the stability of the chip voltage. It can more effectively filter out high-frequency noise on the power line and reduce the interference of power noise on signal transmission, thereby maintaining the purity of the signal, reducing signal distortion, and ensuring the integrity and accuracy of the power signal.

[0074] When the electrical component is an impedance-matching resistor, integrating it within a via can save printed circuit board space compared to traditional surface-mount solutions. Embedding the resistor in the via reduces surface mount manufacturing steps, saves investment in mounting equipment, and reduces the cost of the resistor itself (embedded resistors can use smaller packages). Placing the impedance-matching resistor close to the signal source or load can also shorten signal traces.

[0075] In some optional implementations, an insulating filling material is further provided in the via hole.

[0076] After the components are soldered, insulating filling materials (such as resin) can be used to fill the remaining space in the vias. For example, bubbles can be removed through a vacuum potting process. After curing, the surface is polished to be flush with the surface of the printed circuit board to ensure the stability and reliability of the structure and prevent subsequent processing from affecting the electrical components in the vias.

[0077] Based on the same inventive concept, the present application also provides a method for preparing a printed circuit board. Figure 6 A schematic diagram of a process for preparing a printed circuit board provided in an embodiment of the present application is shown in FIG. Figure 6 As shown, the method for preparing a printed circuit board includes:

[0078] S101 , forming a via hole on a printed circuit board.

[0079] For example, laser drilling can be used to create vias at designated locations on a printed circuit board. The hole diameter is designed based on the dimensions of the electrical component (e.g., a 0.4mm diameter via for a 0201 package capacitor). After drilling, the hole walls can be roughened and chemically cleaned to remove any residual impurities, ensuring adhesion between the subsequent conductive layer and the hole wall.

[0080] S102 , forming a pad structure on the inner wall of the via hole.

[0081] The embodiments of the present application do not limit the specific process of forming the pad structure on the inner wall of the via hole, such as electroplating, exposure and etching.

[0082] S103 , forming solder on the pad structure, placing an electrical component in the via hole, and electrically connecting the pin of the electrical component to the pad structure through the solder.

[0083] Solder such as tin paste is printed or sprayed on the surface of the pad structure. The thickness of the tin paste can be controlled according to the requirements of the via diameter, electrical component size, etc. The solder covers the effective welding area of ​​the pad structure.

[0084] Electrical components (such as filter capacitors) are vertically inserted into vias (which can be assembled using a robotic arm), ensuring precise alignment between the pins and pads. The printed circuit board is then placed in a reflow oven, undergoing preheating, holding, reflow, and cooling stages. The solder paste melts and fills the gaps between the pins and pads, forming a metallurgical solder joint. Solder, such as solder paste, acts as a medium to electrically connect and mechanically secure the pins to the pads. The reflow process utilizes heat conduction to evenly melt the solder, forming a reliable solder joint.

[0085] By embedding electrical components within vias, this embodiment significantly saves planar space compared to traditional surface mount methods. This frees up surface space for high-density circuit boards, allowing for the layout of more chips or signal lines. This approach is particularly suitable for space-sensitive applications such as server boards and high-speed interface modules. Directly connecting the electrical component pins to the pad structure on the inner wall of the via shortens the signal transmission path and significantly reduces parasitic inductance and capacitance.

[0086] In response to the design of printed circuit boards for high-speed signals in the prior art, an embodiment of the present application provides a printed circuit board with vias, and electrical components are arranged in the vias. By integrating the signal layer switching vias with the electrical components, the impedance discontinuity nodes in the high-speed signal link are effectively reduced, and the layout and wiring space of the printed circuit board is significantly reduced.

[0087] Compared to the prior art structure where chips and electrical components are placed on opposite sides of a printed circuit board, the present embodiment places the electrical components in vias, placing them closer to the chip pins. This provides a better buffering effect when the chip voltage fluctuates, thereby maintaining chip voltage stability. This more effectively filters high-frequency noise on the power line, reducing interference from power noise on signal transmission, thereby maintaining signal purity, reducing signal distortion, and ensuring the integrity and accuracy of the power signal.

[0088] In some optional embodiments, the pad structure includes a first electroplated pad and a second electroplated pad, and the pad structure is formed on the inner wall of the via hole, including:

[0089] forming an annular insulating layer in a middle area of ​​an inner wall of the via hole;

[0090] A first electroplating pad is formed by electroplating on an inner wall of the via hole above the annular insulating layer, and a first electroplating pad is formed on an inner wall of the via hole below the annular insulating layer.

[0091] by Figure 2 For example, an annular insulating layer 13 is formed in the middle area of ​​the inner wall of the via hole 10, and then electroplating is performed. Due to the isolation of the annular insulating layer 13, the first electroplated pad 111 covers the inner wall of the via hole above the annular insulating layer 13. The second electroplated pad 112 covers the inner wall of the via hole below the annular insulating layer 13.

[0092] In an embodiment of the present application, after drilling a via hole on a laminated printed circuit board, a resin adhesive can be applied to the middle of the via hole's inner wall to form an annular insulating layer. Electroplating is then performed. Due to the presence of the annular insulating layer in the middle of the via hole's inner wall, the electroplated conductive layer forms a first electroplated pad on the via hole's inner wall above the annular insulating layer, and a second electroplated pad on the via hole's inner wall below the annular insulating layer. This prevents the upper and lower ends of the via hole from being connected, causing a signal short circuit. The width of the adhesive application area can be set to, for example, 0.2 mm.

[0093] The annular insulating layer electrically isolates the first and second electroplated pads, preventing high-frequency signal coupling along the via wall and preventing the upper and lower ends of the via from being connected, causing a signal short circuit. The first and second electroplated pads can connect to circuits on different layers, enabling three-dimensional signal routing. For example, the output signal of the top chip is connected to the capacitor input via the upper first electroplated pad, while the capacitor output is directly connected to the inner layer trace via the lower second electroplated pad, shortening the cross-layer interconnect path.

[0094] In some optional embodiments, forming an annular insulating layer in the middle area of ​​the inner wall of the via hole includes:

[0095] A preset mold is placed in the via hole, and the preset mold is used to dispense glue in the middle area of ​​the inner wall of the via hole to form an annular insulating layer; the outer contour of the preset mold contacts the inner wall of the annular insulating layer formed by dispensing glue; the outer contour of the preset mold is the same as the outer contour of the electrical component.

[0096] For example, a pre-set mold can be fabricated using high-precision CNC machining based on the outer contour of the target electrical component. A vision-based alignment system controls a robotic arm to vertically insert the pre-set mold into the via hole, aligning the mold axis with the via axis. This ensures uniform clearance between the mold's outer contour and the via's inner wall, facilitating subsequent glue dispensing. Immediately after glue dispensing, UV curing is performed to rapidly solidify the resin adhesive, forming a ring-shaped insulating layer. The pre-set mold is then removed vertically by the robotic arm. Electroplating then proceeds. Due to the presence of a ring-shaped insulating layer in the middle of the via's inner wall, the conductive layer is plated onto the inner wall of the via above the insulating layer, forming the first plated pad, and onto the inner wall below the insulating layer. The electrical component is then vertically inserted into the via hole. The interference fit between the outer diameter of the component and the inner diameter of the insulating layer allows for seamless pre-positioning, eliminating the need for additional positioning tooling. The outer contour of the pre-set mold aligns with the outer contour of the electrical component, ensuring a precise fit between the inner diameter of the insulating layer and the outer diameter of the component, creating an interference fit. This design eliminates the need for additional adjustments when inserting electrical components into vias, relying on physical contact to achieve precise positioning, solving the problem of soldering displacement caused by component size deviation in traditional processes.

[0097] In some optional implementations, forming a pad structure on an inner wall of the via hole includes:

[0098] forming a conductive layer on an inner wall of the via hole;

[0099] forming a photosensitive layer on the conductive layer;

[0100] exposing and developing the photosensitive layer to form a pad structure pattern;

[0101] Etching the conductive layer exposed by the pad structure pattern to form a pad structure;

[0102] The pad structure includes an etched pad and an etched signal line; the etched pad is connected to the etched signal line.

[0103] The embodiment of the present application realizes high-precision forming of the pad structure on the inner wall of the via through the process scheme of "conductive layer-photosensitive layer-exposure development-etching". For example, a conductive layer is first formed on the inner wall of the via, and then a vacuum laminator is used to form a photosensitive layer on the inner wall of the via. After exposure, development and etching, the required pad structure pattern is exposed. Exposure is to align the mask with the pad structure pattern with the side wall of the via groove covered with the photosensitive film, and then irradiate it with ultraviolet light or other specific wavelengths. During the exposure process, the transparent part on the mask allows light to pass through and illuminate the photosensitive film. These irradiated areas will undergo a photochemical reaction, thereby changing the properties of the photosensitive film. Development is to use a developer to remove the photosensitive film in the exposed area after exposure, thereby revealing the pad structure pattern. After development, the copper foil of the non-pad structure pattern is etched to leave the required pad structure pattern.

[0104] The present invention forms the pad structure through exposure, development, and etching. This allows for more accurate pad dimensional accuracy and line width, meeting the stringent requirements for pad symmetry for high-speed differential signals. Compared to traditional electroplated pads, the edge roughness of the etched pad is significantly reduced, minimizing edge scattering during signal transmission.

[0105] This fabrication method reuses the etching process used for the outer layers of printed circuit boards (PCBs), eliminating the need for specialized equipment. Furthermore, the etching process boasts a high degree of automation, consistent pad structures, and high batch production yield, reducing manual intervention and testing costs. By adjusting etching parameters (such as line width, pad spacing, and conductive layer thickness), the process can be flexibly adapted to accommodate different packaged electrical components, creating a standardized, reproducible solution for high-density PCB fabrication and promoting integrated innovation in high-speed, miniaturized electronic devices.

[0106] In some optional embodiments, exposing and developing the photosensitive layer to form a pad structure pattern includes:

[0107] Exposure light is provided from above the via hole and is reflected by a reflector below the via hole to the photosensitive layer on the inner wall of the via hole.

[0108] Figure 7 A light path diagram for exposing a photosensitive layer provided in an embodiment of the present application. A reflector 30 can be fixed to the bottom surface of the printed circuit board directly below the via hole. The focus of the reflector coincides with the axis of the via hole, and the radius of curvature of the mirror is optimized according to the depth and aperture of the via hole. For example, a parallel light source can be used to be incident vertically from directly above the via hole. After being reflected by the reflector, the light converges to the inner wall of the via hole to form an exposure area. The exposure energy is monitored in real time by a light intensity sensor to ensure that the photosensitive layer is fully exposed to light. By adjusting the angle of the reflector, uniform illumination of the inner wall of the via hole can be achieved.

[0109] For example, the present application embodiment utilizes the principle of optical reflection and focusing to construct a three-dimensional exposure system. A reflector is positioned directly below the via hole. A parallel ultraviolet light source is incident from above the via hole, and the reflector converts the light into an annular beam along the tangent direction of the via wall, achieving uniform exposure of the circumferential area of ​​the via hole inner wall. The present application embodiment overcomes the angle limitations of traditional side-illuminated exposure and utilizes the optical focusing properties of the reflector to convert the point light source into an annular uniform light field covering the entire via hole wall, thus resolving exposure defects on the inner wall of deep holes and achieving consistent imaging accuracy of the pad structure pattern across the entire area of ​​the via hole inner wall.

[0110] In some optional embodiments, etching the conductive layer exposed by the pad structure pattern to form the pad structure includes:

[0111] Etching the conductive layer exposed by the pad structure pattern to form a plurality of groups of etched pads of the pad structure;

[0112] The etched pads arranged opposite to each other on the inner wall of the via hole are staggered.

[0113] In the embodiment of the present application, the conductive layer on the inner wall of the via hole can be formed into multiple groups of etched pads through an etching process, and each group of etched pads is electrically connected to a group of electrical components in a one-to-one correspondence, so that multiple signal line transmission links can be set in a via hole. In addition, in the embodiment of the present application, the etched pads arranged relatively on the inner wall of the via hole are staggered, for example Figure 4 Two sets of etched pads are circumferentially distributed along the inner wall of the center via, with the opposing etched pads staggered. The positive differential signal pad DP2 corresponds to the center between the positive differential signal pad DP1 and the negative differential signal pad DN1. This minimizes mutual interference between the two pairs of differential signals and enhances signal stability and integrity.

[0114] In some optional embodiments, when exposing and developing the photosensitive layer to form the pad structure pattern, the method further includes: exposing and developing the photosensitive layer to form a ground signal line pattern;

[0115] When the pad structure pattern is formed by etching to expose the conductive layer, forming the pad structure further includes: etching the conductive layer exposed by the ground signal line pattern to form a ground signal line.

[0116] In the embodiment of the present application, when exposing and developing the photosensitive layer to form a pad structure pattern, the photosensitive layer is simultaneously exposed and developed to form a ground signal line pattern. Correspondingly, when etching to form the conductive layer exposed by the pad structure pattern, the conductive layer exposed by the ground signal line pattern is simultaneously etched to form a ground signal line.

[0117] For example Figure 4 The ground signal line is set in the via hole. The ground signal line GND is set on the inner wall of the via hole. For example, it can be connected to the ground plane of the inner layer of the printed circuit board through a blind hole. The ground signal line GND can be set around the pad structure, for example, wrapping the pad structure corresponding to the differential signal to provide good shielding and prevent the differential signal from being interfered with by other signals. It is beneficial to improve signal integrity, reduce signal jitter, noise, crosstalk and other problems, and improve signal quality.

[0118] If the via contains multiple sets of etched pads, such as Figure 5 As shown, the ground signal line GND can be set between adjacent etched pads to avoid mutual interference between adjacent differential signals.

[0119] In some optional embodiments, after forming solder on the pad structure, placing an electrical component in the via hole, and electrically connecting the pin of the electrical component to the pad structure through the solder, the method further includes:

[0120] Fill the vias with insulating fill material.

[0121] After the components are soldered, insulating filling materials (such as resin) can be used to fill the remaining space in the vias. For example, bubbles can be removed through a vacuum potting process. After curing, the surface is polished to be flush with the surface of the printed circuit board to ensure the stability and reliability of the structure and prevent subsequent processing from affecting the electrical components in the vias.

[0122] Figure 8 A specific example flow chart of a method for preparing a printed circuit board provided in an embodiment of the present application is shown in FIG. Figure 8 As shown, the method for preparing a printed circuit board provided in the embodiment of the present application includes:

[0123] S201 , forming a via hole on a printed circuit board.

[0124] S202 , forming an annular insulating layer in the middle area of ​​the inner wall of the via hole.

[0125] S203 , forming a first electroplating pad on the inner wall of the via hole above the annular insulating layer by electroplating, and forming a first electroplating pad on the inner wall of the via hole below the annular insulating layer by electroplating.

[0126] S204 , forming solder on the pad structure, placing electrical components in the via holes, and electrically connecting the pins of the electrical components to the pad structure through reflow soldering.

[0127] S205. Fill the via hole with an insulating filling material.

[0128] First, a via hole, for example, with a diameter of 0.4mm, is drilled into the laminated printed circuit board. A circle of resin glue is applied to the center of the via's inner wall to prevent the upper and lower ends of the via from connecting and causing a short circuit. The glue-applied area can be, for example, 0.2mm wide. After the glue is applied, copper is electroplated on the inner wall of the via, with a thickness of, for example, 0.8 mils. This creates the first and second electroplated pads, respectively, above and below the resin glue area.

[0129] After electroplating, solder paste is printed onto the first and second plated pads on the inner wall of the via. The thickness of the printed solder paste can be, for example, 2 mils. A robotic arm is used to place an electrical component (e.g., a 0201 capacitor) into the solder-pasted via. After high-temperature reflow soldering, the 0201 capacitor is fully bonded to the via. To ensure structural stability and reliability and prevent subsequent processing from affecting the electrical component within the via, the via is then filled with resin.

[0130] For example, the size of a 0201 package capacitor is 0.6mm*0.3mm*0.23mm. Figure 1In the example, OB = 0.115mm, AB = 0.15mm, OA = 0.191mm, the via diameter is 0.4mm, and the electroplated copper thickness is 0.8mil. In an application scenario, when transmitting power signals, one pin of the 0201 package capacitor transmits the power signal, and the other pin of the 0201 package capacitor transmits the GND signal. When transmitting high-speed signals, one pin of the 0201 package capacitor transmits the DP / DN signal, and the other pin, C2, of the 0201 package capacitor carries the DP_C / DN_C signal.

[0131] In some other embodiments, the 0201 package capacitor may be replaced with a 0201 package resistor. Thus, when transmitting a low-speed signal, the 0201 package resistor pin R1 transmits the LS signal, and the 0201 package resistor pin R2 transmits the LS_R signal.

[0132] This embodiment breaks through the single conductive function of traditional printed circuit board vias through the collaborative design of "segmented isolation of vias - integration of three-dimensional pads - fully enclosed packaging", and constructs a three-dimensional interconnection structure that integrates electrical isolation, mechanical support, and signal optimization. An annular insulation layer with a width of 0.2mm is formed in the middle area of ​​the inner wall of the via, and the via is axially divided into upper and lower independent conductive areas, so that the first electroplated pad is isolated from the second electroplated pad to avoid direct coupling of upper and lower layer signals. The processes of annular insulation layer molding, electroplating, insulation filling, etc. are all compatible with existing printed circuit board production lines. By adjusting the dimensions of the annular insulation layer and the pad structure, it can be flexibly adapted to various scenarios such as power supply filtering, high-speed differential, and radio frequency signals.

[0133] Figure 9 A flow chart of a specific example of a method for preparing a printed circuit board provided in an embodiment of the present application is shown in FIG. Figure 9 As shown, the method for preparing a printed circuit board provided in the embodiment of the present application includes:

[0134] S301 , forming a via hole on a printed circuit board.

[0135] S302 , electroplating copper on the inner wall of the via hole to form a conductive layer.

[0136] S303: forming a photosensitive layer on the conductive layer on the inner wall of the via hole, and etching a pad structure through exposure and development. The pad structure includes an etched pad and an etched signal line, and the etched pad is connected to the etched signal line.

[0137] S304 , forming solder on the pad structure, placing electrical components in the via holes, and electrically connecting the pins of the electrical components to the pad structure through reflow soldering.

[0138] S305 , filling the via hole with an insulating filling material.

[0139] The embodiment of the present application forms a conductive layer by electroplating copper on the entire inner wall, establishing a complete conductive foundation for the via. The subsequent S303 exposure, development and etching process can accurately form a pad structure on the conductive layer to achieve high-precision circuit layout. The structural size, shape and signal line direction can also be flexibly defined according to design requirements to adapt to high-frequency and high-speed signal transmission scenarios. The pad and signal line are directly integrated into the inner wall of the via, which upgrades the via from a single "conduction channel" to a "signal transmission node", reduces surface wiring intersections, and improves the wiring density of the printed circuit board, which is particularly suitable for high-density interconnect boards or system-level packaging scenarios.

[0140] The embodiment of the present application transfers the pattern to the photosensitive layer on the inner wall of the via hole through optical imaging via an exposure and development process. Compared with traditional silk screen printing or electroplating hole filling processes, it can achieve micron-level line width and line spacing, solve the problem of fine composition of deep holes and small aperture inner walls, and provide a process basis for the embedded installation of miniaturized components.

[0141] In this embodiment, step S305 fills the vias with an insulating material (e.g., epoxy resin) to provide mechanical reinforcement, eliminate the internal cavity of the vias, and prevent component pins from shifting or breaking due to vibration. The insulating material also isolates contaminants such as moisture and dust, preventing oxidation and corrosion of the pads and pins, thereby extending the life of the printed circuit board. The surface smoothing process ensures that the vias are flush with the printed circuit board surface, preventing protruding structures from interfering with subsequent patch processing and improving processing compatibility.

[0142] This embodiment of the present application is suitable for designs where high-speed signals are differential lines. The DP and DN signal lines must maintain a certain coupling spacing, so when designing the capacitance within a via, consider a pair of differential line vias as a unit. First, drill a layer-change via, for example, an ellipse measuring 60 mils long and 30 mils wide. Electroplate the inner wall of the via with 1 mil of copper.

[0143] To more precisely etch the pad structure on the via's inner wall, a photosensitive layer is first applied to the via's inner wall. After exposure, development, and etching, the desired pad structure is exposed. Exposure involves aligning a mask with a circuit pattern with the photosensitive layer's inner wall and then irradiating it with ultraviolet light or other specific wavelengths. During exposure, transparent areas on the mask allow light to pass through and strike the photosensitive layer, where it undergoes a photochemical reaction, altering the properties of the photosensitive layer. During exposure, a reflector at the bottom of the via reflects light of a specific wavelength onto the via's inner wall. Adjusting the angle of the reflector ensures uniform illumination of the via's inner wall. After exposure, development involves removing the photosensitive layer from the exposed areas with a developer, revealing the pad structure. Following development, the copper outside the pad structure's pattern is etched away, leaving the desired pad structure.

[0144] Then print solder paste on the pad structure with a thickness of 2mil, assemble the capacitor, and after high-temperature reflow soldering, the capacitor and the circuits at both ends of the via are connected together. The structure diagram after soldering the capacitor in the via is as follows Figure 10 As shown in the figure, the capacitor pins are connected to pads etched into the sidewalls. The spacing between the DP and DN signals is always maintained at S, maximizing the coupling and impedance continuity of the differential signal lines, which helps improve the integrity of high-speed signals. After the capacitor assembly step is completed, the via slots are filled with resin. This prevents impurities from depositing inside the vias during later operation of the printed circuit board, causing signal problems and enhancing the reliability of the board.

[0145] The schematic diagram of the inner wall of the via groove after etching is as follows Figure 3 As shown. D, E, F, and G represent the pads for the TX coupling capacitors, measuring 0.3 x 0.2 mm, meaning MP = NQ = 0.3 mm and MN = PQ = 0.2 mm. D and F are the capacitor pads for the DP signal, with a spacing of 0.2 mm between them. E and G are the capacitor pads for the DN signal, with a spacing of 0.2 mm between them. The distance S between the DP and DN signal capacitors is 8 mils, the minimum spacing that can be soldered to a 0201 device. The width W of the DP and DN signal lines is calculated using impedance calculation software based on the target impedance value and the 8 mil differential line spacing.

[0146] This application improves the internal structure of the vias to achieve the integration of electrical components such as filter capacitors and signal layer switching vias, effectively reducing the layout and wiring space of the printed circuit board and significantly improving the circuit integration. This design not only helps to reduce the board area and production costs, but also improves the reliability and stability of the circuit through the following advantages, promoting the development of printed circuit boards towards high density and miniaturization:

[0147] The power filter capacitors, with pads on the inner walls of the vias, are positioned close to the chip pins. This allows for a more efficient buffer response when the power supply voltage fluctuates, effectively suppressing voltage ripple and maintaining power supply voltage stability. Furthermore, the shortened signal path enables the capacitors to more accurately filter high-frequency noise on the power line, reducing crosstalk interference from power supply noise on signal transmission, ensuring the integrity and accuracy of the power supply signal and providing a clean power supply environment for the chip.

[0148] For high-speed differential signal links, the integrated design of decoupling capacitors and signal layer-switching vias significantly reduces impedance discontinuities along the link. The sophisticated trace layout on the via sidewalls (such as differential signal pads with preset spacing and etched signal traces with controlled line widths) enables precise impedance matching, effectively reducing signal reflections and losses.

[0149] The fabrication process described in this application is highly compatible with existing printed circuit board (PCB) production lines. Standardized processes such as conductive layer deposition, photosensitive layer exposure and development, and etching are performed on the inner walls of the vias to integrate the sidewall pad structure with electrical components. This process eliminates the need for specialized equipment, maintains controllable processing costs, and offers a stable process flow with high replicability and engineering value. This provides a practical and feasible technical path for high-density board design and represents a significant innovation in PCB integration technology.

[0150] Through the organic combination of structural innovation and process optimization, the above technical solution achieves an excellent balance between space efficiency, signal integrity, reliability and manufacturing cost, laying a key technical foundation for the design of printed circuit boards for the next generation of high-performance electronic devices.

[0151] Based on the same inventive concept, the present application also provides an electronic device, comprising the printed circuit board in any of the above embodiments.

[0152] Since the principle of solving the problem of the electronic device is similar to that of the aforementioned printed circuit board, the embodiment of the electronic device can refer to the embodiment of the printed circuit board, and the repeated parts will be omitted.

[0153] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0154] Professionals may further appreciate that the modules and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0155] The above is a detailed introduction to the storage component provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only intended to help understand the method and core ideas of the present application. It should be pointed out that, for those skilled in the art, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A printed circuit board, characterized in that: include: A via hole; a pad structure is provided on the inner wall of the via hole; the pad structure includes an etched pad and an etched signal line; the etched pad is connected to the etched signal line; Electrical components; The pins of the electrical components are arranged in the via holes, and are electrically connected to the pad structures through solder.

2. The printed circuit board according to claim 1, wherein: The etched pads include positive differential signal pads and negative differential signal pads; The electrical component includes a first electrical component and a second electrical component; the pins of the first electrical component are electrically connected to the positive differential signal pads through solder; the pins of the second electrical component are electrically connected to the negative differential signal pads through solder.

3. The printed circuit board according to claim 2, wherein: The spacing between the positive differential signal pad and the negative differential signal pad is a preset spacing; the etched signal line includes a positive differential signal line and a negative differential signal line; the positive differential signal line is electrically connected to the positive differential signal pad; the negative differential signal line is electrically connected to the negative differential signal pad; The line widths of the positive differential signal line and the negative differential signal line are preset line widths.

4. The printed circuit board according to claim 1, wherein: Multiple groups of electrical components are arranged in the via holes; the pad structure includes multiple groups of etched pads; and each group of etched pads is electrically connected to each group of electrical components in a one-to-one correspondence.

5. The printed circuit board according to claim 4, wherein: The etched pads arranged relatively to each other on the inner wall of the via hole are staggered.

6. The printed circuit board according to claim 1, wherein: A ground signal line is also provided on the inner wall of the via hole.

7. The printed circuit board according to any one of claims 1 to 6, characterized in that: The electrical components include filter capacitors and / or impedance matching resistors.

8. The printed circuit board according to any one of claims 1 to 6, characterized in that: Insulating filling material is also provided in the via hole.

9. A method for preparing a printed circuit board, characterized in that: include: forming vias on a printed circuit board; A pad structure is formed on the inner wall of the via hole; the pad structure includes an etched pad and an etched signal line; the etched pad is connected to the etched signal line; Solder is formed on the pad structure, an electrical component is disposed in the via hole, and the pin of the electrical component is electrically connected to the pad structure through the solder.

10. The method for preparing a printed circuit board according to claim 9, wherein: The forming of a pad structure on the inner wall of the via hole comprises: forming a conductive layer on an inner wall of the via hole; forming a photosensitive layer on the conductive layer; exposing and developing the photosensitive layer to form a pad structure pattern; The conductive layer exposed by etching the pad structure pattern is formed to form the pad structure.

11. The method for preparing a printed circuit board according to claim 10, wherein: Exposing and developing the photosensitive layer to form a pad structure pattern includes: Exposure light is provided from above the via hole and is reflected by a reflector below the via hole to the photosensitive layer on the inner wall of the via hole.

12. The method for preparing a printed circuit board according to claim 10, wherein: The step of etching the conductive layer to expose the pad structure pattern to form the pad structure includes: Etching the conductive layer exposed by the pad structure pattern to form a plurality of groups of etched pads in the pad structure; Wherein, the etched pads arranged relatively to each other on the inner wall of the via hole are staggered.

13. The method for preparing a printed circuit board according to claim 10, wherein: When the exposing and developing the photosensitive layer to form a pad structure pattern, the method further includes: exposing and developing the photosensitive layer to form a ground signal line pattern; When the conductive layer exposed by etching the pad structure pattern is formed to form the pad structure, the method further includes: etching the conductive layer exposed by etching the ground signal line pattern to form a ground signal line.

14. The method for preparing a printed circuit board according to any one of claims 9 to 13, characterized in that: After forming solder on the pad structure, placing an electrical component in the via hole, and electrically connecting the pin of the electrical component to the pad structure through the solder, the method further includes: The via hole is filled with an insulating filling material.

15. A method for preparing a printed circuit board, characterized in that: include: forming vias on a printed circuit board; A preset mold is placed in the via hole, and glue is applied to the middle area of ​​the inner wall of the via hole using the preset mold to form an annular insulating layer; the outer contour of the preset mold contacts the inner wall of the annular insulating layer formed by glue application; and the outer contour of the preset mold is the same as the outer contour of the electrical component; Electroplating an inner wall of the via hole above the annular insulating layer to form a first electroplating pad, and forming a second electroplating pad on the inner wall of the via hole below the annular insulating layer; Solder is formed on the pad structure, the electrical component is disposed in the via hole, and the pin of the electrical component is electrically connected to the pad structure through the solder.

16. An electronic device, characterized in that: The method comprises the printed circuit board according to any one of claims 1 to 8.

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