Apparatus and method for coupling multiple semiconductor devices

Abstract

Apparatus and methods for coupling a plurality of semiconductor devices are disclosed. Terminals of a plurality of semiconductor devices (e.g., die pads) may be coupled in a daisy chain manner through a conductive structure that couples one or more terminals of the semiconductor devices to two conductive bond pads. The conductive structure may be included in a redistribution layer (RDL) structure. In some embodiments of the present disclosure, the RDL structure may be 'U'-shaped. Each end of the "U" shape may be coupled to a respective one of the two conductive bond pads, and the terminal of the semiconductor device may be coupled to the RDL structure. The conductive bond pads of a semiconductor device may be coupled to conductive bond pads of other semiconductor devices through conductors (e.g., bond wires). Accordingly, the terminals of the semiconductor device may be coupled in a daisy chain manner through the RDL structures, conductive bond pads, and conductors.

Description

[0001] Relevant information on divisional applications

[0002] This application is a divisional application. Its parent application is a patent application for an invention titled "Device and Method for Coupling Multiple Semiconductor Devices" with an application date of March 1, 2021, an application number of 202110225352.7. Technical Field

[0003] This application relates to semiconductors and, in particular, to devices and methods for coupling multiple semiconductor devices. Background Art

[0004] In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by vertically stacking dies and coupling the dies using through-silicon vias (TSVs) and / or wire bonds. Thus, 3D memories can also be referred to as "stacked memories." Compared to non-3D memories, 3D memories can provide greater memory capacity and / or higher bandwidth with less area increase. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and Master-Slave Memory (MSM), each of which can include multiple dynamic random access memory (DRAM) dies coupled to each other in a stack.

[0005] Memory devices can be coupled to an external circuit that provides command signals, address signals, and data signals to the stacked dies to access the memory. The stacked dies are typically coupled to the external circuit in parallel. Thus, when providing signals to the stacked dies, the external circuit drives the signals against a potentially large load of all the dies. The heavy load presented by the stacked dies can reduce signal integrity (SI), which may cause data to be latched incorrectly at the receiver and / or result in increased power consumption. In some applications, reduced SI and increased power may be unacceptable. Summary of the Invention

[0006] In one aspect, the present application relates to a device that includes: a plurality of semiconductor devices, the plurality of semiconductor devices including a first semiconductor device, a second semiconductor device, and a third semiconductor device, each semiconductor device of the plurality of semiconductor devices including a die pad coupled to at least one circuit of the corresponding semiconductor device, and further including a redistribution layer structure coupled to the die pad and further coupled to a first bond pad and a second bond pad, wherein the second bond pad of the first semiconductor device is coupled to the first bond pad of the second semiconductor device, and the second bond pad of the second semiconductor device is coupled to the first bond pad of the third semiconductor device.

[0007] In another aspect, the present application relates to a multi-die device, comprising: a substrate including conductive signal lines; a stack of semiconductor devices attached to the substrate, each semiconductor device in the stack including a terminal and a redistribution layer structure coupled to the terminal, and wherein the terminals of the semiconductor devices in the stack are coupled together in a daisy chain through the redistribution layer structure; and a circuit attached to the substrate and coupled to a first semiconductor device in the stack of semiconductor devices through the conductive signal lines.

[0008] In another aspect, the present application relates to a device, comprising: a memory array configured to store data; a terminal; an input / output circuit configured to receive data from the memory array and provide read data, and receive write data to be stored in the memory array; a command and address input circuit configured to receive command and address signals; a first bonding pad and a second bonding pad; and a U-shaped conductive structure coupled to the terminal and including a first portion extending between the terminal and the first bonding pad and coupled to the terminal and the first bonding pad, and further including a second portion extending between the terminal and the second bonding pad and coupled to the terminal and the second bonding pad.

[0009] In another aspect, the present application relates to a method, comprising: coupling a bonding pad of a first semiconductor device to a first U-shaped conductive structure; coupling a bonding pad of a second semiconductor device to a second U-shaped conductive structure; coupling a bonding pad of a third semiconductor device to a third U-shaped conductive structure; coupling a second portion of the first U-shaped conductive structure to a first portion of the second U-shaped conductive structure; and coupling a second portion of the second U-shaped conductive structure to a first portion of the third U-shaped conductive structure, wherein a first portion of the first U-shaped conductive structure is coupled to a circuit, and wherein a second portion of the third U-shaped conductive structure is coupled to a fourth semiconductor device. Description of the Drawings

[0010] Figure 1 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 2 is a diagram showing a multi-die device according to an embodiment of the present disclosure.

[0012] Figure 3 is a layout diagram of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 4 A cross-sectional view of a conductive structure of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 5 A schematic diagram of semiconductor devices coupled together according to an embodiment of the present disclosure.

[0015] Figure 6 A diagram showing an RDL structure for coupling terminals of a semiconductor device to bonding pads according to an embodiment of the present disclosure.

[0016] Figure 7 A plan view of bonding pads of semiconductor devices coupled together according to an embodiment of the present disclosure. Detailed Description

[0017] Devices and methods for coupling semiconductor devices are disclosed. Multiple semiconductor device terminals can be coupled in a daisy chain manner by coupling one or more terminals of a semiconductor device to a conductive structure of two conductive bonding pads. The terminals can be die pads of the semiconductor device. The conductive structure can be included in a redistribution layer (RDL) structure. In some embodiments of the present disclosure, the RDL structure can be "U"-shaped. Each end of the "U" shape can be coupled to a corresponding one of the two conductive bonding pads, and the terminals of the semiconductor device can be coupled to the RDL structure. The conductive bonding pads of the semiconductor device can be coupled to the conductive bonding pads of other semiconductor devices through conductors (such as bonding wires). Thus, the terminals of the semiconductor device can be coupled in a daisy chain manner through the RDL structure, the conductive bonding pads, and the conductors.

[0018] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the accompanying drawings, which illustrate specific aspects and embodiments of the present disclosure by way of illustration. The detailed description includes sufficient details for those skilled in the art to practice the embodiments of the present disclosure. Without departing from the scope of the present disclosure, other embodiments can be utilized, and structural, logical, and electrical changes can be made. The various embodiments disclosed herein do not necessarily exclude each other, as some disclosed embodiments can be combined with one or more other disclosed embodiments to form new embodiments.

[0019] Figure 1 A block diagram of a semiconductor device 110 according to an embodiment of the present disclosure. For example, in some embodiments, the semiconductor device 110 can be a memory integrated into a single semiconductor chip (e.g., a semiconductor die). Example memories can include volatile memories such as dynamic random access memory (DRAM) and static random access memory (SRAM), as well as non-volatile memories such as flash memory, resistive memory, and ferroelectric memory, or any combination thereof.

[0020] The semiconductor device 10 includes a memory cell array 111. The memory cell array 111 includes a plurality of banks, each bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by a row decoder / driver 112, and selection of the bit lines BL is performed by a column decoder / driver 113. A sense amplifier 118 is coupled to a corresponding bit line BL and connected to a local I / O line pair LIOT / B. The local I / O line pair LIOT / B is connected to a main I / O line pair MIOT / B through a transmission gate TG 119 serving as a switch.

[0021] The semiconductor device 110 includes a plurality of terminals. In some embodiments of the present disclosure, the terminals may be die pads. The plurality of terminals include command and address terminals 121, clock terminals 123 and 123', data terminals 124, data strobe terminals 124', power supply terminals 125 and 126. The data terminals 124 may be coupled to an output buffer of the input / output circuit 117 for a read operation. Alternatively, the data terminals 124 may be coupled to an input buffer of the input / output circuit 117 for write access to the memory in response to a data strobe signal DQS provided at the data strobe terminals 124'.

[0022] The command and address terminals 121 are supplied with a command and address signal CA, which includes a command address and a memory address. The address provided to the command and address terminals 121 is transmitted to an address decoder 132 through a command / address input circuit 131. The address decoder 132 receives the address and supplies a decoded row address to the row decoder / driver 112 and a decoded column address to the column decoder / driver 113. The address decoder 132 also receives a group address and provides a group address signal to the row decoder / driver 112 and / or the column decoder / driver 113. In the self-refresh mode, a self-refresh circuit 138 may provide a row address to the row decoder / driver 112 for a self-refresh operation.

[0023] The command provided to the command and address terminals 121 is provided to a command decoder 134 through the command / address input circuit 131. The command decoder 134 decodes the command and provides the decoded command to an internal control signal generator 137. In response to the decoded command from the command decoder 134, the internal control signal generator 137 may generate various internal command signals. For example, the internal commands may include a row command signal for selecting a word line and a column command signal for selecting a bit line, such as a read command or a write command, etc.

[0024] Therefore, when an activation command is issued and a row address is supplied in a timely manner with the activation command, and a column address is supplied in a timely manner with a read command, read data is read from the memory cell MC specified by the row address and the column address in the memory cell array 111. The read data DQ is output from the data terminal 124 through the read / write amplifier 115 and the input / output circuit 117. Similarly, when an activation command is issued and a row address is supplied in a timely manner with the activation command, and a column address is supplied in a timely manner with a write command, write data DQ supplied to the data terminal 124 is supplied to the memory cell array 111 through the input / output circuit 117 and the read / write amplifier 115, and the DQ is written into the memory cell MC specified by the row address and the column address.

[0025] The clock terminals 123 are respectively supplied with the clock signals CK_t and CK_c, and the clock terminal 123' is supplied with the data clock signals WCK_t and WCK_c. The clock input circuit 135 receives the clock signals CK_t and CK_c and WCK_t and WCK_c, and generates an internal clock signal ICLK. The internal clock signal ICLK may include an internal clock signal based on the clock signals CK_t and CK_c and / or an internal clock signal based on the data clock signals WCK_t and WCK_c. Some or all of the internal clock signal ICLK is supplied to the internal clock and timing generator 136, which in response generates a phase-controlled internal clock signal LCLK. Although not limited thereto, the internal clock and timing generator 136 may include a DLL circuit. The phase-controlled internal clock signal LCLK may be supplied to the input and / or output circuit 117 and used for the timing of data input and output. The internal clock and timing generator 136 may further generate various other internal clock signals for various memory operations.

[0026] Power potentials VDD and VSS are supplied to the power supply terminal 125. These power potentials VDD and VSS are supplied to the power supply circuit 139. The power supply circuit 139 may generate various internal potentials, for example, VPP, VOD, VARY, VPERI, etc. The internal potential VPP is mainly used in the row decoder / driver 112, the internal potentials VOD and VARY are mainly used in the sense amplifiers 118 included in the memory cell array 111, and the internal potential VPERI is used in many other circuit blocks. Power potentials VDDQ and VSSQ are supplied to the power supply terminal 126. These power potentials VDDQ and VSSQ are supplied to the input / output circuit 117. The power potentials VDDQ and VSSQ may respectively be the same potentials as the power potentials VDD and VSS supplied to the power supply terminal 125. However, the power potentials VDDQ and VSSQ may be used in the input / output circuit 117 such that power noise generated by the input / output circuit 117 does not propagate to other circuit blocks.

[0027] Figure 2 FIG. is a diagram showing a multi-die device 200 in accordance with an embodiment of the present disclosure. The multi-die device 200 may include a stack 215 of semiconductor devices 220. Embodiments of the present disclosure are not limited to Figure 2 the specific number of semiconductor devices 220 included in the stack 215 shown in. In some embodiments of the present disclosure, each of the semiconductor devices 220 includes Figure 1 semiconductor device 110.

[0028] The semiconductor devices 220 may be stacked in a staggered manner, thereby providing a "shingle-stack" configuration for the stack 215. The semiconductor devices 220 may be attached to each other. In some embodiments of the present disclosure, the semiconductor devices 220 are attached to each other by an adhesive epoxy. The semiconductor devices 220 are offset from each other to allow the edge regions of the semiconductor devices 220 to be exposed. The exposed edge regions may include bond pads to which conductors 225 may be coupled. In some embodiments of the present disclosure, the bond pads in the edge regions may be conductive pads. The bond pads may be coupled to the terminals of the respective semiconductor devices 220. In some embodiments of the present disclosure, the conductors 225 are bonding wires.

[0029] The stack 215 may be attached to a substrate 230. In some embodiments of the present disclosure, the stack may be attached to the substrate 230 by an adhesive epoxy. The substrate 230 may include conductive signal lines for routing signals along the substrate, for example, to or from the semiconductor devices 220. Other circuits may also be attached to the substrate 230 and may also be coupled to the conductive signal lines. Thus, the circuits attached to the substrate 230 may be coupled to the semiconductor devices 220, for example, through the conductive signal lines of the substrate 230 and the conductors coupling the conductive signal lines and the bond pads to the semiconductor devices. Figure 2 An example circuit 235 attached to the substrate 230 and coupled to the semiconductor devices in the stack 215 is shown in. In some embodiments of the present disclosure, the circuit 235 may be a register clock driver (RCD). In such embodiments of the present disclosure, the RCD circuit receives and buffers signals provided to the multi-die device 200 and may provide signals to the semiconductor devices 220. Additional or alternative circuits may be included in the multi-die device 200 without departing from the scope of the present disclosure, and / or the circuit 235 may also be other circuits.

[0030] Figure 3 FIG. is a layout diagram of a semiconductor device 310 in accordance with an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device 310 includes Figure 1 semiconductor device 110. In some embodiments of the present disclosure, the semiconductor device 310 is included inFigure 2 in the semiconductor device 220 in the stack 215 shown in

[0031] The semiconductor device 310 may have edges 350a, 350b, 350c, and 350d that define the ends of the semiconductor device 310. The edges 350b and 350d may extend in a first direction 357a, and the edges 350a and 350c may extend in a second direction 357b that may be perpendicular to the first direction 357a. The semiconductor device 310 may include a pad formation region 351, a peripheral circuit region 352, and a memory cell array region 353 that includes memory cells, circuits, and signal lines such as sense amplifier circuits, address decoder circuits, data input / output lines, etc. The peripheral circuit region 352 may include various circuits and signal lines for performing various operations of the semiconductor device 310. For example, the peripheral circuit region 352 may include command and address input circuits, address and command decoders, clock circuits, power supply circuits, and input / output circuits. The peripheral circuit region 352 may also include terminals (e.g., as previously described for Figure 1 the semiconductor device 170) that are coupled to various circuits of the semiconductor device. The terminals may be, for example, die pads of the semiconductor device.

[0032] The pad formation region 351 may include a plurality of bonding pads 354 disposed along the edge 350a. The plurality of bonding pads 354 may be coupled to the terminals (e.g., die pads) of the semiconductor device and represent the external terminals of the semiconductor device 310. For example, the plurality of pads 354 may include data terminals, command and address terminals, clock terminals, and / or power supply terminals.

[0033] The circuits included in the memory cell array region 353 and / or the circuits of the peripheral circuit region 352 may be coupled to one or more of the bonding pads 354 included in the pad formation region 351. As previously described, the various circuits of the semiconductor device 300 may be coupled to the terminals (e.g., die pads). Conductive structures may be used to couple the terminals to one or more of the bonding pads 354. Thus, the circuits coupled to the terminals are also coupled to the bonding pads 354. The conductive structures may extend from the locations of the terminals included in the memory cell array region 353 and / or the peripheral circuit region 352 to the pad formation region 351. In some embodiments of the present disclosure, the conductive structures may include conductive redistribution layers (RDLs).

[0034] Figure 4 is a cross-sectional view of a conductive structure of a semiconductor device according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the conductive structures may be included in Figure 1 the semiconductor device 110 of Figure 2the semiconductor device 220 of the multi-die device 200, Figure 3 the semiconductor device 310, and / or any semiconductor device according to embodiments of the present disclosure. For example, in some embodiments of the present disclosure, the conductive structure may be included in Figures 1 - 3 the conductive redistribution layer (RDL) in one or more semiconductor devices of the semiconductor device.

[0035] The conductive structure 430 may couple the terminal 440 of the semiconductor device to the bonding pad 420. In some embodiments of the present disclosure, the terminal 440 may be a die pad. The terminal 440 may be coupled to one or more circuits 445 of the semiconductor device. Thus, the bonding pad 420 may be coupled to the circuit 445 through the conductive structure 430 and the terminal 440. In some embodiments of the present disclosure, the circuit 445 may be, for example, a circuit included in a memory cell array region (e.g., Figure 3 the memory cell array region 352). In some embodiments of the present disclosure, the circuit 445 may be, for example, a circuit included in a peripheral circuit region (e.g., Figure 3 the peripheral circuit region 354). The circuit 445 may be used to perform various operations of the semiconductor device. In some embodiments of the present disclosure, the circuit 445 may include a command and address input circuit, an address and command decoder, a clock circuit, a power supply circuit, an input / output circuit, and other circuits.

[0036] The bonding pad 420, the conductive structure 430, the terminal 440, and the circuit 445 of the semiconductor device may be formed of a semiconductor structure. The semiconductor structure may include a conductive layer, a conductive via, an insulating intermediate layer, etc. The terminal 440 may be coupled to the circuit 445 through, for example, a metal layer and / or a conductive via. The conductive structure 430 may be disposed on one or more insulating intermediate layers. As previously described, the conductive structure 430 may be further coupled to the bonding pad 420. The conductive structure 430 extends from the terminal 440 to the bonding pad 420 such that the bonding pad 420 and the circuit terminal 440 may be coupled together. Thus, the circuit 445 coupled to the terminal 440 may be externally accessible through the bonding pad 420. The bonding pad 420 may be exposed through an opening 425 in the passivation layer 435. In some embodiments of the present disclosure, the passivation layer 435 may be a polyimide material.

[0037] In some embodiments of the present disclosure, the conductive structure 430 can be coupled to a terminal 440 of a semiconductor device (e.g., a die pad of the semiconductor device) to provide a bonding pad 420 for coupling to the terminal 440 at a different location. For example, the terminal 440 can represent a die pad that is typically positioned in a peripheral circuit region along a central region of the semiconductor device, and the conductive structure 430 can couple the die pad in the central region to the bonding pad 420 positioned along an edge of the semiconductor device. The bonding pads 420 along the edge can be more conveniently positioned and provide a coupling to the circuit 445 of the semiconductor device, that is, through the conductive structure 430 and the terminal 440.

[0038] Figure 5 is a schematic diagram of semiconductor devices coupled together according to an embodiment of the present disclosure. In some embodiments of the present disclosure, Figure 5 the semiconductor device can be included in the semiconductor device of a multi-die device (e.g., Figure 2 the semiconductor device 220 of the multi-die device 200). In some embodiments of the present disclosure, Figure 5 each semiconductor device in the semiconductor device can include Figure 1 the semiconductor device 110, and can be a memory device.

[0039] The semiconductor devices 510(1)-510(10) are coupled together by conductive structures 520(1)-520(20), which can be included in a redistribution layer (RDL). The conductive structures 520 are Figure 5 represented as signal lines in. The conductive structures can couple the die pads 515 (e.g., terminals) of the semiconductor devices 510 to the bonding pads 525 of the corresponding semiconductor devices. The bonding pads 525 of each semiconductor device in the semiconductor devices 510 can be coupled together by corresponding conductors BW(1)-BW(9). In some embodiments of the present disclosure, the conductors BW can be bonding wires.

[0040] The circuit 540 can be coupled to the semiconductor device 510. For example, the circuit 540 is coupled to the semiconductor device 510(1) through the conductive signal line 545 and the conductor BW(0), and further through the bonding pad 525(1) and the conductive structure 520(1), which is coupled to the die pad 515 of the semiconductor device 510(1). In some embodiments of the present disclosure, the circuit 540 can be a register clock driver (RCD) attached to a substrate including the conductive signal line 545, and the conductor BW(0) can be a bonding wire. For example, in some embodiments of the present disclosure, the circuit 540 and the conductive signal line 545 can represent the circuit 235 and the conductive signal line included in the substrate 230, and the semiconductor device 510(1) can represent Figure 2The semiconductor device 220 in the stack 215.

[0041] In some embodiments of the present disclosure, two bonding pads 525 and two conductive structures 520 can be coupled to one die pad 515 of a semiconductor device. For example, the die pad 515(1) of the semiconductor device 510(1) is coupled to the bonding pads 525(1) and 525(2) through the conductive structures 520(1) and 520(2), respectively. Similarly, the die pad 515(2) of the semiconductor device 510(2) is coupled to the bonding pads 525(3) and 525(4) through the conductive structures 520(3) and 520(4), respectively; the die pad 515(3) of the semiconductor device 510(3) is coupled to the bonding pads 525(5) and 525(6) through the conductive structures 520(5) and 520(6), respectively; and so on.

[0042] In some embodiments of the present disclosure, the two conductive structures 520 coupled to the die pad 515 of the semiconductor device 510 can represent a "U"-shaped RDL structure. The "U"-shaped RDL structure can include two branch portions. Each of the branch portions has a first end coupled to the first end of the other branch portion, and each of the branch portions has a second end opposite to the first end. The second end of each branch portion can be coupled to a corresponding bonding pad. The first ends of the branch portions coupled together can represent the closed end of the RDL structure, and the second ends of the two branch portions opposite to the first end can represent the open end of the RDL structure. For example, referring to Figure 5 , the conductive structures 520(1) and 520(2) represent the branch portions closest to the die pad 515 of the semiconductor device 510(1) with the first ends coupled together. The second ends of the branch portions are closest to the bonding pads 525(1) and 525(2). The die pad of the semiconductor device can be coupled to any part of the RDL structure. In some embodiments of the present disclosure, the die pad of the semiconductor device can be coupled to the closed end of the RDL structure.

[0043] The semiconductor devices 510 can be coupled together in a daisy chain fashion through an RDL structure (e.g., conductive structure 520), bond pads 525, and conductors BW. For example, semiconductor devices 510(1)-510(3) can be coupled together in a daisy chain starting from bond pad 525(1) as follows: Bond pad 525(1) is coupled to die pad 515(1) of semiconductor device 510(1) through conductive structure 520(1); Die pad 515(1) is coupled to bond pad 525(2) through conductive structure 520(2); Bond pad 525(2) is coupled to bond pad 525(3) through conductor BW(1); Bond pad 525(3) is coupled to die pad 515(2) of semiconductor device 510(2) through conductive structure 520(3); Die pad 515(2) is coupled to bond pad 525(4) through conductive structure 520(4); Bond pad 525(4) is coupled to bond pad 525(5) through conductor BW(2); Bond pad 525(5) is coupled to die pad 515(3) of semiconductor device 510(3) through conductive structure 520(5). Similarly, semiconductor devices 510(4)-510(10) are also coupled to each other in a daisy chain fashion and are coupled to semiconductor devices 510(1)-510(3).

[0044] Compared to a parallel coupling of semiconductor devices 510, a daisy chain coupling can present a lower load to a circuit (e.g., circuit 540 (e.g., RCD)) coupled to the semiconductor devices 510. For example, with a parallel coupling of stacked devices, the load presented to the circuit can include the loads of all the devices in the stack. In contrast, with a daisy chain (e.g., series) coupling of stacked devices, the load presented to the circuit is generated by the first circuit in the chain of semiconductor dies, followed by the distributed loads of each subsequent circuit. This electrical distribution results in an effective reduction in the load observed at frequencies higher than those of a parallel configuration. U-turn RDL can be used to implement a true daisy chain. In the absence of using U-turn RDL, there can be long electrical stubs (from bond pads to die pads) that cause reflections and degrade signal integrity. However, by using U-turn RDL, the "branches" of the RDL no longer form stubs but rather a series path without parallel segments. Such an arrangement can be beneficial for signal integrity. Thus, it may be advantageous to have a daisy chain coupling as provided by one or more embodiments of the present disclosure.

[0045] Figure 5A semiconductor device 510 having a die pad 515 (e.g., a terminal) is shown. However, the semiconductor device 510 may have additional die pads. The additional die pads may also be coupled to the bond pads through conductive structures, for example, in a daisy-chain manner, and coupled to the bond pads through conductors. In some embodiments of the present disclosure, some of the die pads in each semiconductor device are not coupled to other semiconductor devices in a daisy-chain manner, while other die pads in the semiconductor device are coupled in a daisy-chain manner. For example, some of the die pads in each semiconductor device may be coupled in parallel to corresponding die pads of another semiconductor device in the semiconductor device, and some of the die pads in each semiconductor device may be coupled in a daisy-chain form (e.g., serially coupled) to corresponding die pads of another semiconductor device in the semiconductor device. In some embodiments of the present disclosure, the data terminals and / or command and address terminals of the semiconductor device may be coupled in a daisy-chain manner.

[0046] Figure 6 FIG. is a diagram showing an RDL structure that couples terminals of a semiconductor device to bond pads according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the RDL structure may be included in any of the semiconductor devices described previously with reference to Figures 1 - 5 any of the semiconductor devices. For example, the RDL structure may be included in Figure 3 the semiconductor device 310 to couple the bond pad 354 to a terminal included in the peripheral circuit region.

[0047] The bond pads 610(1)-610(6) are coupled to at least one of the die pads 620(1)-620(3) through the RDL structures 630(1)-630(3). For example, at least two bond pads 610 are coupled to at least one die pad 620 through corresponding RDL structures 630. In Figure 6 an example, the bond pads 610(1) and 610(2) are coupled to the die pad 620(1) through the RDL structure 630(1); the bond pads 610(3) and 610(4) are coupled to the die pad 620(2) through the RDL structure 630(2); and the bond pads 610(5) and 610(6) are coupled to the die pad 620(3) through the RDL structure 630(3). In some embodiments of the present disclosure, the RDL structure 630 may have a "U" shape that couples two bond pads 610 to one die pad 620.

[0048] The RDL structure 630(1) may include a first portion 632(1) extending from a bonding pad 610(1) (e.g., a first bonding pad) to a die pad 620(1), and may further include a second portion 634(1) extending from a bonding pad 610(2) (e.g., a second bonding pad) to the die pad 620(1). The portion 632(1) may include a conductive structure, and the portion 634(1) may include a conductive structure. In some embodiments of the present disclosure, each of the conductive structures may be included in the RDL. The first portion 632(1) and the second portion 634(1) are coupled to the die pad 620(1). In some embodiments of the present disclosure, the first portion 632(1) and the second portion 634(1) may be coupled to the die pad 620(1) through a third portion coupled to the first portion 632(1) and the second portion 634(1). For example, in Figure 6 , the third portion 636(1) is coupled to the first portion 632(1) and the second portion 634(1), and is coupled to the die pad 620(1). The third portion 636(3) may be included in the RDL structure 630(1). In some embodiments of the present disclosure, the first portion 632(1) and the second portion 634(1) are coupled to the die pad 620 without a third portion. For example, the first portion and the second portion may be shaped to provide a coupling to the same die pad 620 without a third portion between the first bonding pad and the second bonding pad.

[0049] The RDL structures 630(2) and 630(3) may include corresponding first and second portions as previously described for the RDL structure 630(1), and the first and second portions are coupled to the corresponding die pads 620(2) and 620(3). Similarly, in some embodiments of the present disclosure, the RDL structures 630(2) and 630(3) may include corresponding third portions as previously described for the RDL structure 630(1).

[0050] The RDL structure 630 may be formed of a conductive material of one or more conductive layers. For example, in some embodiments of the present disclosure, the first and second portions of the RDL structure 630 may be formed of the same conductive layer. The third portion may be formed of the same conductive layer. In some embodiments of the present disclosure, one or more of the portions of the RDL layer may be formed of a conductive layer different from other portions. The portion itself may be formed of one or more conductive layers. The conductive structure may be formed of a conductive layer located below the bonding pad 610 and above the die pad 620.

[0051] The RDL structure 630 has been provided by way of example, and the embodiments of the present disclosure are not limited to Figure 6 the specific examples.

[0052] Figure 7 is a plan view of bonding pads of semiconductor devices coupled together according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device may be included in a multi-die device (e.g., Figure 2 the multi-die device 200).

[0053] The bonding pads 731-736 may be included in the pad formation regions of the respective semiconductor devices 710(1)-710(4). The bonding pad pairs may be coupled to the respective die pads of the semiconductor devices. For example, referring to the bonding pads 731(1)-736(1) of the semiconductor device 710(1), the bonding pads 731(1) and 732(1) of the bonding pad pair 721(1) may be coupled to the same die pad of the semiconductor device 710(1). Similarly, the bonding pads 733(1) and 734(1) of the bonding pad pair 722(1) may be coupled to another die pad of the semiconductor device 710(1), and the bonding pads 735(1) and 736(1) of the bonding pad pair 723(1) may be coupled to yet another die pad of the semiconductor device 710(1). The bonding pad pairs of the other semiconductor devices 710(2)-710(4) may also be coupled to the corresponding common die pads.

[0054] The bonding pad pairs may be coupled by conductive structures extending from the respective bonding pads to the same die pad. For example, the bonding pads 731(1) and 732(1) may be coupled by conductive structures extending from the respective bonding pads 731(1) and 732(1) to the same die pad. Similarly, the bonding pads 733(1) and 734(1) may be coupled by conductive structures extending from the respective bonding pads 733(1) and 734(1) to the same die pad. The conductive structures may be included in the RDL structure. In some embodiments of the present disclosure, a U-shaped RDL structure may be used to couple the bonding pads to the same die pad. For example, in some embodiments of the present disclosure, Figure 5 the conductive structures and RDL structures may be used. In some embodiments of the present disclosure, Figure 6 the conductive structures and RDL structures may be used.

[0055] The die pads of semiconductor devices 710(1)-710(4) can be coupled together in a daisy chain manner through the bonding pad pairs coupled to the respective die pads. For example, assume that die pad "A" is the die pad of semiconductor device 710(1) coupled to the bonding pad pair 721(1); die pad "B" is the die pad of semiconductor device 710(2) coupled to bonding pad pair 721(2); die pad "C" is the die pad of semiconductor device 710(3) coupled to bonding pad pair 721(3); and die pad "D" is the die pad of semiconductor device 710(4) coupled to bonding pad pair 721(4). Die pad A can be coupled to die pad B by coupling bonding pad 732(1) to bonding pad 731(2) by means of conductor BW1(1); die pad B can be coupled to die pad C by coupling bonding pad 732(2) to bonding pad 731(3) by means of conductor BW1(2); and die pad C can be coupled to die pad D by coupling bonding pad 732(3) to bonding pad 731(4) by means of conductor BW1(3). Thus, die pads A, B, C, and D can be coupled in a daisy chain manner.

[0056] The daisy chain of die pads A, B, C, and D can be further coupled to a circuit (e.g., an RCD attached to a substrate) through conductor BW1(0). For example, pad 731(1) can be coupled to a conductive signal line through BW1(0), and the conductive signal line can in turn be coupled to the circuit.

[0057] The daisy chain of die pads A, B, C, and D can also be further coupled to the die pads of other semiconductor devices (e.g., additional semiconductor devices in a multi-die stack) through conductor BW1(4). For example, bonding pad 732(4) can be coupled to the bonding pad of another semiconductor device through BW1(4), and the bonding pad can in turn be coupled to the die pad of the other semiconductor device.

[0058] Other die pads of semiconductor devices 710(1)-710(4) can be coupled together in a similar daisy-chain manner. For example, the die pads coupled to the bonding pad pairs 722(1), 722(2), 722(3), and 722(4) can be coupled in a daisy-chain manner as follows: bonding pad 734(1) is coupled to bonding pad 733(2) through conductor BW2(1); bonding pad 734(2) is coupled to bonding pad 733(3) through conductor BW2(2); bonding pad 734(3) is coupled to bonding pad 733(4) through conductor BW2(3). Similarly, the die pads coupled to the bonding pad pairs 723(1), 723(2), 723(3), and 723(4) can be coupled in a daisy-chain manner as follows: bonding pad 736(1) is coupled to bonding pad 735(2) through conductor BW3(1); bonding pad 736(2) is coupled to bonding pad 735(3) through conductor BW3(2); bonding pad 736(3) is coupled to bonding pad 735(4) through conductor BW3(3). Conductors BW2(0) and BW2(4) respectively coupled to bonding pads 733(1) and 734(4) can be used to couple the daisy-chain die pads to a circuit (e.g., an RCD) and other semiconductor devices (e.g., in a multi-die stack). Similarly, conductors BW3(0) and BW3(4) respectively coupled to bonding pads 735(1) and 736(4) can be used to couple the daisy-chain die pads to a circuit (e.g., an RCD) and other semiconductor devices (e.g., in a multi-die stack).

[0059] In Figure 7 the example of, six bonding pads 731-736 from each of the semiconductor devices 710(1)-710(4) are shown. The six bonding pads 731-736 are provided by way of example, and each of the semiconductor devices 710(1)-710(4) can include a greater or lesser number of bonding pads without departing from the scope of the present disclosure. Additionally, Figure 7 four semiconductor devices 710(1)-710(4) are shown. However, a greater or lesser number of semiconductor devices can be coupled together without departing from the scope of the present disclosure.

[0060] Some details have been described to provide a thorough understanding of the examples of the present disclosure. However, it will be clear to those skilled in the art that the examples of the present disclosure can be practiced without these specific details. In addition, the specific examples of the present disclosure described herein should not be construed as limiting the scope of the present disclosure to these specific examples. In other instances, well-known circuits, control signals, timing protocols, and software operations are not shown in detail to avoid unnecessarily obscuring the present disclosure. Additionally, terms such as "coupled" and "coupled to" mean that two components can be directly or indirectly electrically coupled. Indirect coupling may imply that the two components are coupled through one or more intermediate components.

[0061] Based on the foregoing, it should be understood that although specific embodiments of the present disclosure have been described herein for purposes of illustration, various modifications can be made without departing from the spirit and scope of the present disclosure. Accordingly, the scope of the present disclosure should not be limited by any of the specific embodiments described herein.

Claims

1. An apparatus, comprising: a memory array configured to store data; terminals; an input / output circuit configured to receive data from the memory array and provide read data, and receive write data to be stored in the memory array; a command and address input circuit configured to receive command and address signals; a first bonding pad and a second bonding pad; and a U-shaped conductive structure coupled to the terminals and including a first portion extending between and coupled to the terminals and the first bonding pad, and further including a second portion extending between and coupled to the terminals and the second bonding pad.

2. The apparatus according to claim 1, wherein the input / output circuit is coupled to the terminals and configured to provide the read data to the terminals and configured to receive the write data from the terminals.

3. The apparatus according to claim 1, wherein the command and address input circuit is coupled to the terminals and configured to receive command and address signals from the terminals.

4. The apparatus according to claim 1, wherein the U-shaped conductive structure further includes a third portion coupled to the first portion and the second portion and further coupled to the terminals.

5. The apparatus according to claim 1, wherein the terminals include die pads included in a peripheral circuit region.

6. The apparatus according to claim 1, wherein the first bonding pad and the second bonding pad are located at an edge, and the terminals are located in a region along a central region disposed between memory cell array regions of the memory array.

7. The apparatus according to claim 1, wherein the first bonding pad and the second bonding pad are coupled together by a conductor.

8. The apparatus according to claim 1, further comprising: a register clock driver circuit coupled to a conductive signal line coupled to the second bonding pad.

9. An apparatus, comprising: a volatile memory; a first redistribution layer structure coupled to the volatile memory; a second redistribution layer structure coupled to the volatile memory and coupled to the first redistribution layer structure at the same node; and a third redistribution layer structure serially coupled with the first redistribution layer structure.

10. The apparatus according to claim 9, further comprising: a plurality of bonding pads disposed between the first redistribution layer structure and the third redistribution layer structure.

11. The apparatus according to claim 10, wherein the plurality of bonding pads are located at an edge.

12. The apparatus according to claim 9, further comprising: die pads coupled to the volatile memory, wherein the volatile memory is coupled to the first redistribution layer structure and the second redistribution layer structure through the die pads.

13. The device according to claim 12, wherein the volatile memory includes a memory array, and wherein the die pad is positioned in a region along a central region disposed between the memory cell array regions of the memory array.

14. The device according to claim 9, further comprising: A conductive signal line serially coupled to the second redistribution layer structure.

15. The device according to claim 14, further comprising: One or more bonding pads interposed between the second redistribution layer structure and the conductive signal line.

16. The device according to claim 14, further comprising: A register clock driver circuit coupled to the conductive signal line.

17. A device comprising: A semiconductor device; A register clock driver circuit coupled to a conductive signal line; And A portion of a series path of a redistribution layer structure and a bonding pad, the portion being coupled between the semiconductor device and the conductive signal line.

18. The device according to claim 17, wherein the series path extends beyond the portion of the series path between the semiconductor device and the conductive signal line through the semiconductor device, and wherein the die pad of the semiconductor device is coupled to two redistribution layer structures of the series path of the redistribution layer structure at the same node.

19. The device according to claim 18, wherein the semiconductor device includes a memory array, and wherein the die pad is positioned in a region along a central region disposed between the memory cell array regions of the memory array.

20. The device according to claim 17, wherein the series path of the redistribution layer structure and the bonding pad includes a repeating pattern of two bonding pads followed by two redistribution layer structures along the series path.

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