A bipolar transistor and a method for manufacturing the same

Abstract

The present application provides a bipolar transistor and a manufacturing method thereof, wherein the bipolar transistor includes an emitter region, a base region, a collector region, a first target trench, a second target trench, an emitter, a base and a collector, wherein the emitter region, the base region and the collector region are arranged vertically in sequence, the base region is located above the collector region, the emitter region is located above the base region, the sidewalls of the first target trench are provided with oxide and polysilicon is deposited in the trench, the bottom polysilicon of the first target trench is in contact with the base region, the second target trench is provided on one side of the first target trench, the sidewalls of the second target trench are provided with oxide and polysilicon is deposited in the trench, the bottom polysilicon of the second target trench is in contact with the collector region, the base is provided on the polysilicon on the surface of the first target trench, the collector is provided on the polysilicon on the surface of the second target trench, and the emitter is provided on the surface of the emitter region on the other side of the first target trench.

Description

Technical Field

[0001] The present application relates to the technical field of transistor manufacturing, and in particular to a bipolar transistor and a manufacturing method thereof. Background Art

[0002] Bipolar transistors (BJTs) are current-steering devices in which both charge carriers (electrons and holes) function simultaneously. They are commonly used in current amplification, power amplification, and high-speed circuits. Conventional bipolar transistors, etched on the wafer plane, have a large planar dimension, resulting in low integration density and high cost. Summary of the Invention

[0003] In view of this, the purpose of the present application is to provide at least a bipolar transistor and a manufacturing method thereof, by arranging the emitter region, the base region and the collector region in sequence in the longitudinal direction, and setting a first target trench and a second target trench therein, the inner walls of the first target trench and the second target trench are both provided with oxide and polysilicon is deposited in the trenches, and the bottom polysilicon of the first target trench directly contacts the base region, and the bottom polysilicon of the second target trench directly contacts the collector region, a base is set on the surface polysilicon of the first target trench, a collector is set on the surface polysilicon of the second target trench, a collector is set on the surface of the emitter region, and the base is set between the emitter and the collector, so as to increase the electron isolation capability by arranging the regions longitudinally and adding oxide in the first target trench and the second target trench, thereby solving the technical problem in the prior art that the electrodes of the bipolar transistor need to be separated by a certain distance in order to maintain the electron isolation capability, resulting in a large planar size and low integration, thereby achieving the technical effect of reducing the planar size and increasing the integration.

[0004] This application mainly includes the following aspects:

[0005] In a first aspect, an embodiment of the present application provides a bipolar transistor, comprising an emitter region, a base region, a collector region, a first target trench, a second target trench, an emitter, a base and a collector, wherein the emitter region, the base region and the collector region are arranged vertically in sequence, the base region is located above the collector region, the emitter region is located above the base region, the sidewalls of the first target trench are provided with oxide and polysilicon is deposited in the trench, the bottom polysilicon of the first target trench is in contact with the base region, the second target trench is provided on one side of the first target trench, the sidewalls of the second target trench are provided with oxide and polysilicon is deposited in the trench, the bottom polysilicon of the second target trench is in contact with the collector region, the base is provided on the polysilicon on the surface of the first target trench, the collector is provided on the polysilicon on the surface of the second target trench, and the emitter is provided on the surface of the emitter region on the other side of the first target trench.

[0006] Optionally, the bipolar transistor also includes a gate and a third target trench, the gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages, wherein the third target trench is arranged on the other side of the first target trench, the sidewalls and bottom of the third target trench are provided with oxide and polysilicon is deposited in the trench, the gate is arranged on the polysilicon on the surface of the third target trench, and the emitter is arranged between the gate and the base.

[0007] In a second aspect, an embodiment of the present application further provides a method for manufacturing a bipolar transistor, the method being used to manufacture a bipolar transistor as described in the first aspect or any possible embodiment of the first aspect, wherein the method comprises: etching a first initial trench on an initial substrate, and depositing oxide in the first initial trench, the initial substrate comprising a collector region and a base region located above the collector region, the bottom of the first initial trench being located in the base region; after etching away the bottom oxide of the first initial trench, filling the trench by depositing polysilicon to obtain a first target trench corresponding to the first initial trench; etching a second initial trench on one side of the first target trench, and depositing oxide in the first initial trench. Oxide is deposited in the second initial trench, the bottom of the second initial trench is in the collector region, and one side of the first target trench is located in a transistor arrangement direction perpendicular to the etching direction; after etching away the bottom oxide of the second initial trench, the trench is filled with polysilicon deposition to obtain a second target trench corresponding to the second initial trench; an emitter region is formed on the surface of the base region after the target trench is generated, and the emitter region does not cover each target trench; a base is formed on the polysilicon on the surface of the first target trench, a collector is formed on the polysilicon on the surface of the second target trench, and an emitter is formed on the emitter region on the other side of the first target trench, so as to prepare the bipolar transistor.

[0008] Optionally, the method also includes: simultaneously etching the second initial trench and the third initial trench on both sides of the first target trench, and depositing oxide in the third initial trench, the bottom of the third initial trench is in the collector region, and the critical dimension of the third initial trench is smaller than the critical dimension of the second initial trench; filling the trench by polysilicon deposition to obtain a third target trench corresponding to the third initial trench; forming a gate on the polysilicon on the surface of the third target trench, and the gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages.

[0009] Optionally, the initial substrate is formed by: forming a collector region on a P-type silicon substrate; forming a P-type silicon epitaxial layer on the collector region by epitaxial growth, and then forming a base region on the P-type silicon epitaxial layer to obtain the initial substrate.

[0010] Optionally, after filling the trench by depositing polysilicon to obtain a first target trench corresponding to the first initial trench, the method further includes: removing oxide and polysilicon outside the first target trench so that the portion of the surface of the initial substrate other than the first target trench becomes the surface of the base region.

[0011] Optionally, before forming an emitter region on the surface of the base region after generating the target trench, the method further includes: removing oxide and polysilicon outside the second target trench and the third target trench so that the portion of the surface of the initial substrate other than the target trenches is the surface of the base region.

[0012] Optionally, the emitter region, the collector region and the base region are obtained by performing photolithography and ion implantation respectively according to the type of the bipolar transistor.

[0013] Optionally, for each initial trench, the top width of the initial trench is greater than or equal to the bottom width, and the angle between the trench side and the trench top plane is limited to a preset angle range, the thickness of the oxide deposited in the initial trench is limited to a thickness that does not fill the trench, and the trench side is used to indicate the edge formed by connecting the top and bottom of the same side; and / or, the second initial trench and the third initial trench have the same depth.

[0014] Optionally, the method further comprises: forming an interlayer dielectric layer on the emitter region after forming the base, the collector, the emitter and the gate, and performing grinding.

[0015] An embodiment of the present application provides a bipolar transistor and a manufacturing method thereof, wherein the bipolar transistor includes an emitter region, a base region, a collector region, a first target trench, a second target trench, an emitter, a base and a collector, wherein the emitter region, the base region and the collector region are arranged vertically in sequence, the base region is located above the collector region, the emitter region is located above the base region, the sidewalls of the first target trench are provided with oxide and polysilicon is deposited in the trench, the bottom polysilicon of the first target trench is in contact with the base region, the second target trench is provided on one side of the first target trench, the sidewalls of the second target trench are provided with oxide and polysilicon is deposited in the trench, the bottom polysilicon of the second target trench is in contact with the collector region, the base is provided on the polysilicon on the surface of the first target trench, the collector is provided on the polysilicon on the surface of the second target trench, and the emitter is provided on the surface of the emitter region on the other side of the first target trench. The emitter region, the base region and the collector region are arranged in sequence in a longitudinal direction, and a first target trench and a second target trench are provided therein, the inner walls of the first target trench and the second target trench are provided with oxide and polysilicon is deposited in the trenches, and the bottom polysilicon of the first target trench directly contacts the base region, and the bottom polysilicon of the second target trench directly contacts the collector region, a base is provided on the surface polysilicon of the first target trench, a collector is provided on the surface polysilicon of the second target trench, a collector is provided on the surface of the emitter region, and the base is provided between the emitter and the collector, so as to increase the electron isolation capability by arranging the regions longitudinally and adding oxide in the first target trench and the second target trench, thereby solving the technical problem in the prior art that a certain distance needs to be kept between the electrodes of the bipolar transistor in order to maintain the electron isolation capability, resulting in a larger planar size and lower integration, thereby achieving the technical effect of reducing the planar size and increasing the integration.

[0016] In order to make the above-mentioned objects, features and advantages of the present application more obvious and easy to understand, preferred embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 A flow chart of a method for manufacturing a bipolar transistor provided in an embodiment of the present application is shown.

[0019] Figure 2A schematic diagram of an initial substrate provided in an embodiment of the present application is shown.

[0020] Figure 3 A schematic diagram of the first initial trench provided in an embodiment of the present application is shown.

[0021] Figure 4 A schematic diagram of a target groove provided in an embodiment of the present application is shown.

[0022] Figure 5 A schematic diagram of the emission area provided in an embodiment of the present application is shown.

[0023] Figure 6 A schematic diagram of a bipolar transistor provided in an embodiment of the present application is shown.

[0024] Figure 7 A schematic diagram showing the electric field strength of the bipolar transistor provided in an embodiment of the present application is shown.

[0025] Figure 8 A schematic diagram showing the potential of a bipolar transistor provided by an embodiment of the present application is shown.

[0026] Figure 9 A schematic diagram showing the current density of the bipolar transistor provided in an embodiment of the present application is shown.

[0027] Figure 10 A curve diagram showing the relationship between the base current and the collector current of the bipolar transistor provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0028] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It should be understood that the drawings in the present application only serve the purpose of illustration and description and are not used to limit the scope of protection of the present application. In addition, it should be understood that the schematic drawings are not drawn to scale. The flowcharts used in this application illustrate the operations implemented according to some embodiments of the present application. It should be understood that the operations of the flowcharts can be implemented out of sequence, and steps without logical context can be reversed or implemented simultaneously. In addition, those skilled in the art, under the guidance of the contents of this application, can add one or more other operations to the flowchart, or remove one or more operations from the flowchart.

[0029] In addition, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. The components of the embodiments of the present application generally described and shown in the drawings here can be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0030] The BCD process (Bipolar-CMOS-DMOS) is a monolithic integrated circuit manufacturing process that combines bipolar transistors, CMOS (complementary metal oxide semiconductor), and DMOS (double diffused metal oxide semiconductor) on a single chip. Bipolar transistors are favored due to their simple manufacturing process, low manufacturing cost, and high yield. Furthermore, they offer advantages in circuit performance, such as high speed, high transconductance, low noise, high analog accuracy, and strong current drive capability. Bipolar transistors are current-steering devices, and both charge carriers (electrons and holes) operate simultaneously. They are commonly used in current amplification, power amplification, and high-speed circuits. However, conventional bipolar transistors currently have large planar dimensions and low integration density, which affects manufacturing costs.

[0031] Based on this, an embodiment of the present application provides a bipolar transistor and a manufacturing method thereof, wherein an emitter region, a base region, and a collector region are arranged in sequence in a longitudinal direction, and a first target trench and a second target trench are provided therein, the inner walls of the first target trench and the second target trench are both provided with oxide, and polysilicon is deposited in the trenches, and the polysilicon at the bottom of the first target trench directly contacts the base region, and the polysilicon at the bottom of the second target trench directly contacts the collector region, a base is provided on the surface polysilicon of the first target trench, a collector is provided on the surface polysilicon of the second target trench, a collector is provided on the surface of the emitter region, and the base is provided between the emitter and the collector, so as to increase the electron isolation capability by arranging the regions longitudinally and adding oxide in the first target trench and the second target trench, thereby solving the technical problem in the prior art that a certain distance is required between the electrodes of the bipolar transistor to maintain the electron isolation capability, resulting in a large planar size and low integration, thereby achieving the technical effect of reducing the planar size and increasing the integration, as described below:

[0032] See also Figure 1 , Figure 1 This is a flow chart of a method for manufacturing a bipolar transistor provided in an embodiment of the present application. Figure 1 As shown, the manufacturing method of the bipolar transistor provided in the embodiment of the present application includes the following steps:

[0033] S101: etching a first initial trench on an initial substrate, and depositing oxide in the first initial trench.

[0034] The initial substrate includes a collector region and a base region located above the collector region, and the bottom of the first initial trench is located in the base region.

[0035] Specifically, the initial substrate is formed by: forming a collector region on a P-type silicon substrate; forming a P-type silicon epitaxial layer on the collector region by epitaxial growth, and then forming a base region on the P-type silicon epitaxial layer to obtain the initial substrate.

[0036] The emitter region, the collector region and the base region are obtained by performing photolithography and ion implantation respectively according to the type of the bipolar transistor.

[0037] That is to say, according to the type of bipolar transistor, corresponding photolithography and ion implantation are performed to obtain the emitter region, collector region and base region. The types of bipolar transistors include NPN bipolar transistors and PNP bipolar transistors. That is to say, according to the emitter region, collector region and base region of the NPN bipolar transistor, photolithography is performed respectively and ion implantation is performed according to the corresponding doping type and concentration. According to the emitter region, collector region and base region of the PNP bipolar transistor, photolithography is performed respectively and ion implantation is performed according to the corresponding doping type and concentration. The ions, doping types and concentrations implanted in the same area of ​​the NPN bipolar transistor and the PNP bipolar transistor are different, that is, the ion implantation performed by the NPN bipolar transistor and the PNP bipolar transistor is different when generating the emitter region.

[0038] For example, see Figure 2 , Figure 2 Schematic diagram of the initial substrate provided in the embodiment of the present application. Figure 2 As shown, photolithography and ion implantation are performed on the upper portion of the P-type silicon substrate to generate a collector region on the upper portion of the P-type silicon substrate; a P-type silicon epitaxial layer is formed on the collector region through an epitaxial growth (EPI) process, or the P-type silicon epitaxial layer is equivalent to the portion generated on the P-type silicon substrate, and the thickness h of the P-type silicon epitaxial layer is 0.5 to 20 microns (μm); photolithography and ion implantation are performed on the upper portion of the P-type silicon epitaxial layer to generate a base region on the P-type silicon epitaxial layer, and the entire P-type silicon epitaxial layer can be optionally converted into a base region to form an initial substrate.

[0039] Among them, the lithography performed to generate the collector region can be middle ultraviolet lithography (MUV), deep ultraviolet lithography (DUV), etc., and the lithography performed to generate the base region can also be middle ultraviolet lithography (MUV), deep ultraviolet lithography (DUV), etc. This application does not limit the specific method of lithography, nor does it limit the specific method of ion implantation.

[0040] For example, if the bipolar transistor to be prepared is an NPN bipolar transistor, it is necessary to form an N-type semiconductor by injecting a high concentration of doped donor impurities to obtain an emitter region, to form a P-type semiconductor by injecting a low concentration of doped acceptor impurities to obtain a base region, and to form an N-type semiconductor by injecting a medium concentration of doped donor impurities (between the concentrations of the emitter region and the base region) to obtain a collector region. If the bipolar transistor to be prepared is a PNP bipolar transistor, it is necessary to form a P-type semiconductor by injecting a high concentration of doped acceptor impurities to obtain an emitter region, to form an N-type semiconductor by injecting a low concentration of doped donor impurities to obtain a base region, and to form a P-type semiconductor by injecting a medium concentration of doped acceptor impurities (between the concentrations of the emitter region and the base region) to obtain a collector region. This application does not limit the types of donor impurities and acceptor impurities used in the actual ion implantation.

[0041] Furthermore, the upper portion of the P-type silicon epitaxial layer includes a base region and an emitter region, with the emitter region located above the base region, or in other words, both the base region and the emitter region are located in the P-type silicon epitaxial layer. The upper portion of the P-type silicon substrate is the collector region, or in other words, the collector region is located in the P-type silicon substrate.

[0042] After the initial substrate is formed, a first initial trench is formed by etching in the initial substrate, with the bottom of the first initial trench located in the base region. That is, since the base region in the initial substrate is located above the collector region, when the bottom of the first initial trench is located in the base region, it means that the first initial trench is etched only into the base region and not into the collector region, and the entire first initial trench is located in the base region.

[0043] For example, see Figure 3 , Figure 3 This is a schematic diagram of the first initial groove provided in the embodiment of the present application. Figure 3As shown, the side view of the first initial trench is a trapezoid, and the side view refers to a cross-section obtained by cutting the initial substrate along the etching direction on the surface of the initial substrate. The top width a1 of the first initial trench is greater than or equal to the bottom width a2, and the angle α between the trench side B and the trench top plane A is limited to a preset angle range. The trench side is used to indicate the edge formed by connecting the top and bottom of the same side, and the depth b1 of the first initial trench is less than or equal to the depth of the base region, so that the complete first initial trench is located in the base region.

[0044] Exemplarily, the angle α between the trench side and the trench top plane should be non-obtuse, i.e., within a predetermined range of greater than or equal to 70° and less than or equal to 90°. When the angle α between the trench side and the trench top plane is 90°, the top width a1 of the first initial trench is equal to the bottom width a2, and the side view of the first initial trench should be rectangular. The first initial trench is etched using a dry etch method. Because the etching is performed from top to bottom, the top width a1 of the trench must be greater than or equal to the bottom width a2. The depth of the first initial trench should be less than the depth of the P-type silicon epitaxial layer and greater than the depth of the emitter region, and the depth of the first initial trench does not reach the collector region. Exemplarily, the critical dimension (CD) of the first initial trench is 0.3 to 3 microns (μm), or in other words, the top width a1 of the first initial trench is 0.3 to 3 μm, and the depth b1 of the first initial trench is greater than 0.5 μm.

[0045] After etching the first initial trench, an oxide is deposited in the first initial trench. The oxide can be deposited in the first initial trench by chemical vapor deposition (CVD) or a furnace process. The thickness of the oxide should be limited to a thickness that does not fill the first initial trench, typically 0.01 to 1 micron (μm). Silicon dioxide (SiO2) can be selected as the oxide.

[0046] return Figure 1 S102: After etching away the bottom oxide of the first initial trench, the trench is filled with polysilicon by depositing polysilicon to obtain a first target trench corresponding to the first initial trench.

[0047] That is, after oxide is deposited in the first initial trench, the bottom oxide of the first initial trench is removed by etching, and after the bottom oxide is removed, the trench is filled with polysilicon deposition to obtain the first target trench.

[0048] Exemplarily, dry etching is used to remove the bottom oxide of the first initial trench, and then polysilicon (poly) is deposited in the trench through a furnace process to fill the trench and obtain the first target trench.

[0049] After the first target trench corresponding to the first initial trench is obtained by filling the trench with polysilicon deposition, the method further includes: removing oxide and polysilicon outside the first target trench so that the portion of the surface of the initial substrate other than the first target trench becomes the surface of the base region.

[0050] That is, after the first target trench is generated, it is necessary to remove excess oxide and polysilicon outside the trench by oxide layer etch back or grinding (CMP), or a combination of the two processes to flatten the surface of the initial substrate, so that the top surface of the first target trench and the remaining base region are displayed on the surface of the initial substrate.

[0051] S103: etching a second initial trench on one side of the first target trench, and depositing oxide in the second initial trench.

[0052] The bottom of the second initial trench is located in the collector region, and one side of the first target trench is located in a transistor arrangement direction perpendicular to the etching direction.

[0053] That is, the bipolar transistors on the wafer are arranged in a matrix, and the first target trench should be located in the row or column direction of the matrix arrangement of the second initial trench. Furthermore, because the bottom of the second initial trench is located in the collector region, the depth of the second initial trench is greater than the depth of the first initial trench, so that the side of the second initial trench covers the base region, the P-type silicon epitaxial layer, and the collector region, and the bottom of the second initial trench is located in the collector region and is not etched into the P-type silicon substrate.

[0054] Exemplarily, dry etching is used to etch the second initial trench. The side view of the second initial trench may also be a trapezoid. The top width of the second initial trench is greater than or equal to the bottom width. The angle between the side edge of the trench and the top plane of the trench is limited to within a preset angle range. The angle between the side edge of the second initial trench and the top plane of the trench should be non-obtuse, that is, the preset angle range is greater than or equal to 70° and less than or equal to 90°. When the angle between the side edge of the second initial trench and the top plane of the trench is 90°, the top width of the second initial trench is equal to the bottom width, and the side view of the second initial trench should be a rectangle.

[0055] After etching the second initial trench, an oxide is deposited in the trench. The oxide can be deposited in the first initial trench by chemical vapor deposition (CVD) or a furnace process. The oxide thickness should be limited to a thickness that does not fill the first initial trench, typically 0.01 to 1 micron (μm). Silicon dioxide (SiO2) can be selected as the oxide.

[0056] S104: After etching away the bottom oxide of the second initial trench, the trench is filled with polysilicon by depositing polysilicon to obtain a second target trench corresponding to the second initial trench.

[0057] Furthermore, in the second initial trench after the oxide is deposited, dry etching is used to remove the bottom oxide of the second initial trench, and then polysilicon (poly) is deposited in the trench through a furnace process to fill the trench and obtain a second target trench.

[0058] Specifically, the method also includes: simultaneously etching the second initial trench and the third initial trench on both sides of the first target trench, and depositing oxide in the third initial trench, the bottom of the third initial trench is in the collector region, and the critical dimension of the third initial trench is smaller than the critical dimension of the second initial trench; filling the trench by polysilicon deposition to obtain a third target trench corresponding to the third initial trench; forming a gate on the polysilicon on the surface of the third target trench, and the gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages.

[0059] That is, after obtaining the first target groove, a second initial groove and a third initial groove can be etched on both sides of the first target groove, respectively, and the second initial groove and the third initial groove are both located in the row arrangement direction or the column arrangement direction of the matrix arrangement. That is, the second initial groove is located on one side of the first target groove in the row arrangement direction, and the third initial groove is located on the other side of the first target groove in the row arrangement direction, or the second initial groove is located on one side of the first target groove in the column arrangement direction, and the third initial groove is located on the other side of the first target groove in the column arrangement direction.

[0060] That is, since dry etching is used to etch the second initial trench and the third initial trench simultaneously, and the bottoms of the second initial trench and the third initial trench are both in the collector region, the depths of the third initial trench and the second initial trench can be the same.

[0061] The top width of the third initial groove is greater than or equal to the bottom width, and the angle between the groove side and the groove top plane is limited to a preset angle range. The angle between the groove side of the third initial groove and the groove top plane should be non-obtuse, that is, the preset angle range is greater than or equal to 70° and less than or equal to 90°. When the angle between the groove side of the third initial groove and the groove top plane is 90°, the top width of the third initial groove is equal to the bottom width, and the side view of the third initial groove should be rectangular.

[0062] Exemplarily, the critical dimension of the third initial trench is smaller than the critical dimension of the second initial trench, or in other words, the top width of the third initial trench is smaller than the top width of the second initial trench. Furthermore, after etching the second and third initial trenches, oxide is simultaneously deposited in the second and third initial trenches by chemical vapor deposition or a furnace process. Because the critical dimension of the third initial trench is smaller than that of the second initial trench, it is necessary to prevent the oxide from filling the third initial trench during the deposition process. Therefore, the thickness of the oxide deposited in each of the second and third initial trenches should be limited to a thickness that does not fill the trenches.

[0063] For example, after simultaneously depositing oxide in the second and third preliminary trenches by chemical vapor deposition or a furnace process, the deposited oxides in the second and third preliminary trenches can be dry-etched to remove the bottom oxide of the second preliminary trench. However, since the top width of the third preliminary trench is smaller than the top width of the second preliminary trench, the bottom oxide of the third preliminary trench will not be completely removed. In other words, after the oxide removal, the bottom of the second preliminary trench is exposed as the collector region, and the bottom of the third preliminary trench is the deposited oxide.

[0064] That is, the second initial trench and the third initial trench are etched out at the same time, and the top width of the second initial trench is maintained larger than the top width of the third initial trench. Oxide is then deposited on the second initial trench and the third initial trench at the same time, and the second initial trench and the third initial trench should not be filled with oxide. The second initial trench and the third initial trench after oxide deposition are then etched to remove the bottom oxide of the second initial trench and expose the collector area at the bottom of the second initial trench. The bottom oxide of the third initial trench is not removed, and the trenches are then filled with polysilicon deposition to obtain a second target trench corresponding to the second initial trench and a third target trench corresponding to the third initial trench.

[0065] Furthermore, by simultaneously depositing oxide on the second and third initial trenches, process costs are reduced. Furthermore, since oxide is deposited on the sidewalls of both the first target trench and the second target trench to increase electron isolation, the distance between the first target trench and the second target trench is reduced. This also reduces the distance between the base and emitter, and the distance between the base and collector, which are subsequently constructed, thereby increasing the number of bipolar transistors that can be integrated.

[0066] Specifically, before forming an emitter region on the surface of the base region after generating the target trench, the method further includes: removing oxide and polysilicon outside the second target trench and the third target trench so that the portion of the surface of the initial substrate other than the target trenches is the surface of the base region.

[0067] That is, after the second target trench and the third target trench are generated, excess oxide and polysilicon outside the second target trench and the third target trench are removed by oxide layer etchback or grinding (CMP), or a combination of the two processes, to planarize the surface of the initial substrate, so that the top surface of the first target trench, the top surface of the second target trench, the top surface of the third target trench and the remaining base region are displayed on the surface of the initial substrate.

[0068] For example, see Figure 4 , Figure 4 This is a schematic diagram of the target groove provided in the embodiment of the present application. Figure 4 As shown, the first target trench is connected to the base region via polysilicon, and the second target trench is connected to the collector region via polysilicon. The structure of the first target trench along the orientation of the target trenches on both sides is oxide, polysilicon, and oxide. That is, the lateral structure of the first target trench is oxide, polysilicon, and oxide, and the lateral structure of the second target trench is also oxide, polysilicon, and oxide. The third target trench is connected to the collector region via oxide, and the lateral structure of the third target trench is also oxide, polysilicon, and oxide. Since the first and second target trenches will later be used to form electrodes for bipolar transistors, and since oxide is non-conductive, the oxide, polysilicon, and oxide structure enhances electron isolation. Therefore, there is no need to set a large lateral distance m between the first and second target trenches to maintain a certain level of electron isolation. The lateral distance m between the first and second target trenches can be reduced, thereby reducing the planar size of the bipolar transistors, increasing the number of bipolar transistors etched on the same wafer, and increasing the degree of integration.

[0069] S105: forming an emitter region on the surface of the base region after the target trenches are generated, and the emitter region does not cover each target trench.

[0070] For example, see Figure 5 , Figure 5 This is a schematic diagram of the emission area provided in the embodiment of the present application. Figure 5 As shown, the upper portion of the base region is photolithographically patterned using middle ultraviolet lithography (MUV) or deep ultraviolet lithography (DUV), and ion implantation is performed to form the emitter region. Furthermore, the bipolar transistor fabricated in this application is a vertical bipolar transistor, with the emitter, base, and collector regions arranged vertically.

[0071] S106: forming a base on the polysilicon on the surface of the first target trench, forming a collector on the polysilicon on the surface of the second target trench, and forming an emitter on the emitter region on the other side of the first target trench, so as to prepare the bipolar transistor.

[0072] Furthermore, the bipolar transistor is fabricated by forming the base, collector, and emitter electrodes of the bipolar transistor on the polysilicon surface of the target trench. Furthermore, a gate is formed on the polysilicon surface of the third target trench to add electrodes for the bipolar transistor. By connecting the gate to different external voltages, the current amplification factor of the bipolar transistor is changed, thereby achieving the purpose of regulating the current amplification factor of the bipolar transistor.

[0073] Furthermore, when a bipolar transistor is amplifying in the forward direction, the emitter junction is forward biased and the collector junction is reverse biased. If the bipolar transistor is an NPN bipolar transistor, the forward bias of the emitter junction causes electrons from the emitter region to be injected into the base region, resulting in an unbalanced accumulation of minority carriers in the P-type base region and a certain electron concentration gradient. This electron concentration gradient causes electrons to diffuse toward the collector junction. Due to the reverse bias of the collector junction, electrons that diffuse to the boundary of the space charge region of the collector junction are accelerated by the electric field and drift toward the collector region, becoming the main source of collector current. The presence of the gate induces strong inversion in the base semiconductor. The electron concentration within the inversion layer is sufficiently high, forming an N-type conductive channel on the gate side. This conductive channel connects the two N-type semiconductors, the emitter and collector regions. Under the influence of the electric field, electrons flow from the emitter region to the collector region, increasing the collector current, thereby significantly enhancing the current amplification factor of the bipolar transistor. Furthermore, the current amplification factor of the bipolar transistor can be controlled in real time by the gate voltage, making the current amplification controllable.

[0074] For example, the effect of applying different gate voltages on the bipolar transistor can be reflected by determining the current amplification factor, collector current peak value, and base current peak value. Table 1 is a schematic table of various parameters of the bipolar transistor when applying different gate voltages.

[0075] Table 1:

[0076]

[0077] For example, see Figure 6 , Figure 6 Schematic diagram of a bipolar transistor provided in an embodiment of the present application. Figure 6 As shown, a base, collector, emitter, and gate are generated above the emitter region, with the emitter located laterally between the gate and base. After the base, collector, emitter, and gate are formed, a dielectric layer is deposited on the emitter region. The dielectric layer may include at least one of the following: silicon nitride, silicon oxynitride, or phosphorus-doped silicon glass. The deposited dielectric layer is then subjected to chemical mechanical polishing (CMP) to form an interlayer dielectric layer. Contact holes are then formed on the base, collector, emitter, and gate of the interlayer dielectric layer through photolithography and etching processes to fabricate a bipolar transistor with an additional gate. The contact holes can be filled with titanium (Ti), titanium nitride (TiN), and tungsten (W) to facilitate connection to metal in the back-end process.

[0078] Based on the same application concept, the embodiments of the present application also provide a bipolar transistor corresponding to the manufacturing method of the bipolar transistor provided in the above embodiments. Since the principle of solving the problem by the bipolar transistor in the embodiments of the present application is similar to the manufacturing method of the above embodiments of the present application, the implementation of the bipolar transistor can refer to the implementation of the method, and the repeated parts will not be repeated.

[0079] Exemplarily, a bipolar transistor is also provided in an embodiment of the present application, which includes an emitter region, a base region, a collector region, a first target trench, a second target trench, an emitter, a base and a collector, wherein the emitter region, the base region and the collector region are arranged vertically in sequence, the base region is located above the collector region, the emitter region is located above the base region, the sidewalls of the first target trench are provided with oxide and polysilicon is deposited in the trench, the bottom polysilicon of the first target trench is in contact with the base region, the second target trench is provided on one side of the first target trench, the sidewalls of the second target trench are provided with oxide and polysilicon is deposited in the trench, the bottom polysilicon of the second target trench is in contact with the collector region, the base is provided on the polysilicon on the surface of the first target trench, the collector is provided on the polysilicon on the surface of the second target trench, and the emitter is provided on the surface of the emitter region on the other side of the first target trench.

[0080] In which, the bipolar transistor also includes a gate and a third target trench, the gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages, wherein the third target trench is arranged on the other side of the first target trench, the sidewalls and bottom of the third target trench are provided with oxide and polysilicon is deposited in the trench, the gate is arranged on the polysilicon on the surface of the third target trench, and the emitter is arranged between the gate and the base.

[0081] That is, the polysilicon at the bottom of the first target trench contacts the P-type silicon epitaxial layer, the polysilicon at the bottom of the second target trench contacts the P-type silicon substrate, and the vertical structure of the third target trench is polysilicon and an oxide layer. The oxide layer at the bottom of the third target trench contacts the collector region, that is, the oxide layer at the bottom of the third target trench contacts the P-type silicon substrate. Exemplarily, the depth of the second target trench is the same as the depth of the third target trench.

[0082] Exemplarily, the bipolar transistors include NPN bipolar transistors and PNP bipolar transistors. In addition, the bipolar transistors provided in this application are generally integrated into a power management chip.

[0083] For example, see Figure 7 , Figure 7 A schematic diagram of the electric field strength of a bipolar transistor provided in an embodiment of the present application. Figure 7 Reflects the electric field strength at each location in the cross section of a bipolar transistor in the lateral direction. Figure 8 , Figure 8 A schematic diagram of the potential of a bipolar transistor provided in an embodiment of the present application. Figure 8 Reflects the potential at each location in the cross section of a bipolar transistor in the lateral direction. Figure 9 , Figure 9 A schematic diagram of the current density of a bipolar transistor provided in an embodiment of the present application. Figure 9 Reflects the current density at each location in the cross section of the bipolar transistor in the lateral direction. Figure 10 , Figure 10 A curve diagram showing the relationship between the base current and the collector current of the bipolar transistor provided in an embodiment of the present application. Figure 10 Reflects the collector current of the bipolar transistor at different base currents, in amperes (A). Figures 7 to 10 This demonstrates the electrical characteristics of the bipolar transistor prepared in this application.

[0084] Those skilled in the art will clearly understand that, for ease of description and brevity, the specific operating processes of the systems and devices described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here. In the several embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods can be implemented in other ways. The device embodiments described above are merely illustrative. For example, the division of units described is merely a logical functional division, and actual implementations may employ other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be omitted or not implemented. Furthermore, the coupling or direct coupling or communication connection shown or discussed between each other may be through some communication interface, or the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the units may be selected to achieve the objectives of the present embodiment according to actual needs.

[0085] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0086] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0087] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A bipolar transistor, characterized in that: The bipolar transistor includes an emitter region, a base region, a collector region, a first target trench, a second target trench, an emitter, a base and a collector. The emitter region, the base region, and the collector region are arranged vertically in sequence, the base region is located above the collector region, the emitter region is located above the base region, the sidewalls of the first target trench are provided with oxide, and polysilicon is deposited in the trench, the bottom polysilicon of the first target trench is in contact with the base region, the second target trench is provided on one side of the first target trench, the sidewalls of the second target trench are provided with oxide, and polysilicon is deposited in the trench, the bottom polysilicon of the second target trench is in contact with the collector region, The base is arranged on the polysilicon on the surface of the first target trench, the collector is arranged on the polysilicon on the surface of the second target trench, and the emitter is arranged on the surface of the emitter region on the other side of the first target trench; The bipolar transistor further includes a gate and a third target trench, wherein the gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages. The third target trench is arranged on the other side of the first target trench, the sidewalls and bottom of the third target trench are both provided with oxide and polysilicon is deposited in the trench. The gate is arranged on the polysilicon on the surface of the third target trench, and the emitter is arranged between the gate and the base.

2. A method for manufacturing a bipolar transistor, characterized in that: The method is used to manufacture the bipolar transistor according to claim 1, The method comprises: Etching a first initial trench on an initial substrate, and depositing oxide in the first initial trench, wherein the initial substrate comprises a collector region and a base region located above the collector region, and the bottom of the first initial trench is located at the base region; After etching away the bottom oxide of the first initial trench, filling the trench with polysilicon deposition to obtain a first target trench corresponding to the first initial trench; Simultaneously, a second initial trench and a third initial trench are etched on both sides of the first target trench, and oxide is deposited in the second initial trench and the third initial trench, respectively, wherein the bottom of the second initial trench is located in the collector region, one side of the first target trench is located in a transistor arrangement direction perpendicular to the etching direction, the bottom of the third initial trench is located in the collector region, and the critical dimension of the third initial trench is smaller than the critical dimension of the second initial trench; After etching away the bottom oxide of the second initial trench, filling the trenches with polysilicon deposition to obtain a second target trench corresponding to the second initial trench and a third target trench corresponding to the third initial trench; forming an emitter region on the surface of the base region after the target trenches are generated, wherein the emitter region does not cover each target trench; forming a base on the polysilicon on the surface of the first target trench, forming a collector on the polysilicon on the surface of the second target trench, and forming an emitter on the emitter region on the other side of the first target trench, so as to fabricate the bipolar transistor; A gate is formed on the polysilicon on the surface of the third target trench, and the gate is used to change the current amplification factor of the bipolar transistor by connecting different external voltages.

3. The method according to claim 2, characterized in that The initial substrate is formed by: forming a collector region on a P-type silicon substrate; After forming a P-type silicon epitaxial layer on the collector region by epitaxial growth, a base region is formed on the P-type silicon epitaxial layer to obtain the initial substrate.

4. The method according to claim 2, characterized in that After the trench is filled with polysilicon by depositing polysilicon to obtain a first target trench corresponding to the first initial trench, the method further includes: The oxide and polysilicon outside the first target trench are removed, so that a portion of the surface of the initial substrate except the first target trench becomes the surface of the base region.

5. The method according to claim 2, characterized in that After the target trench is generated, and before the emitter region is formed on the surface of the base region, the method further includes: The oxide and polysilicon outside the second target trench and the third target trench are removed, so that a portion of the surface of the initial substrate except for each target trench becomes the surface of the base region.

6. The method according to claim 2, characterized in that The emitter region, the collector region and the base region are obtained by performing photolithography and ion implantation respectively according to the type of the bipolar transistor.

7. The method according to claim 2, characterized in that For each initial trench, the top width of the initial trench is greater than or equal to the bottom width, and the angle between the trench side and the trench top plane is limited to a preset angle range. The thickness of the oxide deposited in the initial trench is limited to a thickness that does not fill the trench. The trench side is used to indicate the edge formed by connecting the top and bottom of the same side. And / or, the second initial trench and the third initial trench have the same depth.

8. The method according to claim 2, characterized in that The method further comprises: An interlayer dielectric layer is formed on the emitter region after the base, the collector, the emitter and the gate are formed, and then ground.

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