Two-dimensional reconfigurable transistor and preparation method and application thereof

Abstract

The invention discloses a two-dimensional reconfigurable transistor and a preparation method and application thereof, and belongs to the technical field of two-dimensional semiconductor materials. The two-dimensional reconfigurable transistor comprises a polar gate electrode layer, a dielectric layer, a two-dimensional semiconductor layer and an electrode layer which are sequentially arranged above a substrate layer, the polar gate electrode layer comprises two polar gate electrodes and back gate electrodes which are arranged between the two polar gate electrodes and are not in contact with each other, and the two polar gate electrodes are in short circuit; the electrode layer comprises a source flow electrode and a source drain electrode, the source flow electrode and the source drain electrode are in contact with the two-dimensional semiconductor layer, and the source flow electrode and the source drain electrode are not in contact with each other; and the source flow electrode and the source drain electrode are respectively positioned right above the two polar gate electrodes. The polarity-controllable two-dimensional reconfigurable transistor provided by the invention is expected to open up a new way for two-dimensional electronic application.

Description

Technical Field

[0001] The present invention belongs to the technical field of two-dimensional semiconductor materials, and particularly relates to a two-dimensional reconfigurable transistor, a preparation method thereof, and an application thereof. Background Art

[0002] The regulation of the transport polarity of semiconductor materials is crucial for the development of electronic devices, and doping and defect introduction are the main methods to achieve this regulation. Due to their excellent properties, two-dimensional semiconductor materials are considered ideal materials for fabricating high-performance electronic devices and are expected to solve the limit problems faced by traditional silicon-based integrated circuit processes. However, there are many problems with traditional doping methods in two-dimensional semiconductor materials. For example, in the ion implantation doping method commonly used in silicon-based integrated circuits, since the thickness of two-dimensional materials is only at the atomic level, it is extremely easy to damage their lattice structure; while doping achieved by interfacial molecular modification or controlling the electrostatic gate voltage faces problems such as poor stability and electrical breakdown.

[0003] In contrast, the electrostatic gate voltage acting on the dielectric layer is a more direct polarity regulation method. By field-effect regulating the Fermi level of two-dimensional materials, polarity conversion can be achieved. However, in two-dimensional devices, it is difficult to synergistically regulate the barrier height and the double-interface doping level, resulting in difficulty in balancing simplified design and rich reconfigurable functions for two-dimensional programmable logic circuits based on electrostatic field regulation. Currently, only a single vertical double-gate transistor relying on the regulation of the double-interface conductive channel can achieve certain logic functions, but its function types are limited. If more logic functions are to be achieved, it is necessary to increase the area of a single transistor or cascade multiple devices, which not only increases the redundancy of the circuit but also greatly increases the manufacturing complexity. Summary of the Invention

[0004] Aiming at the above technical problems, the present invention proposes a two-dimensional reconfigurable transistor, a preparation method thereof, and an application thereof.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] One object of the present invention is to provide a two-dimensional reconfigurable transistor, comprising: a polarity gate electrode layer, a dielectric layer, a two-dimensional semiconductor layer, and an electrode layer sequentially disposed above a substrate layer; the polarity gate electrode layer includes two polarity gate electrodes and a back gate electrode disposed between the two polarity gate electrodes and not in contact with each other, and the two polarity gate electrodes are short-circuited; the electrode layer includes a source flow electrode and a source-drain electrode, the source flow electrode and the source-drain electrode are in contact with the two-dimensional semiconductor layer, and the source flow electrode and the source-drain electrode are not in contact with each other; the source flow electrode and the source-drain electrode are respectively located directly above the two polarity gate electrodes. The polarity-controllable two-dimensional reconfigurable transistor provided by the present invention is expected to open up a new way for two-dimensional electronic applications.

[0007] Further, the material of the substrate layer is silicon / silicon dioxide; and / or,

[0008] the material of the dielectric layer includes silicon oxide, hafnium oxide, hafnium zirconium oxide, calcium fluoride or boron nitride; and / or,

[0009] the material of the two-dimensional semiconductor layer includes tungsten disulfide, tungsten diselenide or molybdenum ditelluride; and / or,

[0010] the material of the polar gate electrode layer and the electrode layer includes a metal electrode material (such as Cr or Au) or a two-dimensional semimetal material (such as 1T-MoTe2, 1T-WS2, graphene, etc.); and / or,

[0011] the thickness of the polar gate electrode layer and the electrode layer is 10 - 50 nm.

[0012] The second object of the present invention is to provide a method for manufacturing a two-dimensional reconfigurable transistor, comprising the following steps:

[0013] Deposit the polar gate electrode layer above the substrate layer, and then perform oxidation cleaning;

[0014] After oxidizing and cleaning the polar gate electrode layer, deposit a dielectric layer above it;

[0015] Deposit the two-dimensional semiconductor layer above the deposited dielectric layer;

[0016] Deposit an electrode layer above the two-dimensional semiconductor layer;

[0017] Wherein, the polar gate electrode layer includes two polar gate electrodes and a back gate electrode disposed between the two polar gate electrodes and not in contact with each other, and the two polar gate electrodes are short-circuited;

[0018] The electrode layer includes a source flow electrode and source-drain electrodes, and the source flow electrode and the source-drain electrodes are not in contact with each other.

[0019] Further, the deposition method of the polar gate electrode layer includes the following steps: First, perform patterned exposure on the substrate layer by electron beam lithography, and then use thermal evaporation technology to prepare two polar gate electrodes and a back gate electrode.

[0020] Further, the deposition method of the dielectric layer includes the following steps: Use atomic layer deposition to prepare a dielectric layer above the polar gate electrode layer, first perform patterned exposure on the dielectric layer by ultraviolet exposure, and then use plasma etching to etch the exposed area.

[0021] Further, the deposition method of the two-dimensional semiconductor layer includes the following steps: transferring the two-dimensional semiconductor layer above the dielectric layer, first patterning the two-dimensional semiconductor layer by electron beam lithography, and then etching the exposed area by plasma etching.

[0022] Further, the deposition method of the electrode layer includes the following steps: first patterning and exposing the two-dimensional semiconductor layer by electron beam lithography, and then preparing the source electrode and the source-drain electrodes by thermal evaporation technology.

[0023] The third object of the present invention is to provide an application of the two-dimensional reconfigurable transistor in the field of two-dimensional logic circuits.

[0024] The fourth object of the present invention is to provide an application of the two-dimensional reconfigurable transistor in two-dimensional reconfigurable devices.

[0025] The fifth object of the present invention is to provide a method for regulating a two-dimensional reconfigurable transistor, including: when the two-dimensional reconfigurable transistor is operating, a voltage is applied to the source-drain electrodes and the source electrode is grounded, then the combination modes of the two polar gate electrodes include: when the gate voltages of the two polar gate electrodes are negative voltages, the hole barrier height and width at the metal-semiconductor contact interface are reduced, and holes can be injected into the channel, and the transistor is regulated to a P-type transistor; on the contrary, when the gate voltages of the two polar gate electrodes are positive voltages, the electron barrier height and width at the metal-semiconductor contact interface are reduced, and N-type transport dominated by electrons can be achieved through the regulation of the two polar gate electrodes.

[0026] Compared with the prior art, the present invention has the following advantages and technical effects:

[0027] The two-dimensional reconfigurable transistor of the present invention allows reversible reconfiguration between n-type and p-type operating modes and additional functions in a single device, that is, enhanced logic capabilities and device versatility, meeting the application requirements of future high-density integration. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] The accompanying drawings constituting a part of the present invention are used to provide a further understanding of the present invention. The schematic embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation to the present invention. In the drawings:

[0029] Figure 1 is a schematic structural diagram of the two-dimensional reconfigurable transistor of the present invention; wherein, 1 - substrate layer; 2 - polar gate electrode layer; 21 - polar gate electrode; 22 - back gate electrode; 3 - dielectric layer; 4 - two-dimensional semiconductor layer; 5 - electrode layer; 51 - source electrode; 52 - source-drain electrode;

[0030] Figure 2 is a light microscope image of the tungsten diselenide reconfigurable transistor prepared in Example 1;

[0031] Figure 3 For the N-type transport characteristics of the tungsten diselenide reconfigurable transistor with a positive voltage on the polar gate in Example 1;

[0032] Figure 4 For the P-type transport characteristics of the tungsten diselenide reconfigurable transistor with a negative voltage on the polar gate in Example 1;

[0033] Figure 5 For the XNOR logic function under different gate and back-gate configurations in Example 1;

[0034] Figure 6 For the optical micrograph of the inverter of the transistor in Example 2;

[0035] Figure 7 For the circuit diagram of the inverter in Example 2;

[0036] Figure 8 For the voltage transfer curve of the inverter in Example 2;

[0037] Figure 9 For the voltage gain of the inverter in Example 2. Detailed implementation manners

[0038] Now, various exemplary implementation manners of the present invention will be described in detail. This detailed description should not be considered as a limitation of the present invention, but rather as a more detailed description of certain aspects, characteristics, and implementation schemes of the present invention.

[0039] It should be understood that the terms described in the present invention are only for describing specific implementation manners and are not used to limit the present invention. Additionally, for the numerical ranges in the present invention, it should be understood that each intermediate value between the upper and lower limits of the range is also specifically disclosed. Each intermediate value within any stated value or stated range, as well as each smaller range between any other stated value or intermediate value within the stated range, is also included in the present invention. The upper and lower limits of these smaller ranges can be independently included or excluded from the range.

[0040] Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present invention pertains. Although the present invention only describes preferred methods and materials, any methods and materials similar or equivalent to those described herein can also be used in the implementation or testing of the present invention. All documents mentioned in this specification are incorporated by reference to disclose and describe the methods and / or materials related to the documents. In case of conflict with any incorporated document, the content of this specification shall prevail.

[0041] Without departing from the scope or spirit of the present invention, various improvements and changes can be made to the specific embodiments of the specification of the present invention, which are obvious to those skilled in the art. Other embodiments obtained from the specification of the present invention are obvious to those skilled in the art. The specification and embodiments of the present invention are merely exemplary.

[0042] Regarding the terms "comprising", "including", "having", "containing", etc. used herein, they are all open-ended terms, meaning including but not limited to.

[0043] An embodiment of the present invention provides a two-dimensional reconfigurable transistor. The structural schematic diagram is shown in Figure 1 , including: a polar gate electrode layer 2, a dielectric layer 3, a two-dimensional semiconductor layer 4, and an electrode layer 5 sequentially disposed above the substrate layer 1; the polar gate electrode layer 2 includes two polar gate electrodes 21 and a back gate electrode 22 disposed between the two polar gate electrodes 21 and not in contact with each other. The two polar gate electrodes 21 are short-circuited, and the two polar gate electrodes 21 are not short-circuited to the back gate electrode 22; the electrode layer 5 includes a source-drain electrode 51 and a source-drain electrode 52. The source-drain electrode 51 and the source-drain electrode 52 are in contact with the two-dimensional semiconductor layer 4, and the source-drain electrode 51 and the source-drain electrode 52 are not in contact with each other; the source-drain electrode 51 and the source-drain electrode 52 are respectively located directly above the two polar gate electrodes 21.

[0044] In a preferred embodiment of the present invention, the material of the substrate layer 1 is silicon / silicon dioxide.

[0045] In a preferred embodiment of the present invention, the material of the dielectric layer 3 includes: silicon oxide, hafnium oxide, hafnium zirconium oxide, calcium fluoride, or boron nitride. The preparation method of the dielectric layer 3 is selected from: atomic deposition process, micromechanical exfoliation, physical vapor deposition, etc. The specific preparation process belongs to the prior art and is not a factor for creative exploration of the present invention, as long as the target material can be prepared. As a typical but non-limiting example, hafnium oxide is selected as the material of the dielectric layer in the following embodiments of the present invention.

[0046] In a preferred embodiment of the present invention, the material of the two-dimensional semiconductor layer 4 is a bipolar material, specifically including: tungsten disulfide, tungsten diselenide, or molybdenum ditelluride. The material can be prepared by conventional micromechanical exfoliation method, CVD growth method, or PVD growth method. The specific preparation process is not a factor for creative exploration of the present invention, as long as the target material can be prepared. As a typical but non-limiting example, tungsten diselenide is selected as the material of the two-dimensional semiconductor layer in the following embodiments of the present invention.

[0047] In a preferred embodiment of the present invention, the materials of the polar gate electrode layer 2 (two polar gate electrodes 21 and a back gate electrode 22) and the electrode layer 5 (a source-drain current electrode 51 and source-drain electrodes 52) include metal electrode materials or two-dimensional semimetal materials. These materials can be prepared by electron beam evaporation, thermal evaporation, or transfer electrode methods. The specific preparation process is not a factor for exploring the creativity of the present invention, as long as the target materials can be prepared. As a typical but non-limiting example, in the following embodiments of the present invention, Cr is selected as the material for the two-dimensional back gate electrode, Au is selected as the material for the polar gate electrode; and Au is selected as the material for the source-drain current electrode and source-drain electrodes.

[0048] In a preferred embodiment of the present invention, the thickness of the polar gate electrode layer 2 and the electrode layer 5 is 10 - 50 nm. As a typical but non-limiting example, in the following embodiments of the present invention, the thicknesses of the polar gate electrode and the back gate electrode are 15 nm and 5 nm respectively.

[0049] The embodiment of the present invention also provides a method for manufacturing a two-dimensional reconfigurable transistor, including the following steps:

[0050] (1) Deposit the polar gate electrode layer 2 above the substrate layer 1, and then perform oxidation cleaning;

[0051] (2) After oxidizing and cleaning the polar gate electrode layer 2, deposit a dielectric layer 3 above it;

[0052] (3) Deposit the two-dimensional semiconductor layer 4 above the deposited dielectric layer 3;

[0053] (4) Deposit the electrode layer 5 above the two-dimensional semiconductor layer 4;

[0054] Wherein, the polar gate electrode layer 2 includes two polar gate electrodes 21 and a back gate electrode 22 disposed between the two polar gate electrodes 21 and not in contact with each other, and the two polar gate electrodes 21 are short-circuited;

[0055] The electrode layer 5 includes a source-drain current electrode 51 and source-drain electrodes 52, and the source-drain current electrode 51 and the source-drain electrodes 52 are not in contact with each other.

[0056] In a preferred embodiment of the present invention, the deposition method of the polar gate electrode layer 2 includes the following steps: First, use electron beam lithography to pattern-expose the substrate layer 1, and then use thermal evaporation technology to prepare two polar gate electrodes 21 and a back gate electrode 22.

[0057] In a preferred embodiment of the present invention, the patterning methods for the regions of the two polar gate electrodes 21, the back gate electrode 22, the source-drain current electrode 51, and the source-drain electrodes 52 are selected from: electron beam lithography and ultraviolet lithography processes for patterning, and then use physical vapor deposition and organic-assisted transfer technology to complete the deposition of metal electrodes.

[0058] In a preferred embodiment of the present invention, the deposition methods of the dielectric layer 3 and the two-dimensional semiconductor layer 4 include the following steps: First, perform patterning using an electron beam lithography process or an ultraviolet lithography process, and then perform etching on the exposed area using plasma etching.

[0059] In a preferred embodiment of the present invention, the deposition method of the dielectric layer 3 includes the following steps: Prepare the dielectric layer 3 above the polar gate electrode layer 2 by atomic layer deposition. First, perform patterned exposure on the dielectric layer 3 using an ultraviolet lithography process, and then perform etching on the exposed area using plasma etching. The preparation method of the dielectric layer 3 can adopt atomic layer deposition, physical vapor deposition, or micro-mechanical exfoliation method. The specific preparation process is not a factor for creative exploration in the present invention, as long as the dielectric layer can be prepared.

[0060] In a preferred embodiment of the present invention, the deposition method of the two-dimensional semiconductor layer 4 includes the following steps: Transfer the two-dimensional semiconductor layer 4 above the dielectric layer 3. First, perform patterning on the two-dimensional semiconductor layer 4 using an electron beam lithography process, and then perform etching on the exposed area using plasma etching. The method for transferring the two-dimensional semiconductor layer 4 is selected from: PDMS-assisted transfer, gold-assisted transfer, water-assisted transfer, or wet etching transfer.

[0061] In a preferred embodiment of the present invention, the deposition method of the electrode layer 5 includes the following steps: First, perform patterned exposure on the two-dimensional semiconductor layer 4 using an electron beam lithography process, and then prepare the source electrode 51 and the source-drain electrode 52 using thermal evaporation technology.

[0062] The two-dimensional reconfigurable transistor can be applied in the field of two-dimensional logic circuits. The involved logic functions include: exclusive NOR gate, inverter, and combinational logic circuits formed by inverters.

[0063] The two-dimensional reconfigurable transistor can be applied in two-dimensional reconfigurable devices.

[0064] The present invention also provides a method for regulating a two-dimensional reconfigurable transistor, including: When the two-dimensional reconfigurable transistor is operating, a voltage is applied to the source-drain electrode 52, and the source electrode 51 is grounded. Then the combination modes of the two polar gate electrodes 21 include: When the gate voltages of the two polar gate electrodes 21 are negative voltages, the hole barrier height and width at the metal-semiconductor contact interface decrease, and holes can be injected into the channel, and the transistor is regulated to a P-type transistor; On the contrary, when the gate voltages of the two polar gate electrodes 21 are positive voltages, the electron barrier height and width at the metal-semiconductor contact interface decrease, and N-type transport dominated by electrons can be achieved through the regulation of the two polar gate electrodes 21.

[0065] All raw materials used in the present invention are obtained by purchasing on the market.

[0066] The technical solution of the present invention will be further described below through embodiments.

[0067] Embodiment 1

[0068] A method for preparing a two-dimensional reconfigurable transistor includes the following steps:

[0069] (1) Deposition of back gate electrode and polar gate electrode: Spin-coat PMMA (polymethyl methacrylate) on the Si / Si02 substrate at a speed of 3000 rpm for 1 min, and dry it on a hot plate at 160 °C for 1 min; Use an electron beam exposure system to pattern-expose and develop the spin-coated PMMA substrate for 20 - 30 s, where the interval between the polar gate electrode and the back gate electrode is 2 μm, and the electrode width is 10 μm. In the subsequent patterned deposition process, use thermal evaporation technology to prepare a Cr / Au back gate electrode and a polar gate electrode with thicknesses of 5 nm and 15 nm respectively;

[0070] Use a plasma etching machine to oxidize and clean the substrate deposited with the back gate electrode and the polar gate electrode in an O2 atmosphere. The etching parameters are: oxygen 10 sccm, power 5 sccm, time 5 s;

[0071] (2) Deposition of dielectric layer: Prepare hafnium oxide with a thickness of 15 nm by atomic layer deposition method, the preparation temperature is 140 °C, and the number of cycles is 150 times; Use an ultraviolet (365 nm) exposure system to expose the patterned area, and use plasma etching technology to etch under SF6 15 sccm, Ar 220 sccm and ICP power 500 W, ARE power 50 W;

[0072] (3) Deposition of two-dimensional semiconductor layer: Prepare few-layer tungsten diselenide nanosheets by mechanical exfoliation method: Stick the two sides of the bulk tungsten diselenide with tape, repeatedly fold and tear the sticky tape coated with the bulk tungsten diselenide material, and it can be thinned after about four to five times. Then attach the sticky tape to a pre-prepared PDMS substrate and slowly detach it from the substrate. Finally, monolayer or few-layer tungsten diselenide nanosheets can be obtained. Use an accurate transfer platform and a dry transfer process to transfer the obtained monolayer or few-layer tungsten diselenide nanosheets to the hafnium oxide dielectric layer prepared in step (2); Then use an electron beam exposure system to pattern-expose and develop the two-dimensional semiconductor layer for 20 - 30 s, and use a plasma etching machine to bombard it in an SF6 and O2 atmosphere to prepare a patterned tungsten diselenide sample. The specific etching parameters are: SF6 15 sccm, O2 5 sccm, etching time 5 s;

[0073] (4) Deposition of source-drain electrodes and source-drain electrodes: Use an electron beam exposure system to pattern-expose and develop the two-dimensional semiconductor layer for 20 - 30 s to expose the patterned source-drain electrodes and source-drain electrode regions, and then use thermal evaporation technology to prepare 30 nm of gold as the source-drain electrodes and source-drain electrodes (with a thickness of 30 nm), thus obtaining a two-dimensional reconfigurable transistor (denoted as: tungsten diselenide reconfigurable transistor).

[0074] Figure 2 Figure of the tungsten diselenide reconfigurable transistor prepared in Example 1 under an optical microscope.

[0075] The present invention uses a B1500A semiconductor device parameter analyzer and a Lakeshore probe station to explore the electrical characteristics of the device at room temperature and high vacuum. Figure 3 N-type transport characteristics of the tungsten diselenide reconfigurable transistor in Example 1 when the polar gate electrode is at a positive voltage. Figure 4 P-type transport characteristics of the tungsten diselenide reconfigurable transistor in Example 1 when the polar gate electrode is at a negative voltage. Figure 3 and Figure 4 It can be seen from that when the polar gate voltage is 5 V, good N-type transport is achieved, the on-state current is greater than 10 -5 A, and the off-state current is close to 10 -13 A. When the polar gate is -5 V, a switching ratio greater than 10 7 is achieved for P-type transport characteristics when the back gate voltage is swept from -5 V to 5 V.

[0076] To demonstrate the logic application based on the tungsten diselenide reconfigurable transistor, a positive gate voltage and a negative gate electrode are used to represent logic "0" and "1" respectively, and the logic output is represented by the high and low of the source-drain current, where a high channel current is the logic output "1", otherwise it is the logic output "0". When the polar gate and the back gate voltage are configured as (0, 0), (0, 1), (1, 0), and (1, 1) respectively, the reconfigurable device successfully implements the exclusive NOR logic gate ( Figure 5 ). In traditional silicon-based circuits, more than ten transistors are required to implement the exclusive NOR logic function, while this device only needs one transistor to achieve it. Due to its multifunctionality and design compactness, the tungsten diselenide reconfigurable transistor shows great potential in both the "more than Moore" and "beyond Moore" futures of electronic devices.

[0077] Example 2

[0078] To demonstrate the application of the reconfigurable transistor in logic circuits, the present invention constructs as Figure 6The shown inverter based on two reconfigurable transistors. Similar to Embodiment 1, the only difference is that two tungsten diselenide reconfigurable transistors are simultaneously fabricated on the same substrate, and the back gates of the two devices (Device 1 and Device 2) are shorted to the inverter input, and the source of Device 1 and the drain of Device 2 are shorted as the inverter output. As Figure 7 , in the present invention, a voltage of -5V is applied to the polar gate of Device 1, a voltage of -5V is applied to the polar gate of Device 2, the drain of Device 1 is connected to the driving voltage (VDD), and the source of Device 2 is grounded. Figure 8 shows the voltage transfer characteristics of the inverter at different driving voltages. When the driving voltage is 5V, a voltage gain of 67V / V is obtained ( Figure 9 ). This excellent inverter performance stems from the unique polarity reconfigurable technology of the present invention, providing a new strategy for future high-computing-power and high-density integrated circuits.

[0079] The above is only the preferred specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present invention should be covered by the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A two-dimensional reconfigurable transistor, characterized in that, Comprising: A polar gate electrode layer (2), a dielectric layer (3), a two-dimensional semiconductor layer (4), and an electrode layer (5) sequentially disposed above the substrate layer (1); the polar gate electrode layer (2) includes two polar gate electrodes (21) and a back gate electrode (22) disposed between the two polar gate electrodes (21) and not in contact with the two polar gate electrodes (21), and the two polar gate electrodes (21) are short-circuited; the electrode layer (5) includes a source current electrode (51) and a source-drain electrode (52), the source current electrode (51) and the source-drain electrode (52) are in contact with the two-dimensional semiconductor layer (4), and the source current electrode (51) and the source-drain electrode (52) are not in contact with each other; the source current electrode (51) and the source-drain electrode (52) are respectively located directly above the two polar gate electrodes (21).

2. The two-dimensional reconfigurable transistor according to claim 1, wherein The material of the substrate layer (1) is silicon / silicon dioxide; and / or, The material of the dielectric layer (3) is selected from silicon oxide, hafnium oxide, hafnium zirconium oxide, calcium fluoride, or boron nitride; and / or, The material of the two-dimensional semiconductor layer (4) is selected from tungsten disulfide, tungsten diselenide, or molybdenum ditelluride; and / or, The materials of the polar gate electrode layer (2) and the electrode layer (5) are selected from metal electrode materials or two-dimensional semimetal materials; and / or, The thicknesses of the polar gate electrode layer (2) and the electrode layer (5) are 10 - 50 nm.

3. A method for preparing a two-dimensional reconfigurable transistor according to any one of claims 1-2, characterized in that, Including the following steps: Depositing the polar gate electrode layer (2) above the substrate layer (1), and then performing oxidation cleaning; After oxidizing and cleaning the polar gate electrode layer (2), depositing the dielectric layer (3) above it; Depositing the two-dimensional semiconductor layer (4) above the deposited dielectric layer (3); Depositing the electrode layer (5) above the two-dimensional semiconductor layer (4); Wherein, the polar gate electrode layer (2) includes two polar gate electrodes (21) and a back gate electrode (22) disposed between the two polar gate electrodes (21) and not in contact with each other, and the two polar gate electrodes (21) are short-circuited; The electrode layer (5) includes a source current electrode (51) and a source-drain electrode (52), and the source current electrode (51) and the source-drain electrode (52) are not in contact with each other.

4. The preparation method according to claim 3, characterized in that, The deposition method of the polar gate electrode layer (2) includes the following steps: first, performing patterned exposure on the substrate layer (1) by an electron beam exposure process, and then preparing two polar gate electrodes (21) and a back gate electrode (22) by a thermal evaporation technique.

5. The preparation method according to claim 3, characterized in that, The deposition method of the dielectric layer (3) includes the following steps: preparing the dielectric layer (3) above the polar gate electrode layer (2) by atomic layer deposition, first performing patterned exposure on the dielectric layer (3) by an ultraviolet exposure process, and then performing etching treatment on the exposed area by plasma etching.

6. The preparation method according to claim 3, characterized in that, The deposition method of the two-dimensional semiconductor layer (4) includes the following steps: transferring the two-dimensional semiconductor layer (4) above the dielectric layer (3), first performing patterned processing on the two-dimensional semiconductor layer (4) by an electron beam exposure process, and then performing etching treatment on the exposed area by plasma etching.

7. The preparation method according to claim 3, wherein The deposition method of the electrode layer (5) comprises the following steps: firstly, performing patterned exposure on the two-dimensional semiconductor layer (4) by using an electron beam lithography process, and then preparing a source electrode (51) and a source-drain electrode (52) by using a thermal evaporation technique.

8. An application of the two-dimensional reconfigurable transistor according to any one of claims 1-2 in the field of two-dimensional logic circuits.

9. An application of the two-dimensional reconfigurable transistor according to any one of claims 1-2 in a two-dimensional reconfigurable device.

10. A method for regulating a two-dimensional reconfigurable transistor as described in any one of claims 1-2, characterized in that, Comprising: When the two-dimensional reconfigurable transistor operates, a voltage is applied to the source-drain electrode (52) and the source electrode (51) is grounded. The combination modes of the two polar gate electrodes (21) include: when the gate voltages of the two polar gate electrodes (21) are negative voltages, the hole barrier height and width at the metal-semiconductor contact interface are reduced, holes can be injected into the channel, and the transistor is regulated to be a P-type transistor; on the contrary, when the gate voltages of the two polar gate electrodes (21) are positive voltages, the electron barrier height and width at the metal-semiconductor contact interface are reduced, and an electron-dominated N-type transport can be achieved through the regulation of the two polar gate electrodes (21).

Images