Electronic device

Abstract

An electronic device includes a substrate and at least one first input / output pad, each first pad coupled to the substrate through a component, each component including a first well and a second well, the first well located in the second well, the second well located in the substrate, the substrate and the first well being doped with a first conductivity type, the first conductivity type being doped with a second conductivity type, and the second conductivity type being doped with a second conductivity type. The first well is doped with a first conductivity type, the second well is doped with a second conductivity type opposite to the first conductivity type, and each component is configured such that a threshold voltage of a diode formed by the first well and the second well is lower than a threshold voltage of a diode formed by the second well and the substrate when the first conductivity type is type P, or lower than a threshold voltage of a diode formed by the second well and the substrate when the first conductivity type is type N; the threshold voltage is higher than the threshold voltage of a diode formed by the second well and the substrate.

Description

[0001] Cross - reference to related applications

[0002] This application is a translation of French Patent Application No. 2400632, titled "Dispositif électronique", filed on January 23, 2024, and claims the benefit of its priority, which is hereby incorporated by reference in its entirety to the maximum extent permitted by law. Technical field

[0003] The present disclosure generally relates to electronic devices, and more particularly to input and output connections of electronic devices. Background art

[0004] In a semiconductor electronic device that receives an external voltage, the reference voltage is, for example, the voltage that biases the substrate thereto.

[0005] In some electronic devices, applying a voltage lower than the reference voltage causes leakage, which does not exist when a voltage higher than the reference voltage is applied. In other electronic devices, applying a voltage higher than the reference voltage causes leakage, while there is no leakage when a voltage lower than the reference voltage is applied. Summary of the invention

[0006] Embodiments overcome all or part of the disadvantages of known electronic devices.

[0007] Embodiments provide an electronic device including a substrate and at least one first input / output pad, each first input / output pad being coupled to the substrate through a component, each component including a first well and a second well, the first well being located in the second well, the second well being located in the substrate, the substrate and the first well of each component being doped with a first conductivity type, the second well of each component being doped with a second conductivity type opposite to the first conductivity type, each component being configured such that the threshold voltage of the diode formed by the first and second wells of the component: (i) is lower than the threshold voltage of the diode formed by the second well and the substrate when the first conductivity type is type P, or (ii) is higher than the threshold voltage of the diode formed by the second well and the substrate when the first conductivity type is type N.

[0008] According to an embodiment, the first well of each component is coupled to the substrate through an element external to the substrate.

[0009] According to an embodiment, the first well of each component is coupled to the substrate through a wire element.

[0010] According to an embodiment, the device includes at least two first input / output pads.

[0011] According to an embodiment, the first well of each component is separated from the substrate by the second well of the same component.

[0012] According to an embodiment, the device includes a second input / output pad coupled to a substrate through a component, and the second pad is configured to receive a reference voltage.

[0013] According to an embodiment, the reference voltage is a zero potential.

[0014] According to an embodiment, the first input / output pad is coupled to an electronic circuit.

[0015] According to an embodiment, the electronic circuit includes a bipolar transistor. Description of the Drawings

[0016] The foregoing features and advantages, as well as other features and advantages, will be described in detail in the remainder of the present disclosure of specific embodiments given in a non-limiting illustrative manner with reference to the accompanying drawings, in which:

[0017] Figure 1 An electronic device according to an embodiment is shown; and

[0018] Figure 2 Is schematically shown Figure 1 of the device. Detailed Description

[0019] Like features are denoted by like reference numerals in the various drawings. In particular, structural and / or functional features common between the various embodiments may have the same reference numerals and may have the same structure, dimensions, and material properties.

[0020] For clarity, only the steps and elements useful for understanding the described embodiments are illustrated and described in detail.

[0021] Unless otherwise specified, when referring to two elements being connected together, this means a direct connection without any intermediate element other than a conductor, and when referring to two elements being coupled together, this means that the two elements may be connected or they may be coupled via one or more other elements.

[0022] In the following description, when referring to terms defining absolute positions (such as the terms "front", "rear", "top", "bottom", "left", "right", etc.) or terms defining relative positions (such as the terms "upper", "lower", "upper part", "lower part", etc.) or terms defining directions (such as the terms "horizontal", "vertical", etc.), unless otherwise specified, it refers to the orientation of the drawings.

[0023] Unless otherwise specified, the expressions "about", "approximate", "substantially", and "approximately" mean plus or minus 10%, preferably plus or minus 5%.

[0024] Figure 1 An electronic device 10 according to an embodiment is shown.

[0025] The device 10 corresponds to, for example, an electronic chip. The device 10 includes a semiconductor substrate 12. The substrate 12 is made of, for example, silicon. The substrate 12 is doped with a first conduction type (e.g., P-type).

[0026] The device 10 includes at least one electronic circuit 14. The circuit 14 is configured, for example, to perform at least one function. The circuit 14 is, for example, a power management circuit. More precisely, the device 10 includes electronic components forming the circuit 14. The electronic components of the circuit 14 are formed, for example, inside and on top of the substrate 12. The device 10 is an electronic control device, for example, intended to be integrated into electrical, electromechanical, or optoelectronic devices. The device 10 is, for example, intended to be integrated into industrial devices, household appliances, or automotive devices for controlling such devices. The device 10 is, for example, suitable for controlling devices via a wired bus of the LIN or CAN type. The device 10 is, for example, suitable for controlling devices according to the IEC61131-2 standard.

[0027] The circuit 14 is coupled to at least one input / output pad 16, preferably an input pad. In Figure 1 the example, the circuit 14 is connected to two input / output pads 16a and 16b. Each of the two input / output pads 16 is configured, for example, to receive an input voltage. Similarly, the circuit 14 is configured to receive an input voltage. For example, at least one pad 16 is coupled to (preferably connected to) the terminal of a transistor (e.g., a bipolar transistor, a MOSFET transistor, or other types of transistors) of the circuit 14.

[0028] The device 10 further includes an input / output pad 16c. The pad 16c is configured to receive a reference voltage, such as ground. The pad 16c is configured, for example, to receive zero potential.

[0029] Each input pad 16 is also coupled to the substrate 12 via a component 18. More specifically, the pad 16a is coupled to the substrate 12 via a component 18a. The pad 16b is coupled to the substrate 12 via a component 18b. The pad 16c is coupled to the substrate 12 via a component 18c. Preferably, the device 10 does not include input / output pads directly connected to the substrate 12.

[0030] Each component 18 includes a first well 20. The well is located in the substrate 12. The well 20 is preferably flush with the upper surface of the substrate 12. The well 20 is made of a semiconductor material (e.g., the same material as the substrate 12). The well 20 is doped with a conduction type opposite to that of the substrate 12. The well 20 is, for example, N-doped.

[0031] Each component 18 also includes a well 22 located within well 20. Well 22 is preferably flush with the upper surface of well 20. The upper surface of substrate 12 and the upper surfaces of wells 20 and 22 are, for example, coplanar. Except for its upper surface, well 22 is, for example, completely surrounded by well 20. Well 22 is completely separated from substrate 12 by well 20. Well 22 is made of semiconductor material (e.g., the same material as substrate 12 and well 20). Well 22 is doped with a conductivity type opposite to that of well 20 (i.e., the same conductivity type as substrate 12). Well 22 is, for example, P-type doped.

[0032] Thus, component 18a includes wells 20 and 22 (designated by reference numerals 20a and 22a), such as those described previously. Component 18b includes wells 20 and 22 (designated by reference numerals 20b and 22b), such as those described previously. Component 18c includes wells 20 and 22 (designated by reference numerals 20c and 22c), such as those described previously.

[0033] Each component 18 also includes a contact 24. Contact 24 is located within well 20 of the same component 18. Contact 24 corresponds, for example, to a region of well 20 of the same component that is more heavily doped than the remainder of well 20. Contact 24 is coupled (preferably connected) to pad 16 associated with component 18 to which contact 24 belongs. Contact 24 of at least some of the components 18 (e.g., all components except component 18c) is, for example, coupled (preferably connected) to circuit 14. Thus, well 20 of each component 18 is biased to the voltage delivered on pad 16 associated with component 18.

[0034] Each component 18 also includes a contact 26. Contact 26 is located within well 22 of the same component 18. Contact 26 corresponds, for example, to a region of well 22 of the same component that is more heavily doped than the remainder of well 22.

[0035] Each component 18 also includes a contact 28. Contact 28 is located in substrate 12, for example, around well 20. Contact 28 corresponds, for example, to a region of substrate 12 (e.g., the region of the substrate around well 20) that is more heavily doped than the remainder of substrate 12.

[0036] The regions forming contacts 26 and 28 of the same component 18 are coupled (preferably, connected) by a connection element external to substrate 12. For example, the regions forming contacts 26 and 28 of the same component 18 are coupled (preferably, connected) by wire connection element 30 (e.g., a metal wire).

[0037] At Figure 1In the case of the device 10, the component 18a includes contact portions 24, 26, and 28 denoted by reference numerals 24a, 26a, and 28a, respectively, and a connection element 30 denoted by reference numeral 30a, such as those described previously. The component 18b includes contact portions 24, 26, and 28 denoted by reference numerals 24b, 26b, and 28b, respectively, and a connection element 30 denoted by reference numeral 30b, such as those described previously. The component 18c includes contact portions 24, 26, and 28 denoted by reference numerals 24c, 26c, and 28c, respectively, and a connection element 30 denoted by reference numeral 30c, such as those described previously.

[0038] A PN junction between the wells 20 and 22 in the same component 18 (i.e., a PN junction formed at the interface between the wells 20 and 22 in the same component 18) forms a diode 32. Similarly, a PN junction between the well 20 of the component and the substrate 12 surrounding the component 18 (i.e., a PN junction formed at the interface between the well 20 of the component and the substrate 12 surrounding the component 18) forms a so-called parasitic diode 34. By way of illustration, the diodes 32 and 34 are schematically represented by their symbols in Figure 1 the figure.

[0039] In Figure 1 the example shown, the doping levels of the substrate 12 and the wells 20 and 22 are selected such that the saturation current of the diode 32 in the component 18 is at least ten times greater than the saturation current of the diode 34 in the same component. For example, the PN junction between the wells 20 and 22 in the same component 18 is configured to be abrupt, while the junction between the well 20 of this component and the substrate 12 is configured to be more gradual.

[0040] Figure 2 Schematically shows Figure 1 the device 10.

[0041] Similar to Figure 1 that, Figure 2 shows the substrate 12 and the circuit 14 located in the substrate 12. Figure 2 Also shown are the input / output pads 16, more precisely, Figure 1 the pads 16a, 16b, and 16c in Figure 1 the figure. Similar to

[0042] that in Figure 1 the figure, the pad 16c is coupled to a source of reference voltage (e.g., external to the substrate 12). Figure 2 As in

[0043] The diodes 32 and 34 of component 18 are coupled in parallel between node 36 and node 38. Accordingly, diodes 32a and 34a are coupled in parallel between node 36a and node 38a. Diodes 32b and 34b are coupled in parallel between node 36b and node 38b. Diodes 32c and 34c are coupled in parallel between node 36c and node 38c. Each node 36 is coupled (preferably, connected) to pad 16 associated with component 18. Each node 38 is coupled (preferably, connected) to substrate 12. Accordingly, the cathodes of diodes 32 and 34 of the component are coupled (preferably, connected) together and are coupled (preferably, connected) to pad 16 associated with the component. The anodes of diodes 32 and 34 of the component are coupled (preferably, connected) together and are coupled (preferably, connected) to substrate 12.

[0044] The cathodes of diodes 32 and 34 of component 18 are formed by well 20 of component 18. The anode of diode 34 of the component is formed by substrate 12. The anode of diode 32 is formed by well 22. The coupling between the anode of diode 32 and substrate 12 is formed by connection element 30 of the component.

[0045] As described in connection with Figure 1 the threshold voltage of diode 32 is lower than the threshold voltage of diode 34. Accordingly, during operation of device 10, substrate 12 is biased to the lowest voltage among the voltages received on pad 16. Accordingly, the ground of circuit 14 is the lowest voltage among the voltages delivered on pad 16. The potential difference between pads 16 (e.g., the potential difference between pad 16a or 16b and pad 16c) remains the same. However, all voltages are positive voltages.

[0046] It may have been chosen not to provide component 18 in device 10, thereby coupling pad 16c directly to substrate and coupling the other pads directly to circuit 14. However, in this case, when a negative voltage is applied to circuit 14 and particularly to a bipolar transistor, a high leakage current will be formed between the bipolar transistor and substrate.

[0047] According to other embodiments (not shown), the conduction type may be reversed. Accordingly, in this other embodiment, substrate 12 is N-doped, well 20 is P-doped, and well 22 is N-doped. Then the doping levels of diode 32 and wells 20, 22, and substrate 12 are configured such that the saturation current of diode 32 is at least ten times greater than the saturation current of diode 34. For example, this embodiment is applicable to a device in which applying a positive voltage results in a more significant leakage current than applying a negative voltage. For example, the device includes an NPN-type bipolar transistor in circuit 14.

[0048] One advantage of the described embodiment is that the device generates less leakage current.

[0049] Various embodiments and variations have been described. Those skilled in the art will understand that certain features of these various embodiments and variations can be combined, and other variations will occur to those skilled in the art.

[0050] Finally, based on the functional indications given above, the actual implementation of the described embodiments and variations is within the capabilities of those skilled in the art.

Claims

1. An electronic device, comprising: a substrate; and at least one first input / output pad, each first input / output pad being coupled to the substrate through a component, each component including a first well and a second well, the first well being located in the second well, the second well being located in the substrate, the substrate and the first well of each component being doped with a first conductivity type, the second well of each component being doped with a second conductivity type opposite to the first conductivity type, each component being configured such that the threshold voltage of the diode formed by the first well and the second well of the component: (i) is lower than the threshold voltage of the diode formed by the second well and the substrate when the first conductivity type is type P, or (ii) is higher than the threshold voltage of the diode formed by the second well and the substrate when the first conductivity type is type N.

2. The device according to claim 1, wherein the first well of each component is coupled to the substrate through an element external to the substrate.

3. The device according to claim 2, wherein the first well of each component is coupled to the substrate through a wire element.

4. The device according to claim 1, wherein the device includes at least two first input / output pads.

5. The device according to claim 1, wherein the first well of each component is separated from the substrate by the second well of the same component.

6. The device according to claim 1, wherein the device includes a second input / output pad coupled to the substrate through a component, the second pad being configured to receive a reference voltage.

7. The device according to claim 6, wherein the reference voltage is a zero potential.

8. The device according to claim 1, wherein the at least one first input / output pad is coupled to an electronic circuit.

9. The device according to claim 8, wherein the electronic circuit includes a bipolar transistor.

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