Barrier structure, preparation method and display chip

Abstract

The invention provides a barrier structure, a preparation method and a display chip, and the barrier structure at least comprises a first passivation layer which at least covers the side surface of a light-emitting mesa, and the first passivation layer is made of phosphide; the second passivation layer is located on the side, away from the light-emitting table top, of the first passivation layer, and the material of the second passivation layer is different from that of the first passivation layer. The side face of the light-emitting table top is coated with the double passivation layers, chemical corrosion can be reduced, physical damage can be prevented, the stability of the micro light-emitting diode is improved, and the service life is prolonged.

Description

Technical Field

[0001] The present invention generally relates to the field of display chip technology, and more specifically, to a barrier structure, a preparation method, and a display chip. Background Art

[0002] Micro Light Emitting Diode (Micro-LED) is an emerging display technology. By miniaturizing traditional light emitting diodes, their size reaches the micron level, and these tiny LED arrays are integrated onto a chip, enabling the formation of a high-density display chip. As a semiconductor component that is small in size and capable of emitting light, the micro light emitting diode device has advantages such as low power consumption, long lifespan, high brightness, and high contrast. With the gradual development of display technology, micro light emitting diode technology has gradually become a trend in new display technologies and has received increasing attention.

[0003] In micro light emitting diodes, the light emitting mesa, as a core component, is of self-evident importance. To effectively protect the light emitting mesa, the industry generally uses the method of coating a passivation layer on its side, which can significantly enhance the stability of micro light emitting diodes and extend their service life. However, currently, there is still room for improvement in the long-term stability and service life of existing micro light emitting diode devices, and further optimization is urgently needed. Summary of the Invention

[0004] To solve at least some of the above problems in the prior art, the task of the present invention is to provide a barrier structure, which at least includes:

[0005] A first passivation layer that at least coats the side of the light emitting mesa, and the material of the first passivation layer is a phosphide; and

[0006] A second passivation layer located on the side of the first passivation layer away from the light emitting mesa, where the material of the second passivation layer is different from that of the first passivation layer.

[0007] Further, the phosphide is a single-metal phosphide.

[0008] Further, the single-metal phosphide is InP or GaP or AlP or GeP.

[0009] Further, the material of the phosphide is a multi-metal phosphide.

[0010] Further, the multi-metal phosphide is AlInP or AlGaInP or InGaP.

[0011] Further, the material of the second passivation layer is an oxide, and the oxide is SiO2 or Al2O3 or Al2O3 or TiO2 or Ti2O5 or MgO or ZnO or HFO2; or

[0012] The material of the second passivation layer is a nitride, and the nitride is one of silicon nitride, silicon oxynitride, and aluminum nitride.

[0013] Further, the barrier structure further includes a third passivation layer, a fourth passivation layer,..., an nth passivation layer, where n is a positive integer and n is not less than 3;

[0014] The third passivation layer to the nth passivation layer are located between the first passivation layer and the second passivation layer; or

[0015] The third passivation layer to the nth passivation layer are located on the side of the second passivation layer away from the first passivation layer.

[0016] Further, the material of the third passivation layer to the nth passivation layer is an oxide, and the oxide is one of SiO2 or Al2O3 or Al2O3 or TiO2 or Ti2O5 or MgO or ZnO or HFO2.

[0017] Or the material of the third passivation layer to the nth passivation layer is a nitride, and the nitride is one of silicon nitride, silicon oxynitride, and aluminum nitride.

[0018] Further, among the second passivation layer to the nth passivation layer, the materials of adjacent passivation layers are different.

[0019] Further, it includes but is not limited to the following parameters:

[0020] The thickness range of the first passivation layer is 0.5 - 1000 nm;

[0021] The thickness range of the second passivation layer is 0.5 - 1000 nm;

[0022] The refractive index range of the first passivation layer is 1.2 - 4;

[0023] The refractive index range of the second passivation layer is 1.2 - 4.

[0024] The present invention also provides a display chip, including the above barrier structure.

[0025] Further, it further includes a conductive layer, which is located under the light-emitting mesa and is electrically connected to the light-emitting mesa.

[0026] Further, the barrier structure at least covers the sides of the light-emitting mesa and the conductive layer.

[0027] Further, the light-emitting mesa includes:

[0028] Light-emitting layer;

[0029] A first-type epitaxial layer, which is located under the light-emitting layer, the first-type epitaxial layer is a semiconductor material with a first conductivity type, and includes a plurality of semiconductor layers;

[0030] A second-type epitaxial layer, which is located above the light-emitting layer, the second-type epitaxial layer is a semiconductor material with a second conductivity type, and includes a plurality of semiconductor layers, wherein the second conductivity type is different from the first conductivity type.

[0031] Furthermore, the light-emitting layer is a quantum well layer.

[0032] Furthermore, the material of the light-emitting layer is InGaP or AlInP or AlGaInP; the first-type epitaxial layer includes a P-type AlGaInP layer, a P-type Mg-doped AlInP layer, and a GaP layer from top to bottom; and

[0033] The second-type epitaxial layer includes an N-type GaAs layer, an N-type AlGaInP layer, and an N-type Si-doped AlInP layer from top to bottom.

[0034] Furthermore, the bottom lateral dimension of the light-emitting mesa is smaller than the top lateral dimension;

[0035] The tops of the second-type epitaxial layers of adjacent light-emitting mesas are connected to each other.

[0036] Furthermore, the top of the second-type epitaxial layer includes a rough structure, wherein the rough structure is a convex structure regularly or irregularly distributed on the top of the second-type epitaxial layer.

[0037] Furthermore, the morphology of the convex structure is columnar, conical or hemispherical.

[0038] Furthermore, it further includes an upper electrode layer, which is electrically connected to the second-type epitaxial layer.

[0039] Furthermore, the upper electrode layer surrounds a plurality of the light-emitting mesas, and adjacent upper electrode layers are connected, and all the upper electrode layers are connected into a whole.

[0040] Furthermore, it further includes a microlens, which is arranged on the top of the light-emitting mesa, and adjacent microlenses are connected.

[0041] Furthermore, the material of the conductive layer is one or a combination of graphene, indium tin oxide, aluminum-doped zinc oxide, and fluorine-doped tin oxide; and / or

[0042] The material of the upper electrode layer is one or a combination of conductive metal, graphene, indium tin oxide, aluminum-doped zinc oxide, or fluorine-doped tin oxide.

[0043] Further, a reflective layer is further included, which is located on the surface of the barrier structure and the conductive layer away from the light-emitting mesa, and the material of the reflective layer is metal.

[0044] Further, the second-type epitaxial layer has a convex portion, which is located under the upper electrode layer, and the shape of the convex portion is the same as that of the upper electrode layer.

[0045] Further, it further includes:

[0046] A substrate, which is located below the light-emitting mesa;

[0047] A bonding layer, which is located between the substrate and the light-emitting mesa, wherein the bonding layer includes a first bonding layer and a second bonding layer, the second bonding layer is located on the substrate, and the first bonding layer fills the gaps between the light-emitting mesas.

[0048] Further, it further includes:

[0049] A first reflective layer, which is formed on the surface of the conductive layer away from the light-emitting mesa, and the first reflective layer is electrically connected to the conductive layer;

[0050] A second reflective layer, which is formed on the surface of the barrier structure away from the light-emitting mesa.

[0051] Further, the first reflective layer and the second reflective layer are not connected;

[0052] Adjacent second reflective layers are connected;

[0053] The materials of the first reflective layer and the second reflective layer are metal.

[0054] Further, the barrier structure covers the sides of the light-emitting mesa, the conductive layer, and the first reflective layer.

[0055] Further, it further includes: a lower electrode structure, which is located under the first reflective layer and is electrically connected to the first reflective layer.

[0056] Further, it further includes:

[0057] A driving backplane, which includes a substrate and a driving circuit located in the substrate;

[0058] A driving conductive structure, which is located on the driving backplane and is electrically connected to the driving circuit.

[0059] Further, it further includes: a first conductive structure, which is electrically connected to the driving conductive structure and the lower electrode structure, and the first conductive structure is bonded to the lower electrode structure.

[0060] Further, it further includes: a protective layer, which is located between the driving conductive structure and the first conductive structure.

[0061] Further, the materials for bonding the protective layer, the driving conductive structure, the first conductive structure and the lower electrode structure are metals.

[0062] Further, it further includes:

[0063] an insulating dielectric layer, which fills the gap between the driving conductive structures;

[0064] a bonding layer, which is located between the driving backplane and the light-emitting mesa, and fills the gaps between the first conductive structures, the gaps between the lower electrode structures and the gaps between the light-emitting mesas.

[0065] Further, the bonding layer includes a first bonding layer and a second bonding layer, which are bonded to each other, wherein the first bonding layer fills the gaps between the lower electrode structures and the gaps between the light-emitting mesas, and the second bonding layer fills the gaps between the first conductive structures.

[0066] Further, the material of the insulating dielectric layer is a solid inorganic material or a plastic material;

[0067] The material of the bonding layer is a solid inorganic material.

[0068] Further, the bottom lateral dimension of the light-emitting mesa is larger than the top lateral dimension.

[0069] Further, it further includes:

[0070] a driving backplane, which includes:

[0071] a substrate;

[0072] a driving circuit, which is located in the substrate; and

[0073] a contact pad, which is located in the substrate, and its upper surface exposes the substrate and is electrically connected to the driving circuit; and

[0074] a lower electrode layer, which is located between the conductive layer and the driving backplane and is electrically connected to the conductive layer and the driving backplane.

[0075] Further, the lower electrode layer is a metal bonding composite layer, and the light-emitting mesa is bonded to the driving backplane through the lower electrode layer.

[0076] Further, the barrier structure at least covers the side surfaces of the light-emitting mesa, the conductive layer, and the lower electrode layer.

[0077] The present invention also provides a microdisplay device including the above barrier structure.

[0078] The present invention also provides a display system including the above barrier structure.

[0079] The present invention also provides a near-eye display device, characterized by including the above barrier structure.

[0080] The present invention also provides a method for preparing a barrier structure, including:

[0081] Forming a first passivation layer that at least covers the side surface of the light-emitting mesa; and

[0082] Forming a second passivation layer on a side of the first passivation layer away from the light-emitting mesa.

[0083] Further, the first passivation layer is formed by an epitaxial growth method, and the first passivation layer is indium phosphide or gallium phosphide.

[0084] Further, the epitaxial growth method includes molecular beam epitaxy or metalorganic chemical vapor deposition.

[0085] Further, a plasma-enhanced chemical vapor deposition method is used to form the second passivation layer, and the second passivation layer is silicon nitride or silicon oxynitride; or

[0086] The second passivation layer is formed by sputtering or chemical vapor deposition, and the second passivation layer is aluminum nitride.

[0087] The present invention has at least the following beneficial effects:

[0088] Using a double-layer passivation layer to cover the side surface of the light-emitting mesa can reduce chemical corrosion and prevent physical damage, improve the stability of the micro light-emitting diode, and increase the service life;

[0089] The first passivation layer in the double-layer passivation layer is a phosphide passivation layer, which can reduce the surface refractive index and increase light reflection. The second passivation layer in the double-layer passivation layer can protect the first passivation layer;

[0090] The first passivation layer is a non-doped material homologous to the light-emitting mesa, which can better fill the defects on the surface of the light-emitting mesa, reduce the surface state density, reduce the surface recombination rate, and thus improve the light-emitting efficiency. Description of the Drawings

[0091] The present invention will be further described below with reference to the specific embodiments and the accompanying drawings.

[0092] Figure 1AA cross-sectional schematic view of a micro light-emitting diode structure of a display chip according to an embodiment of the present invention is shown.

[0093] Figure 1B A top-view schematic view of a 4×4 micro light-emitting diode structure surrounded by an upper electrode layer according to an embodiment of the present invention is shown.

[0094] Figure 2 A cross-sectional schematic view of a micro light-emitting diode structure of a display chip according to another embodiment of the present invention is shown.

[0095] Figure 3 A cross-sectional schematic view of a micro light-emitting diode structure according to still another embodiment of the present invention is shown. Detailed implementation manners

[0096] It should be noted that the components in the respective figures may be exaggeratedly shown for illustration purposes and are not necessarily to scale. In the respective figures, the same or functionally identical components are provided with the same reference numerals.

[0097] In the present invention, unless otherwise specified, "arranged on", "arranged above", and "arranged over" do not exclude the situation that there is an intermediate object between the two. In addition, "arranged on or above" only represents the relative positional relationship between the two components, and in certain cases, such as after reversing the product direction, it can also be converted to "arranged under or below", and vice versa.

[0098] In the present invention, the respective embodiments are only intended to illustrate the solutions of the present invention and should not be construed as restrictive.

[0099] In the present invention, unless otherwise specified, the quantifiers "a" and "one" do not exclude the scenario of multiple elements.

[0100] In the present invention, the term "connected" can refer to both direct connection between the two and indirect connection between the two through an intermediate element.

[0101] In the present invention, the term "configured" means setting the shape, structure, material, and / or function of an object to achieve the desired technical effect, where "configured" includes various alternative technical means for achieving the technical effect, and these technical means become obvious under the teachings of the present invention.

[0102] It should also be noted here that, in the embodiments of the present invention, for the sake of clarity and simplicity, only a part of the components or assemblies may be shown. However, those of ordinary skill in the art can understand that, under the teaching of the present invention, the required components or assemblies can be added according to the specific scenario requirements. In addition, unless otherwise specified, the features in different embodiments of the present invention can be combined with each other. For example, a certain feature in the second embodiment can be used to replace the corresponding or functionally identical or similar feature in the first embodiment, and the obtained embodiment also falls within the scope of disclosure or the scope of recording of this application.

[0103] It should also be noted here that within the scope of the present invention, terms such as "identical", "equal", "equivalent" do not mean that the two values are absolutely equal, but allow a certain reasonable error. That is to say, these terms also cover "substantially identical", "substantially equal", "substantially equivalent". By analogy, in the present invention, terms indicating directions such as "perpendicular to" and "parallel to" also cover the meanings of "substantially perpendicular to" and "substantially parallel to".

[0104] The main function of the barrier structure (passivation layer) is to protect the micro light-emitting diode device, especially the light-emitting mesa, from being damaged by the external environment, such as moisture, oxygen, and mechanical stress, etc., which helps to extend the service life of the micro light-emitting diode and improve its long-term stability.

[0105] Traditional passivation layers often use SiO2. However, due to the porous structure of SiO2 itself, its ability to resist the migration of mobile charges and the penetration of impurities is poor, and moisture and oxygen are likely to penetrate through SiO2 and corrode the light-emitting mesa. Therefore, the stability and service life of micro light-emitting diodes need to be improved.

[0106] Figure 1A A cross-sectional schematic diagram of the micro light-emitting diode structure of a display chip according to an embodiment of the present invention is shown. Figure 1B A top view schematic diagram of a 4×4 micro light-emitting diode structure surrounded by an upper electrode layer according to an embodiment of the present invention is shown.

[0107] As Figure 1A shown, a display chip includes a substrate 110 and a micro light-emitting diode array located on the substrate. The micro light-emitting diode array includes a plurality of micro light-emitting diode structures. The micro light-emitting diode structure includes a reflective layer 120, a conductive layer 130, a light-emitting mesa 140, an upper electrode layer 150, a barrier structure 160, a microlens 170, and a bonding layer 180.

[0108] A micro light-emitting diode is a basic element that constitutes a micro light-emitting diode pixel. Each micro light-emitting diode pixel may include one or more micro light-emitting diode structures. A plurality of micro light-emitting diode pixels are arranged in an array to form a microdisplay chip (micro light-emitting diode chip). For example, each pixel in a color micro light-emitting diode chip may include a plurality of micro light-emitting diode structures of different colors, while each pixel in a monochromatic micro light-emitting diode chip may include only one color of micro light-emitting diode structure.

[0109] In some embodiments, the length and width of the light-emitting area of the display chip range from a few millimeters to one hundred micrometers, and the light-emitting area includes a plurality of micro light-emitting diode structures arranged in an array.

[0110] The micro light-emitting diode structures are formed in an array in the microdisplay chip, and the resolution is, for example, 720*480, 640*480, 1920*1080, 1280*720, 2K or 4K. The diameter of the micro light-emitting diode structures is at the nanometer level, for example, 20nm to 100nm. In some embodiments, the pitch of the micro light-emitting diode array, that is, the minimum center-to-center distance between the micro light-emitting diodes, may be between about 2 micrometers and about 50 micrometers. In some embodiments, the number of pixels on the micro light-emitting diode chip may be between several thousand and several million.

[0111] In some embodiments, the substrate 110 is a Si substrate. In other embodiments, the substrate 110 is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates.

[0112] The light-emitting mesa 140 includes a first-type epitaxial layer 141, a second-type epitaxial layer 143, and a light-emitting layer 142 located therebetween. The first-type epitaxial layer 141 is electrically connected to the conductive layer 130. The second-type epitaxial layer 143 is electrically connected to the upper electrode layer 150. The cross-sectional shape of the light-emitting mesa 140 is an inverted trapezoid. The lateral dimension of the bottom of the light-emitting mesa 140 is smaller than the lateral dimension of the top. There is an inclination angle between the side wall of the light-emitting mesa 140 and the bottom of the light-emitting mesa 140, and the inclination angle is greater than or equal to 90°. In one embodiment, the inclination angle range of the side wall of the light-emitting mesa 140 is: 90° to 135°.

[0113] In some embodiments, the tops of the second-type epitaxial layers 143 of adjacent light-emitting mesa 140 are connected to each other. In some embodiments, the tops of the second-type epitaxial layers 143 include a rough structure 1431. The rough structure 1431 is fabricated on the surface of the second-type epitaxial layer 143 by a dry etching process, a wet etching process, or a nanoimprint technique, increasing the randomness of the angles of the light emitted from the interface between the second-type epitaxial layer 143 and the microlens material or other encapsulation materials, reducing the probability of total internal reflection of light, and thus improving the light extraction efficiency. In some embodiments of the present invention, the rough structure 1431 may be a convex structure regularly or irregularly distributed on the top of the second-type epitaxial layer 143. The morphology of the convex structure may be a columnar protrusion, a conical protrusion, a hemispherical protrusion, and so on. In some embodiments of the present invention, the size of the rough structure 1431 should at least reach the nanometer level.

[0114] In some embodiments, the light-emitting mesa of each micro light-emitting diode in the micro light-emitting diode array may be a micro-meter-level light-emitting mesa. In the three-layer structure, the first-type epitaxial layer 141 is the closest to the substrate 110; the light-emitting layer 142 is located above the first-type epitaxial layer and is farther from the substrate 110; the second-type epitaxial layer 143 is located above the light-emitting layer 142 and is the farthest from the substrate 110.

[0115] In some embodiments, the light-emitting layer 142 is formed by a plurality of stacked quantum well layers, particularly superlattice-stacked quantum well layers. Preferably, the superlattice-stacked quantum well layers include multiple pairs of quantum well layers stacked with quantum barrier layers.

[0116] In some embodiments, the first-type epitaxial layer 141 is a semiconductor material of a first conductivity type and includes a plurality of semiconductor layers. The main matrix material of the first-type epitaxial layer 141 may be, but is not limited to, composed of materials such as Ga, N, As, P, In, or Al. In addition, the first-type epitaxial layer 141 may include, but is not limited to, a waveguide layer, a confinement layer, a transition layer, and a window layer from top to bottom; in addition, an ohmic contact layer may be formed below the window layer. In some embodiments, the second-type epitaxial layer 143 is a semiconductor material of a second conductivity type and includes a plurality of semiconductor layers. The main matrix material of the second-type epitaxial layer 143 may be, but is not limited to, composed of materials such as Ga, N, As, P, In, or Al. In addition, the second-type epitaxial layer 143 may include, but is not limited to, a confinement layer and a waveguide layer from top to bottom; in addition, in some embodiments, an ohmic contact layer may be formed on the confinement layer. In one embodiment, the first conductivity type is different from the second conductivity type.

[0117] In some embodiments, the first type of epitaxial layer 141 is an N-type GaN layer or an N-type AlGaN layer, and the second type of epitaxial layer 143 is a P-type GaN layer or a P-type AlGaN layer. That is, the material of the second type of epitaxial layer 143 can be a material layer of the second conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P, and the first type of epitaxial layer 141 can be a material layer of the first conductive type composed of at least two or more elements including Ga, N, As, Al, In, and P. In some embodiments, the light-emitting layer 142 includes a multi-quantum well layer and an electron blocking layer. The multi-quantum well layer is an InGaN / GaN multi-quantum well layer or an InGaN / AlGaN multi-quantum well layer or an InGaAs / AlGaAs multi-quantum well layer. In some embodiments, the light-emitting layer 142 further includes an electron blocking layer, and the electron blocking layer is disposed on the first side of the light-emitting layer. The first side refers to the side along which electrons migrate out of the light-emitting layer. In another embodiment, the first type of epitaxial layer 141 can also be a P-type GaN layer or a P-type AlGaN layer, and the second type of epitaxial layer 143 is an N-type GaN layer or an N-type AlGaN layer.

[0118] In some embodiments, the light-emitting layer 142 includes at least one quantum well layer. The thickness of the quantum well layer is between 20 nm and 40 nm, for example, the thickness is 30 nm. In some embodiments, the material of the quantum well layer is GaInP / (Al x Ga 1-x ) y In 1-y P, where the range of x is 0.5 to 0.9, and the range of y is 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y.

[0119] In some embodiments, one of the first type of epitaxial layer 141 and the second type of epitaxial layer 143 is an N-type semiconductor layer, and the other is a P-type semiconductor layer. In some embodiments, the N-type semiconductor layer further includes a doped N-type contact layer and an N-type cladding layer, and the N-type cladding layer is formed on the doped N-type contact layer. The material of the N-type cladding layer is Al x In 1-x P, where the range of x is 0.1 to 0.5, for example, x is 0.5. In addition, in these embodiments, the thickness of the N-type cladding layer is not greater than 350 nm. For example, the thickness of the N-type cladding layer is 320 nm. The doping concentration of the N-type cladding layer is 5e 17 cm -3 to 1e 18 cm -3。The material of the doped N-type contact layer is GaAs. In some embodiments, the thickness of the doped N-type contact layer is 10 nm to 30 nm. In some embodiments, the doping concentration of the doped N-type contact layer is 2e 18 cm -3 to 1e 19 cm -3 。In some embodiments, the N-type semiconductor layer further includes an N-type spacer layer formed on the N-type cladding layer. The material of the N-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is 0.5 to 0.9 and the range of y is 0.1 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. The thickness of the N-type spacer layer is 50 nm to 75 nm, for example 65 nm.

[0120] In some embodiments, the P-type semiconductor layer includes a P-type cladding layer and a doped P-type contact layer. The P-type cladding layer is formed on the light-emitting layer, and the doped P-type contact layer is formed on the P-type cladding layer. In some embodiments, the material of the P-type cladding layer is Al x In 1-x P, where x is 0.3 to 0.5, for example x is 0.5. In such embodiments, the thickness of the P-type cladding layer is not greater than 380 nm. For example, the thickness of the P-type cladding layer is 360 nm. In some embodiments, the material of the doped P-type contact layer is GaAs. The thickness of the doped P-type contact layer is 10 nm to 30 nm, for example 20 nm.

[0121] In some embodiments, the P-type semiconductor layer further includes a P-type spacer layer formed under the P-type cladding layer, a first doped P-type transition layer formed on the P-type cladding layer, and a second doped P-type transition layer formed on the first doped P-type transition layer. In some embodiments, the material of the P-type spacer layer is (Al x Ga 1-x ) y In 1-y P, where the range of x is 0.5 to 0.9 and the range of y is 0.3 to 0.5. For example, x is 0.8 and y is 0.5. In some embodiments, the relationship between x and y is that x is 1 to 2 times y. In some embodiments, the thickness of the P-type spacer layer is 50 nm to 70 nm, for example 65 nm.

[0122] In some embodiments, the material of the first doped P-type transition layer is (Al x Ga 1-x ) y In 1-yP, where the range of x is from 0.1 to 0.3, and the range of y is from 0.3 to 0.5. For example, x is 0.17 and y is 0.5. In some embodiments, the relationship between x and y is that y is 1 to 5 times of x. In some embodiments, the thickness of the first doped P-type transition layer is from 20 nm to 40 nm, such as 30 nm.

[0123] In some embodiments, the material of the second doped P-type transition layer is Al x Ga 1-x As, where the range of x is from 0.5 to 0.9, such as x is 0.6. In some embodiments, the thickness of the second doped P-type transition layer is from 10 nm to 30 nm, such as 20 nm.

[0124] In some embodiments, the doping concentration of the second doped P-type transition layer is greater than the doping density of the first doped P-type transition layer. The doping concentration of the doped P-type contact layer is 1 to 10 times that of the second doped P-type transition layer.

[0125] In some embodiments, the doping concentration of the doped P-type contact layer is greater than that of the second doped P-type transition layer. In addition, in some embodiments, the doping concentration of the second doped P-type transition layer is 2 to 4 times that of the first doped P-type transition layer.

[0126] For example, the doping concentration of the first doped P-type transition layer is greater than 1e 18 cm -3 , the doping density of the second doped P-type transition layer is in the range of 2e 18 cm -3 -4e 18 cm -3 and the doping density of the doped P-type contact layer is greater than 5e 18 cm -3 .

[0127] In some embodiments, the material of the quantum well layer is InGaP or AlInP or AlGaInP. In some embodiments, the first type of epitaxial layer 141 is a P-type semiconductor layer, and the first type of epitaxial layer 141 includes a P-type AlGaInP layer, a P-type AlInP layer doped with Mg, and a GaP layer from top to bottom. In some embodiments, the second type of epitaxial layer 143 is an N-type semiconductor layer, and the second type of epitaxial layer 143 includes an N-type GaAs layer, an N-type AlGaInP layer, and an N-type AlInP layer doped with Si from top to bottom. In other embodiments, the materials of the first type of epitaxial layer 141 and the second type of epitaxial layer 143 can be interchanged, the first type of epitaxial layer 141 is an N-type semiconductor layer, and the second type of epitaxial layer 143 is a P-type semiconductor layer.

[0128] In some embodiments, the light-emitting mesa 140 can emit red light, blue light, green light, or light of any other color.

[0129] In some embodiments, the conductive layer 130 is formed on the bottom surface of the light-emitting mesa 140 for forming an electrical connection between the light-emitting mesa 140 and the reflective layer 120. In some embodiments, the conductive layer 130 can be a conductive transparent layer that is transparent to the light emitted by the light-emitting mesa 140 to improve conductivity and light transmittance.

[0130] In one embodiment, the conductive layer 130 can be one or a combination of one or more of, such as graphene, indium tin oxide (ITO), antimony doped zinc oxide (AZO), fluorine doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0131] In some embodiments, the electrode polarity of the conductive layer 130 is determined by the first-type epitaxial layer 141, and the electrode polarity of the upper electrode layer 150 is determined by the second-type epitaxial layer 143. The electrode polarity of the conductive layer 130 is opposite to the electrode polarity of the upper electrode layer 150. The conductive layer 130 can be, for example, a P electrode or an anode electrode, and the upper electrode layer 150 is an electrode with a polarity opposite to that of the conductive layer 130, such as an N electrode or a cathode electrode, and vice versa.

[0132] In some embodiments, the upper electrode layer 150 is formed on the top surface of the light-emitting mesa 140, and the second-type epitaxial layer 143 is electrically connected to the upper electrode layer 150. In some embodiments, as Figure 1B shown, the upper electrode layer 150 is annular and surrounds a plurality of micro light-emitting diode structures 100, that is, surrounds a plurality of light-emitting mesas. Adjacent upper electrode layers 150 are connected to each other, and all the upper electrode layers 150 are connected into a whole. In some embodiments, a single upper electrode layer 150 is a square ring, and the top view shape of the overall upper electrode layer is the grid shape remaining after removing the square. The upper electrode layer 150 can also be a rectangular ring, a parallelogram ring, a hexagonal ring, etc. In some embodiments, the upper electrode layer 150 can be used as a common electrode, and a plurality of micro light-emitting diode structures share one upper electrode layer 150.

[0133] In some embodiments, the number of micro light-emitting diode structures surrounded by the upper electrode layer 150 can be 1x2, 2x2, 2x3, 3x3, 4x4, etc. In other words, the micro light-emitting diode structures surrounded by the upper electrode layer 150 can be arranged in an N×M pixel array, where N is a positive integer greater than or equal to 1, and M is a positive integer greater than or equal to 2. AsFigure 1B As shown, the upper electrode layer 150 is a square ring and surrounds 4×4 micro light-emitting diode structures 100, and the cross-section of each micro light-emitting diode structure is circular.

[0134] In some embodiments, the upper electrode layer 150 may be a conductive metal, such as including one or more of Ni, Al, Ti, Pt, Au, etc. In other embodiments, the upper electrode layer 150 may be a combination of one or more of graphene or indium tin oxide (ITO) or antimony doped zinc oxide (AZO) or fluorine doped tin oxide (FTO) or other transparent conductive oxides (TCO).

[0135] In some embodiments, a convex portion 144 is provided under the upper electrode layer 150, and the shape of the convex portion 144 is the same as that of the upper electrode layer 150. The convex portion 144 surrounds a plurality of micro light-emitting diode structures. In some embodiments, the convex portion 144 is located on the top of the second type epitaxial layer 143 and is integrally formed with the second type epitaxial layer 143. The upper electrode layer 150 is electrically connected to the second type epitaxial layer 143 through the convex portion 144.

[0136] In some embodiments, the barrier structure 160 covers the side surfaces of the conductive layer 130 and the light-emitting mesa 140. In some embodiments, the tops of the second type epitaxial layers 143 of adjacent light-emitting mesas 140 are connected to each other, and the barrier structure 160 covers the bottom surface of the connected portion of the second type epitaxial layer 143. The conductive layer 130 is located on the bottom surface of the light-emitting mesa 140 and forms an electrical connection therewith. At least a part of the bottom surface of the conductive layer 130 is not covered by the barrier structure 160. In some embodiments, the barrier structures 160 of two adjacent micro light-emitting diode structures are connected.

[0137] In some embodiments, the barrier structure 160 includes a first passivation layer 161 and a second passivation layer 162. The first passivation layer 161 covers the side surfaces of the conductive layer 130 and the light-emitting mesa 140. At least a part of the bottom surface of the conductive layer 130 is not covered by the first passivation layer 161. The second passivation layer 162 is located on the side of the first passivation layer 161 away from the light-emitting mesa 140.

[0138] In some embodiments, the material of the barrier structure 160 is a transparent insulating material. In some embodiments, the material of the first passivation layer 161 is a phosphide. Further, the material of the first passivation layer 161 is a single-metal phosphide, such as indium phosphide (InP), gallium phosphide (GaP), or AlP or GeP, etc. In some embodiments, the material of the first passivation layer 161 is a multi-metal phosphide, such as AlInP, AlGaInP, or InGaP.

[0139] In some embodiments, the material of the second passivation layer 162 is an oxide, such as SiO2, Al2O3, TiO2, Ti2O5, MgO, ZnO, or HFO2, etc. In some embodiments, the material of the second passivation layer 162 is a nitride, such as one of silicon nitride SiNx, silicon oxynitride SiON, and aluminum nitride AlN.

[0140] In some embodiments, the thickness of the first passivation layer 161 is 0.5 - 1000 nm, and the thickness of the second passivation layer 162 is 0.5 - 1000 nm. The refractive index of the first passivation layer is 1.2 - 4, and the refractive index of the second passivation layer is 1.2 - 4.

[0141] In some other embodiments, the barrier structure 160 further includes a third passivation layer, a fourth passivation layer, …, an nth passivation layer, where n is a positive integer and n is not less than 3. The third passivation layer to the nth passivation layer are located between the first passivation layer 161 and the second passivation layer 162, or the third passivation layer to the nth passivation layer are located between the second passivation layer 162 and the bonding layer. In some other embodiments, among the second passivation layer 152 to the nth passivation layer, the materials of adjacent passivation layers are different.

[0142] In some embodiments, the preparation of the barrier structure includes the following steps:

[0143] Form the first passivation layer 161, and the first passivation layer 161 at least coats the side surfaces of the light-emitting mesa 140; and form the second passivation layer 162 on the side of the first passivation layer 161 away from the light-emitting mesa 140.

[0144] In some embodiments, the first passivation layer 161 coats the side surfaces of the light-emitting mesa 140 and the conductive layer 130.

[0145] In some embodiments, the first passivation layer 161 is a phosphide. Generally, epitaxial growth techniques, such as molecular beam epitaxy (MBE), metalorganic chemical vapor deposition (MOCVD), etc., are used to grow a uniform layer of phosphide, such as indium phosphide or gallium phosphide, on the side surfaces of the light-emitting mesa 140 and the conductive layer 130. Optionally, post-treatment such as annealing and cleaning is performed after growth to optimize the performance and stability of the passivation layer.

[0146] Indium phosphide (InP), as a second-generation semiconductor material, has a zinc blende crystal structure, a bandgap of 1.34 eV, a relatively high mobility at room temperature, a high saturated electron drift velocity, an appropriate emission wavelength for low-loss optical fiber communication, strong radiation resistance, good thermal conductivity, and high optoelectronic conversion efficiency. As a passivation layer, it can reduce the light loss inside the micro light-emitting diode structure and improve the light output efficiency. At the same time, the wide bandgap structure of indium phosphide enables electrons to pass through quickly, which helps to reduce the recombination time of electrons and holes, thereby improving the luminescence efficiency. The indium phosphide passivation layer can be applied to light-emitting diodes in special application fields such as aerospace solar cells and satellite signal receivers, where extremely high requirements are placed on the stability and performance of the devices.

[0147] In some embodiments, when the second passivation layer 162 is silicon nitride (SiNx) or silicon oxynitride (SiON), methods such as plasma-enhanced chemical vapor deposition (PECVD) are often used to prepare the second passivation layer. SiNx or SiON thin films have good antireflection performance and passivation effects, which can reduce the reflection loss on the surface of the micro light-emitting diode and improve the light extraction efficiency. At the same time, they also have certain moisture-proof and corrosion-proof capabilities, which help to protect the micro light-emitting diode, especially the light-emitting mesa, from damage by the external environment. The nitride passivation layer is widely used in the passivation and antireflection layers of micro light-emitting diode chips.

[0148] In some embodiments, when the second passivation layer 162 is aluminum nitride (AlN), a layer of aluminum nitride thin film is often deposited on the first passivation layer by methods such as sputtering or chemical vapor deposition. Aluminum nitride (AlN) has excellent heat transfer capabilities due to its high sound velocity and low constant dielectric loss, which can effectively conduct the heat generated by the microdisplay chip, thereby reducing the operating temperature of the chip and improving the reliability and thermal stability of the device. Moreover, aluminum nitride has a high resistivity and good electrical insulation properties, which improve the breakdown voltage and frequency response characteristics of the device. In addition, the refractive index of aluminum nitride is moderate, which can reduce the light loss inside the LED chip and improve the light output efficiency. At the same time, its good light transmittance also helps to improve the luminescence brightness of the LED. The aluminum nitride (AlN) passivation layer is widely used in LEDs in special application fields such as automotive lighting and outdoor displays, where extremely high requirements are placed on the performance and thermal stability of the devices.

[0149] Traditional passivation layers often use SiO2. Due to the porous structure of SiO2 itself, its ability to resist the migration of mobile charges and the penetration of impurities is poor, and moisture and oxygen are likely to penetrate through SiO2 and corrode the light-emitting mesa. In a hydrogen environment, nitrides (such as SiNx, SiON, AlN) have a lower internal air pressure, higher electron freedom, lower dielectric constant, higher thermal stability, and outstanding blocking effect on external ions compared to SiO2, and can effectively prevent water vapor penetration and resist mobile charges (such as Na +Migration of (ions). The phosphide passivation layer (such as InP, GaP) is a homologous material for non-doped and luminescent mesa, which can better fill the defects on the surface of the luminescent mesa, reduce the surface state density, and reduce the surface recombination rate. Changing the traditional SiO2 passivation layer to a nitride passivation layer can improve the stability of micro light-emitting diodes. The passivation layer can prevent the surface of the micro light-emitting diode from reacting with chemical substances such as oxygen and water in the atmosphere, thereby reducing chemical corrosion.

[0150] Improve luminous efficiency: By reducing the defects and non-radiative recombination centers on the surface of the luminescent mesa, the passivation layer can reduce the leakage current and dark current of the micro light-emitting diode, thereby improving its luminous efficiency. For example, in the industrial atomic layer deposition (ALD) technology, the ALD passivation technology is used to repair the damage of the fine nanoscale structure of the LED, which can not only restore the illumination intensity but also increase it to a higher level.

[0151] Replace the single-layer passivation layer with a double-layer passivation layer. The first passivation layer is a phosphide passivation layer, which reduces the surface refractive index and increases the light reflection. The second passivation layer can protect the first phosphide passivation layer.

[0152] As a physical barrier, the passivation layer can prevent the micro light-emitting diode from being physically damaged during manufacturing, packaging, and use. The double-layer passivation layer is more conducive to protecting the micro light-emitting diode than the single-layer passivation layer.

[0153] The passivation layer helps to reduce the scattering and reflection of the light emitted by the micro light-emitting diode, thereby improving the color purity of the light. For example, in metal halide perovskite nanocrystal (NCs) LEDs, the use of ligand exchange and passivation layers has been proven to significantly improve the external quantum efficiency (EQE) and brightness of the LEDs while maintaining high photoluminescence quantum yield (PLQY) and color purity.

[0154] The passivation layer promotes the miniaturization of LEDs: With the continuous development of LED technology, miniaturization has become an important trend. The use of the passivation layer helps to achieve the miniaturization of LEDs while maintaining their high performance and stability. For example, in the research of the US Naval Research Laboratory (NRL), scientists developed a laser processing technology to achieve the miniaturization of single-layer LEDs by passivating the optical material defects of single-layer molybdenum disulfide (MoS2) and increased the light emission efficiency by 200 times.

[0155] In some embodiments, the reflective layer 120 is formed on the surfaces of the passivation layer 160 and the conductive layer 130 away from the luminescent mesa 140. In some embodiments, the reflective layers 120 of adjacent micro light-emitting diode structures are connected to each other. The reflective layer 120 reflects the light emitted by the light-emitting layer 143 to its bottom and side walls, so that more light is emitted upward, enhancing the brightness and luminous efficiency.

[0156] In some embodiments, the thickness of the reflective layer 120 below the conductive layer 130 is greater than, equal to, or less than the thickness of the reflective layer 120 on the side of the light-emitting mesa 140.

[0157] In some embodiments, the reflective layer 120 may be a metal layer with high reflectivity, which includes one or more of Pt, Rh, Al, Au, Cr, and Ag.

[0158] In one embodiment, the bonding layer 180 includes a first bonding layer 181 and a second bonding layer 182. The first bonding layer 181 is formed by filling the gap between the light-emitting mesas 140 with a non-conductive material. The first bonding layer 181 is transparent to the light emitted by the light-emitting mesas 140. In some embodiments, the non-conductive material may be a solid inorganic material. In some embodiments, the solid inorganic material includes SiO2, Al2O3, Si3N4, SiCN, HfO2, Ta2O5, TiO2, ZrO2, La2O3, MgO, borophosphosilicate glass, or any combination thereof.

[0159] In some embodiments, the second bonding layer 182 is located on the surface of the substrate 110. The material of the second bonding layer 182 is similar to that of the first bonding layer 181. Preferably, the materials of both the second bonding layer 182 and the first bonding layer 181 are SiO2.

[0160] In other embodiments, the bonding layer 180 may further include a bonding layer made of a conductive material, such as a metal or a metal alloy. The conductive material includes one or more of Au, Sn, In, Cu, or Ti. The bonding layer made of the conductive material is located between the first bonding layer 181 and the second bonding layer 182.

[0161] In some embodiments, the light-emitting mesa 140 of the micro light-emitting diode can be bonded to the surface of the substrate 110 through a bonding process. The first bonding layer 181 is bonded to the second bonding layer 182. For example, in the bonding process, an oxide bonding layer is deposited on the bottom of the light-emitting mesa structure; a corresponding oxide bonding layer is deposited on the substrate 110. Then, the light-emitting mesa 140 is bonded to the substrate 110 under high pressure and high temperature.

[0162] In some embodiments, microlenses 170 are formed on the top of the light-emitting mesas 140, and adjacent microlenses are connected. In some embodiments, the lateral dimension at the bottom of the microlenses 170 may be greater than or equal to the lateral dimension of the micro light-emitting diode.

[0163] In some embodiments, a microlens 170 may cover a plurality of lensless micro light-emitting diodes. A plurality of microlenses constitute a microlens array. The microlens array sequentially includes a spacer layer and a microlens head array from bottom to top. There are gaps between the microlens head arrays. Part of the surface of the spacer layer is exposed at the bottom of the gap. The focal length of the microlens head is located below the spacer layer.

[0164] The microlens array is disposed above the micro light-emitting diode array, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro light-emitting diode, and the horizontal profile of the microlens is larger than the maximum horizontal profile of the micro light-emitting diode. The microlens is mainly used to converge and / or collimate light. For example, by adjusting parameters such as the thickness and curvature of the microlens, the focus of the microlens can be located in the light-emitting mesa of the micro light-emitting diode. The microlenses in the microlens array are usually the same. Examples of microlenses include spherical microlenses, aspherical microlenses, Fresnal microlenses, and cylindrical microlenses. In one embodiment, the typical shape of the bottom cross-section of each microlens includes a circle, a square, a rectangle, and a hexagon. The microlenses in the microlens array of the display panel may be the same or different in terms of shape, curvature, optical power, size, base, spacing, etc.

[0165] In some embodiments, the microlens 170 may be made of various materials that are transparent to light of each wavelength emitted by the micro light-emitting diode. Exemplary transparent materials for the microlens 170 include polymers and dielectric materials. In some embodiments, the dielectric material includes one or more materials such as silicon oxide, silicon nitride, silicon carbide, titanium oxide, zirconium oxide, aluminum oxide, etc. In some embodiments, the microlens 170 is made of a photoresist. In some embodiments, the microlens is directly deposited on the surface of the micro light-emitting diode by chemical vapor deposition (CVD) technology.

[0166] Figure 2 A cross-sectional schematic diagram of the micro light-emitting diode structure of a display chip according to another embodiment of the present invention is shown. As Figure 2 shown, a plurality of micro light-emitting diode structures arranged in an array form are located on the driving backplane 210. The micro light-emitting diode structure includes a driving backplane 210, a driving conductive structure 211, a lower electrode structure 220, a first conductive structure 221, a conductive layer 230, a light-emitting mesa 240, an upper electrode layer 250, a barrier structure 260, a microlens 270, a bonding layer 280, an insulating dielectric layer 283, a first reflective layer 291, and a second reflective layer 292.

[0167] In some embodiments, the driving backplane 210 may employ an integrated circuit chip. The driving backplane 210 includes a substrate and driving circuits located in the substrate. The driving conductive structure 211 is located on the driving backplane 210 and is electrically connected to the driving circuits. Each micro light-emitting diode corresponds to a driving conductive structure 211, and the driving conductive structure 211 is electrically connected to the lower electrode structure 220. Each driving circuit is a pixel driver. In some cases, the driving circuit is a thin-film transistor pixel driver or a silicon CMOS pixel driver. In one embodiment, the substrate of the driving backplane 210 is a Si substrate. In another embodiment, the substrate of the driving backplane 210 is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. The driving backplane 210 is used to control the lighting and extinguishing of the micro light-emitting diodes within each pixel. In one embodiment, the material of the driving conductive structure 211 is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au.

[0168] In some embodiments, the driving backplane may be electrically connected to each micro light-emitting diode in the micro light-emitting diode array through separate metal interconnections. In some embodiments, each micro light-emitting diode may be individually electrically controlled by the driving backplane. In some embodiments, the driving backplane 210 may be electrically connected to the electrodes of the micro light-emitting diodes through metal interconnections.

[0169] The light-emitting mesa 240 includes a first-type epitaxial layer 241, a second-type epitaxial layer 243, and a light-emitting layer 242 located therebetween. The first-type epitaxial layer 241 is electrically connected to the conductive layer 230. The second-type epitaxial layer 243 is electrically connected to the upper electrode layer 250.

[0170] The light-emitting mesa 240, the conductive layer 230, the upper electrode layer 250, and the microlens 270 are respectively similar to the light-emitting mesa 140, the conductive layer 130, the upper electrode layer 150, and the microlens 170, and will not be described in detail herein.

[0171] In some embodiments, Figure 2 As shown, a convex portion 244 is provided under the upper electrode layer 250. Figure 2 The convex portion 244 shown is Figure 1A similar to the convex portion 144 shown and will not be described in detail herein.

[0172] In some embodiments, the barrier structure 260 at least coats the sides of the conductive layer 230, the light-emitting mesa 240, and the first reflective layer 291. In some embodiments, the tops of the second-type epitaxial layers 243 of adjacent light-emitting mesas 240 are connected to each other, and the barrier structure 260 covers the bottom surface of the connected portion of the second-type epitaxial layers 243. The conductive layer 230 is located on the bottom surface of the light-emitting mesa 240 and forms an electrical connection therewith. The first reflective layer 291 is located on the side of the conductive layer 230 away from the light-emitting mesa 240, and at least a part of the bottom surface of the first reflective layer 291 is not covered by the barrier structure 260. In some embodiments, the barrier structures 260 of two adjacent micro light-emitting diode structures are connected.

[0173] In some embodiments, the barrier structure 260 includes a first passivation layer 261 and a second passivation layer 262. The first passivation layer 261 coats the sides of the conductive layer 230, the light-emitting mesa 240, and the first reflective layer 291. The second passivation layer 262 is located on the side of the first passivation layer 261 away from the light-emitting mesa 240.

[0174] The materials of the first passivation layer 261 and the second passivation layer 262 are similar to those of the first passivation layer 161 and the second passivation layer 162, and for the sake of simplifying this specification, they will not be repeated here.

[0175] In some embodiments, the first reflective layer 291 is formed on the surface of the conductive layer 230 away from the light-emitting mesa 240, and the first reflective layer 291 is electrically connected to the conductive layer 230. The second reflective layer 292 is formed on the surface of the barrier structure 260 away from the light-emitting mesa 240. Adjacent second reflective layers 292 are connected to each other. The first reflective layer 291 and the second reflective layer 292 are not connected and are insulated by the barrier structure 260.

[0176] In some embodiments, the first reflective layer 291 and the second reflective layer 292 can be metal layers with high reflectivity, which include one or more of Pt, Rh, Al, Au, Cr, and Ag.

[0177] In some embodiments, the lower electrode structure 220 is located under the first reflective layer 291 and is electrically connected to the first reflective layer 291. In some embodiments, the lower electrode structure 220 can be a conductive metal, for example, including one or more of Ni, Al, Ti, Pt, Au, etc.

[0178] In some embodiments, the first conductive structure 221 is electrically connected to the lower electrode structure 220, and the first conductive structure 221 is located between the first conductive structure 221 and the driving conductive structure 211. The first conductive structure 221 is connected to the lower electrode structure 220 through a bonding process.

[0179] In some embodiments, a protective layer 212 is provided between the first conductive structure 221 and the driving conductive structure 211 for protecting the driving conductive structure 211 during the formation of the first conductive structure 221. In some embodiments, the protective layer 212 may be one or more of Au, Pt, Rh, Al, Cr, and Ag.

[0180] In some embodiments, the bonding layer 280 includes a first bonding layer 281 and a second bonding layer 282. An insulating dielectric layer 283 is located under the bonding layer 280.

[0181] In some embodiments, the first bonding layer 281 fills the gaps between the light-emitting mesa 240 and the lower electrode structure 220; the second bonding layer 282 fills the gaps between the first conductive structures 221; and the insulating dielectric layer 283 fills the gaps between the driving conductive structures 211.

[0182] The first bonding layer 281, the second bonding layer 282, and the insulating dielectric layer 283 are transparent to the light emitted by the light-emitting mesa 240. The materials of the first bonding layer 281 and the second bonding layer 282 are similar to those of the first bonding layer 181, and for the sake of simplicity of this specification, they will not be repeated here. Preferably, the materials of the first bonding layer 281, the second bonding layer 282, and the insulating dielectric layer 283 are SiO2.

[0183] In some embodiments, the material of the insulating dielectric layer 283 may be a solid inorganic material. In some embodiments, the solid inorganic material includes SiO2, Al2O3, Si3N4, SiCN, HfO2, Ta2O5, TiO2, ZrO2, La2O3, MgO, phosphosilicate glass (PSG), borophosphosilicate glass, or any combination thereof.

[0184] In some embodiments, the second bonding layer 282 is located between the first bonding layer 281 and the insulating dielectric layer 283. The second bonding layer 282 is connected to the first bonding layer 281 through a bonding process.

[0185] In some embodiments, the light-emitting mesa 240 of the micro light-emitting diode structure can be bonded to the surface of the driving backplane 210 through a hybrid bonding process. For example, in the hybrid bonding process, an oxide bonding layer is deposited on the bottom of the light-emitting mesa structure; a corresponding oxide bonding layer is deposited on the driving backplane 210. Then, vias can be formed in the oxide bonding layer and filled with metal to form the lower electrode structure 220 and the first conductive structure 221. A CMP process can be performed on the surfaces of the lower electrode structure 220 and the first conductive structure 221 such that the surfaces of the lower electrode structure 220 and the first conductive structure 221 are flush with the surface of the oxide bonding layer. Then, the light-emitting mesa 240 is bonded to the substrate 210 under high pressure and high temperature. In some embodiments, the lower electrode structure 220 is electrically connected between the first conductive structure 221 and the light-emitting mesa 240 above the lower electrode structure 220, serving as a P electrode.

[0186] Figure 3 A cross-sectional schematic diagram of a micro light-emitting diode structure showing another embodiment of the present invention. As Figure 3 shown, in some embodiments, the micro light-emitting diode structure includes a driving backplane 310, a lower electrode layer 320, a conductive layer 330, a light-emitting mesa 340, an upper electrode layer 350, a barrier structure 360, a microlens 370, and an insulating dielectric 380.

[0187] In some embodiments, the driving backplane 310 can employ an integrated circuit chip. The driving backplane 110 includes a substrate, a driving circuit, and a contact pad 311. The driving circuit is located in the substrate, the contact pad 311 is located in the substrate, and the upper surface of the contact pad 311 exposes the substrate and is electrically connected to the driving circuit. Each micro light-emitting diode corresponds to a contact pad 311, and the contact pad 311 is electrically connected to the lower electrode layer 320. Each driving circuit is a pixel driver. In some cases, the driving circuit is a thin-film transistor pixel driver or a silicon CMOS pixel driver. In one embodiment, the substrate of the driving backplane 310 is a Si substrate. In another embodiment, the substrate of the driving backplane 310 is a transparent substrate, such as a glass substrate. Examples of other substrates include GaAs, GaP, InP, SiC, ZnO, and sapphire substrates. The driving backplane 310 is used to control the lighting and extinguishing of the micro light-emitting diodes. In one embodiment, the material of the contact pad 311 is an alloy of one or more of the following metals: Ni, Al, Ti, Cu, Pt, and Au. In some embodiments of the present invention, the driving backplane can be electrically connected to each micro light-emitting diode in the micro light-emitting diode array through separate metal interconnections. In some embodiments, each micro light-emitting diode can be individually electrically controlled by the driving backplane.

[0188] In some embodiments, the lower electrode layer 320 may be a metal-bonded composite layer. The light-emitting mesa 340 of the micro light-emitting diode may be bonded to the surface of the driving backplane 310 through the lower electrode layer 320, and the bonding can be completed by means such as eutectic bonding, thermocompression bonding, and transient liquid phase (TLP) bonding. In some embodiments, the lower electrode layer 320 may be located on the driving backplane 310. In another embodiment, the lower electrode layer 320 grows on the driving backplane 310. In some embodiments, the thickness of the lower electrode layer 320 is from 0.1 micrometer to 3 micrometers. In a preferred embodiment, the thickness of the lower electrode layer 320 is 0.3 μm. In some embodiments, the material of the lower electrode layer 320 is an alloy of one or more of the following metals: Cr, Al, Ti, Ni, Pt, Au, Ag, and Sn. The lower electrode layer 320 may include an ohmic contact layer and a metal bonding layer. In some cases, the lower electrode layer 320 includes two metal layers. One of the two metal layers is deposited on a layer above the metal bonding layer within the LED. The corresponding bonding metal layer is deposited on the driving backplane 310. For example, the lower electrode layer 320 may be Au-Au bonding, Au-Sn bonding, Au-In bonding, Ti-Ti bonding, Cu-Cu bonding, or a combination of the above. For example, if Au-Au bonding is selected, two layers of Au respectively require a Cr layer as an adhesion layer and a Pt layer as an anti-diffusion layer. The Pt layer is located between the Au layer and the Cr layer. The Cr and Pt layers are located on the top and bottom of the two bonded Au layers. In some embodiments, when the thicknesses of the two Au layers are substantially the same, at high pressure and high temperature, the Au on the two layers diffuses into each other to bond the two layers together.

[0189] In some embodiments, the lower electrode layer 320 may also be used as a mirror to reflect the light emitted from the upper light-emitting mesa 340.

[0190] In some embodiments, a conductive layer 330 is formed on the bottom surface of the light-emitting mesa 340 for forming an electrical connection between the light-emitting mesa 340 and the lower electrode layer 320. In some embodiments, the conductive layer 330 may be a conductive transparent layer that is transparent to the light emitted from the light-emitting mesa 340 to improve conductivity and light transmittance. In some embodiments, an upper electrode layer 350 is formed on the top surface of the light-emitting mesa 340, and the upper electrode layer 350 is electrically connected to a current spreading structure or a top electrode (not shown).

[0191] In some embodiments, the conductive layer 330, the upper electrode layer 350, and their connecting components can be one or more combinations of, for example, graphene, indium tin oxide (ITO), aluminum-doped zinc oxide (AZO), fluorine-doped tin oxide (FTO), or other transparent conductive oxides (TCO).

[0192] In some embodiments, the bottom lateral dimension of the light-emitting mesa 340 is larger than the top lateral dimension. The light-emitting mesa 340 includes a first-type semiconductor layer 341, a second-type semiconductor layer 343, and a light-emitting layer 342 located therebetween. The first-type semiconductor layer 341 is electrically connected to the conductive layer 330. The second-type semiconductor layer 343 is electrically connected to the upper electrode layer 350. The area of the first-type semiconductor layer 341 is larger than the area of the second-type semiconductor layer 343, and thus the cross-section of the light-emitting mesa 140 is approximately a right trapezoid. That is, there is an inclination angle between the side wall of the light-emitting mesa 340 and the bottom of the light-emitting mesa, and the inclination angle is less than or equal to 90°. In some embodiments, the range of the inclination angle of the side wall of the light-emitting mesa is: 45° to 90°. In some embodiments, the bottom lateral dimension of the light-emitting mesa 340 exceeds 2 microns. In some embodiments, the top lateral dimension of the light-emitting mesa 340 does not exceed 1.5 microns. In some embodiments, the lateral dimension of the lower electrode layer 320 is larger than the bottom lateral dimension of the light-emitting mesa 340. The material of the light-emitting mesa 340 is similar to that of the light-emitting mesa 140, and for the sake of simplicity of this specification, it will not be repeated.

[0193] In some embodiments, the electrode polarity of the conductive layer 330 is determined by the first-type semiconductor layer 341, and the electrode polarity of the upper electrode layer 350 is determined by the second-type semiconductor layer 343. The electrode polarity of the conductive layer 330 is opposite to that of the upper electrode layer 350. The conductive layer 330 can be, for example, a P electrode or an anode electrode, and the upper electrode layer 350 is an electrode with a polarity opposite to that of the conductive layer 330, such as an N electrode or a cathode electrode, and vice versa. The material of the conductive layer 330 is similar to that of the conductive layer 130, and for the sake of simplicity of this specification, it will not be repeated.

[0194] In some embodiments, the barrier structure 360 coats the sides of the lower electrode layer 320, the conductive layer 330, and the light-emitting mesa 340. In some embodiments, the barrier structure 360 may also cover a part of the side of the upper electrode layer 350, and a part of the top surface of the upper electrode layer 350 is exposed to form an electrical connection with the top electrode. In other embodiments of the present invention, the barrier structure 360 does not cover the top surface and the side of the upper electrode layer 350, so that the upper electrode layers 350 of adjacent LED structures can be connected to each other to form a common cathode or anode. In some embodiments, the barrier structure 360 coats the sides of the lower electrode layer 320, the conductive layer 330, the first-type semiconductor layer 341, the light-emitting layer 342, and a part of the side of the second-type semiconductor layer 343.

[0195] In some embodiments, the barrier structure 360 includes a first passivation layer 361 and a second passivation layer 362. The first passivation layer 361 coats at least the sides of the lower electrode layer 320, the conductive layer 330, and the light-emitting mesa 340. The second passivation layer 362 is located on the surface of the first passivation layer 361 away from the light-emitting mesa 340. At least a part of the top of the light-emitting mesa 340 is not covered by the barrier structure 360.

[0196] The materials of the first passivation layer 361 and the second passivation layer 362 are similar to those of the first passivation layer 161 and the second passivation layer 162. For the sake of simplicity of this specification, they will not be repeated here.

[0197] In one embodiment, the insulating medium 380 fills the gap between the light-emitting mesas 340. The insulating medium 380 is transparent to the light emitted by the light-emitting mesas 340.

[0198] In some embodiments, the insulating medium 380 is made of a dielectric material such as a solid inorganic material. In some embodiments, the solid inorganic material includes SiO2, Al2O3, Si3N4, SiCN, HfO2, Ta2O5, TiO2, ZrO2, La2O3, MgO, phosphosilicate glass (PSG), borophosphosilicate glass, or any combination thereof. In some embodiments, the insulating medium 380 can facilitate the transmission of the light emitted from the LED structure.

[0199] In some embodiments, a microlens 370 is formed on top of the light-emitting mesa 340. The lateral dimension of the bottom of the microlens 370 may be greater than the lateral dimension of the micro light-emitting diode light-emitting region. In some embodiments, the lateral dimension of the bottom of the microlens 370 may be equal to the lateral dimension of the micro light-emitting diode light-emitting region. In some embodiments, one microlens 370 may cover multiple lensless micro light-emitting diodes. Multiple microlenses constitute a microlens array. The microlens array is disposed above the micro light-emitting diode array, wherein at least one microlens is disposed on the surface of the top conductive layer of the micro light-emitting diode, and the horizontal profile of the microlens is greater than the maximum horizontal profile of the micro light-emitting diode. The microlens 370 is similar to the microlens 170 and will not be described herein again.

[0200] The micro light-emitting diode structure further includes a current spreading structure (not shown), which is located between two light-emitting mesas and is electrically connected to the upper electrode layer 350. In some embodiments, the current spreading structure is annular and surrounds the light-emitting mesa 340. The current spreading structure can be formed by magnetron sputtering or evaporation, and its material can be, for example, Al or an Al alloy for the sidewall reflecting mirror surface. The stacked metal of the current spreading structure can be metal materials such as Ni, Al, Ti, Ni, Pt, Au, etc. In some embodiments, the current spreading structures are interconnected.

[0201] The present invention provides a barrier structure that includes at least a first passivation layer and a second passivation layer; the first passivation layer at least coats the side surface of the light-emitting mesa, and the material of the first passivation layer is a phosphide; the second passivation layer is located on the side of the first passivation layer away from the light-emitting mesa. The structure and material of the barrier structure have been described in detail in the above embodiments and will not be described herein again.

[0202] The present invention also provides a microdisplay device that includes the above-described barrier structure.

[0203] The present invention also provides a display system that includes the above-described barrier structure.

[0204] The present invention also provides a near-eye display device that includes the above-described barrier structure.

[0205] Although some embodiments of the present invention have been described in this application document, those skilled in the art can understand that these embodiments are merely shown as examples. Those skilled in the art can conceive of numerous variant schemes, alternative schemes, and improvement schemes under the teaching of the present invention without exceeding the scope of the present invention. The appended claims are intended to define the scope of the present invention and thus cover the methods and structures within the scope of these claims themselves and their equivalent transformations.

Claims

1. A barrier structure, characterized in that, Comprising at least: A first passivation layer that at least coats the side surface of the light-emitting mesa, and the material of the first passivation layer is a phosphide; And A second passivation layer located on the side of the first passivation layer away from the light-emitting mesa, wherein the material of the second passivation layer is different from that of the first passivation layer.

2. The barrier structure of the display chip according to claim 1, characterized in that The phosphide is a single-metal phosphide.

3. The barrier structure according to claim 2, characterized in that, The single-metal phosphide is InP or GaP or AlP or GeP.

4. The barrier structure according to claim 1, wherein The material of the phosphide is a multi-metal phosphide.

5. The barrier structure according to claim 4, wherein The multi-metal phosphide is AlInP or AlGaInP or InGaP.

6. The barrier structure according to claim 1, wherein The material of the second passivation layer is an oxide, and the oxide is SiO2 or Al2O3 or TiO2 or Ti2O5 or MgO or ZnO or HFO2; or The material of the second passivation layer is a nitride, and the nitride is one of silicon nitride, silicon oxynitride, and aluminum nitride.

7. The barrier structure according to claim 1, wherein The barrier structure further includes a third passivation layer, a fourth passivation layer,..., an nth passivation layer, where n is a positive integer and n is not less than 3; The third passivation layer to the nth passivation layer are located between the first passivation layer and the second passivation layer; Or The third passivation layer to the nth passivation layer are located on the side of the second passivation layer away from the first passivation layer.

8. The barrier structure according to claim 7, wherein The material of the third passivation layer to the nth passivation layer is an oxide, and the oxide is SiO2 or Al2O3 or TiO2 or Ti2O5 or MgO or ZnO or HFO2; or The material of the third passivation layer to the nth passivation layer is a nitride, and the nitride is one of silicon nitride, silicon oxynitride, and aluminum nitride.

9. The barrier structure according to claim 8, wherein Among the second passivation layer to the nth passivation layer, the materials of adjacent passivation layers are different.

10. The barrier structure according to claim 1, wherein Including but not limited to the following parameters: The thickness range of the first passivation layer is 0.5 - 1000 nm; The thickness range of the second passivation layer is 0.5 - 1000 nm; The refractive index range of the first passivation layer is 1.2 - 4; The refractive index range of the second passivation layer is 1.2 - 4.

11. A display chip, characterized in that, Including the barrier structure as described in claim 1.

12. The display chip according to claim 11, wherein Further including a conductive layer located under the light-emitting mesa and electrically connected to the light-emitting mesa; the barrier structure at least coats the side surfaces of the light-emitting mesa and the conductive layer.

13. The display chip according to claim 12, characterized in that, The light-emitting mesa includes: A light-emitting layer; A first-type epitaxial layer located under the light-emitting layer, the first-type epitaxial layer is a semiconductor material with a first conductivity type and includes multiple semiconductor layers; A second-type epitaxial layer located above the light-emitting layer, the second-type epitaxial layer is a semiconductor material with a second conductivity type and includes multiple semiconductor layers, where the second conductivity type is different from the first conductivity type; Wherein, the light-emitting layer is a multi-layer quantum well layer.

14. The display chip according to claim 13, characterized in that, The material of the quantum well layer is InGaP or AlInP or AlGaInP; the first-type epitaxial layer includes a P-type AlGaInP layer, a P-type Mg-doped AlInP layer, and a GaP layer from top to bottom; and The second-type epitaxial layer includes an N-type GaAs layer, an N-type AlGaInP layer, and an N-type Si-doped AlInP layer from top to bottom.

15. The display chip according to claim 13, wherein The bottom lateral dimension of the light-emitting mesa is smaller than the top lateral dimension; The tops of the second type of epitaxial layers of adjacent light-emitting mesa are connected to each other; The top of the second type of epitaxial layer includes a rough structure, where the rough structure is a raised structure regularly or irregularly distributed on the top of the second type of epitaxial layer.

16. The display chip according to claim 13, characterized in that, It further includes: An upper electrode layer, which is electrically connected to the second type of epitaxial layer, the upper electrode layer surrounds a plurality of the light-emitting mesa, and adjacent upper electrode layers are connected, and all the upper electrode layers are integrated into a whole; And Micro-lenses, which are arranged on the tops of the light-emitting mesa, and adjacent micro-lenses are connected to each other.

17. The display chip according to claim 13, characterized in that, It further includes a reflective layer, which is located on the surfaces of the barrier structure and the conductive layer away from the light-emitting mesa, and the material of the reflective layer is metal.

18. The display chip according to claim 16, wherein The second type of epitaxial layer has a convex portion, which is located under the upper electrode layer, and the shape of the convex portion is the same as that of the upper electrode layer.

19. The display chip according to claim 18, characterized in that, It further includes: A substrate, which is located below the light-emitting mesa; A bonding layer, which is located between the substrate and the light-emitting mesa, where the bonding layer includes a first bonding layer and a second bonding layer, the second bonding layer is located on the substrate, and the first bonding layer fills the gaps between the light-emitting mesa.

20. The display chip according to claim 12, characterized in that, It further includes: A first reflective layer, which is formed on the surface of the conductive layer away from the light-emitting mesa, and the first reflective layer is electrically connected to the conductive layer; A second reflective layer, which is formed on the surface of the barrier structure away from the light-emitting mesa.

21. The display chip according to claim 20, wherein, The first reflective layer and the second reflective layer are not connected; Adjacent second reflective layers are connected; The materials of the first reflective layer and the second reflective layer are metal.

22. The display chip according to claim 20, wherein The barrier structure coats the sides of the light-emitting mesa, the conductive layer and the first reflective layer; The display chip further includes: A lower electrode structure, which is located under the first reflective layer and is electrically connected to the first reflective layer; A driving backplane, which includes a substrate and a driving circuit located in the substrate; A driving conductive structure, which is located on the driving backplane and is electrically connected to the driving circuit; A contact pad, which is located in the substrate, and the upper surface exposes the substrate and is electrically connected to the driving circuit; A lower electrode layer, which is located between the conductive layer and the driving backplane and is electrically connected to the conductive layer and the driving backplane; a first conductive structure, which is electrically connected to the driving conductive structure and the lower electrode structure, and the first conductive structure is bonded to the lower electrode structure; a protective layer, which is located between the driving conductive structure and the first conductive structure; the materials of the protective layer, the driving conductive structure, the first conductive structure and the bonding of the lower electrode structure are metal; An insulating dielectric layer, which fills the gaps between the driving conductive structures; A bonding layer, which is located between the driving backplane and the light-emitting mesa, and fills the gaps between the first conductive structures, the gaps between the lower electrode structures and the gaps between the light-emitting mesa.

23. The display chip according to claim 22, wherein The bonding layer includes a first bonding layer and a second bonding layer, which are bonded to each other, where the first bonding layer fills the gaps between the lower electrode structures and the gaps between the light-emitting mesa, and the second bonding layer fills the gaps between the first conductive structures; The material of the insulating dielectric layer is a solid inorganic material; the material of the bonding layer is a solid inorganic material.

24. The display chip according to claim 22, wherein The barrier structure covers at least the side surfaces of the light-emitting mesa, the conductive layer, and the lower electrode layer.

25. A microdisplay device, characterized in that, Comprising the barrier structure according to claim 1.

26. A method for preparing a barrier structure, characterized in that, Comprising: Forming a first passivation layer that covers at least the side surface of the light-emitting mesa; And Forming a second passivation layer on a side of the first passivation layer away from the light-emitting mesa.

27. The method for preparing the barrier structure according to claim 26, wherein The first passivation layer is formed by an epitaxial growth method, and the first passivation layer is indium phosphide or gallium phosphide.

28. The method for preparing the barrier structure according to claim 27, wherein The epitaxial growth method includes molecular beam epitaxy or metalorganic chemical vapor deposition.

29. The preparation method of the barrier structure according to claim 26, wherein The second passivation layer is formed using a plasma-enhanced chemical vapor deposition method, and the second passivation layer is silicon nitride or silicon oxynitride; or The second passivation layer is formed using sputtering or chemical vapor deposition, and the second passivation layer is aluminum nitride.

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