GaN substrate

Abstract

The present invention relates to a GaN substrate having a main surface (1) inclined from a (0001) crystal surface, which is a Ga polar surface, by 0-10 DEG, and having an Si-doped GaN layer on at least the surface of the main surface (1), the Si concentration of the Si-doped GaN layer being 1 * 1018 atoms / cm3 or more, and the total of the bottom areas of recessed defects in the surface of the Si-doped GaN layer being 15% or less of the overall surface area of the Si-doped GaN layer.

Description

Technical Field

[0001] The present invention relates to a gallium nitride (GaN) substrate. Background Art

[0002] The substrate used in commercially produced InGaN-based laser diodes (LDs) is a conductive GaN substrate having a high carrier concentration. In addition, in recent years, research and development of vertical GaN power devices using such a conductive GaN substrate have also been actively carried out.

[0003] In the GaN substrate used in laser diodes and vertical GaN power devices, an n-type GaN substrate is made into a conductive GaN substrate by doping the entire substrate with an n-type donor or by providing a doped layer in a part of the layer structure of the substrate. Low resistance of the n-type GaN substrate is required, and many attempts have been made to increase the donor doping concentration in the doped layer. When manufacturing a device, a metal for a negative electrode is provided on the n-type GaN substrate. The higher the donor concentration, the better the ohmic property between the metal and the semiconductor, and thus an n-type GaN substrate with a high carrier concentration has been desired for a long time.

[0004] However, for example, if an n-type GaN substrate with a high carrier concentration is to be obtained by using a Ge-doped layer with Ge as a donor, pits will be generated.

[0005] Therefore, Non-Patent Document 1 discloses a GaN substrate having an Si-doped GaN layer doped with Si as a donor at a high concentration.

[0006] Prior Art Documents

[0007] Non-Patent Documents

[0008] Non-Patent Document 1: M Iwinska et al., “Homoepitaxial growth of HVPE-GaN doped with Si”, Journal of Crystal Growth, Vol. 456, pp. 91 - 96, 2016 Summary of the Invention

[0009] However, if Si is to be doped at a high concentration reaching an order of magnitude of 10 18 atoms / cm 3 or more, shrinkage holes will be generated. Shrinkage holes refer to SiNx films formed on the surface of the GaN crystal, and the higher the Si doping concentration, the more will be generated in large quantities.

[0010] In the portion where voids are generated, the epitaxial growth of GaN is inhibited, and thus recesses are formed on the surface of the obtained GaN substrate. Since the portions where the recesses are formed cannot be used as devices, the yield of device manufacturing deteriorates.

[0011] In addition, the ionization energy of Si is small enough to be fully ionized at room temperature. Therefore, in principle, the activation rate should be approximately 100%. However, as shown in Non-Patent Document 1, it is known that when Si is doped at a high concentration, Si, which is a carrier impurity to be doped, cannot function as a carrier originally, and there is a tendency for the activation rate to decrease. It is considered that the reason is that Si atoms do not enter the Ga sites as their original positions, but enter, for example, the interstitial sites, anti-sites (N sites), etc.

[0012] Thus, an increase in the Si concentration is in a trade-off relationship with the yield of device manufacturing. In addition, even when Si is doped at a high concentration, it is difficult to achieve a corresponding low resistance, and further improvement is desired.

[0013] Therefore, as Mode A of the present invention, an object is to provide a GaN substrate that can achieve both low resistance and improvement in the deterioration of the yield of devices. In addition, an object of the above Mode A of the present invention is also to provide a GaN substrate that has achieved low resistance corresponding to the doped Si concentration.

[0014] In addition, it is known that if Si is to be doped at a high concentration of up to the order of 10 18 atoms / cm 3 or more, the conductivity becomes low at the end of the GaN substrate, and the resistance on the negative electrode side of the semiconductor device manufactured using this GaN substrate becomes high.

[0015] Therefore, as Mode B of the present invention, an object is to provide a GaN substrate in which low resistance corresponding to the doped Si concentration is uniformly achieved throughout the substrate.

[0016] The inventors of the present invention conducted in-depth research and found that by narrowing the terrace width during the epitaxial growth of a Si-doped GaN crystal, the generation of voids is suppressed, and further, Si atoms are easily and appropriately incorporated into kink sites. From this, it was found that a GaN substrate that solves the above problems can be obtained, and thus Mode A of the present invention was completed.

[0017] In addition, the present inventors conducted in-depth research, and the results showed that the non-uniformity of the above-mentioned resistance was due to the non-uniform doping of Si, especially in the end portion of the GaN substrate, Si could not be doped well. In contrast, the present inventors conducted further research and found that by using a vapor deposition method in the formation of the Si-doped GaN layer and narrowing the platform width at this time, and in addition, making the distance between the nozzle of the GaCl gas as a raw material and the substrate surface in a specific range in the reactor, a GaN substrate that solves the above-mentioned problems can be obtained, thus completing Mode B of the present invention.

[0018] That is, the gist of the present invention including the above-mentioned Mode A and Mode B is as follows.

[0019] [1] A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as a Ga polar plane, and having an Si-doped GaN layer at least on the surface of the main surface 1,

[0020] The Si concentration of the above Si-doped GaN layer is 1×10 18 atoms / cm 3 or more,

[0021] In the surface of the above Si-doped GaN layer, the total bottom area of the concave defects is 15% or less of the total surface area of the surface of the Si-doped GaN layer.

[0022] [2] A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as a Ga polar plane, and having an Si-doped GaN layer at least on the surface of the main surface 1,

[0023] The Si concentration of the above Si-doped GaN layer is 1×10 18 atoms / cm 3 or more,

[0024] In the above Si-doped GaN layer, when the Si concentration is set to a (atoms / cm 3 ), and the carrier concentration is set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%) is 90% or more.

[0025] [3] A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as a Ga polar plane, and having an Si-doped GaN layer at least on the surface of the main surface 1,

[0026] The Si concentration of the above Si-doped GaN layer is 1×10 18 atoms / cm 3 or more,

[0027] Regarding the Si concentration on the surface of the above Si-doped GaN layer, the maximum value is set to α (atoms / cm 3 ), and when the minimum value is set to β (atoms / cm 3 ), the value represented by [{(α - β) / α} × 100] (%) is 10% or less.

[0028] [4] The GaN substrate according to any one of [1] to [3], wherein the thickness of the above Si-doped GaN layer is 50 μm or more.

[0029] [5] The GaN substrate according to any one of [1] to [4], wherein, on the surface of the above Si-doped GaN layer, the total bottom area of the recesses with a depth of 5 μm or more is 15% or less of the entire surface area of the Si-doped GaN layer.

[0030] [6] The GaN substrate according to any one of [1] to [5], wherein there is one or more 5 mm × 5 mm squares on the surface of the above Si-doped GaN layer where no concave defects exist.

[0031] [7] The GaN substrate according to any one of [1] to [6], wherein there is one or more 5 mm × 5 mm squares on the surface of the above Si-doped GaN layer where no recesses with a depth of 5 μm or more exist.

[0032] [8] The GaN substrate according to any one of [1] to [7], wherein the specific resistance of the above Si-doped GaN layer at 300 K is 1 × 10 －2 Ω·cm or less.

[0033] [9] The GaN substrate according to any one of [1] to [8], wherein the specific resistance of the above Si-doped GaN layer at 300 K is 8 × 10 －3 Ω·cm or less.

[0034]

[10] The GaN substrate according to any one of [1] to [9], wherein the specific resistance of the above Si-doped GaN layer at 300 K is 4 × 10 －3 Ω·cm or less.

[0035]

[11] The GaN substrate according to any one of [1] to

[10] , wherein the Si concentration of the above Si-doped GaN layer is 5 × 10 18 atoms / cm 3 or more.

[0036]

[12] The GaN substrate according to any one of [1] to

[11] , wherein the Si concentration of the above Si-doped GaN layer is 9 × 10 18 atoms / cm3 Above.

[0037]

[13] The GaN substrate according to any one of [1] to

[12] , wherein the GaN substrate is a wafer and the diameter of the wafer is 50 mm or more.

[0038]

[14] A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as the Ga polar plane, and having an Si-doped GaN layer at least on the surface of the main surface 1.

[0039] The thickness of the Si-doped GaN layer is 50 μm or more.

[0040] In the surface of the Si-doped GaN layer, the total bottom area of the recesses with a depth of 5 μm or more is 15% or less of the total surface area of the surface of the Si-doped GaN layer.

[0041]

[15] A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as the Ga polar plane, and having an Si-doped GaN layer at least on the surface of the main surface 1.

[0042] The thickness of the Si-doped GaN layer is 50 μm or more.

[0043] In the Si-doped GaN layer, when the Si concentration is set to a (atoms / cm 3 ) and the carrier concentration is set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%) is 90% or more.

[0044]

[16] A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as the Ga polar plane, and having an Si-doped GaN layer at least on the surface of the main surface 1.

[0045] The Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more.

[0046] The thickness of the Si-doped GaN layer is 50 μm or more.

[0047] For the Si concentration on the surface of the Si-doped GaN layer, when the maximum value is set to α (atoms / cm 3 ) and the minimum value is set to β (atoms / cm 3 ), the value represented by [{(α - β) / α}×100] (%) is 10% or less.

[0048] In addition, one mode of the above mode A of the present invention is as follows.

[0049] [1] A GaN substrate having a main surface 1 inclined by 0 to 10° from the (0001) crystal plane as the Ga-polar surface, and having an Si-doped GaN layer at least on the surface of the main surface 1,

[0050] The thickness of the Si-doped GaN layer is 50 μm or more,

[0051] In the surface of the Si-doped GaN layer, the total bottom area of the recesses with a depth of 5 μm or more is 15% or less of the entire surface area of the Si-doped GaN layer.

[0052] [2] A GaN substrate having a main surface 1 inclined by 0 to 10° from the (0001) crystal plane as the Ga-polar surface, and having an Si-doped GaN layer at least on the surface of the main surface 1,

[0053] The thickness of the Si-doped GaN layer is 50 μm or more,

[0054] In the Si-doped GaN layer, when the Si concentration is a (atoms / cm 3 ), and the carrier concentration is b (atoms / cm 3 ), the value represented by {(b / a)×100} (%) is 90% or more.

[0055] [3] The GaN substrate according to the above [1] or [2], wherein the Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more.

[0056] [4] The GaN substrate according to any one of the above [1] to [3], wherein there is at least one 5 mm × 5 mm square on the surface of the Si-doped GaN layer where there are no recesses with a depth of 5 μm or more.

[0057] [5] The GaN substrate according to any one of the above [1] to [4], wherein the specific resistance of the Si-doped GaN layer at 300 K is 1×10 －2 Ωcm or less.

[0058] [6] The GaN substrate according to any one of the above [1] to [5], wherein the specific resistance of the Si-doped GaN layer at 300 K is 8×10 －3 Ωcm or less.

[0059] [7] The GaN substrate according to any one of the above [1] to [6], wherein the specific resistance of the Si-doped GaN layer at 300 K is 4×10 －3 Ωcm or less.

[0060] [8] The GaN substrate according to any one of [1] to [7] above, wherein the Si concentration of the Si-doped GaN layer is 5×10 18 atoms / cm 3 or more.

[0061] [9] The GaN substrate according to any one of [1] to [8] above, wherein the Si concentration of the Si-doped GaN layer is 9×10 18 atoms / cm 3 or more.

[0062]

[10] The GaN substrate according to any one of [1] to [9] above, wherein the GaN substrate is a wafer, and the diameter of the wafer is 50 mm or more.

[0063] In addition, one mode of Mode B of the present invention is as follows.

[0064] [1] A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as a Ga polar plane, and at least having a Si-doped GaN layer on the surface of the main surface 1,

[0065] The Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more,

[0066] the thickness of the Si-doped GaN layer is 50 μm or more,

[0067] Regarding the Si concentration on the surface of the Si-doped GaN layer, when the maximum value is set to α (atoms / cm 3 ), and the minimum value is set to β (atoms / cm 3 ), the value represented by [{(α - β) / α}×100](%) is 10% or less.

[0068] [2] The GaN substrate according to [1] above, wherein the GaN substrate is a wafer, and the diameter of the wafer is 50 mm or more.

[0069] [3] The GaN substrate according to [1] or [2] above, wherein the specific resistance of the Si-doped GaN layer at 300 K is 1×10 －2 Ωcm or less.

[0070] [4] The GaN substrate according to any one of [1] to [3] above, wherein the specific resistance of the Si-doped GaN layer at 300 K is 8×10 －3 Ωcm or less.

[0071] [5] The GaN substrate according to any one of [1] to [4] above, wherein the specific resistance of the Si-doped GaN layer at 300 K is 4×10 －3 Ω·cm or less.

[0072] [6] The GaN substrate according to any one of [1] to [5] above, wherein the Si concentration of the Si-doped GaN layer is 9×10 18 atoms / cm 3 or more.

[0073] According to Mode A of the present invention, a GaN substrate can be provided which improves the yield deterioration of the device while achieving low resistance. In addition, a GaN substrate that achieves low resistance corresponding to the doped Si concentration can also be provided.

[0074] Therefore, it is very suitable as an n-type conductive GaN substrate used in laser diodes and vertical GaN power devices.

[0075] In addition, according to Mode B of the present invention, a GaN substrate can be provided in which low resistance corresponding to the doped Si concentration is uniformly achieved throughout the substrate.

[0076] Therefore, it is very suitable as an n-type conductive GaN substrate used in laser diodes and vertical GaN power devices. Description of the Drawings

[0077] Figure 1 is a cross-sectional schematic view showing one mode of the GaN substrates of the first to fourth embodiments.

[0078] Figure 2 is an explanatory diagram of the off angle provided in the substrate crystal used in the method for forming the Si-doped GaN layer, Figure 2 where (a) shows the case of obliquely cutting with respect to the (0001) surface of the substrate crystal, Figure 2 where (b) shows the substrate crystal after cutting, Figure 2 where (c) shows Figure 2 an enlarged view of the portion surrounded by the circular symbol in (b).

[0079] Figure 3 is a diagram showing Figure 2 the case of increasing the off angle of the (0001) surface of the substrate crystal for (c).

[0080] Figure 4 is a process cross-sectional view for explaining the method for manufacturing the first c-plane GaN wafer used in the manufacture of the GaN substrates of the first to fourth embodiments, Figure 4(a) shows a seed wafer, Figure 4 (b) of shows the state in which a first GaN thick film is grown on the seed wafer, Figure 4 (c) of shows the state in which the obtained first GaN thick film is thinned to obtain a plurality of first c-plane GaN wafers.

[0081] Figure 5 is a process cross-sectional view for explaining a method for manufacturing a second c-plane GaN wafer used in the manufacture of the GaN substrates according to the first to fourth embodiments, Figure 5 (a) of shows the state of a first c-plane GaN wafer, Figure 5 (b) of shows the state in which a second GaN thick film is grown on the first c-plane GaN wafer, Figure 5 (c) of shows the state in which the obtained second GaN thick film is thinned to obtain a second c-plane GaN wafer.

[0082] Figure 6 is a process cross-sectional view for explaining a method for manufacturing the GaN substrates according to the first to fourth embodiments, Figure 6 (a) of shows the state of a second c-plane GaN wafer, Figure 6 (b) of shows the state in which an Si-doped GaN layer is grown on the second c-plane GaN wafer.

[0083] Figure 7 is a schematic diagram showing the basic configuration of an HVPE apparatus.

[0084] Figure 8 is a fluorescence image of the surface of the GaN substrate obtained in Example 1-1.

[0085] Figure 9 is a fluorescence image of the surface of the GaN substrate obtained in Comparative Example 1-1. Detailed Description of the Invention

[0086] Hereinafter, the present invention will be described in detail, but the present invention is not limited to the following embodiments and can be implemented with various modifications within the scope of its gist.

[0087] In addition, "~" indicating a numerical range is used to mean including the numerical values described before and after it as a lower limit value and an upper limit value.

[0088] [GaN Substrate (1)]

[0089] One aspect of the GaN substrate according to the first embodiment has a main surface 1 inclined by 0 to 10° from the (0001) crystal plane which is a Ga polar plane, and at least an Si-doped GaN layer on the surface of the main surface 1. The Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3As described above. Moreover, in the surface of the Si-doped GaN layer, the total bottom area of the recesses is 15% or less of the entire surface area of the Si-doped GaN layer.

[0090] Another form of the GaN substrate of the first embodiment has a main surface 1 inclined 0 to 10° from the (0001) crystal plane which is a Ga-polar surface, and at least has a Si-doped GaN layer on the surface of the main surface 1, and the thickness of the Si-doped GaN layer is 50 μm or more. Moreover, in the surface of the Si-doped GaN layer, the total bottom area of the recesses with a depth of 5 μm or more is 15% or less of the entire surface area of the Si-doped GaN layer.

[0091] One form of the GaN substrate of the second embodiment has a main surface 1 inclined 0 to 10° from the (0001) crystal plane which is a Ga-polar surface, and at least has a Si-doped GaN layer on the surface of the main surface 1, and the Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more. Moreover, in the above Si-doped GaN layer, when the Si concentration is set to a (atoms / cm 3 ) and the carrier concentration is set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%) is 90% or more.

[0092] Another form of the GaN substrate of the second embodiment has a main surface 1 inclined 0 to 10° from the (0001) crystal plane which is a Ga-polar surface, and at least has a Si-doped GaN layer on the surface of the main surface 1, and the thickness of the Si-doped GaN layer is 50 μm or more. Moreover, in the above Si-doped GaN layer, when the Si concentration is set to a (atoms / cm 3 ) and the carrier concentration is set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%) is 90% or more.

[0093] In both of the first and second embodiments, the main surface 1 only needs to be inclined 0 to 10° from the (0001) crystal plane, preferably 0 to 5°, more preferably 0 to 2.5°. Although the lower limit of the inclination is 0°, it can be 0.2° or more. In addition, although the upper limit of the inclination is 10°, it is preferably 5° or less, more preferably 2.5° or less, can be 1.5° or less, and can also be 1° or less.

[0094] In addition, in both the first embodiment and the second embodiment, the GaN substrate has an Si-doped GaN layer on the surface of the main surface 1. In this specification, "having an Si-doped GaN layer on the surface of the main surface 1" means that the outermost surface of the main surface 1 of the GaN substrate coincides with the outermost surface of the Si-doped GaN layer.

[0095] In both the first embodiment and the second embodiment, as Figure 1 shown, the GaN substrate 100 has an (0001) orientation, and may have a GaN crystal layer 120 and an Si-doped GaN layer 110 on the (0001) surface 101 on the Ga-polar surface side. In addition, after forming the Si-doped GaN layer 110, the GaN crystal layer 120 used as the base crystal is removed, whereby a GaN substrate 110 composed only of the Si-doped GaN layer 110 can be produced.

[0096] The (0001)-oriented GaN substrate refers to a substrate having a main surface, that is, a large-area surface, parallel or substantially parallel to the (0001) crystal plane, that is, the c-plane, and is also referred to as a c-plane GaN substrate. Here, parallel or substantially parallel means inclined 0 to 10° from the (0001) crystal plane that is the Ga-polar surface.

[0097] The Si-doped GaN layer 110 in both embodiments refers to a layer obtained by substituting a part of Ga in the GaN crystal with Si. By making the GaN substrate have an Si-doped GaN layer, low-resistivity of the substrate can be achieved, and it is useful as a conductive substrate.

[0098] The Si concentration in the Si-doped GaN layer 110 is preferably 1×10 18 atoms / cm 3 or more. In this case, further low-resistivity of the substrate can be achieved, and the usefulness as a conductive substrate is improved. From the viewpoint of low-resistivity, the Si concentration in the Si-doped GaN layer 110 is more preferably 2×10 18 atoms / cm 3 or more, further preferably 5×10 18 atoms / cm 3 or more, still further preferably 7×10 18 atoms / cm 3 or more, particularly preferably 9×10 18 atoms / cm 3 or more, and the higher the better. The upper limit of the Si concentration is not particularly limited, for example, it is 1×10 21 atoms / cm 3 or less.

[0099] It should be noted that in this specification, the concentration of donor impurities such as Si (silicon) in the Si-doped GaN layer can be determined by secondary ion mass spectrometry (SIMS). The concentration of donor impurities such as Si concentration may vary along the c-axis direction, and the average value of the donor impurity concentration from a depth of 3 μm to a depth of 50 μm from the surface of the Si-doped GaN layer can be defined as the concentration of the above donor impurities.

[0100] The higher the Si concentration in the Si-doped GaN layer 110, the easier it is to generate shrinkage holes. As described above, shrinkage holes refer to the SiNx film formed on the surface of the GaN crystal, and the N atoms originally bonded to the Ga atoms are bonded to the Si atoms to form a silicon nitride film.

[0101] In the part where shrinkage holes are generated, the epitaxial growth of GaN is inhibited. If the epitaxial growth continues in this state, it will become a concave portion on the surface of the obtained GaN substrate. Sometimes this concave portion on the surface is referred to as a "concave defect" in this specification. If there is a concave portion on the surface of the GaN substrate, the yield of device manufacturing using this GaN substrate deteriorates.

[0102] In contrast, since the Si-doped GaN layer 110 in the first embodiment suppresses the generation of shrinkage holes, the concave portions on the surface of the GaN substrate are reduced, and the low-resistivity of the substrate can be achieved without deteriorating the yield of device manufacturing.

[0103] The detailed content of the mechanism for obtaining such a GaN substrate is not yet clear, but it is considered as follows.

[0104] If molecules containing Si atoms and molecules such as NH3 containing N atoms are in the gas phase state, they hardly react to form silicon nitride. It is considered that shrinkage holes are formed when molecules containing Si atoms and molecules such as NH3 coexist on the same terrace on the surface of the GaN crystal and meet due to thermal motion or the like, and then react.

[0105] In contrast, in the present invention, it is found that by narrowing the terrace, the generation of shrinkage holes can be suppressed. It is considered that by shortening the time for Si atoms adsorbed on the terrace, that is, Si adsorbed atoms, to reach the kink sites at the step edges, the probability of molecules such as NH3 adsorbed on the terrace meeting the Si adsorbed atoms and generating shrinkage holes can be reduced. As a result, even if the Si concentration is increased to increase the density of Si adsorbed atoms in the terrace, the probability of meeting the adsorbed N atoms can be reduced, the concave portions on the surface of the Si-doped GaN layer accompanying the generation of shrinkage holes can be reduced, and a smooth surface can be obtained.

[0106] The concave portions on the surface of the Si-doped GaN layer in this specification have the same meaning as the concave defects as described above, which means that there are no crystal defects in the concave portions on the surface, and the concave portions particularly refer to the parts with a depth of 5 μm or more.

[0107] In the first embodiment, the total bottom area of the concave defects is 15% or less, preferably 10% or less, more preferably 5% or less, still more preferably 1% or less, particularly preferably 0.1% or less, the lower the better, and it can be 0%, with respect to the total area of the surface of the Si-doped GaN layer. The smaller the total bottom area of the above-mentioned concave portions, the fewer the generation of shrinkage holes, and it can be said that the deterioration of the yield of device manufacturing can be suppressed.

[0108] In the first embodiment, the total bottom area of the concave portions with a depth of 5 μm or more is also preferably 15% or less, more preferably 10% or less, further preferably 5% or less, still more preferably 1% or less, particularly preferably 0.1% or less, the lower the better, and it can be 0%, with respect to the total area of the surface of the Si-doped GaN layer.

[0109] The presence of the concave defects can be identified by observation using a microscope or the like, and the total bottom area thereof can also be calculated. Particularly for the concave portions with a depth of 5 μm or more, regarding the total bottom area of the concave portions, when the surface of the Si-doped GaN layer is observed under ultraviolet irradiation to obtain a fluorescence image, it can be distinguished based on the color difference. The total bottom area of all the concave portions with a depth of 5 μm or more can be obtained by utilizing this color difference and based on the fluorescence image. Therefore, the total bottom area of the concave portions with a depth of 5 μm or more with respect to the total area of the surface of the Si-doped GaN layer can be calculated more precisely.

[0110] In addition, it is known that if the Si concentration in the Si-doped GaN layer 110 becomes high, the activation rate becomes low. The activation rate refers to the proportion of the doped carrier impurities present in the crystal that function as carriers. In this specification, when the Si concentration in the Si-doped GaN layer is set to a (atoms / cm 3 ), and the carrier concentration is set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%) can be used as the activation rate.

[0111] As described above, since the ionization energy of Si is small enough to be fully ionized at room temperature, the activation rate should be approximately 100% in principle. In contrast, as the reason for the low activation rate, it is considered that Si atoms do not enter the Ga sites as the original positions, but enter, for example, the interstitials, anti-sites (N sites), etc.

[0112] In contrast, the Si-doped GaN layer 110 in the second embodiment can maintain a high activation rate even when the Si concentration is increased, and can achieve low resistance with high Si concentration.

[0113] The detailed situation is not yet clear, but it is considered as follows.

[0114] One of the reasons why it is considered that Si atoms do not enter the Ga sites as the original positions but enter, for example, the interstitial sites or the anti-sites (N sites) is that the terrace is wide and the moving distance until the Si atoms are incorporated into the kink sites is long.

[0115] In contrast, in the present invention, by narrowing the terrace, the activation rate can be increased. It is considered that this is because the distance until the Si atoms reach the kink sites becomes shorter due to the narrowing of the terrace, and the Si atoms are incorporated into the appropriate kink sites, which can increase the probability of functioning as a dopant. As a result, even if the Si concentration is increased to increase the density of Si adsorbed atoms in the terrace, the Si atoms can be incorporated into the appropriate kink sites, so that a high activation rate can be achieved and a low resistivity corresponding to the Si concentration can be realized.

[0116] In the second embodiment, in the Si-doped GaN layer, when the Si concentration is set to a (atoms / cm 3 ) and the carrier concentration is set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%) is 90% or more, preferably 95% or more, more preferably 98% or more, the higher the better, and most preferably 100%.

[0117] It can be said that the higher the activation rate represented by the above value, the more the low-resistance conversion corresponding to the doped Si concentration can be achieved.

[0118] Although the recesses on the surface of the Si-doped GaN layer in the first embodiment and the activation rate in the second embodiment are described separately above, the following are not excluded: the GaN substrate of the first embodiment has a high activation rate in addition to low-resistance conversion and suppression of deterioration in the yield of device manufacturing, and the GaN substrate of the second embodiment can also suppress deterioration in the yield of device manufacturing in addition to low-resistivity conversion corresponding to the Si concentration based on the high activation rate.

[0119] That is, in the first embodiment, when the Si concentration of the Si-doped GaN layer is set to a (atoms / cm 3 ) and the carrier concentration is set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%) is preferably 90% or more, more preferably 95% or more, further preferably 98% or more, the higher the better, and most preferably 100%.

[0120] In the second embodiment, the total bottom area of the concave defects in the surface of the Si-doped GaN layer is preferably 15% or less, more preferably 10% or less, still more preferably 5% or less, further still more preferably 1% or less, particularly preferably 0.1% or less, and the lower the better, and it may be 0%.

[0121] In the second embodiment, the total bottom area of the concave portions with a depth of 5 μm or more in the surface of the Si-doped GaN layer is preferably 15% or less, more preferably 10% or less, still more preferably 5% or less, further still more preferably 1% or less, particularly preferably 0.1% or less, and the lower the better, and it may be 0%.

[0122] In both embodiments, it is preferable that there is at least one 5 mm × 5 mm square on the surface of the Si-doped GaN layer where no concave defect exists. The presence of at least one such square indicates less generation of shrinkage holes in the GaN substrate, and can suppress the deterioration of the yield in device manufacturing. Therefore, the usefulness as a GaN substrate for device manufacturing is high.

[0123] From the same viewpoint, it is more preferable that there is at least one 10 mm × 10 mm square on the surface of the Si-doped GaN layer where no concave defect exists, particularly preferably there is at least one 15 mm × 15 mm square where no concave defect exists, and particularly preferably there is at least one 25 mm × 25 mm square where no concave defect exists. The presence of the above squares can be confirmed by observing the surface of the GaN substrate using a microscope or the like.

[0124] In addition, in both embodiments, it is preferable that there is at least one 5 mm × 5 mm square on the surface of the Si-doped GaN layer where no concave portion with a depth of 5 μm or more exists. The presence of at least one such square indicates less generation of shrinkage holes in the GaN substrate, and can suppress the deterioration of the yield in device manufacturing. Therefore, the usefulness as a GaN substrate for device manufacturing is high. From the same viewpoint, it is more preferable that there is at least one 10 mm × 10 mm square on the surface of the Si-doped GaN layer where no concave portion with a depth of 5 μm or more exists, particularly preferably there is at least one 15 mm × 15 mm square where no concave portion with a depth of 5 μm or more exists, and particularly preferably there is at least one 25 mm × 25 mm square where no concave portion with a depth of 5 μm or more exists. The presence of the above squares can be confirmed by observing the fluorescence image of the GaN substrate.

[0125] It should be noted that the above-mentioned concave defects and concave portions with a depth of more than 5 μm do not limit the size of the GaN substrate. For example, in the case where the GaN substrate is a wafer with a diameter of 45 mm or more, the above content can be directly applied. However, in the case where the GaN substrate is a square substrate with a minor axis of less than 5 mm, a wafer with a diameter of 7 mm or less, etc., it is originally impossible to take out a 5 mm × 5 mm square grid on the surface of the Si-doped GaN layer. Even in this case, if the requirements of the above-mentioned first embodiment and second embodiment are satisfied, it is included in the GaN substrate of the present invention.

[0126] In both embodiments, the thickness of the Si-doped GaN layer is preferably 50 μm or more, more preferably 50 to 300 μm. Thus, even if it is only the Si-doped GaN layer, it has self-supporting properties, and when a GaN substrate composed only of the Si-doped GaN layer is formed, it can also serve as a substrate.

[0127] The thickness of the Si-doped GaN layer is preferably 50 μm or more, more preferably 80 μm or more, and further preferably 100 μm or more. The upper limit of the thickness is not particularly limited. For example, it is 300 μm or less, can be 200 μm or less, or can be 150 μm or less.

[0128] It should be noted that the thickness of the Si-doped GaN layer in this specification refers to the thickness of the layer with a Si concentration of 1×10 18 atoms / cm 3 or more, and can be measured by the above-mentioned SIMS. In the case where the thickness of the Si-doped GaN layer is uneven, as long as the thinnest minimum thickness is within the above range.

[0129] In both embodiments, in addition to Si (silicon), the Si-doped GaN layer may contain group IVA elements such as Ge (germanium), and group VIA elements such as O (oxygen) and S (sulfur) as donor impurities. The total concentration of donor impurities other than Si is, for example, 10% or less of the Si concentration, can be 5% or less, can be 1% or less, or can be 0%, that is, it does not contain.

[0130] As described later, the GaN substrates in both embodiments are preferably grown by vapor deposition, and more preferably by hydride vapor phase epitaxy (HVPE).

[0131] In the Si-doped GaN layer obtained by the above method, even without intentional addition, O (oxygen) can be contained at a concentration of 10 15 atoms / cm 3 or more. That is, the O (oxygen) concentration of the Si-doped GaN layer can be 1×10 15atoms / cm 3 or more.

[0132] On the other hand, in the Si-doped GaN layer, when other donor impurities other than Si and O are contained at a non-negligible concentration, it is the case of intentional doping with the above donor impurities. It should be noted that "intentional doping" means that in order to dope an element as an object into the Si-doped GaN layer, the element is added in the form of a single substance or a compound as a raw material, etc.

[0133] Therefore, if it is not the case of intentional doping with donor impurities other than Si and O, the total donor impurity concentration in the Si-doped GaN layer can be regarded as equal to the sum of the Si concentration and the O concentration.

[0134] Whether the Si-doped GaN layer is doped with donor impurities other than Si and O can be confirmed by elemental analysis or the like.

[0135] From the viewpoint of crystallinity, the concentration of donor impurities other than Si is preferably 1×10 17 atoms / cm 3 or less, more preferably 8×10 16 atoms / cm 3 or less, and even more preferably 5×10 16 atoms / cm 3 or less. In addition, for the same reason, the total concentration of donor impurities other than Si is preferably 2×10 17 atoms / cm 3 or less, more preferably 8×10 16 atoms / cm 3 or less, and even more preferably 5×10 16 atoms / cm 3 or less.

[0136] In the Si-doped GaN layer, other elements may also be included in addition to Ga and N, Si, and group IVA and group VIA element atoms as other donor impurities that constitute the GaN crystal. The other elements may be intentionally contained or may be unavoidably and non-intentionally contained. For example, H (hydrogen), C (carbon), Cl (chlorine), etc. may be mentioned. The total concentration of these other elements may be 10 16 ~10 17 atoms / cm 3 order of magnitude.

[0137] The full width at half maximum (FWHM) of the rocking curve obtained by (004) X-ray diffraction of the Si-doped GaN layer is preferably 50 arcsec or less. The rocking curve is the diffraction intensity distribution when the direction of the incident X-ray and the position of the detector are fixed and only the crystal as the sample is rotated during X-ray diffraction measurement, and is one of the indexes indicating the crystal quality.

[0138] The smaller the value of the full width at half maximum of the rocking curve, the fewer the crystal defects and the better the crystal quality. The full width at half maximum is preferably 40 arcsec or less, more preferably 30 arcsec or less, and further preferably 20 arcsec or less. There is no particular limitation on the lower limit of the full width at half maximum, and it is usually 5 arcsec or more. It should be noted that the full width at half maximum in this specification generally has the same meaning as the concept called the full width at half maximum. That is, it refers to the distance between the positions showing half of its maximum intensity 1 / 2f max showing its half intensity 1 / 2f max of the peak.

[0139] The full width at half maximum can be adjusted by the growth method (vapor phase method, liquid phase method, etc.) of the GaN crystal layer in the Si-doped GaN layer, the crystal characteristics of the seed substrate used when growing the GaN crystal layer, the crystal growth conditions, the selection of the growth surface, or the content of impurities.

[0140] In both embodiments, the dislocation density on the surface of the Si-doped GaN layer is preferably 5×10 6 cm －2 or less. In this case, the performance degradation of the device due to dislocations can be suppressed. From the same point of view, the dislocation density on the surface of the Si-doped GaN layer is more preferably 2×10 6 cm －2 or less, and further preferably 1×10 6 cm －2 or less.

[0141] The dislocation density of the Si-doped GaN layer is preferably equal to or more than the same level as the dislocation density of the GaN crystal layer as the base crystal layer. Specifically, it is preferably 0.5 times or more and less than 2 times the dislocation density of the GaN crystal layer as the base crystal layer. In addition, the same or almost the same dislocation density means that no new dislocations are generated at the GaN crystal layer / Si-doped GaN layer interface.

[0142] In both embodiments, the GaN crystal layer forming the Si-doped GaN layer serves as the base crystal and is a layer grown by GaN epitaxy. The GaN crystal layer can also have a specific resistance less than 1×10 5 Ωcm at room temperature, that is, it is not a semi-insulating layer.

[0143] In both embodiments, the GaN crystal layer may unintentionally and unavoidably contain Si, O, H, etc. as other elements in addition to Ga and N. For example, the Si concentration may be 5×10 17 atoms / cm 3 or less. The O concentration may be 2×10 17 atoms / cm 3 or less. The H concentration may be 5×10 16 atoms / cm 3 or less. In addition, the concentrations of other elements other than these may be 5×10 15 atoms / cm 3 or less.

[0144] It should be noted that in both embodiments, when a GaN substrate is used in the manufacture of a nitride semiconductor device, sometimes the GaN crystal layer is removed and the Si-doped GaN layer is used for the nitride semiconductor device chip. If it is used in such a way, there are no particular requirements for the electrical characteristics of the GaN crystal layer.

[0145] The Si-doped GaN layer in the GaN substrate can be directly formed on the c-plane of the GaN crystal layer, or can be formed via a regrowth interface.

[0146] The regrowth interface refers to the boundary surface generated when the crystal of the Si-doped GaN layer grows on the GaN crystal layer, and its existence can be confirmed by, for example, scanning electron microscope cathodoluminescence observation or fluorescence microscope observation of the cross section of the GaN substrate wafer.

[0147] The regrowth interface also exists when the process of growing the GaN crystal layer and the Si-doped GaN layer is discontinuous.

[0148] The conductivity type, that is, the carrier type, of the Si-doped GaN layer in the GaN substrate of both embodiments is usually n-type.

[0149] The specific resistance of the Si-doped GaN layer in both embodiments at 300K is preferably 1×10 －2 Ωcm or less, more preferably 8×10 －3 Ωcm or less, and further preferably 4×10 －3 Ωcm or less. The lower the specific resistance, the more preferable it is. Usually, it is 1×10 －5 Ωcm or more.

[0150] The lower the specific resistance, the higher the electron mobility, and the nitride semiconductor device can operate at high temperature, perform high-speed operation, and obtain high output.

[0151] The specific resistance of the Si-doped GaN layer was measured by connecting terminals to the Si-doped GaN layer using the four-terminal Van der Pauw method.

[0152] The GaN substrates of the two embodiments are preferably used as wafers. The shape of the main surface can be square, rectangular, hexagonal, octagonal, elliptical, etc., and is not particularly limited. Additionally, it can also be an irregular shape.

[0153] Compared with the GaN substrate of the first embodiment, the conventional GaN substrate cannot fabricate a continuous surface without concave defects or concave portions with a depth of 5 μm or more on the surface of the Si-doped GaN layer. Even if a surface without the above-mentioned concave defects and concave portions is cut out, only a small-sized substrate can be obtained. In contrast, in the Si-doped GaN layer of the first embodiment, a surface without the above-mentioned concave defects and concave portions can be fabricated without cutting, and a large-area GaN substrate can be obtained in which the total bottom area of the concave defects or the total bottom area of the concave portions with a depth of 5 μm or more is 15% or less of the entire surface area of the Si-doped layer.

[0154] That is, when the GaN substrate of the first embodiment is a wafer, the diameter is preferably 25 mm or more. Additionally, in the GaN substrates of the two embodiments, in view of the use of nitride semiconductors, the diameter as a wafer is usually 45 mm or more, can be 50 mm or more, can also be 95 mm or more, and can further be 145 mm or more. Typically, it is 50 - 55 mm (about 2 inches), 100 - 105 mm (about 4 inches), 150 - 155 mm (about 6 inches), etc.

[0155] In addition, when the GaN crystal has a shape other than a disk shape, the diameter of a disk shape with the same area as its main surface can be the above-mentioned size.

[0156] The preferred thickness of the GaN substrate varies according to the diameter of the main surface.

[0157] When the diameter is about 2 inches, the thickness of the GaN substrate is preferably 250 - 450 μm. Here, the above thickness is preferably 250 μm or more, more preferably 300 μm or more, further preferably 350 μm or more, and preferably 450 μm or less, more preferably 400 μm or less.

[0158] When the diameter is about 4 inches, the thickness of the GaN substrate is preferably 350 - 750 μm. Here, the above thickness is preferably 350 μm or more, more preferably 400 μm or more, and preferably 750 μm or less, more preferably 650 μm or less, further preferably 600 μm or less.

[0159] When the diameter is about 6 inches, the thickness of the GaN substrate is preferably 450 to 800 μm. Here, the above thickness is preferably 450 μm or more, more preferably 550 μm or more, and preferably 800 μm or less, more preferably 700 μm or less.

[0160] In the case where the GaN substrate is composed only of an Si-doped GaN layer, the thickness of the Si-doped GaN layer is preferably in the above range.

[0161] The N-polarity surface, i.e., the (000-1) surface 102, of the GaN substrate in both embodiments can be used as the back surface and can be mirror-finished, or can be rough-finished or matte-finished.

[0162] The Ga-polarity surface, i.e., the (0001) surface 101, of the GaN substrate is used as the front surface, and a nitride semiconductor layer is further epitaxially grown on this surface and used for nitride semiconductor devices.

[0163] The (0001) surface 101 as the Ga-polarity surface can be a surface in the as-grown state after crystal growth, and is preferably a surface flattened by processing such as grinding, CMP (Chemical Mechanical Polishing), and etching. In addition, the (0001) surface 101 can be a surface formed by cutting, or can be a surface that has only been flattened without cutting.

[0164] The root mean square roughness (RMS) of the (0001) surface 101 of the GaN substrate in both embodiments measured by an atomic force microscope (AFM) is preferably less than 5 nm, more preferably less than 2 nm, further preferably less than 1 nm, and can also be less than 0.5 nm in the measurement range of 2 μm × 2 μm.

[0165] The edges of the GaN substrate in both embodiments can be chamfered. In addition, various marks such as an orientation plane or notch for indicating crystal orientation and an index plane for easily identifying the front and back surfaces can be applied to the GaN substrate as needed.

[0166] The semiconductor devices using the GaN substrates in both embodiments are basically nitride semiconductor devices. A nitride semiconductor device refers to a semiconductor device in which the main part of the device structure is formed of a nitride semiconductor.

[0167] The above nitride semiconductor is also referred to as a nitride-based III-V compound semiconductor, a group III nitride-based compound semiconductor, a GaN-based semiconductor, etc. In addition to containing GaN, it also contains a compound obtained by substituting part or all of the gallium in GaN with other group IIIA elements (B, Al, In, etc.) in the periodic table.

[0168] The type of nitride semiconductor device using the GaN substrates of the two embodiments is not limited. As an example, light-emitting devices such as laser diodes (LDs) and light-emitting diodes (LEDs), rectifiers, bipolar transistors, field-effect transistors, and other electronic devices can be cited.

[0169] [Manufacturing method of [GaN substrate (1)]]

[0170] The manufacturing methods of the GaN substrate of the first embodiment and the GaN substrate of the second embodiment are not particularly limited as long as the desired characteristics can be obtained.

[0171] As a result of intensive research by the present inventors, it has been found that as one mode of the above manufacturing method, by using a vapor deposition method when forming the Si-doped GaN layer and making the deviation angle of the substrate crystal at this time within a specific range, the GaN substrate of the first embodiment and the GaN substrate of the second embodiment can be manufactured.

[0172] Therefore, a third embodiment of the present invention relates to a method for manufacturing a Si-doped GaN layer, which is a Si-doped GaN layer in which the total bottom area of concave defects on the surface of the Si-doped GaN layer is 15% or less of the total surface area, a Si-doped GaN layer in which the total bottom area of recesses with a depth of 5 μm or more is 15% or less of the total surface area, or a Si-doped GaN layer in which the value represented by {(b / a)×100}(%) is 90% or more when the Si concentration is set to a (atoms / cm 3 ) and the carrier concentration is set to b (atoms / cm 3 ).

[0173] One mode of the manufacturing method of the Si-doped GaN layer of the third embodiment is characterized in that it is a method for manufacturing a Si-doped GaN layer with a thickness of 50 μm or more on a substrate crystal by a vapor deposition method, and the deviation angle of the above substrate crystal is 0.5° or more.

[0174] In addition, another mode of the manufacturing method of the Si-doped GaN layer of the third embodiment is characterized in that it is a method for manufacturing a Si-doped GaN layer with a Si concentration of 1×10 18 atoms / cm 3 or more on a substrate crystal by a vapor deposition method, and the deviation angle of the above substrate crystal is 0.5° or more.

[0175] That is, one mode of the manufacturing method of the GaN substrate of the first embodiment and the GaN substrate of the second embodiment includes the manufacturing method of the Si-doped GaN layer of the third embodiment as one process.

[0176] The Si concentration of the Si-doped GaN layer manufactured by the manufacturing method of the Si-doped GaN layer of the third embodiment is preferably 1×10 18 atoms / cm 3 or more.

[0177] The substrate crystal for forming the Si-doped GaN layer is preferably a c-plane GaN substrate seed crystal, and the Si-doped GaN layer is grown on its surface by chemical vapor deposition, that is, a (0001)-oriented GaN layer doped with Si.

[0178] Figure 2 It is an explanatory diagram of the tilt angle provided in the substrate crystal used in the formation method of the Si-doped GaN layer. Figure 2 In (a) of , the (0001) surface of the substrate crystal is obliquely cut as shown by the dotted line.

[0179] Figure 2 (b) of is the substrate crystal after cutting, and the enlarged view of the part surrounded by the circular symbol is Figure 2 (c) of .

[0180] As Figure 2 shown in (c) of , the angle of the (0001) surface of the cut substrate crystal is called the tilt angle θ, and the cut surface becomes a stepped shape with a step of one atomic layer thickness. According to the tilt angle θ during cutting, the terrace width W representing the width of the terrace T is different. That is, the smaller the tilt angle θ, the wider the terrace width W. For Figure 2 (c) of , as Figure 3 shown, if the tilt angle θ is increased, the terrace width W becomes narrower.

[0181] Here, by making the tilt angle θ 0.5° or more, the terrace width W becomes narrower, and in the surface of the obtained Si-doped GaN layer, the total bottom area of the concave defects or the total bottom area of the concave portions with a depth of 5 μm or more can be made 15% or less of the entire surface area of the Si-doped GaN layer, and the GaN crystal of the first embodiment can be obtained.

[0182] The reason is not clear yet, but it is considered as follows.

[0183] In the case of forming the Si-doped GaN layer by chemical vapor deposition, a gas containing Si atoms and a gas containing N atoms are used as raw materials. As described above, if Si atoms and N atoms are in the gas phase, they hardly react to form silicon nitride that becomes a shrinkage cavity. However, it is considered that if the Si, that is, the Si adsorbed atoms adsorbed on the terrace T, and the molecules containing N atoms adsorbed on the terrace T meet due to thermal motion or the like, they will react to form a shrinkage cavity.

[0184] As Figure 2As shown in (c) thereof, the wider the platform width W is, the longer the time it takes for the Si adsorbed atoms adsorbed on the surface of the platform T to move and reach the step end E where the kink site S, which is the growth site required for GaN crystal incorporation, is located. Thus, during the movement of the Si adsorbed atoms to the step end E, the probability of encountering N atoms adsorbed on the surface of the platform T and reacting to generate shrinkage holes becomes higher.

[0185] In contrast, as Figure 3 shown, it is considered that by making the deviation angle θ of the substrate crystal larger than before, the platform width W becomes narrower. As a result, the probability of encounter between the Si adsorbed atoms and the adsorbed N atoms in the platform T can be reduced. As a result, the generation of shrinkage holes can be suppressed.

[0186] When highly doping Si in a Si-doped GaN layer at a high concentration such that the Si concentration becomes, for example, 1×10 18 atoms / cm 3 or more, in the conventional case, as the density of the Si adsorbed atoms on the platform T increases, the Si adsorbed atoms encounter the adsorbed N atoms and react to form many shrinkage holes. However, by making the deviation angle θ 0.5° or more, the Si adsorbed atoms reach the step end E where the kink site S is located without forming shrinkage holes, and Si is incorporated into the kink site S. As a result, even when epitaxial growth is performed, the obtained Si-doped GaN layer has a smooth surface with few recesses.

[0187] Thus, in order to shorten the movement time of the Si adsorbed atoms on the platform T to reach the step end E, changes in the growth conditions of crystal growth have also been considered. However, it is known that, for example, if one wants to shorten the above-mentioned movement time by changing the growth temperature, a growth temperature increase in units of 100 °C is required.

[0188] Such a high temperature is not practical. For example, if one wants to perform crystal growth of GaN at 1100 °C instead of 1000 °C, GaN will decompose and cannot grow.

[0189] Similarly for the GaN substrate of the second embodiment, by making the deviation angle θ of the substrate crystal 0.5° or more, the platform width W becomes narrower. In the obtained Si-doped GaN layer, when the Si concentration is set to a (atoms / cm 3 ) and the carrier concentration is set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%) can be made 90% or more.

[0190] The reason for this is not yet clear, but it is considered as follows.

[0191] The relationship between the deviation angle θ and the platform width W is as described above. However, the conventional deviation angle θ is, for example, about 0.3°. If the substrate crystal is cut out at this angle, the platform T is wide, and the probability that Si atoms do not enter the Ga sites as their original positions but enter the interstices, anti-sites (N sites), etc. becomes high. The platform width W when the deviation angle θ is 0.3° is about 1.5 times the platform width when the deviation angle θ is 0.5°.

[0192] In contrast, it is considered that by making the deviation angle 0.5° or more, the platform width W becomes smaller, and the moving distance for Si adsorbed atoms to reach the kink site S can be shortened. As a result, Si atoms are incorporated into appropriate kink sites and can function as dopants. As a result, from the viewpoint of reducing resistance, the Si concentration is increased. As a result, even if the density of Si adsorbed atoms in the platform T increases, Si atoms are incorporated into appropriate kink sites, and thus it is considered that a high activation rate can be achieved.

[0193] Therefore, in order to obtain the Si-doped GaN layer in the two embodiments, the deviation angle of the substrate crystal in the third embodiment is preferably 0.5 to 1°. Here, the above deviation angle is preferably 0.5° or more, more preferably 0.55° or more, and further preferably 0.6° or more. On the other hand, from the viewpoint of suppressing bunching and maintaining the surface orientation characteristics of the C plane, the above deviation angle is preferably 1° or less, more preferably 0.9° or less, and further preferably 0.8° or less.

[0194] In addition to such a deviation angle of the substrate crystal, the GaN substrates of the first embodiment and the second embodiment can be obtained by using conventionally known manufacturing methods.

[0195] For example, as shown in (a) of Figure 4 , a seed wafer 1 is prepared. As shown in (b) of Figure 4 , a first GaN thick film 2 composed of unintentionally doped GaN and having a (0001) orientation is grown thereon by the HVPE method or the like. Further, as shown in (c) of Figure 4 , the first GaN thick film 2 can be processed as needed to obtain a plurality of first c-plane GaN wafers 3.

[0196] An example of the seed wafer 1 is preferably a c-plane sapphire wafer, and a peeling layer is provided on the main surface. When the peeling layer is provided, a GaN layer with a thickness of several hundred nm is grown on the c-plane sapphire wafer through a low-temperature buffer layer by an organic metal vapor phase epitaxy (MOVPE) method, and then a Ti (titanium) layer with a thickness of several tens of nm is formed on the above-mentioned GaN layer by vacuum evaporation. Then, for example, annealing is performed at 1060°C for 30 minutes in a mixed gas atmosphere of 80% H2 (hydrogen) and 20% NH3 (ammonia), thereby forming a peeling layer.

[0197] The first GaN thick film 2 is preferably thick enough to form an independent first c-plane GaN wafer 3 . For example, it is preferably grown to a thickness of several mm or more and two or more first c-plane GaN wafers 3 are obtained therefrom.

[0198] In the above obtained Figure 5 On the (0001) crystal plane of the Ga polar plane of the first c-plane GaN wafer 3 shown in (a), as shown in FIG. Figure 5 As shown in (b), a second GaN thick film 4 composed of unintentionally doped GaN and oriented (0001) is grown by HVPE. Figure 5 As shown in (c), the second GaN thick film 4 can be processed as needed to obtain a plurality of second c-plane GaN wafers 5.

[0199] The second c-plane GaN wafer 5 obtained by the above operation becomes the base crystal when the Si-doped GaN layer is formed, but it can also be appropriately flattened by grinding, polishing, CMP and other techniques as needed before the (0001) crystal plane of the Ga polar surface is obliquely cut out. In addition, after flattening, roughening can be performed by etching.

[0200] For the flattening process and the roughening process, conventionally known methods can be applied.

[0201] As described above, the off-angle, that is, the tilt angle when the (0001) crystal plane of the Ga polar plane is obliquely cut is preferably 0.5° or more, and the off-cut direction as the tilt direction is preferably the m-axis direction or the a-axis direction.

[0202] The (0001) crystal plane of the GaN crystal layer can be cut out using a wire slicing device or a laser slicing device.

[0203] right Figure 6The (0001) crystal plane of the second c-plane GaN wafer 5 with the surface shown in (a) is cut out to form an Si-doped GaN layer 6a. Between the second c-plane GaN wafer 5 and the Si-doped GaN layer 6a, as shown in Figure 6 (b), there may also be an intermediate region 6b with an Si concentration less than 1×10 18 atoms / cm 3 .

[0204] When growing the GaN crystal or the Si-doped GaN crystal as described above by the HVPE method, for example, the HVPE apparatus 20 shown in Figure 7 can be used.

[0205] Figure 7 The HVPE apparatus 20 shown in the figure includes a hot-wall reactor 21, a gallium reservoir 22 and a susceptor 23 disposed in the reactor 21, and a first heater 24 and a second heater 25 disposed outside the reactor 21. The first heater 24 and the second heater 25 respectively surround the reactor 21 in a ring shape.

[0206] The reactor 21 is a quartz tube chamber. Inside the reactor 21, there are a first region Z1 mainly heated by the first heater 24 and a second region Z2 mainly heated by the second heater 25. The exhaust pipe P E is connected to the end of the reactor 21 on the second region Z2 side.

[0207] The gallium reservoir 22 disposed in the first region Z1 is a quartz container having a gas inlet and a gas outlet.

[0208] The susceptor 23 disposed in the second region Z2 is formed of graphite, for example. A mechanism for rotating the susceptor 23 can be arbitrarily provided.

[0209] In order to grow GaN in the HVPE apparatus 20, after placing a seed crystal on the susceptor 23, the inside of the reactor 21 is heated by the first heater 24 and the second heater 25, and NH3 (ammonia) diluted by a carrier gas is supplied to the second region Z2 through an ammonia introduction pipe P1. In addition, HCl (hydrogen chloride) diluted by a carrier gas is supplied to the gallium reservoir 22 through a hydrogen chloride introduction pipe P2. The HCl reacts with the metallic gallium in the gallium reservoir 22, and the generated GaCl (gallium chloride) is transported to the second region Z2 through a gallium chloride introduction pipe P3.

[0210] In the second region Z2, NH3 reacts with GaCl, and the generated GaN crystallizes on the seed crystal placed on the susceptor 23.

[0211] When intentionally doping the grown GaN, a doping gas diluted by a carrier gas is introduced into the second region Z2 inside the reactor 21 through a dopant introduction pipe P4.

[0212] The portions of the ammonia introduction pipe P1, the hydrogen chloride introduction pipe P2, the gallium chloride introduction pipe P3, and the dopant introduction pipe P4 disposed within the reactor 21 are formed of quartz.

[0213] The carrier gases for diluting NH3, HCl, and the dopant gas respectively preferably use H2 (hydrogen), N2 (nitrogen), or a mixed gas of H2 and N2.

[0214] The preferred conditions for growing GaN using the HVPE apparatus 20 are as follows.

[0215] The temperature of the gallium reservoir 22 is, for example, 500 to 1000 °C, preferably 700 °C or higher, and further preferably 900 °C or lower.

[0216] The temperature of the susceptor 23 is, for example, 900 to 1100 °C, preferably 930 °C or higher, more preferably 950 °C or higher, and further preferably 1050 °C or lower, more preferably 1020 °C or lower.

[0217] The ratio of the NH3 partial pressure (V) to the GaCl partial pressure (III) in the reactor 21, i.e., the V / III ratio, is, for example, 1 to 20, preferably 2 or higher, more preferably 3 or higher, and further preferably 10 or lower.

[0218] Whether the V / III ratio is too large or too small, it will cause the morphology of the growth surface of GaN to deteriorate. The deterioration of the growth surface morphology will cause the crystal quality to decrease.

[0219] The growth rate of GaN can be controlled with the product of the NH3 partial pressure and the GaCl partial pressure in the reactor as a parameter. The above growth rate is, for example, 20 to 200 μm / h. When growing an Si-doped GaN layer, it is preferably 120 μm / h or lower, more preferably 100 μm / h or lower, and further preferably 80 μm / h or lower.

[0220] An excessively high growth rate causes the surface morphology of the grown GaN to deteriorate.

[0221] When doping with Si, in order to prevent the morphology of the growth surface from deteriorating, it is preferred to gradually increase the supply rate of the dopant gas from the start of supply over several minutes to several tens of minutes to a specified value.

[0222] For the same reason, the supply of the dopant gas is preferably started at the moment when the GaN layer has grown at least several μm.

[0223] The dopant gas for Si doping preferably uses SiH4 (silane), SiH3Cl (monochlorosilane), SiH2Cl2 (dichlorosilane), SiHCl3 (trichlorosilane), or SiCl4 (tetrachlorosilane).

[0224] The partial pressure of the doping gas for Si doping is preferably 1×10 －6 ~2×10 －4 kPa, more preferably 2×10 －6 kPa or more. Additionally, it is more preferably 1×10 －4 kPa or less.

[0225] The molar ratio of H2 in the carrier gas affects the impurity concentration of the grown GaN. The molar ratio of H2 in the carrier gas here is calculated based on the flow rates of the various gases supplied from outside the reactor into the reactor as the carrier gas.

[0226] If the molar ratio of H2 in the carrier gas is increased, the O concentration of GaN grown by the HVPE method during Si doping has a tendency to decrease and will become 2×10 16 atoms / cm 3 or less, and further becomes 1×10 16 atoms / cm 3 or less. This is because the surface morphology during growth is improved.

[0227] Even when GaN grown using the HVPE apparatus 10 is not intentionally doped, it contains O at a concentration detectable by SIMS. The O source is either or both of the quartz (SiO2) used in the reactor and the piping inside the reactor and the moisture remaining or intruding into the reactor. Additionally, besides the Si brought by the doping gas, Si also includes the quartz (SiO2) used in the reactor and the piping inside the reactor as a Si source.

[0228] Figure 7 The [HVPE apparatus 10] includes components whose illustrations are omitted. Besides quartz and carbon, components formed of SiC (silicon carbide), SiNx (silicon nitride), BN (boron nitride), alumina, W (tungsten), Mo (molybdenum), etc. can also be used for the components disposed inside the reactor 11. Thus, the concentration of each impurity other than Si, O, and H in GaN grown using the HVPE apparatus 10 will be 5×10 15 atoms / cm 3 or less as long as there is no intentional doping.

[0229] For the method of manufacturing the Si-doped GaN layer of the third embodiment, the Ga-polar surface of the manufactured Si-doped GaN layer can be the surface in the as-grown state after crystal growth, but it can include a process of planarizing the surface. The planarization process can use known processing methods such as grinding, CMP (Chemical Mechanical Polishing), and etching.

[0230] The method for manufacturing the Si-doped GaN layer of the third embodiment may include the following steps: slicing the Si-doped GaN layer with a thickness of 50 μm or more formed on a substrate crystal to obtain one or more independent GaN substrates. In this case, the thick film of the Si-doped GaN layer is grown to an extent where independent GaN substrates can be obtained.

[0231] In the case of slicing the Si-doped GaN substrate to obtain an independent GaN substrate, the plane orientation of the cut main plane can be arbitrarily adjusted during slicing. For example, if the independent GaN substrate is sliced from the Ga-polar surface in the as-grown state of the Si-doped GaN layer in such a way as to have a lower deviation angle, a GaN substrate with a Si-doped GaN layer and a main plane with a lower deviation angle can be obtained. By using this method, the GaN substrates of the first and second embodiments can also be obtained. In this case, the deviation angle of the main plane of the obtained GaN substrate does not necessarily need to be the same as the deviation angle of the main plane of the substrate crystal used in its manufacturing process.

[0232] [GaN substrate (2)]

[0233] One aspect of the GaN substrate of the fourth embodiment has a main plane 1 inclined 0 to 10° from the (0001) crystal plane as the Ga-polar plane, and at least has a Si-doped GaN layer on the surface of the main plane 1. The Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more. Moreover, for the Si concentration on the surface of the above Si-doped GaN layer, when the maximum value is set to α (atoms / cm 3 ), and the minimum value is set to β (atoms / cm 3 ), the value represented by [{(α - β) / α}×100](%) is 10% or less.

[0234] In addition, another aspect of the GaN substrate of the fourth embodiment has a main plane 1 inclined 0 to 10° from the (0001) crystal plane as the Ga-polar plane, and at least has a Si-doped GaN layer on the surface of the main plane 1. The Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more, and the thickness of the Si-doped GaN layer is 50 μm or more. Moreover, for the Si concentration on the surface of the above Si-doped GaN layer, when the maximum value is set to α (atoms / cm 3 ), and the minimum value is set to β (atoms / cm 3 ), the value represented by [{(α - β) / α}×100](%) is 10% or less.

[0235] In the fourth embodiment, the above-mentioned main plane 1 only needs to be inclined by 0 to 10° from the (0001) crystal plane, preferably 0 to 5°, more preferably 0 to 2.5°. The lower limit of the inclination is 0°, and it can be 0.2° or more. In addition, the upper limit of the inclination is 10°, preferably 5° or less, more preferably 2.5° or less, and can be 1.5° or less, or can be 1° or less.

[0236] In the fourth embodiment, the GaN substrate has an Si-doped GaN layer on the surface of the above-mentioned main plane 1. In this specification, "having an Si-doped GaN layer on the surface of the main plane 1" means that the outermost surface of the main plane 1 of the GaN substrate coincides with the outermost surface of the Si-doped GaN layer.

[0237] In the fourth embodiment, as Figure 1 shown, the GaN substrate 100 is (0001)-oriented, and may have a GaN crystal layer 120 and an Si-doped GaN layer 110 on the (0001) surface 101 on the Ga-polar surface side. In addition, after forming the Si-doped GaN layer 110, the GaN crystal layer 120 used as the base crystal is removed, whereby a GaN substrate 110 composed only of the Si-doped GaN layer 110 can be produced.

[0238] A (0001)-oriented GaN substrate refers to a substrate having a (0001) crystal plane, that is, a main plane parallel or substantially parallel to the c-plane, that is, a large-area plane, and is also called a c-plane GaN substrate. Here, parallel or substantially parallel means being inclined by 0 to 10° from the (0001) crystal plane as the Ga-polar surface.

[0239] The Si-doped GaN layer 110 in the fourth embodiment refers to a layer in which a part of Ga in the GaN crystal is replaced by Si.

[0240] The Si concentration in the Si-doped GaN layer 110 is 1×10 18 atoms / cm 3 or more. Thereby, low resistance can be achieved, and it is useful as a conductive substrate. From the viewpoint of low resistance, the Si concentration in the Si-doped GaN layer 110 is preferably 2×10 18 atoms / cm 3 or more, more preferably 5×10 18 atoms / cm 3 or more, still more preferably 7×10 18 atoms / cm 3 or more, particularly preferably 9×10 18 atoms / cm 3 or more, and the higher the better. The upper limit of the Si concentration is not particularly limited, for example, it is 1×10 21 atoms / cm3 as follows

[0241] It should be noted that in this specification, the concentration of donor impurities such as Si (silicon) in the Si-doped GaN layer can be determined by secondary ion mass spectrometry (SIMS). The concentration of donor impurities such as the Si concentration sometimes varies along the c-axis direction, and the average of the donor impurity concentration from a depth of 3 μm to a depth of 50 μm from the surface of the Si-doped GaN layer can be defined as the concentration of the above donor impurities.

[0242] The higher the Si concentration in the Si-doped GaN layer 110, the more difficult it is to make the Si concentration uniform in the direction parallel to the main surface 1. It is considered that the reason is the inactivation caused by the reaction of reaction precursors such as silane chloride used when doping Si with NH3 or the like as the raw material of N atoms.

[0243] If you want to form a Si-doped GaN layer with a Si concentration of 1×10 18 atoms / cm 3 or more, the inactivation of the above reaction precursor at the substrate end is particularly obvious, the doping concentration of Si decreases, and as a result, the reduction of the resistance is hindered. Therefore, it is considered that the resistance on the negative electrode side of the semiconductor device manufactured at the substrate end becomes higher.

[0244] In contrast, in the fourth embodiment, even if the Si concentration of the Si-doped GaN layer 110 is high, it is possible to uniformly achieve low resistance corresponding to the Si concentration in the entire substrate.

[0245] The detailed content of the mechanism for obtaining such a substrate is not yet clear, but it is considered as follows.

[0246] It is considered that one of the reasons why Si atoms do not enter the Ga site as the original position but enter, for example, the interstice or the anti-site (N site) is that the terrace width is wide and the moving distance until the Si atoms are incorporated into the kink site is long.

[0247] In contrast, in the present invention, it is considered that by narrowing the terrace, the distance until the Si atoms reach the kink site becomes shorter, and it is easy to incorporate the Si atoms into the appropriate kink site. In addition, it is considered that by making the distance L between the nozzle opening of the GaCl gas and the substrate surface longer than before, the diffusibility of the gas is improved, and Si atoms are well incorporated not only in the region of the nozzle close to the substrate but also at the substrate end. As a result, it is considered that the uniformity of the Si concentration is improved, and a GaN substrate in which low resistance corresponding to the Si concentration is uniformly achieved in the entire substrate can be obtained.

[0248] In the fourth embodiment, for the Si concentration on the surface of the Si-doped GaN layer, the maximum value is set to α (atoms / cm 3 ), and the minimum value is set to β (atoms / cm 3) When the value represented by [{(α - β) / α} × 100](%) is 10% or less, preferably 8% or less, more preferably 5% or less, still more preferably 3% or less, particularly preferably 2% or less, the lower the better, and generally 0.01% or more.

[0249] The maximum value α (atoms / cm of the Si concentration on the surface of the Si-doped GaN layer 3 ) and the minimum value β (atoms / cm 3 ) are specifically measured by the following method.

[0250] First, use SIMS to measure the Si concentration at three positions: the central part, the position 12.5 mm away from the center, and the position 25 mm away from the center on the surface of the Si-doped GaN layer. The maximum value α of the Si concentration usually exists in the region near the center of the Si-doped GaN layer. On the other hand, the minimum value β (atoms / cm of the Si concentration 3 ) usually exists in the region near the end of the Si-doped GaN layer. Among the Si concentrations measured at the above three positions, the maximum value is taken as α, and the minimum value is taken as β.

[0251] It should be noted that the size of the GaN substrate is not limited above. For example, in the case where the GaN substrate is a wafer with a diameter of 50 mm or more, the above content can be directly applied. However, in the case where the GaN substrate is a square substrate with a minor diameter less than 50 mm, a wafer with a diameter less than 50 mm, etc., there may sometimes be no position 12.5 mm away from the center and no position 25 mm away from the center. In this case, as long as the Si concentration is measured at three positions: the central part, the end part, and the midpoint between the central part and the end part on the surface of the Si-doped GaN layer using SIMS, and the maximum value is taken as α and the minimum value is taken as β.

[0252] The smaller the value represented by [{(α - β) / α} × 100](%), that is, the smaller the difference between the maximum value α and the minimum value β of the Si concentration, it can be said that the lower resistance corresponding to the doped Si concentration can be more uniformly achieved in the whole substrate.

[0253] In the fourth embodiment, the thickness of the Si-doped GaN layer is preferably 50 μm or more. Thus, even if it is only the Si-doped GaN layer, it has self-supporting properties, and when a GaN substrate composed only of the Si-doped GaN layer is fabricated, it can also serve as a substrate.

[0254] The thickness of the Si-doped GaN layer is preferably 50 to 300 μm. Here, the above thickness is preferably 50 μm or more, more preferably 80 μm or more, and further preferably 100 μm or more. The upper limit of the thickness is not particularly limited. For example, it is 300 μm or less, can be 200 μm or less, or can be 150 μm or less.

[0255] It should be noted that the thickness of the Si-doped GaN layer in this specification refers to the thickness of the layer with a Si concentration of 1×10 18 atoms / cm 3 or more, which can be measured by the above-mentioned SIMS. In the case where the thickness of the Si-doped GaN layer is uneven, as long as the thinnest minimum thickness is within the above range.

[0256] In the fourth embodiment, the Si-doped GaN layer may contain Group IVA elements such as Ge (germanium), and Group VIA elements such as O (oxygen) and S (sulfur) as donor impurities in addition to Si (silicon). The total concentration of donor impurities other than Si is, for example, 10% or less of the Si concentration, can be 5% or less, can also be 1% or less, and can also be 0%, that is, not contained.

[0257] As described later, the GaN substrate of the fourth embodiment is preferably grown by vapor deposition, and more preferably by hydride vapor phase epitaxy (HVPE).

[0258] In the Si-doped GaN layer obtained by the above method, even without intentional addition, O (oxygen) can be contained at a concentration of 10 15 atoms / cm 3 or more. That is, the O (oxygen) concentration of the Si-doped GaN layer can be 1×10 15 atoms / cm 3 or more.

[0259] On the other hand, the case where the Si-doped GaN layer contains other donor impurities other than Si and O at a non-negligible concentration is the case of intentional doping with the above donor impurities. It should be noted that "intentional doping" means adding the element in the form of a single substance or a compound as a raw material in order to dope the element to be targeted into the Si-doped GaN layer.

[0260] Therefore, if it is not the case of intentional doping with donor impurities other than Si and O, the total donor impurity concentration of the Si-doped GaN layer can be regarded as equal to the sum of the Si concentration and the O concentration.

[0261] Whether the Si-doped GaN layer is doped with donor impurities other than Si and O can be confirmed by elemental analysis or the like.

[0262] From the viewpoint of crystallinity, the concentration of donor impurities other than Si is preferably 1×10 17 atoms / cm 3 or less, and more preferably 8×10 16atoms / cm 3 Hereinafter, it is further preferably 5×10 16 atoms / cm 3 Hereinafter. In addition, for the same reason, the total concentration of donor impurities other than Si is preferably 2×10 17 atoms / cm 3 Hereinafter, more preferably 8×10 16 atoms / cm 3 Hereinafter, it is further preferably 5×10 16 atoms / cm 3 Hereinafter.

[0263] In the Si-doped GaN layer, other elements may also be included in addition to Ga, N, Si, and Group IVA and Group VIA element atoms as other donor impurities that constitute the GaN crystal. These other elements may be intentionally contained or may be unavoidably contained non-intentionally. For example, H (hydrogen), C (carbon), Cl (chlorine), etc. may be cited. The total concentration of these other elements may be 10 16 ~10 17 atoms / cm 3 order of magnitude.

[0264] The full width at half maximum (FWHM) of the rocking curve obtained by (004) X-ray diffraction of the Si-doped GaN layer is preferably 50 arcsec or less. The rocking curve is the diffraction intensity distribution when the direction of the incident X-ray and the position of the detector are fixed and only the crystal as the specimen is rotated in X-ray diffraction measurement, and is one of the indexes indicating the crystal quality.

[0265] The smaller the value of the full width at half maximum of the rocking curve, the fewer the crystal defects and the better the crystal quality. The full width at half maximum is preferably 40 arcsec or less, more preferably 30 arcsec or less, and further preferably 20 arcsec or less. The lower limit of the full width at half maximum is not particularly limited and is usually 5 arcsec or more. It should be noted that the full width at half maximum in this specification generally has the same meaning as the concept called the full width at half maximum. That is, it refers to the distance between the positions that show half of the maximum intensity f max showing its half intensity 1 / 2f max of the peak.

[0266] This full width at half maximum can be adjusted by the growth method (vapor phase method, liquid phase method, etc.) of the GaN crystal layer in the Si-doped GaN layer, the crystal characteristics of the seed substrate used when growing the GaN crystal layer, the crystal growth conditions, the selection of the growth surface, or the content of impurities, etc.

[0267] In the fourth embodiment, the dislocation density on the surface of the Si-doped GaN layer is preferably 5×106 cm －2 or less. In this case, it is possible to suppress a reduction in the performance of the device due to dislocations. From the same viewpoint, the dislocation density in the surface of the Si-doped GaN layer is more preferably 2×10 6 cm －2 or less, and even more preferably 1×10 6 cm －2 or less.

[0268] The dislocation density of the Si-doped GaN layer is preferably equal to or more than the dislocation density of the GaN crystal layer as the substrate crystal layer. Specifically, it is preferably 0.5 times or more and less than 2 times the dislocation density of the GaN crystal layer as the substrate crystal layer. In addition, the same or almost the same dislocation densities mean that no new dislocations are generated at the GaN crystal layer / Si-doped GaN layer interface.

[0269] In the fourth embodiment, the GaN crystal layer on which the Si-doped GaN layer is formed serves as the substrate crystal and is a layer formed by epitaxial growth of GaN. The GaN crystal layer may also have a specific resistance at room temperature of less than 1×10 5 Ωcm, that is, it is not a semi-insulating layer.

[0270] In the fourth embodiment, the GaN crystal layer may unavoidably contain Si, O, H, etc. as other elements in addition to Ga and N non-intentionally. For example, the Si concentration may be 5×10 17 atoms / cm 3 or less. The O concentration may be 2×10 17 atoms / cm 3 or less. The H concentration may be 5×10 16 atoms / cm 3 or less. In addition, the concentrations of other elements other than these may be 5×10 15 atoms / cm 3 or less.

[0271] It should be noted that in the fourth embodiment, when a GaN substrate is used in the manufacture of a nitride semiconductor device, the GaN crystal layer is sometimes removed and the Si-doped GaN layer is used for the nitride semiconductor device chip. If it is used in such a way, there are no particular requirements for the electrical characteristics of the GaN crystal layer.

[0272] The Si-doped GaN layer in the GaN substrate may be directly formed on the c-plane of the GaN crystal layer or may be formed via a regrowth interface.

[0273] The regrowth interface refers to the boundary surface generated when a crystal of an Si-doped GaN layer grows on a GaN crystal layer, and its presence can be confirmed by, for example, observing a cross section of a GaN substrate wafer using scanning electron microscope cathodoluminescence or fluorescence microscopy.

[0274] The regrowth interface also exists when the process of growing the GaN crystal layer and the Si-doped GaN layer is discontinuous.

[0275] The conductivity type, i.e., the carrier type, of the Si-doped GaN layer in the GaN substrate of the fourth embodiment is usually n-type.

[0276] The specific resistance of the Si-doped GaN layer in the fourth embodiment at 300 K is preferably 1×10 －2 Ωcm or less, more preferably 8×10 －3 Ωcm or less, and even more preferably 4×10 －3 Ωcm or less. The lower the specific resistance, the more preferable it is, and it is usually 1×10 －5 Ωcm or more.

[0277] The lower the specific resistance, the higher the electron mobility, enabling high-temperature operation, high-speed operation, and a nitride semiconductor device with high output can be obtained.

[0278] The specific resistance of the Si-doped GaN layer is obtained by measuring by connecting terminals to the Si-doped GaN layer using the four-terminal Van der Pauw method.

[0279] The GaN substrate of the fourth embodiment is preferably used as a wafer, and the shape of the main surface can be square, rectangular, hexagonal, octagonal, elliptical, etc., and there is no particular limitation. In addition, it can also be an irregular shape.

[0280] That is, when the GaN substrate of the fourth embodiment is a wafer, in view of the use of nitride semiconductors, its diameter is usually 45 mm or more, can be 50 mm or more, can also be 95 mm or more, and can further be 145 mm or more. Typically, it is 50 - 55 mm (about 2 inches), 100 - 105 mm (about 4 inches), 150 - 155 mm (about 6 inches), etc.

[0281] In addition, when the GaN crystal is in a shape other than a disk shape, a disk shape with the same area as the main surface can be used with a diameter of the above size.

[0282] The preferred thickness of the GaN substrate varies according to the diameter of the main surface.

[0283] When the diameter is about 2 inches, the thickness of the GaN substrate is preferably 250 to 450 μm. Here, the above thickness is preferably 250 μm or more, more preferably 300 μm or more, further preferably 350 μm or more, and preferably 450 μm or less, more preferably 400 μm or less.

[0284] When the diameter is about 4 inches, the thickness of the GaN substrate is preferably 350 to 750 μm. Here, the above thickness is preferably 350 μm or more, more preferably 400 μm or more, and preferably 750 μm or less, more preferably 650 μm or less, further preferably 600 μm or less.

[0285] When the diameter is about 6 inches, the thickness of the GaN substrate is preferably 450 to 800 μm. Here, the above thickness is preferably 450 μm or more, more preferably 550 μm or more, and preferably 800 μm or less, more preferably 700 μm or less.

[0286] In the case where the GaN substrate is composed only of an Si-doped GaN layer, the thickness of the Si-doped GaN layer is preferably in the above range.

[0287] The N-polarity surface, i.e., the (000-1) surface 102, of the GaN substrate of the fourth embodiment can be mirror-finished as the back surface, or can be rough-finished or matte-finished.

[0288] The Ga-polarity surface, i.e., the (0001) surface 101, of the GaN substrate is used as the front surface, and a nitride semiconductor layer is further epitaxially grown on this surface for use in a nitride semiconductor device.

[0289] The (0001) surface 101 as the Ga-polarity surface may be a surface in the as-grown state after crystal growth, and is preferably a surface flattened by processing such as grinding, CMP (Chemical Mechanical Polishing), and etching. In addition, the (0001) surface 101 may be a surface formed by cutting, or may be a surface on which only the above flattening is performed without cutting.

[0290] The root mean square roughness (RMS) of the (0001) surface 101 of the GaN substrate of the fourth embodiment measured by an atomic force microscope (AFM) is preferably less than 5 nm, more preferably less than 2 nm, further preferably less than 1 nm, and may also be less than 0.5 nm in the measurement range of 2 μm × 2 μm.

[0291] The edge of the GaN substrate of the fourth embodiment can be chamfered. In this case, the value represented by [{(α - β) / α} × 100](%) related to the Si concentration is also 10% or less.

[0292] In addition, various marks such as an orientation plane or notch for indicating crystal orientation and an index plane for easily identifying the front and back surfaces can be applied to the GaN substrate as needed.

[0293] The semiconductor device using the GaN substrate of the fourth embodiment is basically a nitride semiconductor device. A nitride semiconductor device refers to a semiconductor device in which the main part of the device structure is formed of a nitride semiconductor.

[0294] The above-mentioned nitride semiconductor is also referred to as a nitride-based III-V compound semiconductor, a group III nitride-based compound semiconductor, a GaN-based semiconductor, etc. In addition to containing GaN, it also contains a compound obtained by substituting part or all of the gallium in GaN with other group IIIA elements (B, Al, In, etc.) of the periodic table.

[0295] The type of the nitride semiconductor device using the GaN substrate of the fourth embodiment is not limited. As an example, light-emitting devices such as a laser diode (LD) and a light-emitting diode (LED), electronic devices such as a rectifier, a bipolar transistor, and a field-effect transistor can be cited.

[0296] [Manufacturing method of GaN substrate (2)]

[0297] The manufacturing method of the GaN substrate of the fourth embodiment is not particularly limited as long as the desired characteristics can be obtained.

[0298] The present inventors have conducted in-depth research and found that as one mode of the above manufacturing method, by using a vapor deposition method when forming the Si-doped GaN layer, and making the deviation angle of the substrate crystal at this time within a specific range, and in addition, making the distance between the nozzle opening of the GaCl gas as a raw material and the substrate surface in the reactor within a specific range, the GaN substrate of the fourth embodiment can be manufactured.

[0299] Therefore, the present invention also relates to a method for manufacturing a Si-doped GaN layer. For the Si concentration on the surface of the Si-doped GaN layer, when the maximum value is set to α (atoms / cm 3 ), and the minimum value is set to β (atoms / cm 3 ), the value represented by [{(α - β) / α} × 100] (%) is 10% or less.

[0300] The manufacturing method of the Si-doped GaN layer is characterized in that a Si-doped GaN layer having a Si concentration of 1 × 10 18 atoms / cm 3The method of forming the Si-doped GaN layer described above makes the deviation angle of the above substrate crystal 0.5° or more, and the distance between the nozzle opening for ejecting the gas containing Ga atoms onto the above substrate crystal surface and the above substrate crystal surface is preferably 100 mm or more. Here, the thickness of the above Si-doped GaN layer is preferably 50 μm or more.

[0301] That is, one aspect of the method for manufacturing the GaN substrate described in the above [GaN substrate (2)] includes the method for manufacturing the above Si-doped GaN layer as one step.

[0302] The substrate crystal for forming the Si-doped GaN layer is preferably a c-plane GaN substrate seed crystal, and a Si-doped GaN layer, that is, a (0001)-oriented GaN layer doped with Si, is grown on its surface by chemical vapor deposition.

[0303] Figure 2 It is an explanatory diagram of the deviation angle provided in the substrate crystal used in the method for forming the Si-doped GaN layer. Figure 2 In (a) of, the (0001) surface of the substrate crystal is obliquely cut as shown by the dotted line.

[0304] Figure 2 (b) of is the substrate crystal after cutting, and the enlarged view of the part surrounded by the circular symbol is Figure 2 (c) of.

[0305] As Figure 2 shown in (c) of, the angle of cutting the (0001) surface of the substrate crystal is called the deviation angle θ, and the cut cross-section becomes a stepped shape with a step difference having a thickness of one atomic layer. According to the deviation angle θ during cutting, the terrace width W indicating the width of the terrace T is different. That is, the smaller the deviation angle θ, the wider the terrace width W. For Figure 2 (c) of, as Figure 3 shown, if the deviation angle θ is increased, the terrace width W becomes narrower.

[0306] Here, by making the deviation angle θ 0.5° or more, the terrace width W becomes narrower. Specifically, as Figure 2 shown in (c) of, the wider the terrace width W, the longer the time it takes for the Si adatoms adsorbed on the surface of the terrace T to move and reach the step edge E where the kink site S required for incorporation into the GaN crystal is located.

[0307] In contrast, as Figure 3 shown, by making the deviation angle θ of the substrate crystal larger than before, the terrace width W becomes narrower, and the time it takes to move and reach the step edge E where the kink site S is located becomes shorter. As a result, Si atoms easily enter the appropriate sites.

[0308] In addition, inFigure 7 In the reactor 21 shown, by making the distance L between the nozzle opening of the introduction pipe P3 that ejects a gas containing Ga atoms onto the substrate crystal and the surface of the substrate crystal preferably 100 mm or more, the gas is further diffused. As a result, Si atoms are easily incorporated into appropriate sites.

[0309] When doping Si into the GaN layer at a high concentration of 1×10 18 atoms / cm 3 or more in the above-described manner, in the past, the uniformity of the Si concentration on the surface of the Si-doped GaN layer decreased. However, by making the deviation angle θ 0.5° or more, and further making the distance L between the nozzle opening of the introduction pipe P3 that ejects a gas containing Ga atoms onto the substrate crystal and the surface of the substrate crystal preferably 100 mm or more, it is possible to increase the Si concentration at the end portion of the substrate to the same level as near the center of the substrate, and it is possible to uniformly achieve low resistance corresponding to the doped Si concentration throughout the substrate.

[0310] Therefore, in order to obtain the Si-doped GaN layer of the fourth embodiment, the deviation angle of the substrate crystal is preferably 0.5 to 1°. Here, the above deviation angle is preferably 0.5° or more, more preferably 0.55° or more, and further preferably 0.6° or more. On the other hand, from the viewpoints of suppressing bunching and maintaining the surface orientation characteristics of the C plane, the deviation angle is preferably 1° or less, more preferably 0.9° or less, and further preferably 0.8° or less.

[0311] In addition, the distance L between the nozzle opening of the introduction pipe P3 that ejects a gas containing Ga atoms onto the substrate crystal and the surface of the substrate crystal is preferably 100 to 300 mm. Here, the above distance L is preferably 100 mm or more, more preferably 110 mm or more, and further preferably 120 mm or more. On the other hand, from the viewpoint of maintaining the growth rate, the distance L is preferably 300 mm or less, more preferably 250 mm or less, and further preferably 200 mm or less.

[0312] From the viewpoint of further improving the uniformity of the Si concentration, it is preferable to arrange the nozzle openings of the introduction pipe P1 that ejects a gas containing N atoms and the dopant introduction pipe P4 onto the substrate crystal on the same horizontal line as the nozzle opening of the above introduction pipe P3. That is, the distance L between the nozzle openings of the introduction pipe P1 and the introduction pipe P4 and the surface of the substrate crystal is preferably equal to the distance L between the nozzle opening of the introduction pipe P3 and the surface of the substrate crystal. In this case, the uniformity of the Si concentration can be further improved.

[0313] In addition to such a deviation angle of the substrate crystal and the above distance L, a GaN substrate having a Si-doped GaN layer of the fourth embodiment can be obtained by using a conventionally known manufacturing method.

[0314] For example, Figure 4 As shown in (a), a seed wafer 1 is prepared, such as Figure 4 As shown in (b), a first GaN thick film 2 composed of unintentionally doped GaN and oriented in the (0001) direction is grown thereon by HVPE method or the like. Figure 4 As shown in (c), the first GaN thick film 2 may be processed as needed to obtain a plurality of first c-plane GaN wafers 3 .

[0315] An example of the seed wafer 1 is preferably a c-plane sapphire wafer, and a peeling layer is provided on the main surface. When the peeling layer is provided, a GaN layer with a thickness of several hundred nm is grown on the c-plane sapphire wafer through a low-temperature buffer layer by an organic metal vapor phase epitaxy (MOVPE) method, and then a Ti (titanium) layer with a thickness of several tens of nm is formed on the above-mentioned GaN layer by vacuum evaporation. Then, for example, annealing is performed at 1060°C for 30 minutes in a mixed gas atmosphere of 80% H2 (hydrogen) and 20% NH3 (ammonia), thereby forming a peeling layer.

[0316] The first GaN thick film 2 is preferably thick enough to form an independent first c-plane GaN wafer 3 . For example, it is preferably grown to a thickness of several mm or more and two or more first c-plane GaN wafers 3 are obtained therefrom.

[0317] In the above obtained Figure 5 On the (0001) crystal plane of the Ga polar plane of the first c-plane GaN wafer 3 shown in (a), as shown in FIG. Figure 5 As shown in (b), a second GaN thick film 4 composed of unintentionally doped GaN and oriented (0001) is grown by HVPE. Figure 5 As shown in (c), the second GaN thick film 4 can be processed as needed to obtain a plurality of second c-plane GaN wafers 5.

[0318] The second c-plane GaN wafer 5 obtained by the above operation becomes the base crystal when the Si-doped GaN layer is formed, but it can also be appropriately flattened by grinding, polishing, CMP and other techniques as needed before the (0001) crystal plane of the Ga polar surface is obliquely cut out. In addition, after flattening, roughening can be performed by etching.

[0319] For the flattening process and the roughening process, conventionally known methods can be applied.

[0320] The tilt angle, i.e., the deviation angle, when obliquely cutting the (0001) crystal plane of the Ga polar plane is preferably 0.5° or more as described above, and the crystal orientation deviation direction as the tilt direction is preferably the m-axis direction or the a-axis direction.

[0321] The cutting of the (0001) crystal plane of the GaN crystal layer can be performed using a wire slicing device or a laser slicing device.

[0322] For Figure 6 the (0001) crystal plane of the second c-plane GaN wafer 5 whose surface shown in (a) is cut out, a Si-doped GaN layer 6a is formed. Between the second c-plane GaN wafer 5 and the Si-doped GaN layer 6a, as Figure 6 shown in (b), there may also be an intermediate region 6b with a Si concentration less than 1×10 18 atoms / cm 3 .

[0323] When growing the GaN crystal or the Si-doped GaN crystal in the above by the HVPE method, for example, the HVPE apparatus 20 shown in Figure 7 can be used.

[0324] Figure 7 The HVPE apparatus 20 shown in

[0325] includes a hot-wall type reactor 21, a gallium reservoir 22 and a susceptor 23 disposed in the reactor 21, and a first heater 24 and a second heater 25 disposed outside the reactor 21. The first heater 24 and the second heater 25 respectively surround the reactor 21 in a ring shape.

[0325] The reactor 21 is a quartz tube chamber. Inside the reactor 21, there is a first region Z1 mainly heated by the first heater 24 and a second region Z2 mainly heated by the second heater 25. The exhaust pipe P E is connected to the end of the reactor 21 on the second region Z2 side.

[0326] The gallium reservoir 22 disposed in the first region Z1 is a quartz container having a gas inlet and a gas outlet.

[0327] The susceptor 23 disposed in the second region Z2 is formed of, for example, graphite. A mechanism for rotating the susceptor 23 can be arbitrarily provided.

[0328] In order to grow GaN in the HVPE apparatus 20, after placing the seed crystal on the susceptor 23, the inside of the reactor 21 is heated by the first heater 24 and the second heater 25, and NH3 (ammonia) diluted with a carrier gas is supplied to the second region Z2 through the ammonia introduction pipe P1. Additionally, HCl (hydrogen chloride) diluted with a carrier gas is supplied to the gallium reservoir 22 through the hydrogen chloride introduction pipe P2. This HCl reacts with the metallic gallium in the gallium reservoir 22, and the generated GaCl (gallium chloride) is transported to the second region Z2 through the gallium chloride introduction pipe P3.

[0329] The distance L between the substrate surface in the second region Z2 and the nozzle opening of the gallium chloride introduction pipe P3 is preferably 100 mm or more as described above. Similarly, the nozzle openings of the ammonia introduction pipe P1 and the dopant introduction pipe P4 are preferably arranged on the same horizontal plane as the nozzle opening of the gallium chloride introduction pipe P3.

[0330] In the second region Z2, NH3 reacts with GaCl, and the generated GaN crystallizes on the seed crystal placed on the susceptor 23.

[0331] When intentionally doping the grown GaN, a dopant gas diluted with a carrier gas is introduced into the second region Z2 inside the reactor 21 through the dopant introduction pipe P4.

[0332] The portions of the ammonia introduction pipe P1, the hydrogen chloride introduction pipe P2, the gallium chloride introduction pipe P3, and the dopant introduction pipe P4 disposed inside the reactor 21 are formed of quartz.

[0333] The carrier gases used to dilute NH3, HCl, and the dopant gas are preferably H2 (hydrogen), N2 (nitrogen), or a mixed gas of H2 and N2.

[0334] The preferred conditions for growing GaN using the HVPE apparatus 20 are as follows.

[0335] The temperature of the gallium reservoir 22 is, for example, 500 to 1000 °C, preferably 700 °C or higher, and additionally, preferably 900 °C or lower.

[0336] The temperature of the susceptor 23 is, for example, 900 to 1100 °C, preferably 930 °C or higher, more preferably 950 °C or higher, and additionally, preferably 1050 °C or lower, more preferably 1020 °C or lower.

[0337] The ratio of the NH3 partial pressure (V) to the GaCl partial pressure (III) in the reactor 21, i.e., the V / III ratio, is, for example, 1 to 20, preferably 2 or higher, more preferably 3 or higher, and additionally, preferably 10 or lower.

[0338] Whether the V / III ratio is too large or too small, it will cause the morphology of the growth surface of GaN to deteriorate. The deterioration of the growth surface morphology will cause the crystal quality to decrease.

[0339] The growth rate of GaN can be controlled by taking the product of the partial pressure of NH3 and the partial pressure of GaCl in the reactor as a parameter. The above growth rate is, for example, 20 to 200 μm / h. When growing a Si-doped GaN layer, it is preferably 120 μm / h or less, more preferably 100 μm / h or less, and still more preferably 80 μm / h or less.

[0340] An excessively high growth rate deteriorates the surface morphology of the grown GaN.

[0341] When doping with Si, in order to prevent the surface morphology of the growth surface from deteriorating, it is preferable to gradually increase the supply rate of the doping gas from the start of supply over several minutes to several tens of minutes to a specified value.

[0342] For the same reason, the supply of the doping gas is preferably started at the time when the GaN layer has grown at least several μm.

[0343] The doping gas for Si doping is preferably SiH4 (silane), SiH3Cl (monochlorosilane), SiH2Cl2 (dichlorosilane), SiHCl3 (trichlorosilane), or SiCl4 (tetrachlorosilane).

[0344] The partial pressure of the doping gas for Si doping is preferably 1×10 －6 ~2×10 －4 kPa, more preferably 2×10 －6 kPa or more, and further preferably 1×10 －4 kPa or less.

[0345] The molar ratio of H2 in the carrier gas affects the impurity concentration of the grown GaN. The molar ratio of H2 in the carrier gas here is calculated based on the flow rates of various gases supplied from outside the reactor into the reactor as the carrier gas.

[0346] If the molar ratio of H2 in the carrier gas is increased, the O concentration of GaN grown by the HVPE method when doped with Si has a tendency to decrease and will become 2×10 16 atoms / cm 3 or less, and further becomes 1×10 16 atoms / cm 3 or less. This is because the surface morphology during growth is improved.

[0347] Even when GaN grown using the HVPE apparatus 10 is not intentionally doped, it contains O at a concentration detectable by SIMS. The O source is either or both of the quartz (SiO2) used for the reactor and the pipes inside the reactor and the moisture remaining or intruding into the reactor. In addition, Si contains, as a Si source, the quartz (SiO2) used for the reactor and the pipes inside the reactor, in addition to the Si brought by the doping gas.

[0348] Figure 7 The figure includes components whose illustrations are omitted. Components disposed inside the reactor 11 can use components formed of SiC (silicon carbide), SiNx (silicon nitride), BN (boron nitride), alumina, W (tungsten), Mo (molybdenum), etc., in addition to quartz and carbon. Thus, as long as there is no intentional doping, the concentration of each impurity other than Si, O, and H in the GaN grown using the HVPE apparatus 10 will be 15 atoms / cm 3 or less.

[0349] Regarding the method for manufacturing the Si-doped GaN layer of the fourth embodiment, the Ga-polar surface of the manufactured Si-doped GaN layer can be the surface in the as-grown state after crystal growth, but can include a process of planarizing the surface. The planarization process can use known processing methods such as grinding, CMP (Chemical Mechanical Polishing), and etching.

[0350] The method for manufacturing the Si-doped GaN layer of the fourth embodiment can include the following process: slicing the Si-doped GaN layer manufactured on the substrate crystal to obtain one or more independent GaN substrates. In this case, the thick Si-doped GaN layer is grown to an extent where independent GaN substrates can be obtained.

[0351] When slicing the Si-doped GaN substrate to obtain an independent GaN substrate, the plane orientation of the cut main surface can be arbitrarily adjusted during slicing. For example, if the independent GaN substrate is sliced from the Ga-polar surface in the as-grown state of the Si-doped GaN layer in a manner to achieve a lower deviation angle, a GaN substrate with a Si-doped GaN layer whose main surface is low-deviation-angled can be obtained. Using this method, the GaN substrates of the first and second embodiments can also be obtained. In this case, the deviation angle of the main surface of the obtained GaN substrate does not necessarily need to be the same as the deviation angle of the main surface of the substrate crystal used in its manufacturing process.

[0352] Examples

[0353] Hereinafter, the present invention will be specifically described with reference to examples, but the present invention is not limited to these.

[0354] [Example 1-1]

[0355] 1. Epitaxial growth of GaN crystal

[0356] Using a vapor growth apparatus equipped with a quartz hot-wall reactor, a Si-doped GaN layer of GaN crystal doped with Si is epitaxially grown on an independent GaN seed crystal with a diameter of 62 mm and a thickness of 400 μm by the HVPE method. The crystal orientation deviation direction and deviation angle of the independent GaN seed crystal are the m-axis direction and 0.55°.

[0357] In this process, the following (1) heating step, (2) Si-doped GaN layer growth step, and (3) cooling step are carried out in sequence.

[0358] (1) Heating step

[0359] Initially, an independent GaN seed crystal is set in the reactor.

[0360] Next, while supplying ammonia and carrier gas to the independent GaN seed crystal, the reactor temperature is raised from room temperature to 1000 °C. The carrier gas uses a mixed gas of hydrogen and nitrogen.

[0361] (2) Si-doped GaN layer growth step

[0362] While maintaining the reactor temperature at 1000 °C, a mixed gas shown in the following growth conditions containing ammonia and gallium chloride is supplied as a source gas, so that a Si-doped GaN layer is epitaxially grown on the independent GaN seed crystal to a thickness of 200 μm.

[0363] The growth rate is 50 μm / hr, and the growth conditions are as follows: reactor pressure 101 kPa, ammonia partial pressure 2.57 kPa, GaCl partial pressure 1.23 kPa, hydrogen partial pressure 51.67 kPa, nitrogen partial pressure 45.40 kPa, HCl gas partial pressure 0.13 kPa, dichlorosilane partial pressure 4.36×10 －5 kPa.

[0364] It should be noted that the flow rate of dichlorosilane is increased to reach the specified partial pressure within 1 minute. Thus, it is confirmed that the dislocation density of the Si-doped GaN layer is substantially the same as that of the independent GaN seed crystal, and no new dislocations are generated at the interface between the independent GaN seed crystal / Si-doped GaN layer.

[0365] The gas partial pressure (P G ) means the value obtained by multiplying the ratio (r) of the volume flow rate of this gas in the total volume flow rate of all gases supplied into the reactor by the reactor pressure (P R ), that is, P G = r×PR The value represented.

[0366] (3) Cooling step

[0367] After the growth step of the Si-doped GaN layer in the above (2) is completed, the supply of gallium chloride to the independent GaN seed is stopped, and the heating of the reactor is stopped to lower the reactor temperature to room temperature. The gas flowing into the reactor is ammonia and nitrogen before the temperature drops to 600 °C, and only nitrogen thereafter.

[0368] The entire surface of the as-grown GaN crystal taken out from the reactor is mirror-like and flat.

[0369] 2. Fabrication of GaN substrate

[0370] The as-grown GaN crystal obtained in the above 1. is subjected to laser coring processing to obtain a GaN substrate as a circular epitaxial substrate with a diameter of 50.8 mm.

[0371] Next, grinding and polishing finishing of the +C plane and -C plane are performed in sequence, thereby completing a 2-inch c-plane GaN substrate with a thickness of 100 μm for the Si-doped GaN layer and a thickness of 300 μm for the GaN crystal layer. The crystal orientation deviation direction and deviation angle of the c-plane GaN substrate are the m-axis direction and 0.55°.

[0372] 3. Evaluation of GaN substrate

[0373] <Observation of recesses on the surface of the Si-doped GaN layer>

[0374] The GaN substrate as the circular epitaxial substrate obtained in the above 2. is irradiated with ultraviolet light for observation to obtain a fluorescence image. The results are shown in Figure 8 , and no recesses accompanied by shrinkage holes are observed on the surface of the Si-doped GaN layer. That is, the total bottom area of the concave defects and the total bottom area of the recesses with a depth of 5 μm or more on the surface of the Si-doped GaN layer of the GaN substrate are both 0% of the total surface area of the surface of the Si-doped GaN layer. In addition, on the surface of the Si-doped GaN layer of the GaN substrate, one or more 25 mm × 25 mm squares without concave defects are found, and one or more 25 mm × 25 mm squares without recesses with a depth of 5 μm or more are found.

[0375] <Measurement of Si concentration>

[0376] The Si concentration of the Si-doped GaN layer in the obtained c-plane GaN substrate is measured by SIMS.

[0377] As a result, the Si concentration is 7×10 18 atoms / cm3 .

[0378] [Example 1-2]

[0379] The GaN substrate obtained in Example 1-1 is a substrate in which the used GaN crystal layer is an independent GaN seed, that is, an undoped GaN seed, and an Si-doped GaN layer is formed thereon. Therefore, it is difficult to accurately measure the carrier concentration by Hall measurement.

[0380] Therefore, a semi-insulating GaN seed of an Mn-doped GaN substrate with an Mn concentration of 1×10 18 atoms / cm 3 is used to replace the independent GaN seed in Example 1-1, and an Si-doped GaN layer is grown thereon. For the Si-doped GaN layer, the growth time is changed so that the thickness becomes 50 μm, and except for this, it is grown under the same growth conditions as in Example 1-1.

[0381] Here, the specific resistance of the Mn-doped GaN substrate is 1×10 20 Ωcm or more. Therefore, no current enters the semi-insulating GaN seed part during Hall measurement, and accurate Hall measurement can be performed.

[0382] The entire surface of the as-grown GaN crystal taken out from the reactor via the cooling step is mirror-like and flat.

[0383] <Observation of Concavities on the Surface of the Si-Doped GaN Layer>

[0384] A fluorescence image of the surface of the as-grown GaN crystal is obtained in the same manner as in Example 1-1. As a result, concavities accompanied by shrinkage holes are not observed at all on the surface of the Si-doped GaN layer. That is, the total bottom area of the concave defects and the total bottom area of the concavities with a depth of 5 μm or more on the surface of the Si-doped GaN layer of the GaN substrate are both 0% of the total surface area of the above Si-doped GaN layer. In addition, on the surface of the Si-doped GaN layer of the GaN substrate, a 25 mm×25 mm square without concave defects is found in one or more places, and a 25 mm×25 mm square without concavities with a depth of 5 μm or more is found in one or more places.

[0385] <Measurement of Si Concentration>

[0386] The Si concentration of the Si-doped GaN layer in the obtained c-plane GaN substrate is measured by SIMS.

[0387] As a result, the Si concentration is 7×10 18 atoms / cm 3 .

[0388] <Measurement of Carrier Concentration, Specific Resistance, and Carrier Type>

[0389] For Hall measurement, Ti 30 nm and Au 100 nm were continuously vacuum-evaporated on the surface of the obtained c-plane GaN substrate. The Hall measurement was performed using the four-terminal Van der Pauw method by connecting the terminals to the Si-doped GaN layer of the substrate and measuring at 300 K.

[0390] As a result, the carrier concentration of the Si-doped GaN layer was 7×10 18 atoms / cm 3 , the specific resistance was 5×10 －3 Ωcm, and the carrier type was n-type.

[0391] Based on this result, when the Si concentration of the Si-doped GaN layer was set to a (atoms / cm 3 ), and the carrier concentration was set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%), i.e., the activation rate, was 100%.

[0392] [Examples 1-3]

[0393] In the growth conditions of the Si-doped GaN layer growth step, the dichlorosilane partial pressure was changed to 6.16×10 －5 kPa. Except for this, the as-grown GaN crystals were obtained in the same manner as in Examples 1-2. The entire surface of the as-grown GaN crystals taken out from the reactor via the cooling step was mirror-like and flat.

[0394] <Observation of Concave Portions on the Surface of the Si-doped GaN Layer>

[0395] The fluorescence image of the surface of the as-grown GaN crystals was obtained in the same manner as in Example 1-1. As a result, concave portions accompanied by shrinkage holes were not observed at all on the surface of the Si-doped GaN layer. That is, the total bottom area of the concave defects and the total bottom area of the concave portions with a depth of 5 μm or more on the surface of the Si-doped GaN layer of the GaN substrate were both 0% of the entire surface area of the Si-doped GaN layer. In addition, on the surface of the Si-doped GaN layer of the GaN substrate, a 25 mm×25 mm square without concave defects was found at one or more locations, and a 25 mm×25 mm square without concave portions with a depth of 5 μm or more was found at one or more locations.

[0396] <Measurement of Si Concentration>

[0397] The Si concentration of the Si-doped GaN layer in the obtained c-plane GaN substrate was measured by SIMS.

[0398] As a result, the Si concentration was 9×1018 atoms / cm 3 。

[0399] <Measurement of Carrier Concentration, Specific Resistance, and Carrier Type>

[0400] Hall measurements were carried out at 300 K in the same manner as in Examples 1-2.

[0401] As a result, the carrier concentration of the Si-doped GaN layer was 9×10 18 atoms / cm 3 , the specific resistance was 3.5×10 －3 Ωcm, the carrier type was n-type, and the activation rate was 100%.

[0402] [Comparative Example 1-1]

[0403] In Example 1-1, the deviation direction and deviation angle of the independent GaN seed crystal orientation were the m-axis direction and 0.35°, and except for this, the Si-doped GaN layer was grown by the same method to obtain as-grown GaN crystals.

[0404] A fluorescence image of the surface of the as-grown GaN crystal was obtained in the same manner as in Example 1-1. The fluorescence image is shown in Figure 9 , and concave portions accompanied by shrinkage pores were observed on the surface of the Si-doped GaN layer. The depth of the concave portions as concave defects was approximately 200 μm, which was approximately equal to the growth thickness of the Si-doped GaN layer. In addition, with respect to the total area of the surface of the Si-doped GaN layer, the total bottom area of the concave portions with a depth of 5 μm or more was 16%, and the total bottom area of the concave defects was 16% or more.

[0405] [Comparative Example 1-2]

[0406] In Example 1-1, the deviation direction and deviation angle of the independent GaN seed crystal orientation were the a-axis direction and 0.40°, and except for this, the Si-doped GaN layer was grown by the same method to obtain as-grown GaN crystals.

[0407] A fluorescence image of the surface of the as-grown GaN crystal was obtained in the same manner as in Example 1-1. As a result, concave portions accompanied by shrinkage pores were observed on the surface of the Si-doped GaN layer. The depth of the concave portions as concave defects was approximately 200 μm, which was approximately equal to the growth thickness of the Si-doped GaN layer. In addition, with respect to the total area of the surface of the Si-doped GaN layer, the total bottom area of the concave portions with a depth of 5 μm or more was greater than 16%, and the total bottom area of the concave defects was greater than 16%.

[0408] [Reference Example 1-1]

[0409] In Example 1-1, an Si-doped GaN layer on an independent GaN seed was epitaxially grown to a thickness of 5 mm to obtain a as-grown GaN crystal. After slicing the obtained as-grown GaN crystal using a wire saw, laser core drilling and surface grinding were performed. In addition, a c-plane GaN substrate with a diameter of 50.8 mm was obtained by the same method as in Example 1-1. The crystal orientation deviation direction and deviation angle of the c-plane GaN substrate were in the m-axis direction and 0.35°.

[0410] <Measurement of Carrier Concentration, Specific Resistance, and Carrier Type>

[0411] Similar to Example 1-2, Hall measurements were performed at 300 K.

[0412] As a result, the carrier concentration of the Si-doped GaN layer was 5×10 18 atoms / cm 3 , the specific resistance was 4.9×10 －3 Ωcm, and the carrier type was n-type.

[0413] As inspired by this reference example, by changing the crystal growth conditions and processing conditions of Example 1-1, a c-plane GaN substrate with a deviation angle different from that of the independent GaN seed can be obtained.

[0414] [Example 2-1]

[0415] 1. Epitaxial Growth of GaN Crystal

[0416] Using a vapor-phase growth apparatus equipped with a quartz hot-wall reactor, an Si-doped GaN layer of GaN crystal doped with Si was epitaxially grown on an independent GaN seed with a diameter of 62 mm and a thickness of 400 μm. The crystal orientation deviation direction and deviation angle of the independent GaN seed were in the m-axis direction and 0.55°. In addition, the distance L between the nozzle opening of the GaCl gas and the surface of the independent GaN seed was 150 mm. It should be noted that the nozzle openings of ammonia gas and dopant gas were arranged on the same horizontal plane. That is, the distance L between the nozzle openings of ammonia gas and dopant gas and the surface of the independent GaN seed was also 150 mm.

[0417] In this process, the following (1) heating step, (2) Si-doped GaN layer growth step, and (3) cooling step were performed in sequence.

[0418] (1) Heating Step

[0419] Initially, an independent GaN seed was placed in the reactor.

[0420] Next, while supplying ammonia and carrier gas to the independent GaN seed crystal, the reactor temperature is raised from room temperature to 1000 °C. The carrier gas used is a mixed gas of hydrogen and nitrogen.

[0421] (2) Si-doped GaN layer growth step

[0422] While maintaining the reactor temperature at 1000 °C, a mixed gas shown in the following growth conditions containing ammonia and gallium chloride is supplied as the source gas, so that the Si-doped GaN layer is epitaxially grown on the independent GaN seed crystal to a thickness of 200 μm.

[0423] The growth rate is 50 μm / hr, and the growth conditions are as follows: reactor pressure 101 kPa, ammonia partial pressure 2.57 kPa, GaCl partial pressure 1.23 kPa, hydrogen partial pressure 51.67 kPa, nitrogen partial pressure 45.40 kPa, HCl gas partial pressure 0.13 kPa, dichlorosilane partial pressure 4.36×10 －5 kPa.

[0424] It should be noted that the flow rate of dichlorosilane is increased to reach the specified partial pressure within 1 minute. Thus, it is confirmed that the dislocation density of the Si-doped GaN layer is approximately the same as that of the independent GaN seed crystal, and no new dislocations are generated at the interface between the independent GaN seed crystal / Si-doped GaN layer.

[0425] The gas partial pressure (P G ) here refers to the value obtained by multiplying the ratio (r) of the volume flow rate of the gas to the total volume flow rate of all gases supplied into the reactor by the reactor pressure (P R ), that is, P G = r×P R represents the value.

[0426] (3) Cooling step

[0427] After the Si-doped GaN layer growth step in (2) above is completed, the supply of gallium chloride to the independent GaN seed crystal is stopped, and the heating of the reactor is stopped, so that the reactor temperature drops to room temperature. The gas flowing into the reactor is ammonia and nitrogen before the temperature drops to 600 °C, and only nitrogen thereafter.

[0428] The entire surface of the as-grown GaN crystal taken out from the reactor is mirror-like and flat.

[0429] 2. Fabrication of GaN substrate

[0430] The as-grown GaN crystal obtained in 1. above is subjected to laser core drilling to obtain a GaN substrate as a circular epitaxial substrate with a diameter of 50.8 mm.

[0431] Next, the grinding process and the polishing finish process of the +C surface and the -C surface are successively performed, thereby completing a 2-inch c-plane GaN substrate with a thickness of 100 μm for the Si-doped GaN layer and a thickness of 300 μm for the GaN crystal layer.

[0432] 3. Evaluation of GaN Substrate

[0433] <Measurement of Si Concentration>

[0434] The Si concentration of the Si-doped GaN layer in the obtained c-plane GaN substrate is measured by SIMS.

[0435] As a result, the Si concentration at the center of the surface of the Si-doped GaN layer is 7.5×10 18 atoms / cm 3 .

[0436] In addition, the in-plane distribution of the Si concentration on the surface of the Si-doped GaN layer of the c-plane GaN substrate is measured. Specifically, the Si concentration is measured at three positions on the surface of the Si-doped GaN layer: the center, a position 12.5 mm from the center, and a position 25 mm from the center, i.e., the end. As a result, the maximum value α of the Si concentration is observed at the center, and its value is 7.5×10 18 atoms / cm 3 . In addition, the minimum value β of the Si concentration is observed at the end, and its value is 7.4×10 18 atoms / cm 3 . As a result, the value represented by [{(α - β) / α}×100](%) is 1.3%, indicating that the Si concentration is uniform over the entire surface of the Si-doped GaN layer, suggesting that low resistivity corresponding to the Si concentration can be uniformly achieved over the entire surface of the GaN substrate.

[0437] [Reference Example 2-1]

[0438] The GaN substrate obtained in Example 2-1 is a substrate in which the used GaN crystal layer is an independent GaN seed, i.e., an undoped GaN seed, and a Si-doped GaN layer is formed thereon. Therefore, it is difficult to accurately measure the carrier concentration by Hall measurement.

[0439] Therefore, a semi-insulating GaN seed of a Mn-doped GaN substrate with a Mn concentration of 1×10 18 atoms / cm 3 is used instead of the independent GaN seed in Example 2-1, and a Si-doped GaN layer is grown thereon. The growth time of the Si-doped GaN layer is changed so that its thickness becomes 50 μm, and it is grown under the same growth conditions as in Example 2-1 except for this.

[0440] Here, the specific resistance of the Mn-doped GaN substrate is 1×10 20 Ωcm or more. Therefore, no current flows into the semi-insulating GaN seed part during Hall measurement, and accurate Hall measurement can be performed.

[0441] The entire surface of the as-grown GaN crystal taken out from the reactor via the cooling step is mirror-like and flat.

[0442] <Measurement of Si Concentration>

[0443] The Si concentration of the Si-doped GaN layer in the c-plane GaN substrate obtained above is measured using SIMS.

[0444] As a result, the Si concentration at the center of the surface of the Si-doped GaN layer is 7×10 18 atoms / cm 3 .

[0445] <Measurement of Carrier Concentration, Specific Resistance, and Carrier Type>

[0446] On the surface of the c-plane GaN substrate obtained above, Ti 30 nm and Au 100 nm are continuously vacuum-evaporated for Hall measurement. For Hall measurement, the 4-terminal Van der Pauw method is used to connect the terminals to the Si-doped GaN layer of the substrate, and the measurement is performed at 300 K.

[0447] As a result, the carrier concentration of the Si-doped GaN layer is 7×10 18 atoms / cm 3 , the specific resistance is 5×10 －3 Ωcm, and the carrier type is n-type.

[0448] Based on this result, when the Si concentration of the Si-doped GaN layer is set to a (atoms / cm 3 ), and the carrier concentration is set to b (atoms / cm 3 ), the value represented by {(b / a)×100} (%), i.e., the activation rate, is 100%.

[0449] [Comparative Example 2-1]

[0450] In Example 2-1, the deviation direction and deviation angle of the crystal orientation of the independent GaN seed are the m-axis direction and 0.35°, and the distances between the nozzle openings of the GaCl gas, ammonia gas, and dopant gas and the surface of the independent GaN seed are 100 mm. Otherwise, the Si-doped GaN layer is grown by the same method to obtain an as-grown GaN crystal.

[0451] In the same manner as in Example 2-1, a GaN substrate was obtained as a circular epitaxial substrate with a diameter of 50.8 mm. Moreover, the in-plane distribution of the Si concentration on the surface of the Si-doped GaN layer of the c-plane GaN substrate was measured. Specifically, the Si concentration was measured at three positions on the surface of the Si-doped GaN layer: the central part, a position 12.5 mm from the center, and a position 25 mm from the center, i.e., the end part. As a result, the maximum value α of the Si concentration was observed at the central part, and its value was 3.9×10 18 atoms / cm 3 Moreover, the minimum value β of the Si concentration was observed at the end part, and its value was 1.6×10 18 atoms / cm 3 . As a result, the value represented by [{(α - β) / α}×100](%) was 58%, indicating that, compared with Example 2-1, the Si concentration was very non-uniform over the entire surface of the Si-doped GaN layer, suggesting that it was impossible to uniformly achieve low resistance corresponding to the Si concentration over the entire surface of the GaN substrate.

[0452] The present invention has been described in detail with reference to specific embodiments, but it is obvious that those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. This application is based on Japanese Patent Application (Japanese Patent Application No. 2022-204832) filed on December 21, 2022, and Japanese Patent Application (Japanese Patent Application No. 2022-204833) filed on December 21, 2022, and their contents are incorporated herein by reference.

[0453] Symbol Explanation

[0454] 1 Seed wafer

[0455] 2 First GaN thick film

[0456] 3 First c-plane GaN wafer

[0457] 4 Second GaN thick film

[0458] 5 Second c-plane GaN wafer

[0459] 6a Si-doped GaN layer

[0460] 6b Intermediate region

[0461] 20 HVPE apparatus

[0462] 21 Reactor

[0463] 22 Gallium storage tank

[0464] 23 Base

[0465] 24 First heater

[0466] 25 Second Heater

[0467] 100 GaN Substrate

[0468] 101(0001) Surface

[0469] 102(000-1) Surface

[0470] 110 Si-doped GaN Layer

[0471] 120 GaN Crystal Layer

Claims

1. A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as the Ga-polar surface, and having an Si-doped GaN layer at least on the surface of the main surface 1, The Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more. In the surface of the Si-doped GaN layer, the total bottom area of the concave defects is 15% or less of the total area of the surface of the Si-doped GaN layer.

2. A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as the Ga-polar surface, and having an Si-doped GaN layer at least on the surface of the main surface 1, The Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more. In the Si-doped GaN layer, when the Si concentration is set to a and the carrier concentration is set to b, the value represented by {(b / a)×100}(%) is 90% or more, and the units of a and b are atoms / cm 3 .

3. A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as the Ga-polar surface, and having an Si-doped GaN layer at least on the surface of the main surface 1, The Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more. Regarding the Si concentration on the surface of the Si-doped GaN layer, when the maximum value is set to α and the minimum value is set to β, the value represented by [{(α - β) / α} × 100](%) is 10% or less, and the units of α and β are atoms / cm 3 .

4. The GaN substrate according to any one of claims 1 to 3, wherein The thickness of the Si-doped GaN layer is 50 μm or more.

5. The GaN substrate according to any one of claims 1 to 3, wherein, In the surface of the Si-doped GaN layer, the total bottom area of the recesses with a depth of 5 μm or more is 15% or less of the total area of the surface of the Si-doped GaN layer.

6. The GaN substrate according to any one of claims 1 to 3, wherein, There is at least one 5 mm × 5 mm square on the surface of the Si-doped GaN layer where there are no concave defects.

7. The GaN substrate according to any one of claims 1 to 3, wherein There is at least one 5 mm × 5 mm square on the surface of the Si-doped GaN layer where there are no recesses with a depth of 5 μm or more.

8. The GaN substrate according to any one of claims 1 to 3, wherein, The specific resistance of the Si-doped GaN layer at 300K is 1×10 －2 Ω·cm or less.

9. The GaN substrate according to any one of claims 1 to 3, wherein, The specific resistance of the Si-doped GaN layer at 300K is 8×10 －3 Ω·cm or less.

10. The GaN substrate according to any one of claims 1 to 3, wherein, The specific resistance of the Si-doped GaN layer at 300K is 4×10 －3 Ω·cm or less.

11. The GaN substrate according to any one of claims 1 to 3, wherein, The Si concentration of the Si-doped GaN layer is 5×10 18 atoms / cm 3 or more.

12. The GaN substrate according to any one of claims 1 to 3, wherein, The Si concentration of the Si-doped GaN layer is 9×10 18 atoms / cm 3 or more.

13. The GaN substrate according to any one of claims 1 to 3, wherein, The GaN substrate is a wafer, and the diameter of the wafer is 50 mm or more.

14. A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as the Ga-polar surface, and having an Si-doped GaN layer at least on the surface of the main surface 1, The thickness of the Si-doped GaN layer is 50 μm or more, In the surface of the Si-doped GaN layer, the total bottom area of the recesses with a depth of 5 μm or more is 15% or less of the total area of the surface of the Si-doped GaN layer.

15. A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as the Ga-polar surface, and having an Si-doped GaN layer at least on the surface of the main surface 1, The thickness of the Si-doped GaN layer is 50 μm or more, In the Si-doped GaN layer, when the Si concentration is set to a and the carrier concentration is set to b, the value represented by {(b / a)×100}(%) is 90% or more, and the units of a and b are atoms / cm 3 .

16. A GaN substrate having a main surface 1 inclined 0 to 10° from the (0001) crystal plane as the Ga-polar surface, and having an Si-doped GaN layer at least on the surface of the main surface 1, The Si concentration of the Si-doped GaN layer is 1×10 18 atoms / cm 3 or more. The thickness of the Si-doped GaN layer is 50 μm or more, Regarding the Si concentration on the surface of the Si-doped GaN layer, when the maximum value is set to α and the minimum value is set to β, the value represented by [{(α - β) / α} × 100](%) is 10% or less, and the units of α and β are atoms / cm 3 .

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