Determination of values indicative of plurality of passive components connected to device pins

Abstract

An integrated circuit (IC, 102) includes a pin (105), a first passive component determination circuit (310), and a first switch (S1) having a first switch control input. The first switch (S1) is coupled between the first passive component determination circuit (310) and the pin (105). The IC (102) further includes a second passive component determination circuit (350) and a second switch (S2) having a second switch control input. The second switch (S2) is coupled between the second passive component determination circuit (350) and the pin (105). A logic circuit (380) is coupled to the first switch control input and the second switch control input. The logic circuit (380) is configured to close the first switch (S1) and open the second switch (S2), and then open the first switch (S1) and close the second switch (S2).

Description

Background Art

[0001] Some integrated circuits (ICs) include pins to which external passive components (e.g., resistors, capacitors, etc.) are connected. The IC can be configured for a particular setting based on parameters associated with the passive components. For example, the resistance of a resistor can be mapped to a desired configuration setting of the IC. In one instance, the configuration setting can be used for the output current limit of the IC, the switching frequency of the IC, etc. Summary of the Invention

[0002] In one instance, an integrated circuit (IC) includes a pin, a first passive component determination circuit, and a first switch having a first switch control input. The first switch is coupled between the first passive component determination circuit and the pin. The IC further includes a second passive component determination circuit and a second switch having a second switch control input. The second switch is coupled between the second passive component determination circuit and the pin. A logic circuit is coupled to the first switch control input and the second switch control input. The logic circuit is configured to close the first switch and open the second switch, and then open the first switch and close the second switch. Brief Description of the Drawings

[0003] Figure 1 Schematic diagram of an example switching voltage regulator for an integrated circuit (IC) that in one instance includes mode pins to which multiple passive components can be connected.

[0004] Figure 2 Flowchart depicting a method for sequentially determining the values of multiple passive components in one instance.

[0005] Figure 3 Schematic diagram of a circuit within an IC for sequentially determining the values of multiple passive components connected to the mode pins of the IC in one instance.

[0006] Figure 4 Timing diagram illustrating the behavior of the circuit of an IC for determining the values of multiple passive components connected to the mode pins. Detailed Description

[0007] The same reference numerals or other reference indicators are used in the drawings to denote the same or similar (functional and / or structural) features.

[0008] For an IC having pins to which a single passive component is connected for configuration purposes, the number of different configuration settings depends in part on the resolution of the circuitry of the IC to determine the parameter of the passive component (e.g., resistance in the case of a resistor or capacitance in the case of a capacitor). Such a passive component measurement circuitry may include an analog-to-digital converter (ADC) to convert an analog signal generated using the passive component into a digital code. The digital code indicates the parameter of the passive component. The digital code includes one or more bits. For example, a two-bit ADC can resolve four different levels of the passive component parameter. In this example (two-bit ADC), the passive component measurement circuitry permits four different values (or ranges of values) of the passive component to be connected to the pin of the IC, thereby specifying four different configuration settings of the IC. If more than four different settings are needed to configure the IC, a higher resolution ADC can be implemented, but a higher resolution ADC is more complex, takes up more space on the IC, and consumes more power.

[0009] The examples described herein relate to an IC having configuration pins to which multiple passive components can be connected rather than just a single passive component. The IC includes circuitry to sequentially determine values indicative of the parameters of each of the multiple passive components. For example, in the examples described herein, the passive components include a resistor and a capacitor coupled in parallel between the configuration pin of the IC and ground. The circuitry first determines a value indicative of the resistance of the resistor and then determines a value indicative of the capacitance of the capacitor. By permitting two passive components, each having its permitted multiple levels of parameters or ranges of parameters, the IC can implement a larger number of configuration settings compared to what would otherwise be the case of a pin measurement circuitry with a low resolution ADC.

[0010] Figure 1 Schematic diagram illustrating an example of an IC 102 that can be part of a switching voltage regulator 100. The switching voltage regulator 100 converts an input direct current (DC) voltage VIN into a regulated output voltage VOUT. In this example, the IC 102 includes an internal power transistor (not shown) connected in series between VIN and ground (GND). A controller (not shown) inside the IC 102, such as a pulse width modulator (PWM), controls the on and off states of the power transistor. A switching node (SW) between the power transistors is exposed as a pin 103 of the IC. Several external passive components are connected to respective pins of the IC 102. In one example, the IC 102 and the passive components are mounted on the same circuit board. The passive components can be connected to the IC via conductive traces on the circuit board. In Figure 1 the example, one terminal of an inductor L is coupled to the SW node pin 103 and the other terminal of the inductor provides VOUT. A resistor R FBT and R FBBConnected in series between VOUT and ground to implement a voltage divider to provide a scaled output voltage to the feedback (FB) pin of IC 102. IC 102 can be used in a variety of voltage converter applications. In another example, IC 102 (or other types of such ICs) can be a controller for a boost converter. In another example, IC 102 can be used in a buck-boost converter.

[0011] The configuration pins described above are shown as mode pin (MODE) 105 in the Figure 1 example. Two passive components are shown coupled between mode pin 105 and ground, namely resistor R SET and capacitor C SET coupled in parallel. Referring to Figure 1 and Figure 2 ( Figure 2 being a flowchart), the configuration circuit 120 described internally in IC 102 sequentially determines (step 202) the value of the resistance indicating resistor R SET , and then determines (step 204) the value of the capacitance indicating capacitor C SET . At step 206, the values indicating the passive components R SET and C SET are then used by the configuration circuit 120 to configure at least one parameter associated with IC 102 (e.g., output current limit, switching frequency, etc.).

[0012] Figure 1 The example IC 102 in

[0013] Figure 3 is a controller for a voltage regulator. However, the techniques and circuitry described herein are applicable to any IC for which it is advantageous to specify at least one configuration setting from multiple configuration settings by external passive components connected to a single pin.

[0013] Figure 3 is a schematic diagram of an example of configuration circuit 120. In addition to resistor R SET and capacitor C SET , the components shown in the Figure 3 example are parts of the configuration circuit 120 implemented on an IC with mode pin 105 to which resistor R SET and capacitor C SET are connected.

[0014] In Figure 3In an example, the configuration circuit 120 includes a resistance determination circuit 310, a capacitance determination circuit 350, switches S1, S2, and S3, and a logic circuit 380. Switch S1 is coupled between the resistance determination circuit 310 and pin 105. Switch S2 is coupled between the capacitance determination circuit 350 and pin 105. When switch S1 is closed and switch S2 is open, the resistance determination circuit 310 determines the value of the resistance indicating resistor R SET When switch S2 is closed and switch S1 is open, the capacitance determination circuit 350 determines the value of the capacitance indicating capacitor C SET . The logic circuit 380 provides switch control signals S1_CTL and S2_CTL to control the open and closed (off and on) states of switches S1 and S2, respectively. In one example, to determine the values of the resistance and capacitance indicating resistor R SET and capacitor C SET correspondingly, the logic circuit 380 first closes switch S1 and opens switch S2, thereby causing the resistance determination circuit 310 to generate a digital output value REGR of the resistance indicating resistor R SET . Then, the circuit 380 opens switch S1 and closes switch S2, thereby causing the capacitance determination circuit 350 to generate a digital value of the capacitance indicating capacitor C SET . After determining the value of the resistance indicating resistor R SET , there will be charge across capacitor C SET . After determining the resistance of resistor R SET and before determining the capacitance of capacitor C SET , the logic circuit 380 determines the switch control signal S3_CTL to close switch S3 and discharge capacitor CSET to ground through switch S3.

[0015] The resistance determination circuit 310 includes an operational amplifier (OP AMP) 312, a current mirror 314, a digital-to-analog converter (DAC) 316, a logic gate 318, a counter 320, and a transistor M1. In this example, transistor M1 is an n-channel field-effect transistor (NFET). In other examples, transistor M1 can be implemented as a different type of transistor. In this example, logic gate 318 is an inverter.

[0016] The OP AMP 312 includes a non-inverting (positive, +) input, an inverting (negative, -) input, and an output. A direct current (DC) voltage V1 is provided to the non-inverting input. The source of transistor M1 is coupled to the negative input of OP AMP 312. The output of OP AMP 312 is coupled to the gate of transistor M1. OP AMP 312 and transistor M1 act as a voltage-current converter that converts voltage V1 into current IRset. The voltage on the non-inverting input of OP AMP 312 is also provided on the inverting input and thus on the source of transistor M1. Since the source of transistor M1 is coupled to resistor R SET , the voltage across resistor RESET is V1. The current through resistor RESET is IRset. A larger magnitude of voltage V1 results in a larger magnitude of current IRset, and vice versa. The magnitude of voltage V1 can be any voltage within a fairly wide range.

[0017] Current mirror 314 mirrors current IRset as current I1. The current mirror ratio implemented by current mirror 314 can be 1:1 or another suitable ratio. Current mirror 314 is coupled to DAC 316 and to the input 317 of a logic gate 318 (e.g., an inverter) at node A. The current entering DAC 316 is current I2. The current entering or leaving logic gate 318 is current I3. The sum of currents I2 and I3 is equal to current I1 from current mirror 316. The output of logic gate 318 is coupled to the latch input 319 of counter 320. In response to the latch input being in one logic state (e.g., logic "1"), counter 320 counts the pulses of a clock signal provided on its clock input 311 and generates a continuously increasing digital code (RegR) on its output 321, and holds its output code RegR at the value that existed when the latch input transitioned to logic 1. In response to the latch being in another logic state (e.g., logic "0"), counter 320 stops incrementing its output digital code. The counter can be reset by a signal provided on its reset (RST) input. For example, a logic "1" on its reset input causes the counter to set its output digital count back to 0.

[0018] The output 321 of counter 320 is coupled to the digital input 323 of DAC 316. DAC 316 responds to each continuously increasing digital code RegR by increasing the magnitude of current I2 at its analog output 327. When the magnitude of current I1 is greater than the magnitude of current I2, current I3 flows into logic gate 318, and the voltage at node A is logic high. Figure 4 To illustrate the timing diagram where the voltage at node A is logic high (402) when the output current of the DAC increases but is still less than current I1 (and current I1 is a function of, for example, equal to current IRset).

[0019] In response to the digital code RegR being large enough for the DAC 316 to force the current I2 to be equal to and exceed the current I1, the current I3 becomes negative (discharging the input 317 of the logic gate 318), and the voltage at node A becomes logic low. This transition is shown at 404 in Figure 4 . In response to the voltage at node A becoming logic low, the latch input 319 of the counter 320 becomes logic high, and the counter freezes its output digital code RegR. When the counter 320 stops counting (in response to the output current I2 of the DAC reaching the current I1), the value of RegR at this time indicates the resistance of the resistor RSET. A larger resistance of the resistor R SET results in a larger current IRset. The larger value of the current IRset causes the current mirror 314 to generate a larger current I1. The counter 320 will take more time to count from the digital output code 0 to the value where the current I2 is equal to the current I1, and thus the digital code RegR will be larger. Similarly, a smaller resistance of the resistor R SET results in a smaller current IRset. The smaller value of the current IRset causes the current mirror 314 to generate a smaller current I1. The counter 320 will take less time to count from the digital output code 0 to the value where the current I2 is equal to the current I1, and thus the digital code RegR will be smaller.

[0020] During the time when the switch S1 is closed (turned on) and the switches S2 and S3 are open (turned off), the voltage V1 is also forced to be applied across the capacitor C SET terminals. In the presence of a DC voltage across the plates of the capacitor C SET , little or no current flows into the capacitor C SET . Therefore, the digital code RegR represents the resistance value of the resistor R SET . Before determining the value of the capacitance indicating the capacitor C SET , the logic 380 determines the switch control signal S3_CTL to close the switch S3 for a long enough time to discharge the capacitor C SET .

[0021] During the next operation phase when the capacitance determination circuit 350 determines the value of the capacitance indicating the capacitor C SET , the logic circuit 380 determines the control signals S1_CTL, S2_CTL, and S3_CTL to open (turn off) the switches S1 and S3 and close (turn on) the switch S2. Figure 4 The timing diagram of

[0022] shows that the switch S1 is open and the switch S2 is on at 405. The capacitance determination circuit 350 includes a current source circuit 352, a current mirror 354, an OP AMP 356, a comparator 358, a counter 360, a transistor M2, and a resistor RDET The switch S2 is coupled between the current source circuit 350 (at node C) and the parallel combination of the resistor R SET and the capacitor C SET . The current source circuit 350 generates a current I4. The switch S2 is also coupled to the non-inverting input of the OP AMP 356. The inverting input of the OP AMP 356 is coupled to the source of the transistor M2 and to the resistor R DET . The resistor R DET is coupled between the source of the transistor M2 and ground. In this example, the transistor M2 is an NFET. The drain of the transistor M2 is coupled to one terminal 351 of the current mirror 354, and the other terminal 353 of the current mirror 354 is coupled to the capacitor C SET / resistor R SET parallel combination.

[0023] The non-inverting input of the comparator 358 is coupled at node C to the switch S2, the current source circuit 352, the current mirror 354, and the non-inverting input of the OP AMP 356. A DC threshold voltage V2 is provided to the inverting input of the comparator 358. The output of the comparator 358 is coupled to the latch input 361 of the counter 360. The node coupling the output of the comparator and the latch input of the counter is labeled as node B. The counter 360 counts the pulses of the clock signal on its clock input 363 in response to the voltage on the latch input 361 being in one logic state (e.g., logic 0). In this example, the counter 360 is an up-counter and thus increments its digital output code REGC on its output 365 with each successive pulse of the clock input signal. In response to the logic level on the logic input 361 being in a different logic state (e.g., logic), the counter 360 stops counting and freezes its output digital code REGC.

[0024] The current source circuit 352 forces a constant level current I4 into the parallel combination of the capacitor C SET and the resistor R SET . The voltage across the capacitor C SET is the voltage on the mode pin 105 and is referred to as Vmode. In response to the capacitor C SET being charged by the fixed current I4, the voltage across the capacitor C SET (Vmode) increases approximately linearly, as shown at 406 in Figure 4 . The slope of Vmode is inversely proportional to the capacitance of the capacitor C SET , i.e., a larger value of the capacitance of the capacitor C SET results in a smaller slope of Vmode, and a smaller value of the capacitance of the capacitor C SET results in a larger slope of Vmode.

[0025] Comparator 358 compares voltage Vmode with V2 and generates an output signal indicating whether Vmode is greater than or less than V2. The output of comparator 358 is coupled to latch 361 of counter 360. Counter 360 increments its digital code REGC from 0, for example, when its reset (RST) input is forced high by logic 380, until Vmode equals V2. When Vmode reaches V2 ( Figure 4 point 408 in SET ), the logic level of latch input 361 of comparator 358 changes state, and counter 360 stops incrementing REGC. The value of REGC at this time is a function of the capacitance of capacitor C

[0026] The function performed by the combination of OP AMP 356, transistor M2, resistor R DET and current mirror 354 is to generate a current approximately equal to the current flowing through resistor R SET . Thus, current IRdet from current mirror 354 cancels the current through resistor R SET , such that counter 360 generates a digital code REGC that more accurately indicates the capacitance of capacitor C SET .

[0027] In this example, resistor R DET is a configurable resistor. Configurable resistor R DET has a resistor control input 375 coupled to the counter output 321. The digital code REGR indicating the resistance of resistor R SET is provided to resistor control input 375. Resistor R DET is configured based on digital code REGR DET of its resistance. In one example, configurable resistor R SET includes multiple resistors, each resistor coupled to a switch (e.g., in series or in parallel with the switch), and digital code REGR controls the on and off states of the switch to select only those resistors to be electrically coupled between the source of transistor M2 and ground, thereby estimating the resistance of resistor R

[0028] Voltage Vmode is applied across resistor R SET . The same voltage Vmode is also coupled to the non-inverting input of OP AMP 356. Through OP AMP 356, the same voltage Vmode is also applied across resistor R DET . Thus, resistor R SET and configurable resistor R DET both have the same voltage. When the resistance of configurable resistor R DET is set to be approximately equal to the resistance of resistor R SETIn the case of the resistance, the two resistors have approximately the same current. The current mirror 354 mirrors the current passing through the transistor M2 and the resistor R DET as the current IRdet, which flows through the resistor when the switch S2 is closed RSET .

[0029] The logic 380 receives the digital codes REGR and REGC. The digital code REGR indicates the resistance of the resistor R SET . The digital code REGC indicates the capacitance of the capacitor C SET . One or more parameters regarding the operation of the IC can be configured by the logic 380 or other logic circuitry within the IC 102 based on both the REGB and REGC digital codes. Non-limiting examples of such configuration parameters are provided above. The technical benefit of the resistance determination circuit 310, the capacitance determination circuit 350, the switches S1 and S2, and the logic 380 is that on an IC to which multiple passive components can be connected, only a single pin 105 needs to be available. Multiple pins (each for a separate passive component) are not required. However, in some instances, multiple pins, such as pin 105, can be included so that three, four, or more passive components can be coupled to the IC for configuration parameter purposes.

[0030] In this description, the term "coupled" can encompass a connection, communication, or signal path that enables a functional relationship consistent with this description. For example, if device A generates a signal to a control device B to perform an action, then: (a) in a first instance, device A is coupled to device B by a direct connection; or (b) in a second instance, if an intervening component C does not change the functional relationship between device A and device B such that device B is controlled by device A via the control signal generated by device A, then device A is coupled to device B through the intervening component C.

[0031] Furthermore, in this description, the recitation of "based on" means "at least partially based on". Thus, if X is based on Y, then X can depend on Y and any number of other factors.

[0032] A device "configured to" perform a task or function can be configured (e.g., programmed and / or hardwired) by the manufacturer to perform the function, and / or can be configured (or reconfigured) by the user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be by programming the firmware and / or software of the device, by the construction and / or layout of the hardware components and interconnections of the device, or a combination thereof.

[0033] As used herein, the term "pin" refers to any suitable type of electrical contact to one or more components fabricated on an IC. Different types of packages may be used for the IC, such as flat packages, pin grid arrays, surface mount packages, chip carriers, small packages, etc. Examples of flat packages include quad flat no-lead (QFN) packages and dual flat no-lead (DFN) packages. Some packages may have leads while other packages may not have leads. Regardless of the package type, the "pins" described herein are electrical contacts to the circuitry fabricated on the die.

[0034] A circuit or device described herein as including specific components may in fact be adapted to couple to those components to form the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may in fact include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to couple to at least some of the passive elements and / or sources to form the described structure during or after fabrication, e.g., by an end user and / or a third party.

[0035] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may alternatively be used with little or no change to the rest of the circuitry. For example, field effect transistors ("FETs") (e.g., n-channel FETs (NFETs) or p-channel FETs (PFETs)), bipolar junction transistors (BJTs - e.g., NPN transistors or PNP transistors), insulated gate bipolar transistors (IGBTs), and / or junction field effect transistors (JFETs) may be used instead of or in combination with the devices described herein. The transistors may be depletion mode devices, drain extended devices, enhancement mode devices, natural transistors, or other types of device structure transistors. Additionally, the devices may be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0036] Reference may be made in the claims to the control input of a transistor and its current terminals. In the case of an FET, the control input is the gate, and the current terminals are the drain and source. In the case of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0037] An FET being "on" as referred to herein means that there is a conductive channel in the FET and a drain current can flow through the FET. An FET being "off" as referred to herein means that there is no conductive channel, and thus no drain current flows through the FET. However, an "off" FET may have current flowing through the body diode of the transistor.

[0038] The circuits described herein can be reconfigured to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise indicated, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component can alternatively be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0039] While some of the elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features can be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit can be included in the integrated circuit, and / or some of the features described as internal to the integrated circuit can be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" refers to one or more circuits that: (i) are incorporated in / on a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0040] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise indicated, "about," "substantially," or "essentially" in front of a parameter means within + / - 10% of the stated parameter, or if the parameter is zero, then within a reasonable value that is approximately zero.

[0041] Within the scope of the claims, modifications to the described examples are possible, and other examples are possible.

Claims

1. An integrated circuit (IC) comprising: Pins; A current mirror; A first switch coupled between the current mirror and the pins; A counter having a counter control input and a counter output; A digital-to-analog converter (DAC) having a digital input and an analog output, the analog output being coupled to the current mirror and the counter control input, and the digital input being coupled to the counter output; A current source circuit; And A second switch coupled between the current source circuit and the pins.

2. The IC according to claim 1, further comprising a logic circuit coupled to the first switch and the second switch, the logic circuit being configured to close the first switch and open the second switch, and then open the first switch and close the second switch.

3. The IC according to claim 1, further comprising: A transistor having a transistor control input, a first current terminal, and a second current terminal, the first current terminal being coupled to the current mirror, and the second current terminal being coupled to the first switch; And An operational amplifier (OP AMP) having a first OP AMP input and an OP AMP output, the first OP AMP input being coupled to the second current terminal, and the OP AMP output being coupled to the transistor control input.

4. The IC according to claim 1, wherein the counter is configured to increment a digital value at its counter output until the signal at the counter control input changes logic state.

5. The IC according to claim 1, wherein the current mirror is a first current mirror, and the IC further comprises: A second current mirror coupled to the current source circuit and the second switch; And A configurable resistor having a resistor control input, the counter output being coupled to the resistor control input.

6. The IC according to claim 5, wherein the counter is a first counter, the resistor control input is a first counter control input, and the IC further comprises: A second counter having a second counter control input; And A comparator having a first comparator input, a second comparator input, and a comparator output, the current source circuit and the second current mirror being coupled to the first comparator input, and the comparator output being coupled to the second counter control input.

7. The IC according to claim 6, wherein the configurable resistor is coupled between the second current mirror and a ground terminal.

8. The IC according to claim 5, wherein the second current mirror has a first current mirror terminal and a second current mirror terminal, the first current mirror terminal being coupled to the current source circuit and the second switch, and the IC further comprises: A transistor having a first current terminal and a second current terminal, the first current terminal being coupled to the second current mirror terminal, and the second current terminal being coupled to the configurable resistor.

9. The IC according to claim 8, wherein the transistor has a transistor control input, and the IC further includes an operational amplifier (OP AMP) having a first OP AMP input, a second OP AMP input, and an OP AMP output, the first OP AMP input being coupled to the first current mirror terminal and the current source circuit, the second OP AMP input being coupled to the second current terminal, and the OP AMP output being coupled to the transistor control input.

10. An integrated circuit (IC) comprising: Pins; A current source circuit; A first switch coupled between the current source circuit and the pins; A first current mirror having a current mirror terminal, the first switch being coupled between the current mirror terminal and the pins; A counter having a control input; A comparator having a first comparator input, a second comparator input, and a comparator output, the first comparator input being coupled to the current source circuit and the current mirror terminal, and the comparator output being coupled to the control input; A second current mirror; And A second switch coupled between the second current mirror and the pins.

11. The IC according to claim 10, further comprising a logic circuit coupled to the first switch and the second switch, the logic circuit being configured to close the first switch and open the second switch, and then open the first switch and close the second switch.

12. The IC according to claim 10, wherein the current mirror terminal is a first current mirror terminal, the first current mirror has a second current mirror terminal, and the IC further includes a resistor coupled between the second current mirror terminal and a ground terminal.

13. The IC according to claim 12, wherein the resistor is a configurable resistor.

14. The IC according to claim 12, wherein the second current mirror has a third current mirror terminal and a fourth current mirror terminal, the second switch being coupled between the third current mirror terminal and the pins, and the IC further includes: A digital-to-analog converter (DAC) having a digital input and an analog output, the analog output being coupled to the fourth current mirror terminal.

15. The IC according to claim 14, wherein the counter is a first counter and the control input is a first counter control input, and the IC further includes: A second counter having a second counter control input and a counter output, the counter output being coupled to the digital input.

16. The IC according to claim 10, wherein the current mirror terminal is a first current mirror terminal, the first current mirror has a second current mirror terminal, and the IC further includes: A resistor; A transistor having a transistor control input, a first current terminal, and a second current terminal, the first current terminal being coupled to the second current mirror terminal, and the second current terminal being coupled to the resistor; And An operational amplifier (OP AMP) having a first OP AMP input, a second OP AMP input, and an OP AMP output, the first OP AMP input coupled to the current source circuit, the second OP AMP input coupled to the second current terminal, and the OP AMP output coupled to the transistor control input.

17. An integrated circuit (IC) comprising: A pin; A first passive component determination circuit; A first switch having a first switch control input, the first switch coupled between the first passive component determination circuit and the pin; A second passive component determination circuit; A second switch having a second switch control input, the second switch coupled between the second passive component determination circuit and the pin; And Logic circuitry coupled to the first switch control input and the second switch control input, the logic circuitry configured to close the first switch and open the second switch, and then open the first switch and close the second switch.

18. The IC of claim 17, wherein the first passive component determination circuit is configured to generate a first digital value indicative of a resistance.

19. The IC of claim 18, wherein the second passive component determination circuit is configured to generate a second digital value indicative of a capacitance.

20. The IC of claim 19, wherein the first passive component determination circuit includes a first counter configured to generate the first digital value, and the second passive component determination circuit includes a second counter configured to generate the second digital value.

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