Low-stress silicon-based pressure sensor chip and processing method

Abstract

The present application relates to the technical field of pressure sensor chips, and in particular to a low-stress silicon-based pressure sensor chip and a processing method thereof, wherein the chip comprises: an n-type silicon substrate, a p-type pressure-sensitive resistor, a passivation layer, a metal electrode layer, and a bonding member; the p-type pressure-sensitive resistor is arranged in a resistor placement groove on the top of the n-type silicon substrate; the passivation layer comprises a silicon dioxide layer and a silicon nitride layer, the silicon dioxide layer is arranged on the n-type silicon substrate and the p-type pressure-sensitive resistor, and the silicon nitride layer is arranged on the silicon dioxide layer; an electrical contact area and a stress release area are provided on the silicon dioxide layer and the silicon nitride layer; the electrical contact area is provided at the top outer end of the p-type pressure-sensitive resistor, and the metal electrode layer is provided on the electrical contact area; a silicon cup is provided at the bottom of the n-type silicon substrate, so that the n-type silicon substrate in the area above the silicon cup constitutes a pressure-sensitive diaphragm, and the stress release area is provided on the upper surface of the pressure-sensitive diaphragm, so as to solve the problem that the introduction of the passivation layer affects the output and reliability of the pressure sensor chip

Description

Technical Field

[0001] The present application relates to the technical field of pressure sensor chips, and in particular to a low-stress silicon-based pressure sensor chip and a processing method thereof. Background Art

[0002] Pressure sensor chips based on microelectromechanical systems (MEMS) technology have the characteristics of high sensitivity, low cost, reliable performance, and mass production. They are widely used in aerospace, process industry, smart medical and other fields.

[0003] MEMS pressure sensor chips in related technologies are primarily made of silicon, using PN junction isolation technology to electrically isolate the pressure-sensitive resistor from the substrate. To enhance the chip's resistance to environmental interference, such as moisture, mechanical scratches, and particle contamination, a passivation layer, typically consisting of silicon dioxide and silicon nitride, is applied to the chip surface to ensure stable electrical performance.

[0004] However, the introduction of a passivation layer also has negative consequences. Due to the different thermal expansion coefficients of silicon and the passivation layer, varying film stress is generated at different temperatures. This film stress is transmitted to the pressure-sensitive resistor, causing the resistance value to change, seriously affecting the output and reliability of the pressure sensor chip. The film stress problem is more prominent for low-range pressure-sensitive chips. Summary of the Invention

[0005] The present application provides a low-stress silicon-based pressure sensor chip and a processing method to solve the problem that the introduction of a passivation layer affects the output and reliability of the pressure sensor chip.

[0006] In a first aspect, the present application provides a low-stress silicon-based pressure sensor chip, comprising: an n-type silicon substrate, a p-type pressure-sensitive resistor, a passivation layer, a metal electrode layer, and a bonding member;

[0007] The p-type pressure-sensitive resistor is arranged in a resistor placement groove on the top of the n-type silicon substrate, the p-type pressure-sensitive resistor and the n-type silicon substrate are electrically isolated by a PN junction, and the upper surface of the p-type pressure-sensitive resistor and the n-type silicon substrate are located in the same plane;

[0008] The passivation layer includes a silicon dioxide layer and a silicon nitride layer, the silicon dioxide layer is arranged on the n-type silicon substrate and the p-type pressure-sensitive resistor, and the silicon nitride layer is arranged on the silicon dioxide layer;

[0009] An electrical contact region and a stress release region are provided on the silicon dioxide layer and the silicon nitride layer; the electrical contact region is provided at the top outer end of the p-type pressure sensitive resistor, and the metal electrode layer is provided on the electrical contact region;

[0010] A silicon cup is provided at the bottom of the n-type silicon substrate, so that the n-type silicon substrate above the silicon cup forms a pressure-sensitive membrane, and the stress release area is provided on the upper surface of the pressure-sensitive membrane;

[0011] The bonding element is bonded to the bottom of the n-type silicon substrate.

[0012] The low-stress silicon-based pressure sensor chip disposes a p-type pressure-sensitive resistor within a resistor placement groove of an n-type silicon substrate and utilizes a PN junction to achieve electrical isolation. At the same time, the upper surface of the p-type pressure-sensitive resistor is located on the same plane as the n-type silicon substrate. Combined with the provision of a silicon dioxide layer and a silicon nitride layer in the passivation layer, as well as the provision of electrical contact areas and stress release areas, this can reduce the impact of the passivation layer on chip output, improve the stress distribution of the pressure-sensitive diaphragm, and thus enhance the output stability and reliability of the sensor. Furthermore, by providing a silicon cup and bonding a bonding component at the bottom of the n-type silicon substrate, the mechanical properties of the pressure-sensitive diaphragm are optimized, further enhancing the overall performance of the sensor.

[0013] Optionally, the bonding component is one of bonding glass and bonding silicon wafer.

[0014] By bonding bonding glass or bonding silicon wafer to the bottom of the n-type silicon substrate, the structural stability of the chip can be enhanced, the stress introduced during the packaging process can be reduced, and the matching between the sensor chip and external devices can be improved, thereby improving the overall reliability.

[0015] Optionally, the n-type silicon substrate is a double-polished silicon wafer, and the thickness of the n-type silicon substrate ranges from 300 μm to 800 μm; the doping concentration of the p-type pressure sensitive resistor ranges from 3E18 cm -3 or 2E20cm -3 ; The junction depth of the PN junction ranges from 0.5μm to 3μm; the thickness of the silicon dioxide layer ranges from 50nm to 300nm; the thickness of the silicon nitride layer ranges from 50nm to 300nm; the thickness of the metal electrode layer ranges from 500nm to 2μm; the thickness of the pressure sensitive membrane ranges from 15μm to 300μm.

[0016] By limiting the n-type silicon substrate to a double-polished silicon wafer and controlling its thickness within the range of 300μm-800μm, and at the same time optimizing the doping concentration, PN junction depth, passivation layer thickness, metal electrode layer thickness, and pressure-sensitive diaphragm thickness of the p-type pressure-sensitive resistor, the mechanical strength and process consistency of the chip can be improved, the risk of stress concentration can be reduced, and the electrical isolation effect and signal transmission stability can be improved, thereby optimizing the sensitivity and long-term reliability of the sensor.

[0017] Optionally, the number of the p-type pressure-sensitive resistors is four, each of the p-type pressure-sensitive resistors is provided with two electrical contact areas, the metal electrode layer is electrically connected to the p-type pressure-sensitive resistor through the electrical contact areas, and the four p-type pressure-sensitive resistors are connected to form a Wheatstone bridge through the metal electrode layer wiring.

[0018] Four p-type pressure-sensitive resistors are used, each with two electrical contact areas, and connected to form a Wheatstone bridge structure through metal electrode layer wiring. This can improve the sensitivity of pressure detection and temperature compensation effect, while reducing the measurement error of a single resistor, thereby improving the output signal stability and measurement accuracy of the sensor.

[0019] Optionally, there are multiple stress release areas, and the stress release areas are arranged on the pressure sensitive membrane away from the p-type pressure sensitive resistor area; the interval between two adjacent stress release areas is 5μm-200μm, and the width of each stress release area is 5μm-300μm.

[0020] By setting multiple stress release areas on the pressure-sensitive diaphragm away from the p-type pressure-sensitive resistor area, and controlling the interval between adjacent stress release areas to 5μm-200μm and the width of each stress release area to 5μm-300μm, the stress generated by the passivation layer on the pressure-sensitive diaphragm can be dispersed, reducing the impact of stress concentration on sensor performance while maintaining the mechanical integrity of the diaphragm, thereby improving the output stability and measurement accuracy of the sensor.

[0021] A second aspect of the present application provides a method for processing a low-stress silicon-based pressure sensor chip, which is used to process the low-stress silicon-based pressure sensor chip described in the first aspect. The method comprises:

[0022] Select n-type double-polished silicon wafer as n-type silicon substrate;

[0023] Performing regional doping and annealing on the n-type silicon substrate by ion implantation or diffusion to form a p-type pressure sensitive resistor;

[0024] preparing a silicon dioxide layer and a silicon nitride layer on the n-type silicon substrate and the p-type pressure-sensitive resistor by thermal oxidation, chemical vapor deposition, or magnetron sputtering;

[0025] Etching the silicon nitride layer and the silicon dioxide layer by using one or a combination of inductively coupled plasma etching, reactive ion etching, and wet etching to form an electrical contact area and a stress relief area;

[0026] forming a metal electrode layer by magnetron sputtering or electron beam evaporation;

[0027] Treating the metal electrode layer by annealing to form an ohmic contact;

[0028] Etching the bottom of the n-type silicon substrate by wet etching or deep silicon etching process to form a silicon cup and a pressure sensitive diaphragm;

[0029] The bonding component is bonded to the bottom of the n-type silicon substrate by adopting anodic bonding or silicon-silicon bonding.

[0030] The above-mentioned processing method, based on all the beneficial effects of the low-stress silicon-based pressure sensor chip described in the first aspect, selects an n-type double-polished silicon wafer as a substrate, combines regional doping and annealing to form a p-type pressure sensitive resistor, uses thermal oxidation or chemical vapor deposition to prepare a silicon dioxide layer and a silicon nitride layer, and uses a combination of multiple etching processes to form an electrical contact area and a stress release area. It cooperates with magnetron sputtering or electron beam evaporation to form a metal electrode layer and annealing to achieve ohmic contact. Finally, a silicon cup and a pressure sensitive diaphragm are formed by wet etching or deep silicon etching, and the device packaging is completed by a bonding process. This method can optimize the device stress distribution, improve the stability of the p-type pressure sensitive resistor, improve the electrical contact performance, and at the same time enhance the mechanical reliability of the diaphragm structure, thereby improving the overall performance of the sensor.

[0031] Optionally, the impurities used for the ion implantation are boron atoms, and the diffusion method uses a boron source sheet for doping.

[0032] Using boron atoms as ion implantation impurities and combining them with boron source diffusion doping can help improve the uniformity and controllability of the doping process, optimize the impurity concentration distribution, and thus improve the electrical performance and reliability of semiconductor devices.

[0033] Optionally, the process gases of the inductively coupled plasma etching process and the reactive ion etching process are one or more of carbon tetrafluoride, trifluoromethane, oxygen, argon, and nitrogen, and the corrosive liquid of the wet etching process is a BOE solution, which is a mixed solution of 40% ammonium fluoride solution and 49% hydrofluoric acid solution prepared in a volume ratio of 6:1.

[0034] Using one or more of carbon tetrafluoride, trifluoromethane, oxygen, argon, and nitrogen as process gases for inductively coupled plasma etching and reactive ion etching, and performing wet etching with a BOE solution prepared in a 6:1 volume ratio, can improve the selectivity and controllability of the etching process, optimize pattern transfer accuracy, reduce damage to non-target areas, and improve the processing quality of the device structure.

[0035] Optionally, the silicon etchant in the wet etching method is potassium hydroxide solution or tetramethylammonium hydroxide solution.

[0036] Using potassium hydroxide solution or tetramethylammonium hydroxide solution as the silicon etchant for wet etching can control the corrosion rate and surface morphology of the silicon cup structure, reduce defects generated during the corrosion process, improve the surface flatness and thickness uniformity of the pressure sensitive diaphragm, and thus improve the performance consistency of the sensor.

[0037] Optionally, the process gas of the deep silicon etching process is one or more of octafluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon.

[0038] By using one or more of octafluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon as deep silicon etching process gases, the selectivity and anisotropy of the etching process can be optimized, etching residues can be reduced, and the sidewall morphology of the silicon cup structure can be improved, thereby improving the processing accuracy and mechanical properties of the pressure sensitive diaphragm.

[0039] As can be seen from the above technical solution, the present application provides a low-stress silicon-based pressure sensor chip and a processing method, wherein the chip comprises: an n-type silicon substrate, a p-type pressure sensitive resistor, a passivation layer, a metal electrode layer, and a bonding member; the p-type pressure sensitive resistor is arranged in a resistor placement groove on the top of the n-type silicon substrate, the p-type pressure sensitive resistor and the n-type silicon substrate are electrically isolated by a PN junction, and the upper surface of the p-type pressure sensitive resistor is located in the same plane as the n-type silicon substrate; the passivation layer comprises a silicon dioxide layer and a silicon nitride layer, the silicon dioxide layer is arranged on the n-type silicon substrate and the p-type On the pressure-sensitive resistor, the silicon nitride layer is arranged on the silicon dioxide layer; an electrical contact area and a stress release area are provided on the silicon dioxide layer and the silicon nitride layer; the electrical contact area is provided at the top outer end of the p-type pressure-sensitive resistor, and the metal electrode layer is provided on the electrical contact area; a silicon cup is provided at the bottom of the n-type silicon substrate so that the n-type silicon substrate in the area above the silicon cup constitutes a pressure-sensitive diaphragm, and the stress release area is provided on the upper surface of the pressure-sensitive diaphragm; the bonding part is bonded to the bottom of the n-type silicon substrate to solve the problem that the introduction of the passivation layer affects the output and reliability of the pressure sensor chip. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0041] Figure 1 The planar process board in the low stress silicon-based pressure sensor chip processing method provided in the embodiment of the present application Figure 1 ;

[0042] Figure 2The planar process board in the low stress silicon-based pressure sensor chip processing method provided in the embodiment of the present application Figure 2 ;

[0043] Figure 3 A schematic structural diagram of an n-type silicon substrate in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0044] Figure 4 This is a schematic diagram of the structure of forming a p-type pressure sensitive resistor in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0045] Figure 5 A schematic diagram of the structure of forming a passivation layer in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0046] Figure 6 A schematic diagram of the structure of forming electrical contact areas and stress release areas in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0047] Figure 7 A schematic diagram of the structure for forming ohmic contacts in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0048] Figure 8 A schematic diagram of the structure of a silicon cup and a pressure-sensitive diaphragm formed by a wet etching process in a low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0049] Figure 9 This is a schematic diagram of the structure after a deep silicon etching process is used to form a silicon cup and a pressure-sensitive diaphragm in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0050] Figure 10 This is a schematic diagram of the structure after sealing the non-porous glass in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0051] Figure 11 This is a schematic diagram of the structure after sealing the through-hole glass in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0052] Figure 12 This is a schematic diagram of the structure after sealing the non-porous silicon wafer in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application;

[0053] Figure 13 This is a schematic diagram of the structure after the through-hole silicon wafer is sealed in the low-stress silicon-based pressure sensor chip processing method provided in an embodiment of the present application.

[0054] Illustration:

[0055] Among them, 1-n-type silicon substrate; 2-p-type pressure sensitive resistor; 3-silicon dioxide layer; 4-silicon nitride layer; 5-electrical contact area; 6-stress release area; 7-metal electrode layer; 8-silicon cup; 9-pressure sensitive membrane; 10-non-porous glass; 11-through-hole glass; 12-non-porous silicon wafer; 13-through-hole silicon wafer. DETAILED DESCRIPTION

[0056] The following embodiments are described in detail, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following embodiments are not intended to represent all possible implementations consistent with the present application. They are merely examples of systems and methods consistent with certain aspects of the present application.

[0057] Pressure sensor chips based on MEMS technology have the characteristics of high sensitivity, low cost, reliable performance, and mass production. They are widely used in aerospace, process industry, smart medical and other fields.

[0058] The MEMS pressure sensor chip in the relevant embodiments is primarily made of silicon and uses PN junction isolation technology to electrically isolate the pressure-sensitive resistor from the substrate. To enhance the chip's resistance to environmental interference, such as moisture, mechanical scratches, and particle contamination, a passivation layer, typically consisting of silicon dioxide or silicon nitride, is applied to the chip surface to ensure stable electrical performance.

[0059] However, the introduction of a passivation layer also has negative consequences. Due to the different thermal expansion coefficients of silicon and the passivation layer, varying film stress is generated at different temperatures. This film stress is transmitted to the pressure-sensitive resistor, causing the resistance value to change, seriously affecting the output and reliability of the pressure sensor chip. The film stress problem is more prominent for low-range pressure-sensitive chips.

[0060] To solve the problem that the introduction of the passivation layer affects the output and reliability of the pressure sensor chip, see Figures 1-13 Some embodiments of the present application provide a low-stress silicon-based pressure sensor chip, comprising: an n-type silicon substrate 1, a p-type pressure-sensitive resistor 2, a passivation layer, a metal electrode layer 7, and a bonding part; the p-type pressure-sensitive resistor 2 is arranged in a resistor placement groove on the top of the n-type silicon substrate 1, the p-type pressure-sensitive resistor 2 and the n-type silicon substrate 1 are electrically isolated by a PN junction, and the upper surface of the p-type pressure-sensitive resistor 2 and the n-type silicon substrate 1 are located in the same plane.

[0061] It should be understood that the p-type pressure-sensitive resistor 2 is formed in a specific area of ​​the n-type silicon substrate 1 by ion implantation or diffusion, and is electrically isolated from the n-type silicon substrate 1 by a PN junction to achieve insulation between the p-type pressure-sensitive resistor 2 and the n-type silicon substrate 1.

[0062] The passivation layer includes a silicon dioxide layer 3 and a silicon nitride layer 4. The silicon dioxide layer 3 is arranged on the n-type silicon substrate 1 and the p-type pressure-sensitive resistor 2 to achieve passivation and isolation protection of the chip; the silicon nitride layer 4 is arranged on the silicon dioxide layer 3 to enhance the passivation and isolation protection of the passivation layer.

[0063] An electrical contact region 5 and a stress release region 6 are provided on the silicon dioxide layer 3 and the silicon nitride layer 4 ; the electrical contact region 5 is provided at the top outer end of the p-type pressure sensitive resistor 2 , and the metal electrode layer 7 is provided on the electrical contact region 5 .

[0064] A silicon cup 8 is provided at the bottom of the n-type silicon substrate 1, so that the n-type silicon substrate 1 above the silicon cup 8 forms a pressure-sensitive membrane 9, and the stress release area 6 is provided on the upper surface of the pressure-sensitive membrane 9; the bonding part is bonded to the bottom of the n-type silicon substrate 1.

[0065] It should be understood that the electrical contact area 5 can be connected to the external circuit through an external lead. The stress release area 6 is provided on the upper surface of the pressure sensitive diaphragm 9 to fully release the stress of the chip stress area. Specifically, Figure 1 As shown, in some embodiments, the stress release area 6 extends inward from the edge of the pressure sensitive diaphragm 9 in a circular distribution. Figure 2 As shown, in some other embodiments, the stress relief region 6 extends outward from the edge of the p-type pressure-sensitive resistor 2 in a circular pattern. The metal electrode layer 7 is used to lead the internal signals of the chip. The pressure-sensitive membrane is provided on the silicon cup 8 to sense external pressure signals. The bonding member is bonded to the bottom of the n-type silicon substrate 1 to reduce chip packaging stress.

[0066] Growing silicon dioxide and silicon nitride on the surface of the n-type silicon substrate 1 as a passivation layer not only effectively physically isolates adjacent electronic devices, preventing signal interference and increasing the chip's breakdown voltage threshold, but also serves as a protective layer, protecting the chip from damage from environmental factors such as moisture, oxygen, and scratches, improving the chip's anti-interference capabilities and extending its service life. The stress relief area 6 can relieve film stress caused by the large-area passivation layer, significantly reducing the impact of film stress on the pressure sensor chip, thereby improving the chip's stability and reliability.

[0067] In some embodiments, the bonding member is one of bonding glass and bonding silicon wafer.

[0068] By bonding the bonding glass or bonding silicon wafer to the bottom of the n-type silicon substrate 1, the structural stability of the chip can be enhanced, the stress introduced during the packaging process can be reduced, and the matching between the sensor chip and external devices can be improved, thereby improving the overall reliability.

[0069] It should be understood that the bonding structure is not unique and can be adapted to different packaging requirements. Specifically, the bonding glass can be selected from non-porous glass 10 and through-hole glass 11, such as Figure 10 and Figure 11 The bonded silicon wafer includes a non-porous silicon wafer 12 and a through-hole silicon wafer 13, as shown Figure 12 and Figure 13 shown.

[0070] In some embodiments, the n-type silicon substrate 1 is a double-polished silicon wafer, and the thickness of the n-type silicon substrate 1 is in the range of 300 μm to 800 μm; the doping concentration of the p-type pressure sensitive resistor 2 is in the range of 3E18 cm -3 or 2E20cm -3 ; The junction depth of the PN junction ranges from 0.5μm to 3μm.

[0071] The doping concentration is 3E18cm -3 or 2E20cm -3 The high p-type doping concentration enables self-compensation of temperature drift in resistance and sensitivity, reducing the complexity of external circuits. The 0.5μm-3μm PN junction depth ensures uniform impurity distribution, increases the reverse breakdown voltage of the resistor, and improves chip reliability and stability.

[0072] The thickness of the silicon dioxide layer 3 is in the range of 50 nm to 300 nm; the thickness of the silicon nitride layer 4 is in the range of 50 nm to 300 nm; and the thickness of the metal electrode layer 7 is in the range of 500 nm to 2 μm.

[0073] Controlling the thickness of the silicon dioxide layer 3 and the silicon nitride layer 4 within the range of 50nm-300nm, while maintaining the thickness of the metal electrode layer 7 at 500nm-2μm, helps to balance the insulation performance and mechanical strength of the dielectric layer, optimize the stress matching of the multilayer structure, and improve the conductivity and structural stability of the electrode.

[0074] In some embodiments, the number of the p-type pressure-sensitive resistors 2 is four, each of the p-type pressure-sensitive resistors 2 is provided with two electrical contact areas 5, the metal electrode layer 7 is electrically connected to the p-type pressure-sensitive resistor 2 through the electrical contact areas 5, and the four p-type pressure-sensitive resistors 2 are wired and connected to form a Wheatstone bridge through the metal electrode layer 7.

[0075] It should be understood that the four p-type pressure sensitive resistors 2 ( R1 , R2 , R3 , and R4 ) are connected to form a Wheatstone bridge through external leads to convert the pressure signal into an electrical signal.

[0076] Four p-type pressure-sensitive resistors 2 are used, each with two electrical contact areas 5, and are connected to form a Wheatstone bridge structure through a metal electrode layer 7. This can improve the sensitivity of pressure detection and the temperature compensation effect, while reducing the measurement error of a single resistor, thereby improving the output signal stability and measurement accuracy of the sensor.

[0077] In some embodiments, the number of the metal electrode layers 7 is six, and the metal electrode layers 7 are disposed on the electrical contact region 5 .

[0078] The use of six metal electrode layers 7 and their arrangement on the electrical contact area 5 helps to increase the current conduction path and disperse the current density, thereby reducing the risk of local overheating, improving the electrical connection stability between the electrode and the contact area, and enhancing the heat dissipation performance of the overall structure.

[0079] In some embodiments, the silicon cup 8 is a vertical structure or a trapezoidal structure; the pressure sensitive membrane 9 has a thickness of 15 μm-300 μm.

[0080] It should be understood that the pressure sensitive diaphragm 9 is manufactured by processing the silicon cup 8. When external pressure acts on the pressure sensitive diaphragm 9, the pressure sensitive diaphragm 9 undergoes a slight deformation, generating an electrical signal. Figure 8 and Figure 9 The trapezoidal silicon cup 8 is prepared by a wet etching process, which has the characteristics of low cost, mass production and good consistency; the vertical silicon cup 8 is prepared by a deep silicon etching process, which has the characteristics of high cost and mass production.

[0081] The silicon cup 8 with a vertical or trapezoidal structure, combined with a pressure-sensitive diaphragm 9 with a thickness of 15μm-300μm, can take into account both structural support and pressure sensing functions, improve mechanical stability, optimize the transmission efficiency of pressure signals, and improve the sensitivity and reliability of the sensor.

[0082] In some embodiments, there are multiple stress release areas 6, and each stress release area 6 is arranged on the pressure sensitive diaphragm 9 away from the p-type pressure sensitive resistor 2 area; the interval between two adjacent stress release areas 6 is 5μm-200μm, and the width of each stress release area 6 is 5μm-300μm.

[0083] By providing a plurality of stress release regions 6 on the pressure-sensitive diaphragm 9 away from the p-type pressure-sensitive resistor 2, and controlling the interval between adjacent stress release regions 6 to be 5 μm-200 μm and the width of each stress release region 6 to be 5 μm-300 μm, the stress generated by the passivation layer on the pressure-sensitive diaphragm 9 can be dispersed, reducing the impact of stress concentration on sensor performance while maintaining the mechanical integrity of the diaphragm, thereby improving the output stability and measurement accuracy of the sensor.

[0084] Some embodiments of the present application further provide a method for processing a low-stress silicon-based pressure sensor chip, which is used to process the low-stress silicon-based pressure sensor chip described in the above embodiments. The method includes:

[0085] An n-type double-polished silicon wafer is selected as the n-type silicon substrate 1 .

[0086] It should be understood that the n-type silicon substrate 1 is a double-polished wafer, and the thickness of the n-type silicon substrate 1 is in the range of 300 μm to 800 μm.

[0087] Regional doping and annealing are performed on the n-type silicon substrate 1 by ion implantation or diffusion to form a p-type pressure sensitive resistor 2 .

[0088] It should be understood that the doping concentration of the p-type pressure sensitive resistor 2 is in the range of 3E18cm -3 or 2E20cm -3 After high temperature annealing, the PN junction depth ranges from 0.5μm to 3μm.

[0089] In some embodiments, the impurities used in the ion implantation are boron atoms, and the diffusion method uses a boron source sheet for doping.

[0090] Using boron atoms as ion implantation impurities and combining them with boron source diffusion doping can help improve the uniformity and controllability of the doping process, optimize the impurity concentration distribution, and thus improve the electrical performance and reliability of semiconductor devices.

[0091] A silicon dioxide layer 3 and a silicon nitride layer 4 are formed on the n-type silicon substrate 1 and the p-type pressure-sensitive resistor 2 by thermal oxidation, chemical vapor deposition or magnetron sputtering.

[0092] Specifically, the thickness of the silicon dioxide layer 3 prepared by thermal oxidation, chemical vapor deposition or magnetron sputtering is in the range of 50nm-300nm; the thickness of the silicon nitride layer 4 prepared by thermal oxidation, chemical vapor deposition or magnetron sputtering is in the range of 50nm-300nm.

[0093] The silicon nitride layer 4 and the silicon dioxide layer 3 are etched by using one or a combination of inductively coupled plasma etching, reactive ion etching, and wet etching to form an electrical contact region 5 and a stress release region 6 .

[0094] Specifically, before etching the passivation layer, photoresist can be used as protection on the bottom of the n-type silicon substrate 1 and as an etching mask on the top, and photolithography can be performed. First, the silicon nitride layer 4 is etched, then the silicon dioxide layer 3 is etched, and the etching stops at the silicon layer, and finally the photoresist is removed.

[0095] The metal electrode layer 7 is formed by magnetron sputtering or electron beam evaporation.

[0096] The metal electrode layer 7 is processed by annealing to form an ohmic contact.

[0097] Specifically, a metal electrode layer 7 is first formed on the passivation layer using magnetron sputtering or electron beam evaporation. The thickness of the metal electrode layer 7 is 500 nm to 2 μm. A photoresist is then used as an etching mask on the top layer for photolithography. The metal electrode layer 7 is then etched, and the photoresist is then removed. Finally, a high-temperature annealing process is performed to form an ohmic contact, thereby establishing an electrical connection between the metal electrode layer 7 and the p-type piezoresistor 2.

[0098] The bottom of the n-type silicon substrate 1 is etched by wet etching or deep silicon etching process to form a silicon cup 8 and a pressure sensitive membrane 9 .

[0099] Specifically, the bottom of the n-type silicon substrate 1 is processed by wet etching or deep silicon etching to form a silicon cup 8 and a pressure-sensitive diaphragm 9. The thickness of the pressure-sensitive diaphragm 9 is in the range of 15μm-300μm. The thickness of the pressure-sensitive diaphragm 9 of 15μm-300μm can cover the chip with a range specification of 1kPa-100MPa, meeting the application requirements of different scenarios.

[0100] In some embodiments, the silicon etchant in the wet etching method is a potassium hydroxide solution or a tetramethylammonium hydroxide solution.

[0101] Using potassium hydroxide solution or tetramethylammonium hydroxide solution as the silicon etchant for wet etching can control the corrosion rate and surface morphology of the silicon cup 8 structure, reduce defects generated during the corrosion process, improve the surface flatness and thickness uniformity of the pressure sensitive diaphragm 9, and thus improve the performance consistency of the sensor.

[0102] In some embodiments, before wet etching, the top of the n-type silicon substrate 1 is also protected, and the bottom of the n-type silicon substrate 1 is masked with silicon nitride. The n-type silicon substrate 1 is then anisotropically etched to form the silicon cup 8 and the pressure-sensitive membrane 9. The side of the silicon cup 8 may have a trapezoidal structure.

[0103] It should be understood that wet etching using potassium hydroxide or tetramethylammonium hydroxide solutions efficiently reacts with silicon, maintaining the smoothness and integrity of the silicon surface, reducing equipment corrosion risks, facilitating waste disposal, and easily adjustable process parameters. Potassium hydroxide (KOH) and tetramethylammonium hydroxide (TMAH) solution systems exhibit significant engineering advantages in anisotropic etching of silicon-based materials. By selectively activating specific crystal planes of the silicon lattice, they enable precise control of submicron morphology, maintaining a stable surface roughness (Ra) below 1 nm after etching. These alkaline solutions offer a wide window of parameter control regarding etching kinetics (concentration 5-40wt%, temperature 50-90°C), ensuring efficient etching rates of 0.5-2μm / min while suppressing side reactions through a pH buffering mechanism, protecting the silicon substrate from excessive corrosion. Compared to acidic etching systems, their corrosion byproducts (silicates / silanols) are chemically inert and can be readily neutralized for harmless wastewater disposal.

[0104] In some embodiments, before deep silicon etching, photoresist can be applied to the top of the n-type silicon substrate 1 for protection and to the bottom as an etching mask for photolithography. The silicon layer is then etched to a thickness of 15 μm to 300 μm for the pressure-sensitive membrane 9, and the photoresist is finally removed. The side surfaces of the silicon cup 8 can have a vertical structure.

[0105] It should be understood that deep reactive ion etching (DRIE) is a commonly used technique in micromachining for creating deep and narrow structures. Common gas combinations, such as sulfur hexafluoride for etching and octafluorocyclobutane for passivation, are used in alternating cycles to achieve high aspect ratios. The precision of deep silicon etching directly depends on the stability of the plasma source (such as ICP high-density plasma) and the equipment's ability to respond quickly to gas pulses (millisecond-level switching). Modern equipment has achieved submicron etching uniformity (within ±3%), driving the development of MEMS devices towards higher levels of integration.

[0106] The bonding component is bonded to the bottom of the n-type silicon substrate 1 by using anodic bonding or silicon-silicon bonding.

[0107] Specifically, the bonding method of the bonding glass adopts anodic bonding, specifically:

[0108] In a clean room environment, the n-type silicon substrate 1 is precisely aligned with the bonding glass (error < 2μm), placed on the metal surface plate, and then transferred to the working stage of the sealing machine. A slight pressure (0.1-1N / cm 2 ).

[0109] The n-type silicon substrate 1 is connected to the positive electrode of the DC power supply through the heating plate, and the bonding glass is connected to the negative electrode of the DC power supply through the metal surface electrode.

[0110] Control the vacuum degree ≤1-5×10-4Pa, raise the temperature to 200-400℃, and keep it warm for 0.5-1h.

[0111] Apply a DC voltage (800-1000V) with an initial current density of 1-10 mA / cm 2 , as the bonding progresses it drops to the μA level (completed in about 5-15 minutes) to complete the anodic bonding.

[0112] The bonding method of the bonded silicon wafer adopts silicon-silicon bonding, specifically:

[0113] Use RCA standard cleaning method to remove particles, organic matter and metal ion pollution, and the surface roughness must be controlled below 0.5nm.

[0114] Surface hydroxyl groups (-OH) are formed by oxygen plasma treatment (power 200-400W, oxygen flow rate 100-300sccm, time 5-30min) or wet chemical oxidation (H2O2 solution) to enhance bonding activity.

[0115] In a clean room environment, the two silicon wafers are placed on each other and the initial bonding is achieved through van der Waals forces and hydrogen bonds. Apply uniform pressure (0.1-1N / cm 2 ) and remove bubbles. After bonding, they need to be fixed quickly to prevent interface slippage.

[0116] Annealing is performed at 800-1200°C in nitrogen or inert gas for 2-4 hours to complete silicon-silicon bonding.

[0117] The above-mentioned processing method, based on all the beneficial effects of the low-stress silicon-based pressure sensor chip described in the above embodiments, selects an n-type double-polished silicon wafer as the substrate, combines regional doping and annealing to form a p-type pressure sensitive resistor 2, uses thermal oxidation or chemical vapor deposition to prepare a silicon dioxide layer 3 and a silicon nitride layer 4, and uses a combination of multiple etching processes to form an electrical contact area 5 and a stress relief area 6. A metal electrode layer 7 is formed by magnetron sputtering or electron beam evaporation and annealed to achieve ohmic contact. Finally, a silicon cup 8 and a pressure sensitive diaphragm 9 are formed by wet etching or deep silicon etching, and the device is packaged through a bonding process. This method can optimize the device stress distribution, improve the stability of the p-type pressure sensitive resistor 2, improve the electrical contact performance, and enhance the mechanical reliability of the diaphragm structure, thereby improving the overall performance of the sensor.

[0118] In some embodiments, the process gas of the inductively coupled plasma etching process and the reactive ion etching process is one or more of carbon tetrafluoride, trifluoromethane, oxygen, argon, and nitrogen, and the etching liquid of the wet etching process is a BOE solution, which is a mixed solution of 40% ammonium fluoride solution and 49% hydrofluoric acid solution prepared in a volume ratio of 6:1.

[0119] It should be understood that CF4 and CHF3 can significantly improve etching efficiency due to their high reactivity. By precisely controlling the gas ratio and mixing ratio, micro-nanoscale pattern etching can be accurately achieved. The mixed use of different process gases can not only optimize the consistency of the etching profile, but also achieve differentiated selective etching for different material systems through synergistic effects at the molecular level. This gas combination solution can maintain the stability of the plasma state by dynamically balancing the concentration of active elements in the plasma, thereby effectively suppressing process fluctuations and ensuring the repeatability and yield control of the etching process.

[0120] BOE solution, a key wet etchant in integrated circuit manufacturing, consists of a buffer system composed of hydrofluoric acid (HF) and ammonium fluoride (NH₄F). The buffering effect of NH₄F effectively regulates the fluoride ion concentration in this solution, maintaining its selective etching capability for silicon dioxide while suppressing the nonspecific corrosion of pure HF on the photoresist and silicon substrate, enabling controlled removal of micron- to nanometer-scale oxide structures. This characteristic provides irreplaceable advantages in precise control in processes such as gate oxide etching and dielectric planarization.

[0121] In some embodiments, the process gas of the deep silicon etching process is one or more of octafluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon.

[0122] By using one or more of octafluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon as deep silicon etching process gases, the selectivity and anisotropy of the etching process can be optimized, etching residues can be reduced, and the sidewall morphology of the silicon cup 8 structure can be improved, thereby improving the processing accuracy and mechanical properties of the pressure sensitive diaphragm 9.

[0123] It can be seen from the above technical solution that the embodiment of the present application provides a low-stress silicon-based pressure sensor chip and a processing method, the chip comprising: an n-type silicon substrate 1, a p-type pressure sensitive resistor 2, a passivation layer, a metal electrode layer 7 and a bonding part; the p-type pressure sensitive resistor 2 is arranged in a resistor placement groove on the top of the n-type silicon substrate 1, the p-type pressure sensitive resistor 2 and the n-type silicon substrate 1 are electrically isolated by a PN junction, and the upper surface of the p-type pressure sensitive resistor 2 is located in the same plane as the n-type silicon substrate 1; the passivation layer comprises a silicon dioxide layer 3 and a silicon nitride layer 4, the silicon dioxide layer 3 is arranged between the n-type silicon substrate 1 and the p-type pressure sensitive resistor 2. On the force-sensitive resistor 2, the silicon nitride layer 4 is arranged on the silicon dioxide layer 3; an electrical contact area 5 and a stress release area 6 are provided on the silicon dioxide layer 3 and the silicon nitride layer 4; the electrical contact area 5 is provided at the top outer end of the p-type pressure-sensitive resistor 2, and the metal electrode layer 7 is provided on the electrical contact area 5; a silicon cup 8 is provided at the bottom of the n-type silicon substrate 1, so that the n-type silicon substrate 1 in the area above the silicon cup 8 constitutes a pressure-sensitive diaphragm 9, and the stress release area 6 is provided on the upper surface of the pressure-sensitive diaphragm 9; the bonding part is bonded to the bottom of the n-type silicon substrate 1 to solve the problem that the introduction of the passivation layer affects the output and reliability of the pressure sensor chip.

[0124] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without expending creative work shall fall within the scope of protection of this application.

Claims

1. A low-stress silicon-based pressure sensor chip, characterized in that: include: An n-type silicon substrate (1), a p-type pressure sensitive resistor (2), a passivation layer, a metal electrode layer (7), and a bonding member; The p-type pressure sensitive resistor (2) is arranged in a resistor placement groove on the top of the n-type silicon substrate (1), the p-type pressure sensitive resistor (2) and the n-type silicon substrate (1) are electrically isolated via a PN junction, and the upper surface of the p-type pressure sensitive resistor (2) and the n-type silicon substrate (1) are located in the same plane; The passivation layer comprises a silicon dioxide layer (3) and a silicon nitride layer (4), the silicon dioxide layer (3) being arranged on the n-type silicon substrate (1) and the p-type pressure sensitive resistor (2), and the silicon nitride layer (4) being arranged on the silicon dioxide layer (3); An electrical contact region (5) and a stress release region (6) are provided on the silicon dioxide layer (3) and the silicon nitride layer (4); the electrical contact region (5) is provided at the top outer end of the p-type pressure sensitive resistor (2), and the metal electrode layer (7) is provided on the electrical contact region (5); A silicon cup (8) is provided at the bottom of the n-type silicon substrate (1), so that the n-type silicon substrate (1) in the area above the silicon cup (8) forms a pressure-sensitive diaphragm (9), and the stress release area (6) is provided on the upper surface of the pressure-sensitive diaphragm (9); The bonding element is bonded to the bottom of the n-type silicon substrate (1).

2. The low stress silicon-based pressure sensor chip according to claim 1, characterized in that: The bonding component is one of bonding glass and bonding silicon wafer.

3. The low stress silicon-based pressure sensor chip according to claim 1, characterized in that: The n-type silicon substrate (1) is a double-polished silicon wafer, and the thickness of the n-type silicon substrate (1) ranges from 300 μm to 800 μm; the doping concentration of the p-type pressure sensitive resistor (2) ranges from 3E18 cm -3 or 2E20cm -3 The junction depth of the PN junction ranges from 0.5 μm to 3 μm; the thickness of the silicon dioxide layer (3) ranges from 50 nm to 300 nm; the thickness of the silicon nitride layer (4) ranges from 50 nm to 300 nm; the thickness of the metal electrode layer (7) ranges from 500 nm to 2 μm; and the thickness of the pressure sensitive diaphragm (9) ranges from 15 μm to 300 μm.

4. The low stress silicon-based pressure sensor chip according to claim 1, characterized in that: The number of the p-type pressure sensitive resistors (2) is four, each of the p-type pressure sensitive resistors (2) is provided with two electrical contact areas (5), the metal electrode layer (7) is electrically connected to the p-type pressure sensitive resistor (2) via the electrical contact areas (5), and the four p-type pressure sensitive resistors (2) are wired and connected to form a Wheatstone bridge via the metal electrode layer (7).

5. The low stress silicon-based pressure sensor chip according to claim 1, characterized in that: There are a plurality of stress release areas (6), and the stress release areas (6) are arranged on the pressure sensitive diaphragm (9) away from the p-type pressure sensitive resistor (2) area; the interval between two adjacent stress release areas (6) is 5μm-200μm, and the width of each stress release area (6) is 5μm-300μm.

6. A low-stress silicon-based pressure sensor chip processing method, characterized in that: The method for processing the low-stress silicon-based pressure sensor chip according to any one of claims 1 to 5 comprises: An n-type double-throw silicon wafer is selected as an n-type silicon substrate (1); Performing regional doping and annealing on the n-type silicon substrate (1) by ion implantation or diffusion to form a p-type pressure sensitive resistor (2); A silicon dioxide layer (3) and a silicon nitride layer (4) are prepared on the n-type silicon substrate (1) and the p-type pressure sensitive resistor (2) by adopting thermal oxidation, chemical vapor deposition or magnetron sputtering; Etching the silicon nitride layer (4) and the silicon dioxide layer (3) using one or a combination of inductively coupled plasma etching, reactive ion etching, and wet etching to form an electrical contact region (5) and a stress release region (6); forming a metal electrode layer (7) by magnetron sputtering or electron beam evaporation; The metal electrode layer (7) is treated by annealing to form an ohmic contact; Etching the bottom of the n-type silicon substrate (1) using a wet etching method or a deep silicon etching process to form a silicon cup (8) and a pressure-sensitive membrane (9); The bonding element is bonded to the bottom of the n-type silicon substrate (1) by using an anodic bonding method or a silicon-silicon bonding method.

7. The method for processing a low-stress silicon-based pressure sensor chip according to claim 6, wherein: The impurities used in the ion implantation are boron atoms, and the diffusion method uses a boron source sheet for doping.

8. The method for processing a low-stress silicon-based pressure sensor chip according to claim 6, wherein: The process gases of the inductively coupled plasma etching process and the reactive ion etching process are one or more of carbon tetrafluoride, trifluoromethane, oxygen, argon, and nitrogen. The etching liquid of the wet etching process is a BOE solution, which is a mixed solution of 40% ammonium fluoride solution and 49% hydrofluoric acid solution prepared in a volume ratio of 6:

1.

9. The method for processing a low-stress silicon-based pressure sensor chip according to claim 6, wherein: The silicon etchant in the wet etching method is potassium hydroxide solution or tetramethylammonium hydroxide solution.

10. The method for processing a low-stress silicon-based pressure sensor chip according to claim 6, wherein: The process gas for the deep silicon etching process is one or more of octafluorocyclobutane, carbon tetrafluoride, sulfur hexafluoride, oxygen, and argon.

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