Low-stress, high-temperature pressure sensor chip and processing method

Abstract

The present application relates to the technical field of pressure sensors, and in particular to a low-stress, high-temperature pressure sensor chip and a processing method thereof. The low-stress, high-temperature pressure sensor chip comprises a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer and a silicon carbide sealing wafer; an n-type silicon carbide device layer, a p-type silicon carbide isolation layer and an n-type silicon carbide substrate layer in the silicon carbide epitaxial wafer are connected in sequence from top to bottom; the n-type silicon carbide device layer is etched to form an n-type silicon carbide pressure-sensitive resistor, a sealing area and an isolation channel; the passivation layer comprises a silicon dioxide layer and a silicon nitride layer, and a stress release area is opened on the silicon dioxide layer and the silicon nitride layer; the bottom of the n-type silicon carbide substrate layer is etched to form a pressure cavity, and the p-type silicon carbide isolation layer and the n-type silicon carbide substrate layer in the area directly above the pressure cavity constitute a pressure-sensitive diaphragm, and the stress release area is arranged on the upper surface of the pressure-sensitive diaphragm to solve the problem of low reliability of the low-stress, high-temperature pressure sensor chip.

Description

Technical Field

[0001] The present application relates to the technical field of pressure sensors, and in particular to a low-stress, high-temperature pressure sensor chip and a processing method thereof. Background Art

[0002] Microelectromechanical system (MEMS) pressure sensors based on silicon carbide (SiC) materials demonstrate critical application value in extreme high-temperature conditions. This is particularly true in scenarios such as high-temperature gas monitoring in aerospace propulsion systems, downhole tool measurement and control in deep-earth resource exploration, and pressure feedback in nuclear reactor cooling circuits. These sensors require long-term stable operation in environments above 500°C. These applications place dual demands on pressure-sensitive components: they must withstand the harsh conditions of high-temperature oxidation and thermal shock, while ensuring accurate conversion of deformation signals from sensitive structures across a wide temperature range.

[0003] In order to solve the problem of dielectric protection and electrical stability in high temperature environment, the related technology adopts silicon dioxide / silicon nitride composite passivation layer structure, in which the silicon nitride layer has a hardness of 9.5GPa and >10 9 The Ω·cm resistivity achieves mechanical protection and electrical isolation. The silicon dioxide layer increases the dielectric breakdown field strength to 8MV / cm by filling lattice defects, while reducing the leakage current caused by particle contamination by two orders of magnitude.

[0004] However, the difference in thermal expansion coefficients between silicon carbide and the passivation layer material results in significant film stress over a wide temperature range from -55°C to 600°C. This stress is transmitted to the pressure-sensitive resistor, causing abnormal changes in resistance and severely impacting the stability of the sensor's output signal. This interference with the deformation of the sensitive diaphragm is particularly pronounced during low-range pressure measurements, becoming a key issue limiting the reliability of high-temperature pressure sensors. Summary of the Invention

[0005] The present application provides a low-stress, high-temperature pressure sensor chip and a processing method thereof to solve the problem of low reliability of the low-stress, high-temperature pressure sensor chip.

[0006] In a first aspect, the present application provides a low-stress, high-temperature pressure sensor chip, comprising: a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer, and a silicon carbide sealing wafer;

[0007] The silicon carbide epitaxial wafer comprises an n-type silicon carbide device layer, a p-type silicon carbide isolation layer and an n-type silicon carbide substrate layer, wherein the n-type silicon carbide device layer, the p-type silicon carbide isolation layer and the n-type silicon carbide substrate layer are sequentially connected from top to bottom;

[0008] The n-type silicon carbide device layer is etched to form an n-type silicon carbide pressure sensitive resistor, a sealing area and an isolation channel; wherein the n-type silicon carbide pressure sensitive resistor is isolated from the sealing area by the isolation channel;

[0009] The passivation layer includes a silicon dioxide layer and a silicon nitride layer, the silicon dioxide layer is located on the upper surface of the n-type silicon carbide pressure-sensitive resistor and the isolation channel, the silicon nitride layer is located on the upper surface of the silicon dioxide layer, and a stress release area is opened on the silicon dioxide layer and the silicon nitride layer; the bottom of the n-type silicon carbide substrate layer is etched to form a pressure cavity, and the p-type silicon carbide isolation layer and the n-type silicon carbide substrate layer in the area directly above the pressure cavity constitute a pressure-sensitive diaphragm, and the stress release area is provided on the upper surface of the pressure-sensitive diaphragm;

[0010] The metal electrode layer is disposed on the sealing area, and the metal electrode layer is electrically connected to the n-type silicon carbide pressure sensitive resistor;

[0011] The silicon carbide sealing wafer is bonded to the top of the silicon carbide epitaxial wafer.

[0012] The pressure sensor chip is constructed with silicon dioxide and silicon nitride as a passivation layer. This layer provides physical protection against mechanical damage and contaminants; chemical protection against moisture, ion migration, and acid-base corrosion; electrical protection against insulation, leakage current suppression, and interface stabilization; thermal protection against thermal expansion coefficients to withstand high-temperature environments; and long-term reliability against metal migration and structural aging. Furthermore, stress relief zones are provided on the passivation layer of the pressure-sensitive diaphragm, along the edges of the pressure-sensitive diaphragm and the edges of the n-type silicon carbide pressure-sensitive resistor. By removing portions of the silicon dioxide and silicon nitride layers, stress relief from the large-area passivation layer can be achieved, significantly reducing the impact of this stress on the pressure sensor chip and improving its stability and reliability.

[0013] Optionally, the silicon carbide epitaxial wafer is a double-polished wafer, the thickness of the silicon carbide epitaxial wafer is 300 μm-500 μm; the thickness of the n-type silicon carbide device layer is 200 nm-2 μm, and the doping concentration of the n-type silicon carbide device layer is 1E19 cm -3 ~3E20cm -3 The thickness of the p-type silicon carbide isolation layer is 2μm~10μm, and the doping concentration of the p-type silicon carbide isolation layer is 3E15cm -3 ~3E18cm -3 ; The thickness of the silicon dioxide layer is 50nm~200nm; the thickness of the silicon nitride layer is 50nm~200nm; the thickness of the metal electrode layer is 500nm~1μm; the thickness of the pressure sensitive membrane is 50μm~200μm.

[0014] The silicon carbide epitaxial wafer adopts a double-throw wafer structure, and the thickness is controlled in the range of 300μm-500μm, wherein the thickness of the n-type silicon carbide device layer is 200nm~2μm and the doping concentration is 1E19cm-3 ~3E20cm -3 The thickness of the p-type silicon carbide isolation layer is 2μm~10μm and the doping concentration is 3E15cm -3 ~3E18cm -3 , combined with a silicon dioxide layer and a silicon nitride layer with a thickness of 50nm~200nm, a metal electrode layer with a thickness of 500nm~1μm, and a pressure-sensitive diaphragm with a thickness of 50μm~200μm, this structural design helps to optimize the carrier transport characteristics, improve the uniformity of stress distribution, reduce the interface defect density, and improve the working stability of the device in high temperature and high pressure environments, while ensuring the mechanical strength and sensitivity of the pressure-sensitive diaphragm.

[0015] Optionally, the number of the n-type silicon carbide pressure sensitive resistors is four, and the four n-type silicon carbide pressure sensitive resistors are distributed along the four sides of the pressure sensitive diaphragm. The four n-type silicon carbide pressure sensitive resistors are isolated from each other by the isolation channel and form a closed bridge Wheatstone bridge.

[0016] Four n-type silicon carbide pressure-sensitive resistors are distributed around the pressure-sensitive diaphragm, isolated from each other by isolation channels and forming a closed-bridge Wheatstone bridge. The differential output structure is used to enhance sensitivity and achieve temperature self-compensation, thereby accurately detecting tiny resistance changes. The symmetrical design helps to alleviate common-mode interference and improve measurement stability in complex environments. Its micromachining process compatibility facilitates integration into micro-sensor systems, while providing conditions for hardware compensation and algorithm optimization to improve overall accuracy.

[0017] Optionally, the stress release region is formed by etching the silicon dioxide layer and the silicon nitride layer, and the stress release region is distributed in a ring shape at an edge region of the pressure sensitive diaphragm or around the n-type silicon carbide pressure sensitive resistor.

[0018] The stress release area is formed by etching the silicon dioxide layer and the silicon nitride layer, and is distributed in a ring structure at the edge area of ​​the pressure-sensitive diaphragm or around the n-type silicon carbide pressure-sensitive resistor. It helps to alleviate stress concentration between materials, improve the mechanical stability of the sensor, and reduce the interface stress caused by differences in thermal expansion coefficients, thereby improving the long-term reliability and measurement accuracy of the device.

[0019] Optionally, the stress release zone includes a plurality of concentric annular regions. If there are multiple concentric annular regions, the interval between two adjacent concentric annular regions is 10 μm-50 μm, and the width of each concentric annular region is 20 μm-200 μm.

[0020] The stress release zone adopts a structure of multiple concentric annular areas, with the interval between adjacent annular areas being 10μm-50μm and the width of each annular area being 20μm-200μm. This can optimize the local film stress distribution of the n-type silicon carbide pressure sensitive resistor, alleviate stress concentration, improve the stress matching characteristics of the sensor, thereby reducing measurement errors caused by uneven stress, and at the same time enhance the structural reliability and long-term stability of the device.

[0021] Optionally, a through hole is formed on the silicon carbide sealing wafer near the metal electrode layer; and a blind groove is formed on the silicon carbide sealing wafer near the pressure sensitive diaphragm.

[0022] The silicon carbide sealing wafer is provided with a through hole near the metal electrode layer to facilitate filling with conductive paste to realize electrical signal transmission. At the same time, a blind groove is opened near the pressure-sensitive diaphragm to provide deformation space for the pressure-sensitive diaphragm. This structural design helps to improve the reliability of signal transmission, reduce the impact of packaging stress on sensitive components, and improve the sensor's detection accuracy of tiny deformations.

[0023] A second aspect of the present application provides a low-stress, high-temperature pressure sensor chip processing method, which is used to process the low-stress, high-temperature pressure sensor chip described in the first aspect. The method comprises:

[0024] An npn double-throw silicon carbide epitaxial wafer is selected as the silicon carbide epitaxial wafer to be processed; wherein the top layer of the silicon carbide epitaxial wafer is an n-type silicon carbide device layer; the middle layer of the silicon carbide epitaxial wafer is a p-type silicon carbide isolation layer; and the bottom layer of the silicon carbide epitaxial wafer is an n-type silicon carbide substrate layer;

[0025] Etching the n-type silicon carbide device layer using an inductively coupled plasma etching process or a reactive ion etching process to form an n-type silicon carbide pressure sensitive resistor, a sealing area, and an isolation channel;

[0026] preparing a silicon dioxide layer and a silicon nitride layer on the upper surface of the silicon carbide epitaxial wafer by chemical vapor deposition;

[0027] Etching the silicon nitride layer and the silicon dioxide layer by using one or a combination of inductively coupled plasma etching, reactive ion etching, and wet etching to form a stress relief area;

[0028] forming a metal electrode layer on the sealing area by electron beam evaporation;

[0029] Etching the bottom of the n-type silicon carbide substrate layer using a deep silicon carbide etching process to form a pressure cavity;

[0030] A silicon carbide sealing wafer is sealed on top of the silicon carbide epitaxial wafer.

[0031] The above-mentioned processing method, on the basis of including all the beneficial effects of the low-stress, high-temperature pressure sensor chip described in the first aspect, selects an npn-type double-polished silicon carbide epitaxial wafer as a substrate, adopts inductively coupled plasma etching or reactive ion etching process to form an n-type silicon carbide pressure sensitive resistor and isolation channel, combines chemical vapor deposition to prepare silicon dioxide and silicon nitride layers, and then forms a stress release area through an etching process, and uses electron beam evaporation to make a metal electrode layer. Finally, a pressure cavity is formed by deep silicon carbide etching and bonded to a silicon carbide sealing wafer. This helps to reduce the impact of thermal stress during the processing, improve stress matching between device layers, and improve the stability of the sensor in a high-temperature environment. At the same time, it ensures a reliable connection between the n-type silicon carbide pressure sensitive resistor and the electrode, thereby enhancing the overall performance of the chip.

[0032] Optionally, the etching gas of the inductively coupled plasma etching process and the reactive ion etching process is at least one of tetrafluoromethane, sulfur hexafluoride, and trifluoromethane; the auxiliary gas of the inductively coupled plasma etching process and the reactive ion etching process is at least one of oxygen, argon, and nitrogen, wherein the volume proportion of tetrafluoromethane is 60%-80%.

[0033] At least one of tetrafluoromethane, sulfur hexafluoride and trifluoromethane is used as the main etching gas, and oxygen, argon or nitrogen is used as the auxiliary gas. The volume proportion of tetrafluoromethane is controlled at 60%-80%. By regulating the concentration gradient of the gas components of the plasma chemical reaction, optimizing the free radical transport path and ion bombardment energy, an etching process with highly anisotropic characteristics is formed, which can achieve precise control of submicron feature sizes, thereby improving the stability and accuracy of the etching process.

[0034] Optionally, the wet etching process uses a buffered oxide etchant, which is prepared by mixing 40% ammonium fluoride solution and 49% hydrofluoric acid solution in a volume ratio of 6:1.

[0035] The wet etching process uses a buffered oxide etchant prepared by mixing 40% ammonium fluoride solution and 49% hydrofluoric acid solution in a volume ratio of 6:1. This can adjust the etching rate and reaction activity, improve the stability of the etching process, reduce the risk of over-etching due to excessive hydrofluoric acid concentration, and help obtain a more uniform etched surface morphology, thereby improving the controllability and repeatability of the etching process.

[0036] Optionally, the process gas of the deep silicon carbide etching process is one or more of octafluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen and argon, and the etching mask of the deep silicon carbide etching process is metal nickel.

[0037] The deep silicon carbide etching process uses one or more of octafluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen and argon as process gases, and uses metal nickel as an etching mask. This combination can optimize the etching selectivity and etching rate of the silicon carbide material, improve the verticality and surface roughness of the etched sidewalls, thereby reducing device damage during the etching process, improving the structural accuracy and dimensional consistency of the pressure chamber, and helping to enhance the performance stability of the sensor.

[0038] It can be seen from the above technical solution that the present application provides a low-stress, high-temperature pressure sensor chip and a processing method, wherein the chip includes: a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer and a silicon carbide sealing wafer; the silicon carbide epitaxial wafer includes an n-type silicon carbide device layer, a p-type silicon carbide isolation layer and an n-type silicon carbide substrate layer, and the n-type silicon carbide device layer, the p-type silicon carbide isolation layer and the n-type silicon carbide substrate layer are connected in sequence from top to bottom; the n-type silicon carbide device layer is etched to form an n-type silicon carbide pressure sensitive resistor, a sealing area and an isolation channel; wherein the n-type silicon carbide pressure sensitive resistor is isolated from the sealing area by the isolation channel; the passivation layer includes a silicon dioxide layer and a silicon nitride layer, and the silicon dioxide layer is located at the bottom. The n-type silicon carbide pressure sensitive resistor and the upper surface of the isolation channel, the silicon nitride layer is located on the upper surface of the silicon dioxide layer, and a stress release area is opened on the silicon dioxide layer and the silicon nitride layer; the bottom of the n-type silicon carbide substrate layer is etched to form a pressure cavity, and the p-type silicon carbide isolation layer and the n-type silicon carbide substrate layer in the area directly above the pressure cavity constitute a pressure sensitive diaphragm, and the stress release area is arranged on the upper surface of the pressure sensitive diaphragm; the metal electrode layer is arranged on the sealing area, and the metal electrode layer is electrically connected to the n-type silicon carbide pressure sensitive resistor; the silicon carbide sealing wafer is bonded to the top of the silicon carbide epitaxial wafer to solve the problem of low reliability of low-stress and high-temperature pressure sensor chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0040] Figure 1 The flat process board in the low stress and high temperature pressure sensor chip processing method provided in the embodiment of the present application Figure 1 ;

[0041] Figure 2 The flat process board in the low stress and high temperature pressure sensor chip processing method provided in the embodiment of the present application Figure 2 ;

[0042] Figure 3A schematic diagram of the structure of a silicon carbide epitaxial wafer in the low-stress, high-temperature pressure sensor chip processing method provided in an embodiment of the present application;

[0043] Figure 4 A schematic diagram of the structure of forming a pressure sensitive resistor, a sealing area, and an isolation channel in the low-stress, high-temperature pressure sensor chip processing method provided in an embodiment of the present application;

[0044] Figure 5 A schematic diagram of the structure of forming a passivation layer in the low-stress and high-temperature pressure sensor chip processing method provided in an embodiment of the present application;

[0045] Figure 6 A schematic diagram of the structure of forming a stress relief area in the low-stress and high-temperature pressure sensor chip processing method provided in an embodiment of the present application;

[0046] Figure 7 A schematic diagram of the structure of forming a metal electrode layer in the low-stress and high-temperature pressure sensor chip processing method provided in an embodiment of the present application;

[0047] Figure 8 A schematic diagram of the structure of a pressure cavity formed in the low-stress, high-temperature pressure sensor chip processing method provided in an embodiment of the present application;

[0048] Figure 9 This is a schematic diagram of the structure after bonding the silicon carbide sealing wafer and the silicon carbide epitaxial wafer in the low-stress and high-temperature pressure sensor chip processing method provided in an embodiment of the present application.

[0049] Illustration:

[0050] Among them, 1-n-type silicon carbide device layer; 2-p-type silicon carbide isolation layer; 3-n-type silicon carbide substrate layer; 4-n-type silicon carbide pressure sensitive resistor; 5-sealing area; 6-isolation channel; 7-silicon dioxide layer; 8-silicon nitride layer; 9-stress release area; 10-metal electrode layer; 11-pressure cavity; 12-pressure sensitive diaphragm; 13-silicon carbide sealing wafer. DETAILED DESCRIPTION

[0051] The following embodiments are described in detail, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different figures represent identical or similar elements unless otherwise indicated. The embodiments described in the following embodiments are not intended to represent all possible implementations consistent with the present application. They are merely examples of systems and methods consistent with certain aspects of the present application.

[0052] Silicon carbide-based microelectromechanical system (MEMS) pressure sensors demonstrate critical application value in extreme high-temperature conditions. This is particularly true in scenarios such as high-temperature gas monitoring in aerospace propulsion systems, downhole tool measurement and control in deep-earth resource exploration, and pressure feedback in nuclear reactor cooling circuits. These sensors require long-term stable operation in environments exceeding 500°C. These applications place dual demands on pressure-sensitive components: they must withstand the harsh conditions of high-temperature oxidation and thermal shock, while ensuring accurate conversion of deformation signals from sensitive structures across a wide temperature range.

[0053] In order to solve the problem of dielectric protection and electrical stability in high temperature environment, in the relevant embodiments, a silicon dioxide / silicon nitride composite passivation layer structure is adopted, wherein the silicon nitride layer has a hardness of 9.5GPa and a resistance of >10 9 The Ω·cm resistivity provides mechanical protection and electrical isolation. The silicon dioxide layer, by filling lattice defects, increases the dielectric breakdown field strength to 8 MV / cm, while also reducing leakage current caused by particle contamination by two orders of magnitude. However, the difference in thermal expansion coefficient between silicon carbide and the passivation layer material results in significant film stress over a wide temperature range of -55°C to 600°C. This stress is transmitted to the pressure-sensitive resistor, causing abnormal changes in resistance and seriously affecting the stability of the sensor's output signal. Especially during low-range pressure measurements, the interference of film stress on the deformation of the sensitive diaphragm is more pronounced, becoming a core issue limiting the reliability of high-temperature pressure sensors.

[0054] To solve the problem of low reliability of low stress and high temperature pressure sensor chips, see Figures 1-9 Some embodiments of the present application provide a low-stress, high-temperature pressure sensor chip, comprising: a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer 10 and a silicon carbide sealing wafer 13; the silicon carbide epitaxial wafer comprises an n-type silicon carbide device layer 1, a p-type silicon carbide isolation layer 2 and an n-type silicon carbide substrate layer 3, and the n-type silicon carbide device layer 1, the p-type silicon carbide isolation layer 2 and the n-type silicon carbide substrate layer 3 are connected in sequence from top to bottom; the n-type silicon carbide device layer 1 is etched to form an n-type silicon carbide pressure sensitive resistor 4, a sealing area 5 and an isolation channel 6; wherein the n-type silicon carbide pressure sensitive resistor 4 is isolated from the sealing area 5 by the isolation channel 6.

[0055] It should be understood that the sensor chip's silicon carbide epitaxial wafer and silicon carbide sealing wafer 13 are both made of 4H-silicon carbide. The n-type silicon carbide pressure sensitive resistor 4 and the p-type silicon carbide isolation layer 2 are electrically isolated via a PN junction and can be used in high-temperature environments above 600°C.

[0056] The passivation layer includes a silicon dioxide layer 7 and a silicon nitride layer 8. The silicon dioxide layer 7 is located on the upper surface of the n-type silicon carbide pressure sensitive resistor 4 and the isolation channel 6. The silicon nitride layer 8 is located on the upper surface of the silicon dioxide layer 7. A stress release area 9 is provided on the silicon dioxide layer 7 and the silicon nitride layer 8.

[0057] It should be understood that the passivation layer utilizes a composite dielectric structure design, wherein a silicon dioxide layer 7 is grown directly onto the surface of the silicon carbide epitaxial wafer via chemical vapor deposition, completely covering the sensitive area of ​​the n-type silicon carbide pressure-sensitive resistor 4, thereby suppressing carrier migration and repairing surface state defects. A silicon nitride layer 8 is deposited onto the surface of the silicon dioxide layer 7 via chemical vapor deposition, enhancing the passivation and isolation protection provided by the passivation layer. In terms of physical protection, the passivation layer protects against mechanical damage and contaminants; in terms of chemical protection, it resists moisture, ion migration, and acid-base corrosion; in terms of electrical protection, it insulates, suppresses leakage current, and stabilizes interface states; in terms of thermal protection, it matches the thermal expansion coefficient to withstand high-temperature environments; and in terms of long-term reliability, it slows metal migration and structural aging.

[0058] The bottom of the n-type silicon carbide substrate layer 3 is etched to form a pressure cavity 11. The p-type silicon carbide isolation layer 2 and the n-type silicon carbide substrate layer 3 in the area directly above the pressure cavity 11 constitute a pressure-sensitive diaphragm 12. The stress release area 9 is arranged on the upper surface of the pressure-sensitive diaphragm 12 for sensing external pressure signals.

[0059] It should be understood that the pressure cavity 11 has a rectangular cross-section and is prepared using a deep silicon carbide etching process, which has the characteristics of low cost, mass production, and good consistency. The stress release area 9 is arranged on the pressure sensitive diaphragm 12, and at the same time, the stress release area 9 is not provided with a passivation layer to solve the film stress mismatch existing in the pressure sensor chip, reduce the influence of the film stress on the pressure sensor chip, and improve the reliability and stability of the pressure sensor chip; at the same time, the sealing area 5 is not provided with a passivation layer to avoid the passivation layer affecting the sealing effect. The stress release area 9 removes part of the silicon dioxide layer 7 and the silicon nitride layer 8, which can release the film stress caused by the large-area passivation layer, significantly reduce the influence of the film stress on the pressure sensor chip, and thus improve the stability and reliability of the chip.

[0060] The metal electrode layer 10 is disposed on the sealing area 5 , and the metal electrode layer 10 is electrically connected to the n-type silicon carbide pressure sensitive resistor 4 ; the silicon carbide sealing wafer 13 is bonded to the top of the silicon carbide epitaxial wafer.

[0061] It should be understood that the silicon carbide sealing wafer 13 is front-bonded to the silicon carbide epitaxial wafer to form a positive packaging structure, which can realize the leadless packaging structure of the sensor, improve the natural frequency of the sensor, reduce the size of the sensor, and at the same time increase the application temperature of the sensor to above 400°C.

[0062] The pressure sensor chip is constructed with silicon dioxide and silicon nitride as a passivation layer. This layer provides physical protection against mechanical damage and contaminants, chemical protection against moisture, ion migration, and acid-base corrosion, electrical insulation, leakage current suppression, and interface stability, thermal protection against thermal expansion coefficients, and high-temperature environments. Furthermore, long-term reliability reduces metal migration and structural aging. Furthermore, stress relief regions 9 are provided on the passivation layer of the pressure-sensitive diaphragm 12, along the edges of the pressure-sensitive diaphragm 12 and the edges of the n-type silicon carbide pressure-sensitive resistor 4. By removing portions of the silicon dioxide layer 7 and silicon nitride layer 8, stress relief from the large-area passivation layer can be achieved, significantly reducing the impact of this stress on the pressure sensor chip and improving its stability and reliability.

[0063] In some embodiments, the silicon carbide epitaxial wafer is a double-polished wafer, and the thickness of the silicon carbide epitaxial wafer is 300 μm-500 μm;

[0064] The thickness of the n-type silicon carbide device layer 1 is 200 nm to 2 μm, and the doping concentration of the n-type silicon carbide device layer 1 is 1E19 cm -3 ~3E20cm -3 The thickness of the p-type silicon carbide isolation layer 2 is 2μm~10μm, and the doping concentration of the p-type silicon carbide isolation layer 2 is 3E15cm -3 ~3E18cm -3 .

[0065] It should be understood that the thickness is 200nm~2μm and the doping concentration is 1E19cm -3 ~3E20cm -3 The n-type silicon carbide device layer 1 can ensure the thickness of the n-type silicon carbide pressure sensitive resistor 4 and the sensitivity output of the chip; the thickness is 2μm~10μm, and the doping concentration is 3E15cm -3 ~3E18cm -3 The p-type silicon carbide isolation layer 2 can ensure sufficient breakdown voltage and isolation effect with the n-type silicon carbide device layer 1.

[0066] In some embodiments, the thickness of the silicon dioxide layer 7 is 50 nm to 200 nm; the thickness of the silicon nitride layer 8 is 50 nm to 200 nm.

[0067] It should be understood that the silicon dioxide layer 7 with a thickness ranging from 50nm to 200nm can solidify the mobile ions and interface defects at the interface between silicon carbide and silicon dioxide, resist micromechanical scratches and particle impact, form a smooth interface layer with a surface roughness of <5nm, and effectively reduce the stress concentration factor to below 0.3; the silicon nitride layer 8 with a thickness ranging from 50nm to 200nm can enhance the protection of the device layer, block H2O, Cl - It can prevent the penetration of other corrosive media, enhance the insulation barrier and reduce leakage current.

[0068] In some embodiments, the thickness of the metal electrode layer 10 is 500 nm to 1 μm; the thickness of the pressure sensitive membrane 12 is 50 μm to 200 μm.

[0069] It should be understood that the pressure sensitive diaphragm 12 with a thickness of 50 μm to 200 μm can cover a chip with a range specification of 100 kPa-100 MPa, achieve a higher sensitivity output, and meet the application requirements of different scenarios.

[0070] In some embodiments, the number of the n-type silicon carbide pressure sensitive resistors 4 is four, and the four n-type silicon carbide pressure sensitive resistors 4 (R1, R2, R3, R4) are distributed along the four sides of the pressure sensitive diaphragm 12. The four n-type silicon carbide pressure sensitive resistors 4 are isolated from each other by the isolation channel 6 and form a closed bridge Wheatstone bridge.

[0071] It should be understood that when external pressure acts on the pressure sensitive diaphragm 12 , the pressure sensitive diaphragm 12 undergoes slight deformation, transmitting the pressure to the n-type silicon carbide pressure sensitive resistor 4 , thereby causing the Wheatstone bridge to generate an electrical signal that varies with pressure.

[0072] Four n-type silicon carbide pressure-sensitive resistors 4 are distributed around the pressure-sensitive diaphragm 12, isolated from each other by an isolation channel 6 to form a closed-bridge Wheatstone bridge. The differential output structure is used to improve sensitivity and achieve temperature self-compensation, thereby accurately detecting tiny resistance changes. The symmetrical design helps to alleviate common-mode interference and improve measurement stability in complex environments. Its micromachining process compatibility facilitates integration into the microsensor system, while providing conditions for hardware compensation and algorithm optimization to improve overall accuracy.

[0073] In some embodiments, the stress release region 9 is formed by etching the silicon dioxide layer 7 and the silicon nitride layer 8 , and the stress release region 9 is distributed in a ring shape at the edge of the pressure sensitive diaphragm 12 or around the n-type silicon carbide pressure sensitive resistor 4 .

[0074] Specifically, in some embodiments, Figure 1As shown, the stress release area 9 is located on the pressure sensitive diaphragm 12 and extends inward along the edge of the pressure sensitive diaphragm 12 in a circular distribution, so as to optimize the overall film stress of the pressure sensitive diaphragm 12 .

[0075] In other embodiments, Figure 2 As shown, the stress release area 9 is located on the pressure sensitive membrane 12 and extends outward along the edge of the n-type silicon carbide pressure sensitive resistor 4 in a ring-shaped distribution, so as to optimize the local film stress of the n-type silicon carbide pressure sensitive resistor 4.

[0076] The stress release region 9 is formed by etching the silicon dioxide layer 7 and the silicon nitride layer 8, and is distributed in a ring structure at the edge area of ​​the pressure sensitive diaphragm 12 or around the n-type silicon carbide pressure sensitive resistor 4, which helps to relieve stress concentration between materials, improve the mechanical stability of the sensor, and reduce the interface stress caused by the difference in thermal expansion coefficient, thereby improving the long-term reliability and measurement accuracy of the device.

[0077] In some embodiments, the stress release zone 9 includes a plurality of concentric annular regions. If there are multiple concentric annular regions, the interval between two adjacent concentric annular regions is 10 μm-50 μm, and the width of each concentric annular region is 20 μm-200 μm.

[0078] It should be understood that several concentric annular areas can meet the design requirements of chips of different sizes and different range specifications, adjust the stress to the optimal value, and maximize the chip reliability.

[0079] The stress release zone 9 adopts a structure of multiple concentric annular areas, with the interval between adjacent annular areas being 10μm-50μm and the width of each annular area being 20μm-200μm. This can optimize the local film stress distribution of the n-type silicon carbide pressure sensitive resistor 4, alleviate stress concentration, improve the stress matching characteristics of the sensor, thereby reducing the measurement error caused by uneven stress, and at the same time enhance the structural reliability and long-term stability of the device.

[0080] In some embodiments, a through hole is formed on the silicon carbide sealing wafer 13 near the metal electrode layer 10 ; and a blind groove is formed on the silicon carbide sealing wafer 13 near the pressure sensitive diaphragm 12 .

[0081] The silicon carbide sealing wafer 13 is provided with a through hole near the metal electrode layer 10 to facilitate filling with conductive paste to realize electrical signal transmission. At the same time, a blind groove is opened near the pressure-sensitive diaphragm 12 to provide deformation space for the pressure-sensitive diaphragm 12. This structural design helps to improve the reliability of signal transmission, reduce the impact of packaging stress on sensitive components, and improve the sensor's detection accuracy of small deformations.

[0082] Some embodiments of the present application further provide a method for processing a low-stress, high-temperature pressure sensor chip, which is used to process the low-stress, high-temperature pressure sensor chip described in the above embodiments. The method includes:

[0083] An npn double-throw silicon carbide epitaxial wafer is selected as the silicon carbide epitaxial wafer to be processed.

[0084] Among them, the top layer of the silicon carbide epitaxial wafer is an n-type silicon carbide device layer 1; the middle layer of the silicon carbide epitaxial wafer is a p-type silicon carbide isolation layer 2; the bottom layer of the silicon carbide epitaxial wafer is an n-type silicon carbide substrate layer 3 to achieve electrical isolation. The thickness of the silicon carbide epitaxial wafer ranges from 300μm to 500μm.

[0085] The n-type silicon carbide device layer 1 is etched by an inductively coupled plasma etching process or a reactive ion etching process to form an n-type silicon carbide pressure sensitive resistor 4 , a sealing region 5 , and an isolation channel 6 .

[0086] Specifically, before etching the n-type silicon carbide device layer 1, a photoresist may be used as an etching mask on the top of the n-type silicon carbide device layer 1 to perform photolithography to etch the thickness of the n-type silicon carbide device layer 1 until the p-type silicon carbide isolation layer 2 is reached, and finally the photoresist is removed.

[0087] A silicon dioxide layer 7 and a silicon nitride layer 8 are prepared on the upper surface of the silicon carbide epitaxial wafer by chemical vapor deposition.

[0088] Specifically, the thickness of the silicon dioxide layer 7 is in the range of 50 nm to 200 nm; the thickness of the silicon nitride layer 8 is in the range of 50 nm to 200 nm.

[0089] In some embodiments, the preparation process parameters for the silicon dioxide layer 7 are: precursor gas: silane (5%) / nitrogen oxide = 1:4 (v / v), RF power: 300W (13.56MHz), deposition temperature: 300-350°C, and chamber pressure: 900mTorr; the preparation process parameters for the silicon nitride layer 8 are: precursor gas: silane / ammonia / helium = 1:5:20, RF power: 400W, deposition temperature: 200-400°C, and chamber pressure: 1.2Torr. The silicon dioxide / silicon nitride stack is prepared using a PECVD process, and in-situ H2 plasma treatment is used to eliminate dangling bonds, which can reduce the interface state density to 1×10 10 cm -2 eV -1 level, meeting the long-term reliability requirements in high temperature and high pressure environments.

[0090] The silicon nitride layer 8 and the silicon dioxide layer 7 are etched by using one or a combination of inductively coupled plasma etching, reactive ion etching, and wet etching to form a stress release region 9 .

[0091] Specifically, before etching the passivation layer, a photoresist is used as an etching mask on the top to perform photolithography, wherein the silicon nitride layer 8 is etched first, then the silicon dioxide layer 7 is etched, and the etching stops at the silicon carbide layer, and finally the photoresist is removed.

[0092] A metal electrode layer 10 is formed on the sealing area 5 by electron beam evaporation.

[0093] It should be understood that the pre-processed metal electrode layer 10 can be treated with a high-temperature annealing method to form an ohmic contact, thereby achieving a connection between the metal electrode layer 10 and the n-type silicon carbide pressure-sensitive resistor 4. Specifically, a lift-off process is used: first, negative photoresist is applied, exposed, and developed to complete the photoresist patterning. Next, the metal electrode layer 10 is deposited using electron beam evaporation. Then, a stripping solution is used to remove the photoresist, completing the metal electrode patterning. Finally, a high-temperature annealing process is performed to form an ohmic contact between the metal electrode layer 10 and the silicon carbide.

[0094] In some embodiments, the metal electrode layer 10 may be made of titanium / tungsten / gold / nickel, and the annealing condition is 900-1100° C. in a vacuum atmosphere or an inert gas such as nitrogen or argon.

[0095] The lift-off process can avoid the toxic and harmful effects of chemical wet corrosion and achieve precise transfer of metal patterns. Metals such as titanium / tungsten / gold / nickel have high melting points, high hardness and high corrosion resistance, and have good thermal and chemical stability; vacuum or inert gas annealing environment can avoid metal electrode contamination and oxidation.

[0096] The bottom of the n-type silicon carbide substrate layer 3 is etched using a deep silicon carbide etching process to form a pressure cavity 11 .

[0097] Specifically, the mask used for etching the silicon carbide is nickel. First, a nickel seed layer is prepared; secondly, a nickel layer is grown by electroplating, and the thickness can be 10~20μm; then the nickel layer is patterned; then silicon carbide is etched, and the etching gas is a mixed gas of sulfur hexafluoride, oxygen, argon, hydrogen bromide, etc.; finally, the nickel layer is removed.

[0098] In some embodiments, the process gas of the deep silicon carbide etching process is one or more of octafluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen and argon, and the etching mask of the deep silicon carbide etching process is metal nickel.

[0099] The deep silicon carbide etching process uses one or more of octafluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen and argon as process gases, and uses metal nickel as an etching mask. This combination can optimize the etching selectivity and etching rate of the silicon carbide material, improve the verticality and surface roughness of the etched sidewall, thereby reducing device damage during the etching process, improving the structural accuracy and dimensional consistency of the pressure chamber 11, and helping to enhance the performance stability of the sensor.

[0100] The silicon carbide sealing wafer 13 is sealed on top of the silicon carbide epitaxial wafer.

[0101] The above-mentioned processing method selects an npn double-polished silicon carbide epitaxial wafer as a substrate, adopts inductively coupled plasma etching or reactive ion etching process to form an n-type silicon carbide pressure sensitive resistor 4 and an isolation channel 6, combines chemical vapor deposition to prepare silicon dioxide and silicon nitride layers 8, then forms a stress release area 9 through an etching process, and uses electron beam evaporation to produce a metal electrode layer 10. Finally, a pressure cavity 11 is formed by deep silicon carbide etching and bonded to a silicon carbide sealing wafer 13. This helps to reduce the impact of thermal stress during the processing, improve stress matching between device layers, and improve the stability of the sensor in a high-temperature environment. At the same time, it ensures a reliable connection between the pressure sensitive resistor and the electrode, thereby enhancing the overall performance of the chip.

[0102] In some embodiments, the etching gas of the inductively coupled plasma etching process and the reactive ion etching process is at least one of tetrafluoromethane, sulfur hexafluoride, and trifluoromethane; the auxiliary gas of the inductively coupled plasma etching process and the reactive ion etching process is at least one of oxygen, argon, and nitrogen, wherein the volume proportion of tetrafluoromethane is 60%-80%.

[0103] It should be understood that the etching power of the inductively coupled plasma etching process and the reactive ion etching process may be selected from 1200-1500 W, the RF bias voltage may be selected from 150-300 W, and the working pressure may be selected from 5-20 mTorr.

[0104] Leveraging the high chemical activity potential of the tetrafluoromethane / sulfur hexafluoride / trifluoromethane ternary gas system, an advanced etching process with strong anisotropy can be constructed. By regulating the plasma chemical reaction and establishing a gas component concentration gradient model, atomic-level precision etching control of submicron feature sizes can be achieved. This hybrid process, through the synergistic mechanism of free radical transport path optimization and ion bombardment energy modulation, not only achieves the ideal steep sidewall morphology of 88°±1°, but also ensures process stability with batch-to-batch reproducibility of ≤1.5nm.

[0105] In some embodiments, the wet etching process uses a buffered oxide etchant, which is prepared by mixing 40% ammonium fluoride solution and 49% hydrofluoric acid solution in a volume ratio of 6:1.

[0106] The wet etching process uses a buffered oxide etchant prepared by mixing 40% ammonium fluoride solution and 49% hydrofluoric acid solution in a volume ratio of 6:1. This can adjust the etching rate and reaction activity, improve the stability of the etching process, reduce the risk of over-etching due to excessive hydrofluoric acid concentration, and help obtain a more uniform etched surface morphology, thereby improving the controllability and repeatability of the etching process.

[0107] It can be seen from the above technical solution that the embodiment of the present application provides a low-stress, high-temperature pressure sensor chip and a processing method, the chip comprising: a silicon carbide epitaxial wafer, a passivation layer, a metal electrode layer 10 and a silicon carbide sealing wafer 13; the silicon carbide epitaxial wafer comprises an n-type silicon carbide device layer 1, a p-type silicon carbide isolation layer 2 and an n-type silicon carbide substrate layer 3, the n-type silicon carbide device layer 1, the p-type silicon carbide isolation layer 2 and the n-type silicon carbide substrate layer 3 are sequentially connected from top to bottom; the n-type silicon carbide device layer 1 is etched to form an n-type silicon carbide pressure sensitive resistor 4, a sealing area 5 and an isolation channel 6; wherein the n-type silicon carbide pressure sensitive resistor 4 is isolated from the sealing area 5 by the isolation channel 6; the passivation layer comprises a silicon dioxide layer 7 and a silicon nitride layer 8, the silicon dioxide layer 7 is located at the n The upper surface of the n-type silicon carbide pressure sensitive resistor 4 and the isolation channel 6, the silicon nitride layer 8 is located on the upper surface of the silicon dioxide layer 7, and a stress release area 9 is opened on the silicon dioxide layer 7 and the silicon nitride layer 8; the bottom of the n-type silicon carbide substrate layer 3 is etched to form a pressure cavity 11, and the p-type silicon carbide isolation layer 2 and the n-type silicon carbide substrate layer 3 in the area directly above the pressure cavity 11 constitute a pressure sensitive diaphragm 12, and the stress release area 9 is arranged on the upper surface of the pressure sensitive diaphragm 12; the metal electrode layer 10 is arranged on the sealing area 5, and the metal electrode layer 10 is electrically connected to the n-type silicon carbide pressure sensitive resistor 4; the silicon carbide sealing wafer 13 is bonded to the top of the silicon carbide epitaxial wafer to solve the problem of low reliability of the low-stress and high-temperature pressure sensor chip.

[0108] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the overall concept of this application and do not constitute a limitation on the scope of protection of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without expending creative work shall fall within the scope of protection of this application.

Claims

1. A low-stress, high-temperature pressure sensor chip, characterized in that: include: Silicon carbide epitaxial wafer, passivation layer, metal electrode layer (10) and silicon carbide sealing wafer (13); The silicon carbide epitaxial wafer comprises an n-type silicon carbide device layer (1), a p-type silicon carbide isolation layer (2) and an n-type silicon carbide substrate layer (3), wherein the n-type silicon carbide device layer (1), the p-type silicon carbide isolation layer (2) and the n-type silicon carbide substrate layer (3) are connected in sequence from top to bottom; The n-type silicon carbide device layer (1) is etched to form an n-type silicon carbide pressure sensitive resistor (4), a sealing area (5) and an isolation channel (6); wherein the n-type silicon carbide pressure sensitive resistor (4) is isolated from the sealing area (5) by the isolation channel (6); The passivation layer comprises a silicon dioxide layer (7) and a silicon nitride layer (8), the silicon dioxide layer (7) is located on the upper surface of the n-type silicon carbide pressure sensitive resistor (4) and the isolation channel (6), the silicon nitride layer (8) is located on the upper surface of the silicon dioxide layer (7), and a stress release area (9) is provided on the silicon dioxide layer (7) and the silicon nitride layer (8); the bottom of the n-type silicon carbide substrate layer (3) is etched to form a pressure cavity (11), the p-type silicon carbide isolation layer (2) and the n-type silicon carbide substrate layer (3) in the area directly above the pressure cavity (11) constitute a pressure sensitive diaphragm (12), and the stress release area (9) is provided on the upper surface of the pressure sensitive diaphragm (12); The metal electrode layer (10) is arranged on the sealing area (5), and the metal electrode layer (10) is electrically connected to the n-type silicon carbide pressure sensitive resistor (4); The silicon carbide sealing wafer (13) is bonded to the top of the silicon carbide epitaxial wafer.

2. The low stress and high temperature pressure sensor chip according to claim 1, characterized in that: The silicon carbide epitaxial wafer is a double-polished wafer, and the thickness of the silicon carbide epitaxial wafer is 300 μm-500 μm; the thickness of the n-type silicon carbide device layer (1) is 200 nm-2 μm, and the doping concentration of the n-type silicon carbide device layer (1) is 1E19 cm -3 ~3E20cm -3 The thickness of the p-type silicon carbide isolation layer (2) is 2 μm to 10 μm, and the doping concentration of the p-type silicon carbide isolation layer (2) is 3E15 cm -3 ~3E18cm -3 The thickness of the silicon dioxide layer (7) is 50 nm to 200 nm; the thickness of the silicon nitride layer (8) is 50 nm to 200 nm; the thickness of the metal electrode layer (10) is 500 nm to 1 μm; and the thickness of the pressure sensitive membrane (12) is 50 μm to 200 μm.

3. The low stress and high temperature pressure sensor chip according to claim 1, characterized in that: The number of the n-type silicon carbide pressure sensitive resistors (4) is four, and the four n-type silicon carbide pressure sensitive resistors (4) are distributed along the four sides of the pressure sensitive diaphragm (12). The four n-type silicon carbide pressure sensitive resistors (4) are isolated from each other by the isolation channel (6) and form a closed bridge Wheatstone bridge.

4. The low stress and high temperature pressure sensor chip according to claim 1, characterized in that: The stress release region (9) is formed by etching the silicon dioxide layer (7) and the silicon nitride layer (8), and the stress release region (9) is distributed in an annular shape at the edge of the pressure sensitive diaphragm (12) or around the n-type silicon carbide pressure sensitive resistor (4).

5. The low stress and high temperature pressure sensor chip according to claim 4, characterized in that: The stress release zone (9) includes a plurality of concentric annular regions. If there are multiple concentric annular regions, the interval between two adjacent concentric annular regions is 10 μm-50 μm, and the width of each concentric annular region is 20 μm-200 μm.

6. The low stress and high temperature pressure sensor chip according to claim 1, characterized in that: The silicon carbide sealing wafer (13) is provided with a through hole at a position close to the metal electrode layer (10); and the silicon carbide sealing wafer (13) is provided with a blind groove at a position close to the pressure sensitive diaphragm (12).

7. A low-stress, high-temperature pressure sensor chip processing method, characterized in that: The method for processing the low-stress, high-temperature pressure sensor chip according to any one of claims 1 to 6 comprises: An npn-type double-throw silicon carbide epitaxial wafer is selected as the silicon carbide epitaxial wafer to be processed; wherein the top layer of the silicon carbide epitaxial wafer is an n-type silicon carbide device layer (1); the middle layer of the silicon carbide epitaxial wafer is a p-type silicon carbide isolation layer (2); and the bottom layer of the silicon carbide epitaxial wafer is an n-type silicon carbide substrate layer (3); Etching the n-type silicon carbide device layer (1) using an inductively coupled plasma etching process or a reactive ion etching process to form an n-type silicon carbide pressure sensitive resistor (4), a sealing region (5), and an isolation channel (6); A silicon dioxide layer (7) and a silicon nitride layer (8) are prepared on the upper surface of the silicon carbide epitaxial wafer by chemical vapor deposition; Etching the silicon nitride layer (8) and the silicon dioxide layer (7) using one or a combination of inductively coupled plasma etching, reactive ion etching, and wet etching to form a stress release region (9); forming a metal electrode layer (10) on the sealing area (5) by electron beam evaporation; Etching the bottom of the n-type silicon carbide substrate layer (3) using a deep silicon carbide etching process to form a pressure cavity (11); A silicon carbide sealing wafer (13) is sealed on top of the silicon carbide epitaxial wafer.

8. The low-stress, high-temperature pressure sensor chip processing method according to claim 7, characterized in that: The etching gas of the inductively coupled plasma etching process and the reactive ion etching process is at least one of tetrafluoromethane, sulfur hexafluoride, and trifluoromethane; the auxiliary gas of the inductively coupled plasma etching process and the reactive ion etching process is at least one of oxygen, argon, and nitrogen, wherein the volume proportion of tetrafluoromethane is 60%-80%.

9. The low-stress, high-temperature pressure sensor chip processing method according to claim 7, characterized in that: The wet etching process uses a buffered oxide etching solution, which is prepared by mixing 40% ammonium fluoride solution and 49% hydrofluoric acid solution in a volume ratio of 6:

1.

10. The low-stress, high-temperature pressure sensor chip processing method according to claim 7, characterized in that: The process gas of the deep silicon carbide etching process is one or more of octafluorocyclobutane, tetrafluoromethane, sulfur hexafluoride, oxygen and argon, and the etching mask of the deep silicon carbide etching process is metal nickel.

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