Mask and correction method thereof
By adding auxiliary patterns near the main pattern of the mask, increasing the actual line width and reducing the effective line width, the problem that auxiliary pattern design in the prior art is difficult to take into account both process window and yield, and high resolution and high yield semiconductor device production is achieved.
Patent Information
- Application Number
- CN202411845654.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-13
- Publication Date
- 2025-07-29
AI Technical Summary
The existing sub-resolution auxiliary pattern design methods are difficult to take into account the process window and yield requirements of semiconductor devices. Too large line width of the auxiliary pattern will lead to excess patterns on the wafer, and too small line width will reduce the resolution of the main pattern.
By adding an auxiliary pattern near the main pattern of the mask, its actual line width is increased and effective line width is reduced, the auxiliary pattern includes the outer contour and its surrounding openings to ensure correct exposure and improve the optical proximity effect compensation effect.
It improves the edge resolution and fidelity of the main pattern, reduces the occurrence of product defects, improves the yield of semiconductor devices, and speeds up the convergence of the mask correction algorithm, saving design time and verification costs.
Smart Images
Figure CN120386134A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor manufacturing, and in particular to a mask and a correction method thereof. Background Art
[0002] In the semiconductor manufacturing process, photolithography and etching are both key patterning steps. Photolithography transfers the mask pattern to a resist layer to form a resist pattern. This resist pattern is then transferred to the wafer via ion implantation or etching to form the semiconductor device structure. As semiconductor device process nodes advance, feature sizes continue to shrink, and light interference has an increasingly significant impact on the accuracy of photolithographic patterns.
[0003] As a resolution enhancement technology (RET), sub-resolution assist patterns (SRAFs) are placed on the reticle for optical proximity compensation (OPC), which can at least partially offset the effects of light interference. Ideally, since the line width of the SRAF pattern is smaller than the resolution limit of the lithography, the SRAF pattern is not imaged in the resist layer. The SRAF pattern imparts dense pattern characteristics to both isolated and sparse patterns within the primary pattern, thereby improving light intensity distribution and enhancing the resolution of the primary pattern.
[0004] As the feature size of semiconductor devices continues to decrease, the design of sub-resolution auxiliary patterns becomes increasingly difficult. If the line width of the auxiliary pattern is too large relative to the main pattern, redundant patterns will be generated on the wafer, causing defects on the wafer and thus affecting the yield. If the line width of the auxiliary pattern is too small relative to the main pattern, the resolution of the main pattern will be reduced, which will in turn affect the process window of the semiconductor device. Existing sub-resolution auxiliary pattern design methods modify the auxiliary pattern by changing the number of lines and line width, which makes it difficult to balance the process window and yield requirements of semiconductor devices. Summary of the Invention
[0005] In view of the above problems, the purpose of this application is to provide a mask and a correction method thereof, wherein the actual line width of the auxiliary pattern is increased to maintain the resolution of the main pattern, and the effective line width of the auxiliary pattern is reduced to avoid exposure errors, so as to take into account the process window and yield requirements of the semiconductor device.
[0006] According to one aspect of the present invention, a mask is provided, comprising: a substrate; a main pattern and an auxiliary pattern located on the substrate, wherein the line width of the auxiliary pattern is smaller than the line width of the main pattern, wherein the auxiliary pattern includes an outer contour and an opening surrounding the outer contour, so that the effective line width of the auxiliary pattern is smaller than the actual line width.
[0007] Optionally, the auxiliary pattern is substantially linear, and the opening is substantially rectangular.
[0008] Optionally, the auxiliary pattern is located between adjacent main patterns of the plurality of main patterns.
[0009] Optionally, the main patterns are located between the auxiliary patterns.
[0010] Optionally, the auxiliary pattern is a combined shape of a plurality of lines, and the opening is a combined shape of a plurality of rectangles.
[0011] Optionally, the auxiliary pattern at least partially surrounds the corners of the main pattern.
[0012] Optionally, the main pattern and the auxiliary pattern of the mask are the light-shielding regions of the mask, and the opening of the auxiliary pattern is the light-transmitting region of the mask.
[0013] Optionally, the main pattern and the auxiliary pattern of the mask are the light-transmitting regions of the mask, and the opening of the auxiliary pattern is the light-shielding region of the mask.
[0014] Optionally, the actual line width of the auxiliary pattern is greater than the maximum line width of the sub-resolution auxiliary pattern.
[0015] According to another aspect of the present invention, there is provided a method for correcting a mask, including: obtaining an initial pattern of the mask, the initial pattern including a main pattern corresponding to a structural pattern of a semiconductor device; adding an auxiliary pattern near the main pattern, the auxiliary pattern including solid lines; and correcting the auxiliary pattern according to the optical proximity effect verification result of the mask to obtain a corrected pattern of the mask, wherein the auxiliary pattern includes an outer contour and an opening surrounded by the outer contour, such that the actual line width of the auxiliary pattern is greater than the line width of the sub-resolution auxiliary pattern, and the effective line width of the auxiliary pattern is less than the line width of the sub-resolution auxiliary pattern.
[0016] Optionally, the optical proximity effect verification includes performing simulation calculations to obtain a resist pattern formed by the mask in lithography, or performing a lithography test to obtain a resist pattern formed by the mask in lithography.
[0017] Optionally, in the case where the resist pattern has an exposure error, the auxiliary pattern is corrected multiple times until the resist pattern is correctly exposed.
[0018] Optionally, the opening is added in the first correction step of the multiple corrections, and at least one of the number of lines, the actual line width, and the opening width of the auxiliary pattern is changed in the subsequent correction steps of the first correction step.
[0019] Optionally, the actual line width of the auxiliary pattern is greater than the maximum line width of the sub-resolution auxiliary pattern.
[0020] A photomask according to an embodiment of the present invention adds auxiliary patterns near the main pattern of the photomask to change the light intensity distribution to compensate for the optical proximity effect, thereby improving the edge resolution and fidelity of the main pattern.
[0021] The auxiliary patterns in the photomask include openings surrounded by an outer contour, such that the effective line width of the auxiliary patterns is smaller than the actual line width. On the one hand, in the photomask, by reducing the effective line width of the auxiliary patterns, the size requirements of sub-resolution auxiliary patterns can be met, thereby ensuring the correct exposure of the auxiliary patterns, and only forming a resist pattern corresponding to the main pattern of the photomask in the resist layer, without forming any redundant resist patterns corresponding to the auxiliary patterns of the photomask. On the other hand, in the photomask, by maintaining or even expanding the actual line width of the auxiliary patterns, the effect of compensating the optical proximity effect of the nearby main patterns by the auxiliary patterns can be improved while minimizing the impact on the process window, enhancing the contrast of the main pattern, and thus improving the edge resolution and fidelity of the main pattern.
[0022] After lithography and development, the main pattern of the photomask is transferred to the resist layer to form a resist pattern with high contrast and no redundant patterns. In subsequent etching steps, the resist pattern can also be correctly transferred to the structure layer on the wafer to form a correct structure pattern. Therefore, the pattern design of the photomask can reduce the generation of product defects, thereby improving the product yield.
[0023] In a preferred embodiment, auxiliary patterns are formed in the photomask at least partially surrounding the corners of the main pattern. The auxiliary patterns include openings surrounded by an outer contour, such that the effective line width of the auxiliary patterns is smaller than the actual line width, which can not only expand the process window but also improve the yield of semiconductor devices. Further, at the corner positions of the main pattern, the auxiliary patterns can also improve the compensation effect of the optical proximity effect to obtain a substantially right-angled structure pattern. Therefore, the photomask can ensure that the corner patterns of semiconductor devices are consistent with the designed patterns, further improving the fidelity of the main pattern.
[0024] A photomask correction method according to an embodiment of the present invention, compared with existing photomask correction methods, uses the opening width of the auxiliary patterns as a new correction parameter. Therefore, the convergence of the photomask correction algorithm can be accelerated to save the design time of the photomask and the cost of proximity effect verification. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Through the following description of the embodiments of the present application with reference to the accompanying drawings, the above and other objects, features, and advantages of the present application will become clearer. In the drawings:
[0026] Figure 1 shows a schematic principle diagram of a lithographic projection system;
[0027] Figure 2a andFigure 2b Schematic diagrams respectively showing different positional relationships between a main pattern and an auxiliary pattern in a mask according to the prior art;
[0028] Figure 3a and Figure 3b Resist patterns respectively showing a mask according to the prior art in cases of correct exposure and incorrect exposure;
[0029] Figure 4 Schematic diagram showing a mask according to the first embodiment of the present invention;
[0030] Figure 5 Schematic diagram showing a mask according to the second embodiment of the present invention;
[0031] Figure 6 Flowchart showing a method for correcting a mask according to the third embodiment of the present invention. Detailed description of specific embodiments
[0032] The present application will be described in more detail below with reference to the accompanying drawings. In the respective drawings, the same elements are denoted by like reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.
[0033] The term "mask" as used herein refers to a template for transferring a circuit pattern onto a resist layer in a lithography process. The mask contains the design pattern of the actual circuit or semiconductor device on the wafer, and a microscopic actual pattern is generated by exposing it to the resist layer on the silicon wafer. The design pattern on the mask is designed complexly to ensure that an accurate actual pattern is formed on the wafer after exposure and development.
[0034] The term "Optical Proximity Correction" (OPC for short) is a technique for correcting the optical proximity effect by adjusting the mask pattern. The optical proximity effect refers to the deviation between the actual pattern and the design pattern caused during the exposure process due to the interference and diffraction of light. The OPC technique compensates for the exposure deviation by finely adjusting the geometry of the mask pattern or adding Sub-Resolution Assist Features (SRAF) to improve the pattern accuracy, so that the actual pattern finally formed on the wafer meets the structural requirements.
[0035] The term "Sub-Resolution Assist Feature" (abbreviated as SRAF) refers to a small pattern added next to the main pattern on a photomask. Its size is smaller than the lithography resolution limit and thus will not be imaged in the resist layer. The main function of SRAF is to compensate for the optical proximity effect by changing the light intensity distribution, thereby improving the edge resolution and fidelity of the main pattern. Sub-resolution assist patterns are usually in the shape of long strips or rectangles and are arranged around the main pattern to help maintain a relatively uniform light intensity distribution, enabling isolated or sparse patterns to have an imaging effect similar to that of dense patterns.
[0036] This application can be presented in various forms, and some examples will be described below.
[0037] Figure 1 Fig. shows a schematic diagram of the principle of a lithographic projection system. The lithographic projection system 1000 is used to image the pattern of the photomask 10 in the resist layer PR.
[0038] The lithographic projection system 1000 includes a radiation source 1001, an illumination system 1002, a photomask 10, and an objective lens system 1003.
[0039] The radiation source 1001 is the core part of the lithographic projection system 1000 and generates a radiation beam for exposure. This radiation can be deep ultraviolet (DUV), extreme ultraviolet (EUV), or other electromagnetic radiation suitable for the lithography process. The radiation source 1001 may include lasers, mercury lamps, or other types of light sources that can provide the required wavelength and power to achieve high-precision lithography.
[0040] The illumination system 1002 receives the beam from the radiation source 1001 and shapes and adjusts it to form a specific light intensity distribution. This system may include components such as a beam shaper, a beam homogenizer, and a beam controller. The illumination system 1002 ensures that the beam has a uniform or predetermined intensity distribution before irradiating the photomask 10.
[0041] The photomask 10 contains the pattern to be transferred onto the wafer 110. The photomask 10 can be used for transmissive lithography or reflective lithography. In transmissive lithography, a part of the area of the photomask 10 is a light-transmitting area, which is used to form the corresponding pattern or complementary pattern of the semiconductor device structure. In reflective lithography, a part of the area of the photomask 10 is used to reflect the beam, which is used to form the corresponding pattern or complementary pattern of the semiconductor device structure. The pattern on the photomask 10 determines the exposure pattern of the resist layer PR on the wafer 110.
[0042] The objective lens system 1003 is used to reduce and accurately project the pattern on the reticle 10 onto the resist layer PR on the wafer 110. The objective lens system 1003 usually consists of multiple lenses, and their combined effect is to correct various optical aberrations to ensure the accurate transfer of the pattern. The design and adjustment of the objective lens system 1003 are crucial for achieving high-resolution and high-contrast lithography patterns.
[0043] The surface of the wafer 110 is coated with a resist layer PR. The resist layer PR is a photosensitive material, and its chemical properties change when exposed to light of a specific wavelength. In the lithography step, the lithography projection system 1000 projects the pattern on the reticle 10 onto the resist layer PR, thereby forming a latent image corresponding to the reticle pattern in the resist layer.
[0044] After the above lithography step, development is carried out to convert the latent image in the resist layer into an actual physical pattern. In the development step, a developer is used to dissolve either the exposed area or the unexposed area of the resist layer. Depending on the reaction mode of the resist layer PR1, it can be divided into positive resists and negative resists. The exposed area of the positive resist is removed during development to form an opening area, and the exposed area of the negative resist is retained during development to form a blocking area. It can be understood that in the case of using a negative resist, the connection hole pattern of the reticle is the complementary pattern of using a positive resist.
[0045] Figure 2a and Figure 2b respectively show schematic diagrams of different positional relationships between the main pattern and the auxiliary pattern in the reticle according to the prior art.
[0046] The reticles 10 and 20 respectively include a substrate 101, and a main pattern 11 and an auxiliary pattern 12 located on the substrate 101. Among them, the main pattern 11 and the auxiliary pattern 12 constitute the pattern layer of the reticle. The light transmittance or reflectivity of the main pattern 11 and the auxiliary pattern 12 is the same. The number of auxiliary patterns 12 is at least one.
[0047] In the reticles 10 and 20, the auxiliary pattern 12 is added near the main pattern 11. Refer to Figure 2a , a single main pattern 11 can be located between multiple auxiliary patterns 12. Refer to Figure 2b , at least one auxiliary pattern 12 can be located between multiple main patterns 12. The auxiliary pattern 12 is, for example, in the shape of a solid line.
[0048] As the feature size of semiconductor devices is further reduced, the optical resolution of the lithography system becomes smaller and smaller. The line width of the main pattern 11 and the spacing from adjacent main patterns are getting smaller and smaller. The auxiliary pattern 12 must be smaller than the optical resolution of the lithography system to meet the size requirements of the sub-resolution auxiliary pattern.
[0049] Refer toFigure 3a For an auxiliary pattern 12 of a suitable size, with appropriate lithography process parameters and correct exposure, only a resist pattern 121 corresponding to the main pattern 11 of the mask 10 is formed in the resist layer 120, and no resist pattern corresponding to the auxiliary pattern 12 of the mask 10 is formed. Refer to Figure 3b , whether it is the size deviation of the auxiliary pattern 12 or the lithography process parameter deviation, in the case of incorrect exposure, it is possible to simultaneously form a resist pattern 121 corresponding to the main pattern 11 of the mask 10 and a resist pattern 122 corresponding to the auxiliary pattern 12 of the mask 10 in the resist layer 120.
[0050] In the above existing mask correction method, an auxiliary pattern 12 is added near the main pattern 11 of the mask to change the light intensity distribution to compensate for the optical proximity effect, thereby improving the edge resolution and fidelity of the main pattern 11. However, there is also a risk of incorrect exposure for the auxiliary pattern 12 in the mask 10, forming an incorrect resist pattern in the resist layer. In the subsequent etching step, the incorrect resist pattern is transferred to the structural layer on the wafer, and an incorrect structural pattern will also be formed, forming redundant doping regions, wirings, and / or contact holes on the wafer, thereby generating defective structures in the semiconductor device and reducing the yield of the semiconductor device.
[0051] Although in the above mask correction method, when designing the mask, the size of the auxiliary pattern 12 can be further intentionally reduced to meet the size requirements of the sub-resolution auxiliary pattern, however, using an auxiliary pattern 12 with too small a size will weaken the compensation effect of the optical proximity effect, and thus will have a negative impact on the resolution and process window of the main pattern 11.
[0052] Figure 4 A schematic diagram of a mask according to a first embodiment of the present invention is shown.
[0053] The mask 30 includes a substrate 101, and a main pattern 11 and an auxiliary pattern 31 located on the substrate 101. Among them, the main pattern 11 and the auxiliary pattern 31 constitute the pattern layer of the mask.
[0054] The substrate 101 is composed of, for example, quartz glass. Quartz glass has excellent optical transparency and can effectively transmit the short-wavelength light beam of the light source, especially in the deep ultraviolet (DUV) band and extreme ultraviolet (EUV) band, to ensure high pattern resolution during the lithography process. In addition, quartz glass also has high thermal stability and can maintain the stability of shape and size during the lithography process. In reflective lithography, the pattern layers of the mask templates 10 and 20 are composed of, for example, chromium or chromium oxide. Chromium has good light impermeability and can be used to form a light-shielding area to achieve high-contrast imaging of the pattern. In reflective lithography, the pattern layers of the mask templates 10 and 20 are composed of a multilayer reflective film and an absorption layer, which are used to form a reflective area and an absorption area respectively. Through the coating and etching processes, the mask pattern of the mask template can be formed on the quartz glass substrate.
[0055] In the mask template 30, an auxiliary pattern 31 is added near the side of the main pattern 11. The main pattern 11 and the auxiliary pattern 31 have the same light transmittance or reflectivity, and the number of the auxiliary patterns 31 is at least one.
[0056] The mask template 30 can be used for transmissive lithography or reflective lithography. In transmissive lithography, the main pattern 11 and the auxiliary pattern 31 of the mask template 30 are light-transmitting areas, or the main pattern 11 and the auxiliary pattern 31 of the mask template 30 are light-shielding areas, which are used to form the corresponding pattern or complementary pattern of the semiconductor device structure. In reflective lithography, the main pattern 11 and the auxiliary pattern 31 of the mask template 30 are reflective areas, and the main pattern 11 and the auxiliary pattern 31 of the mask template 30 are absorption areas, which are used to form the corresponding pattern or complementary pattern of the semiconductor device structure. The pattern on the mask template 30 determines the exposure pattern of the resist layer PR on the wafer 130. After lithography and development, the resist layer PR forms a resist pattern, and the resist layer PR is used as a barrier layer, which is the same as or complementary to the structure pattern of the semiconductor device.
[0057] See Figure 4 , the line width of the auxiliary pattern 31 is smaller than that of the main pattern 11. Different from the existing mask template, in the mask template 30 of the present invention, the auxiliary pattern 31 includes an outer contour and an opening 32 surrounded by it. In this embodiment, the auxiliary pattern 31 is substantially linear, and the opening 32 in the auxiliary pattern 31 is substantially rectangular.
[0058] The actual line width of the auxiliary pattern 31 in the mask 30 is the distance between the two innermost and outermost side edges adjacent to the main pattern, and the effective line width is equal to the actual line width minus the opening width. Therefore, the effective line width of the auxiliary pattern 31 is smaller than the actual line width. Optionally, the actual line width of the auxiliary pattern 31 can even be greater than the maximum line width of the sub-resolution auxiliary pattern to maximize the process window. At this time, the effective line width of the auxiliary pattern 31 is smaller than the maximum line width of the sub-resolution auxiliary pattern to ensure correct exposure.
[0059] For the mask according to the first embodiment of the present invention, an auxiliary pattern 31 is added near the main pattern 11 of the mask to change the light intensity distribution to compensate for the optical proximity effect, thereby improving the edge resolution and fidelity of the main pattern 11.
[0060] The auxiliary pattern 31 in the mask 30 includes an opening surrounded by an outer contour, such that the effective line width of the auxiliary pattern 31 is smaller than the actual line width. On the one hand, in the mask 30, by reducing the effective line width of the auxiliary pattern 31, the size requirement of the sub-resolution auxiliary pattern can be met, thereby ensuring the correct exposure of the auxiliary pattern 12. Only the resist pattern corresponding to the main pattern 11 of the mask 30 is formed in the resist layer, and no redundant resist pattern corresponding to the auxiliary pattern 31 of the mask 30 is formed. On the other hand, in the mask 30, by maintaining or even expanding the actual line width of the auxiliary pattern 31, the effect of the auxiliary pattern 31 compensating for the optical proximity effect on the nearby main pattern 11 can be improved, increasing the contrast of the main pattern 11, thereby improving the edge resolution and fidelity of the main pattern.
[0061] After lithography and development, the main pattern of the mask 30 is transferred to the resist layer to form a resist pattern with high contrast and no redundant patterns. In the subsequent etching step, the resist pattern can also be correctly transferred to the structure layer on the wafer to form a correct structure pattern. Therefore, the pattern design of the mask 30 can reduce the generation of product defects, thereby improving the product yield.
[0062] Figure 5 Schematic diagram showing a mask according to the second embodiment of the present invention.
[0063] The mask 40 includes a substrate 101, and a main pattern 11 and an auxiliary pattern 41 located on the substrate 101. Among them, the main pattern 11 and the auxiliary pattern 41 constitute the pattern layer of the mask.
[0064] In the mask 40, an auxiliary pattern 41 is added near the corners of the main pattern 11. The light transmittance or reflectivity of the main pattern 11 and the auxiliary pattern 41 is the same, and the number of the auxiliary patterns 41 is at least one.
[0065] See Figure 5, the line width of the auxiliary pattern 41 is smaller than that of the main pattern 11. Different from the existing photomasks, in the photomask 40 of the present invention, the auxiliary pattern 41 includes an outer contour and an opening 42 surrounded thereby. In this embodiment, the auxiliary pattern 41 is a combined shape of a plurality of lines, and the opening 42 in the auxiliary pattern 41 is a combined shape of a plurality of rectangles. For example, the main pattern 11 of the photomask 40 is substantially in a line shape, and both the auxiliary pattern 41 and its opening 42 are in an L shape. By using the L-shaped auxiliary pattern 41, a resist pattern corresponding to the main pattern 11 of the photomask 40 can be obtained after photolithography and development.
[0066] The actual line width of the auxiliary pattern 41 in the photomask 40 is the distance between the innermost and outermost two side edges adjacent to the main pattern, and the effective line width is equal to the actual line width minus the opening width. Therefore, the effective line width of the auxiliary pattern 41 is smaller than the actual line width. Optionally, the actual line width of the auxiliary pattern 41 can even be greater than the maximum line width of the sub-resolution auxiliary pattern to maximize the process window. At this time, the effective line width of the auxiliary pattern 41 is smaller than the maximum line width of the sub-resolution auxiliary pattern to ensure correct exposure.
[0067] According to the photomask of the second embodiment of the present invention, the auxiliary pattern 41 in the photomask 40 includes an opening surrounded by an outer contour, such that the effective line width of the auxiliary pattern 41 is smaller than the actual line width, which can not only expand the process window, but also improve the yield of semiconductor devices. Further, at the corner positions of the main pattern 11, the auxiliary pattern 41 can also improve the compensation effect of the optical proximity effect to obtain a substantially right-angled structural pattern. Therefore, the photomask 40 can ensure that the corner pattern of the semiconductor device is consistent with the design pattern, further improving the fidelity of the main pattern.
[0068] Figure 6 A flowchart showing a method for correcting a photomask according to a third embodiment of the present invention is shown. This method for correcting a photomask is used, for example, to obtain a photomask 30 as shown in Figure 4 and a photomask 40 as shown in Figure 5 .
[0069] The method for correcting this photomask includes steps S01 to S05.
[0070] In step S01, an initial pattern of the photomask is obtained, and the initial pattern includes a main pattern corresponding to the structural pattern of the semiconductor device.
[0071] The circuit in the wafer includes a plurality of semiconductor devices. Taking a metal-oxide-semiconductor field-effect transistor (abbreviated as MOSFET) as an example, different masks are used to form the structural patterns of different layers of the MOSFET respectively. For example, different masks are used to form the source region and drain region, gate, contact hole, and wiring layer of the MOSFET respectively.
[0072] Taking the mask used to form the source and drain regions of a MOSFET as an example, through lithography and development, the target pattern of the mask is transferred into the resist layer. Then, through ion implantation, the source and drain regions are formed on the wafer via the openings in the resist layer, thereby transferring the resist pattern into the wafer. The initial pattern of this mask corresponds to the structural pattern of the source and drain regions of the MOSFET.
[0073] In step S02, an initial auxiliary pattern is added near the initial pattern. The initial auxiliary pattern includes a single solid line or a combined shape of multiple solid lines.
[0074] The line width of the initial auxiliary pattern is, for example, less than the optical resolution of the lithography system to meet the size requirements of the sub-resolution auxiliary pattern. Different from the existing mask correction methods, in the mask correction method according to the embodiments of the present invention, the line width of the initial auxiliary pattern can be close to the maximum line width of the sub-resolution auxiliary pattern to improve the effect of the optical proximity correction of the auxiliary pattern on the nearby main pattern, thereby expanding the process window.
[0075] In step S03, optical proximity effect is performed on the mask to determine whether there is an exposure error.
[0076] This optical proximity effect verification includes performing simulation calculations to obtain the resist pattern formed by the mask in lithography, or directly performing a lithography test to obtain the resist pattern formed by the mask in lithography.
[0077] When the size of the initial auxiliary pattern is designed appropriately, only the resist pattern corresponding to the main pattern of the mask is formed in the resist layer, and no redundant resist pattern corresponding to the auxiliary pattern of the mask is formed. When the size of the initial auxiliary pattern is designed wrongly, not only the resist pattern corresponding to the main pattern of the mask is formed in the resist layer, but also redundant resist patterns corresponding to the auxiliary pattern of the mask are formed.
[0078] If there are redundant resist patterns in the resist layer, it is determined that there is an exposure error in the auxiliary pattern of the mask, and step S04 is executed to correct the auxiliary pattern.
[0079] If there are no redundant resist patterns in the resist layer, it is determined that the auxiliary pattern in the mask is exposed correctly, and step S05 is executed to use the corrected pattern of the mask as the target pattern.
[0080] In the above step S04, the auxiliary pattern is corrected to obtain the corrected pattern of the mask. By repeating steps S03 and S04, the auxiliary pattern in the mask can be corrected multiple times.
[0081] In the first correction step, openings are added to the auxiliary pattern such that the auxiliary pattern includes an outer contour and the openings surrounded thereby, so that the effective line width of the auxiliary pattern is less than the actual line width.
[0082] Preferably, in the first correction step, the actual line width of the auxiliary pattern can also be increased. At this time, the effective line width of the auxiliary pattern can still meet the size requirements of the sub-resolution auxiliary pattern. Preferably, the actual line width of the auxiliary pattern can be greater than the maximum line width of the sub-resolution auxiliary pattern, further improving the effect of the auxiliary pattern on performing optical proximity effect compensation on the nearby main pattern, thereby further expanding the process window.
[0083] In subsequent correction steps following the first correction step, at least one of the number of lines, the actual line width, and the opening width of the auxiliary pattern can be changed.
[0084] According to the correction method of the third embodiment of the present invention, compared with the existing mask correction method, the opening width of the auxiliary pattern is used as a new correction parameter. Therefore, the convergence of the mask correction algorithm can be accelerated to save the mask design time and the cost of proximity effect verification.
[0085] As described above in accordance with the embodiments of the present application, these embodiments do not elaborate on all details, nor do they limit the application to the specific embodiments described. Obviously, many modifications and variations can be made based on the above description. The present specification selects and specifically describes these embodiments to better explain the principle and practical application of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.
Claims
1. A reticle, comprising: a substrate; a main pattern and an auxiliary pattern located on the substrate, wherein the line width of the auxiliary pattern is smaller than that of the main pattern, wherein the auxiliary pattern includes an outer contour and an opening surrounded thereby, so that the effective line width of the auxiliary pattern is smaller than the actual line width.
2. The reticle according to claim 1, wherein, The auxiliary pattern is substantially in a line shape, and the opening is substantially in a rectangular shape.
3. The mask according to claim 2, wherein The auxiliary pattern is located between adjacent main patterns of a plurality of main patterns.
4. The mask according to claim 2, wherein The main pattern is located between the auxiliary patterns.
5. The mask according to claim 1, wherein The auxiliary pattern is in a combined shape of a plurality of lines, and the opening is in a combined shape of a plurality of rectangles.
6. The reticle according to claim 5, wherein, The auxiliary pattern at least partially surrounds the corners of the main pattern.
7. The mask according to claim 1, wherein The main pattern and the auxiliary pattern of the reticle are the light-shielding regions of the reticle, and the opening of the auxiliary pattern is the light-transmitting region of the reticle.
8. The mask according to claim 1, wherein, The main pattern and the auxiliary pattern of the reticle are the light-transmitting regions of the reticle, and the opening of the auxiliary pattern is the light-shielding region of the reticle.
9. The reticle according to claim 1, wherein, The actual line width of the auxiliary pattern is greater than the maximum line width of the sub-resolution assist feature.
10. A method for correcting a reticle, comprising: obtaining an initial pattern of the reticle, the initial pattern including a main pattern corresponding to a structural pattern of a semiconductor device; adding an auxiliary pattern near the main pattern, the auxiliary pattern including a solid line; and correcting the auxiliary pattern according to an optical proximity effect verification result of the reticle to obtain a corrected pattern of the reticle, wherein the auxiliary pattern includes an outer contour and an opening surrounded thereby, such that the actual line width of the auxiliary pattern is greater than the line width of the sub-resolution assist feature, and the effective line width of the auxiliary pattern is smaller than the line width of the sub-resolution assist feature.
11. The correction method according to claim 10, wherein, The optical proximity effect verification includes performing simulation calculations to obtain a resist pattern formed by the reticle in lithography, or performing a lithography test to obtain a resist pattern formed by the reticle in lithography.
12. The correction method according to claim 11, wherein, In the case where an exposure error occurs in the resist pattern, the auxiliary pattern is corrected multiple times until the resist pattern is correctly exposed.
13. The correction method according to claim 12, wherein, The opening is added in the first correction step of the multiple corrections, and at least one of the number of lines, the actual line width, and the opening width of the auxiliary pattern is changed in subsequent correction steps of the first correction step.
14. The correction method according to claim 10, wherein, The actual line width of the auxiliary pattern is greater than the maximum line width of the sub-resolution assist feature.